Superlattice obtained by layer transfer, structure and production method

Abstract

The invention relates to a method (600) for producing a structure comprising a stack of superlattices, comprising the steps of forming (610Car) two superlattices (Stck1, Stck2) on respective substrates, each formed by a stack of channel layers alternating with sacrificial layers; forming (620Car, 620Don) respective overcoat layers (Cap1, Cap2) on the two superlattices (Stck1, Stck2); and assembling (660) the two superlattices (Stck1, Stck2) by placing their respective overcoat layers (Cap1, Cap2) in contact, so that together they form a bonding layer, the first overcoat layer (Cap1) and the second overcoat layer (Cap2) each having a thickness of less than 2 nm.

Description

Superlattice obtained by layer transfer, structure and manufacturing process TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to superlattices, which are made up of at least one periodic stack of thin layers. The invention relates more particularly to superlattices including layers of semiconductor materials. TECHNOLOGICAL BACKGROUND

[0002] Superlattices have attracted attention for their mechanical and semiconducting properties, and for the possibility they offer of forming quantum dots.

[0003] They are also used for the development of so-called nanosheet transistors, also known as Nanosheet transistors or GAAFET for Gate-all-around Field-Effect Transistors in English terminology, whose conduction channels are formed by a stack of layers of nanometric thickness each surrounded by a gate metal, as described in US patents 10,249,739 B2 and US 11,018,222 B1. These are semiconductor structures with an enveloping gate, or GAA for Gate-All-Around in English terminology.

[0004] This principle has been adopted to form so-called CFET transistors, for Complementary Field Effect Transistor in English terminology, presenting a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form a p-type transistor while a second superlattice formed on the first superlattice is used to form an n-type transistor, or vice versa. This three-dimensional structure is advantageous in terms of integration compared to conventional approaches used to implement CMOS technology, which usually employs p-type transistors and n-type transistors fabricated side-by-side in the same plane.In particular, the CFET approach makes it possible in principle to halve the size of a pair of p- and n-type transistors, or to shorten the connections between the two transistors and therefore to reduce the electrical resistance of the corresponding connections. This approach is described for example in documents US 2019 / 0319095 A1, US 2021 / 0104523 A1, and US 2023 / 0326925 A1.

[0005] Document US 2021 / 082901 A1 discusses the assembly of multilayer stacks formed on separate or non-separate substrates.

[0006] Document FR 2 857 983 A1 discloses a method of manufacturing an epitaxial layer, including the removal of the support substrate.

[0007] Whether it is Nanosheet transistors or CFET transistors, the manufacturing processes considered involve the fabrication of superlattices comprising stacks of two alternating types of materials: one is intended to form the channel regions of the transistors, the other to form sacrificial layers intended to be removed to be replaced by a gate dielectric and gate metal structure during the fabrication of the transistors.

[0008] Manufacturing CFET transistors requires stacking two types of transistors, n-type and p-type, on top of each other. Two approaches are possible.

[0009] The first approach is called "sequential", in the sense that the transistors of the two types are formed sequentially, during separate steps. In this approach, a semiconductor structure made of silicon or other semiconductor material, or a superlattice intended to form second Nanosheet transistors, is transferred onto a semiconductor substrate already carrying, for example, first Nanosheet transistors. In a first step, the first transistors are formed on the substrate, then the semiconductor structure is transferred onto it, in which the second transistors are then formed. The thermal budget for the process of transferring the semiconductor structure and for the formation of the second transistors is limited by the need not to degrade the first transistors.Furthermore, the alignment control of the second transistors with the first transistors must be extremely strict and specific electrical contact structures between the two stages must be provided.

[0010] The second approach is called "monolithic", in the sense that the first and second transistors are formed on the same substrate, at least part of the manufacturing steps being applied simultaneously to all of the layers in which the first and second transistors are formed. Reference may be made to document US 2019 / 0319095 A1. One of the main advantages of this approach is the self-alignment of the second transistors on the first transistors, which allows a higher density of transistors on the substrate, and reduces parasitic capacitances and resistances between the first and second transistors.

[0011] The monolithic approach requires thicker superlattices as the starting structure than the sequential approach, since these superlattices form the basic structure of two stacked transistors fabricated simultaneously. Superlattices are generally fabricated epitaxially. However, the number of stackable layers for the formation of these superlattices is limited by the critical epitaxy thickness, a thickness beyond which the quality of the deposited layers degrades due to elastic relaxation and / or plastic relaxation phenomena. The monolithic approach is close to and could require exceeding the critical epitaxy thickness.

[0012] Thus, there is a need for superlattice structures comprising layers in sufficient number and quality to guarantee the homogeneity and performance of transistors formed from these layers. In addition, the manufacturing processes of CFET transistors require basic structures facilitating and making their manufacturing more reliable, and, if possible, improving the characteristics of the devices obtained, in particular miniaturization, parasitic capacitances, or even the electrical resistances of the connections.

[0013] The applicant's objective is to provide a method for manufacturing a structure capable of facilitating the integration and production of Nanosheet transistors, and optionally CFET transistors, i.e. p-type transistors and stacked n-type transistors. More generally, the method according to the invention aims to form superlattices of arbitrary thickness or number of layers.

[0014] To achieve this aim, one aspect of the invention is a method of manufacturing a structure comprising at least one superlattice, comprising the steps of: forming a first superlattice on a first substrate, by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming a first covering layer on the first superlattice; forming at least one second sacrificial layer on a second substrate; forming a second covering layer on the at least one second sacrificial layer;forming a weakening plane of the carrier substrate by implanting ions of a light species into the donor substrate through the at least one second sacrificial layer and the second capping layer and assembling the at least one sacrificial layer to the first superlattice by contacting the second capping layer with the first capping layer which together form a bonding layer, the first superlattice, the bonding layer and the at least one sacrificial layer being stacked in this order, fracturing the donor substrate at the weakening plane and removing a portion of the donor substrate after the assembling step,;

[0015] wherein the first covering layer and the second covering layer each have a thickness of less than 2 nm.

[0016] A first advantage of the process is to provide a stack of superlattices which can be either identical or distinct in composition and / or orientation.

[0017] A second advantage of the process is the possibility of exceeding the critical epitaxy thickness for the structures obtained, which limits the number and thickness of layers that can be epitaxied on top of each other without losing quality in the crystalline structures of these layers.

[0018] A third advantage of the process lies in the provision within the stack of a bonding layer between two superlattices, this layer being able to be eliminated during the same process as that of the elimination of sacrificial layers included in the superlattices.

[0019] Thus, the manufacturing method according to the invention is suitable for the production of structures which can serve as the basis for a monolithic method for producing an electronic circuit integrating Nanosheet transistors or CFET transistors.

[0020] According to additional non-limiting characteristics of the method according to the invention, considered individually or according to any technically feasible combination:

[0021] - the step of forming at least one second sacrificial layer on the second substrate may consist of forming a second superlattice by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers;

[0022] - the step of forming at least one second sacrificial layer on the second substrate may consist of forming a seed layer, the method may further comprise a step of forming a second superlattice on the seed layer after the assembly step, by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers;

[0023] - the bonding layer may be continuously formed in a plane parallel to a surface of the first substrate on which the first superlattice is formed;

[0024] - the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0025] - the sacrificial layers in direct contact with the bonding layer may each have a thickness equal to or less than half the thicknesses of the other sacrificial layers;

[0026] - the method may further comprise a step of removing at least a portion of the second substrate after the assembly step;

[0027] - the method may further comprise a step of releasing a channel layer from the second superlattice after the step of removing the second substrate;

[0028] - the first covering layer and the second covering layer may each be formed of silicon;

[0029] - one of the first covering layer and the second covering layer may be formed from amorphous silicon and the other may be formed from crystalline silicon;

[0030] - the method may further comprise a step of forming at least one etch stop layer on the second substrate before forming the primer layer;

[0031] - the at least one attack stop layer may comprise a layer of the same material as the primer layer;

[0032] - the first channel layers may be formed of silicon; the first sacrificial layers may be formed of a first alloy of silicon and germanium; the first capping layer may be formed on and in direct contact with one of the sacrificial layers of the first superlattice; the second sacrificial layer may be formed of a second alloy of silicon and germanium; the second capping layer may be formed on and in direct contact with the at least one second sacrificial layer; and the first capping layer and the second capping layer may each be formed of silicon.

[0033] The invention extends to a structure of a superlattice stack, comprising: a carrier substrate; a first superlattice on the carrier substrate; a bonding layer on the first superlattice, formed from a first capping layer and a second capping layer; and a second superlattice on the bonding layer, wherein the first capping layer and the second capping layer each have a thickness of less than 2 nm.

[0034] According to additional non-limiting characteristics of the structure according to the invention, considered individually or according to any technically feasible combination:

[0035] - the bonding layer may be continuously formed in a plane parallel to a surface of the carrier substrate supporting the first superlattice;

[0036] - the first superlattice may be formed from a stack of a plurality of first channel layers alternating with a plurality of first sacrificial layers; the second superlattice may be formed from a stack of a plurality of second channel layers alternating with a plurality of second sacrificial layers; the first channel layers and the second channel layers may each be formed from a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed from a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0037] - one of the first capping layer and the second capping layer may be formed from crystalline silicon and the other of the first capping layer and the second capping layer may be formed from amorphous silicon; and

[0038] - the sacrificial layers in direct contact with the bonding layer may each have a thickness equal to or less than half the thicknesses of the other sacrificial layers. BRIEF DESCRIPTION OF THE FIGURES

[0039] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0040] Illustrates a first manufacturing method according to the invention;

[0041] Illustrates a continuation of the process of the;

[0042] Illustrates variants of structures that can be obtained by the process of figures 1 and 2;

[0043] Illustrates a detail of one of the variants of the bonding layer of the;

[0044] Illustrates an interest in structures in the manufacture of Nanosheet or CFET transistors;

[0045] This is a diagram summarizing the manufacturing process of Figures 1 and 2;

[0046] Illustrates a second manufacturing method according to the invention;

[0047] Illustrates a continuation of the process of the ; and

[0048] This is a diagram summarizing the manufacturing process of Figures 7 and 8. DETAILED DESCRIPTION OF THE INVENTION

[0049] First embodiment

[0050] A first embodiment of the present invention is described by means of Figures 1 to 6 and the associated description below.

[0051] Illustrates in (A) a Strc structure formed from a carrier substrate Car, a first superlattice Stck1, a bonding layer Bnd, and a second superlattice Stck2, stacked in this order. The first superlattice Stck1 comprises a plurality of first Ch1 layers stacked alternately with a plurality of first Sac1 layers, preferably such that each first Ch1 layer is interposed between and in direct contact with two of the first Sac1 layers. The second superlattice Stck2 comprises a plurality of second Ch2 layers stacked alternately with a plurality of second Sac2 layers, preferably such that each second Ch2 layer is interposed between and in direct contact with two of the second Sac2 layers.

[0052] The first Ch1 layers and the second Ch2 layers are layers formed of at least one semiconductor material for forming channel regions of transistors and may be referred to as the first channel Ch1 layers and the second channel Ch2 layers, respectively. These channel layers may be formed of the same material, or of different materials.

[0053] The first Sac1 layers and the second Sac2 layers are layers formed from at least one material capable of exhibiting faster etching rates than the first Ch1 layers and the second Ch2 layers, and may be referred to as the first sacrificial Sac1 layers and the second sacrificial Sac2 layers, respectively. These sacrificial layers may be formed from the same material, or from different materials. In particular, the Sac1 layers may have a Si composition 1-X Ge xand Sac2 layers can have a Si composition 1-y Ge y where x and y represent the proportions of germanium in the Sac1 and Sac2 layers, respectively, with x being different from or equal to y. These Sac1 and Sac2 layers of SiGe alloy can be associated with Ch1 and Ch2 layers of silicon, thanks to the compatibility of epitaxial growth of these two materials which have a fairly close lattice parameter. The proportions x and y are preferably less than 40%, for example between 15% and 35%.

[0054] The second layers Sac1 and Sac2 are intended to serve as sacrificial layers in a Nanosheet transistor formation procedure, during which the layers Sac1 and Sac2 are removed by etching, which may be chemical, so as to obtain a structure of floating ribbons formed of the layers Ch1 and Ch2. These floating ribbons will subsequently be surrounded by a gate dielectric layer and a gate metal so as to form Nanosheet transistors.

[0055] Figures 1, 2 and 6 illustrate a method for manufacturing the Strc structure, which is advantageously based on the separate manufacturing of the two superlattices Stck1 and Stck2 on two respective substrates, then the transfer of the second superlattice Stck2 onto the first superlattice Stck1. The first and second superlattices each comprise at least two channel layers Ch1 and Ch2, respectively. The represents a diagram schematizing the steps of the manufacturing method 600.

[0056] Illustrates in (A) the formation of the first Stck1 supernetwork on a Car carrier substrate, during a step 610 Car . In this example, the carrier substrate Car consists of a monocrystalline silicon wafer. On a surface S Car of the Car substrate, Ch1 layers of silicon Si 5 to 15 nm thick, preferably 7 to 10 nm thick, are grown by epitaxy, alternating with Sac1 layers of a first alloy of silicon and germanium of formula Si 1-x Ge x 5 to 10 nm thick, preferably 6 to 9 nm thick, and where x represents the percentage of germanium in the alloy, preferably starting and ending with a Sac1 layer.

[0057] On and in direct contact with the last layer Sac1 we form, during a step 620 Car, a covering layer Cap1, here formed of silicon Si of crystalline or amorphous structure and having the function of preventing the oxidation of the last layer Sac1. The layer Cap1 may have a thickness of less than 2 nm or 3 nm, for example between 0.5 and 2 nm, preferably between 1 and 2 nm, for reasons which will be explained below, by means of the.

[0058] Illustrates in (B) the formation of the second Stck2 supernetwork on a donor substrate Don, during a step 620 Don . In this example, the donor substrate Don consists of a monocrystalline silicon wafer.

[0059] On a surface S Don of the Don substrate, Ch2 layers of silicon Si 5 to 15 nm thick, preferably 7 to 10 nm thick, are grown by epitaxy, alternating with Sac2 layers of the first alloy of silicon and germanium of formula Si 1-x Ge x5 to 10 nm thick, preferably 6 to 9 nm thick. Preferably, the growth is carried out so that one begins and ends with a sacrificial layer Sac2. On and in direct contact with the last layer Sac2, a covering layer Cap2 is formed, made of silicon of amorphous or crystalline structure, during a step 630 Don. Preferably, one of the silicon layers Cap1 and Cap2 has an amorphous structure while the other has a crystalline structure in order to facilitate their subsequent assembly by direct contact. The function of the Cap2 layer is to prevent the oxidation of the last layer Sac2. This Cap2 layer is however optional, its interest depending on the ease of oxidizing of the material constituting the last layer of the second Stck2 superlattice. The Cap2 layer may have a thickness of less than 2 nm or 3 nm, for example between 0.5 and 2 nm, preferably between 1 nm and 2 nm, for reasons which will be explained below, by means of the.

[0060] Optionally, before the formation of the second superlattice Stck2, a layer Stp formed for example from the first alloy of silicon and germanium of formula Si can be formed on the donor substrate Don 1-x Ge x with a thickness between 5 and 10 nm, during a step 610Don . This layer is an etch stop layer and is intended to protect the integrity of the layers of the second Stck2 superlattice during the fabrication steps following the fracture of the donor substrate described later and illustrated in (B) and (C) of the.

[0061] Illustrates in (C) an implantation of light species such as hydrogen, helium, or a combination of such species into the donor substrate Don through the surface S Don , the second super network Stck2 and the covering layer Cap2, so as to form a weakening plane Imp in the donor substrate Don, during a step 640 Don .

[0062] The implantation is performed here after the formation of the second Stck2 superlattice. This order of operations provides several advantages over the reverse order. In particular, the epitaxial formation temperature of the layers of the second superlattice is not limited by the presence of the Imp embrittlement plane, so it is possible to optimize the layer growth parameters and limit the time required for epitaxy, which limits the diffusion of germanium in the structure. If the implantation were performed before the formation of the second superlattice, there would be a risk of involuntary detachment of the second superlattice during its formation due to the thermal budget it imposes on the embrittlement layer, which would require limiting the temperatures during the growth of the layers.Furthermore, both superlattices can be formed using the same parameters, rather than two sets of parameters, one of which must take into account the presence of a weakening plane, which promotes the homogeneity of their characteristics and simplifies the manufacturing process.

[0063] Following the formation of the embrittlement plane Imp, the donor substrate Don is turned over and the covering layer Cap2 is brought into intimate contact with the silicon layer Cap1 and is assembled there, for example by molecular bonding or any other assembly technique by bringing into direct contact surfaces of elements to be assembled, so as to obtain the structure illustrated in (A) of the, during an assembly step 660. The bonding layer Bnd is formed at this step by bonding the last layers formed respectively on the carrier substrate Car and on the donor substrate Don, and corresponds to the assembly formed by the layers Cap1 and Cap2 separating the first superlattice Stck1 and the second superlattice Stck2, as illustrated by the. This bonding layer Bnd preferably completely overlaps the donor substrate Don. In addition, the bonding layer Bnd is continuously formed in a plane parallel to the surface S Carof the carrier substrate Car supporting the first superlattice Stck1. Even if the bonding layer does not strictly overlap the entire carrier substrate Car, it is at least formed continuously over an area intended to form an assembly of semiconductor components such as transistors, possibly an assembly of Nanosheet transistors or CFET transistors.

[0064] Preferably, the support and donor substrates comprising respectively the first and second superlattices are substantially identical. This advantageously makes it easy to produce them on a large scale, thus facilitating their industrialization. Furthermore, substantially identical support and donor substrates advantageously make it possible to have a symmetrical assembled structure having similar thermal expansion coefficients, which advantageously avoids problems of mechanical deformation following the bonding steps and subsequent heat treatments.

[0065] At this stage of the manufacturing, the superlattices Stck1 and Stck2 are sandwiched between the carrier substrate Car and the donor substrate Don. These superlattices must be cleared in order to make them accessible. This clearing operation 670 is carried out in two successive steps 670A and 670B which will allow direct access to the second superlattice Stck2. Step 670A here consists of removing the majority of the donor substrate while step 670B consists of eliminating the remainder of the donor substrate and exposing the upper part of the second superlattice Stck2.

[0066] Illustrates in (B) the fracture of the donor substrate Don at the level of the embrittlement plane Imp obtained by ion implantation, so that a part Don b is removed from the structure shown in (A) while a part Don aremains fixed there, during the fracture and removal step 670A. This fracture can be obtained by heat treatment, possibly assisted by mechanical stress to initiate the fracture, according to conventional layer transfer techniques well known in the field of microelectronics.

[0067] Following assembly and fracture of the donor substrate, a heat treatment can be applied to consolidate the assembly and heal the assembled layers. The temperature and duration of the heat treatment are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses. The heat treatment can typically consist of an annealing of 2 hours or less at a maximum temperature of 750°C and preferably below 700°C.

[0068] An alternative to the formation of an embrittlement plane and the fracture of the Don donor substrate at this plane may be to thin the Don donor substrate after its assembly, for example by etching, grinding and / or chemical mechanical polishing (CMP). This thinning may be used to completely remove the second Don substrate if it is pushed, for example, up to the barrier layer Stp.

[0069] Illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Don part a of the donor substrate Don, and of the etch stop layer Stp, during step 670B. Thus, the layer Ch2 of the second superlattice furthest from the carrier substrate Car is released during this step.

[0070] The structure in (C) of the represents the structure Strc formed by the carrier substrate Car, the first superlattice Stck1, the capping layer Cap1 formed of silicon, the capping layer Cap2 formed of silicon, and the second superlattice Stck2, stacked in this order. The capping layer Cap1 and the capping layer Cap2 form a bonding layer Bnd between the first superlattice Stck1 and the second superlattice Stck2, as indicated by the in (A). This structure is ready to be subjected to a monolithic process for forming CFET transistors.

[0071] The figures are labeled "Si" or "SiGe" at the locations of certain layers, and in particular those forming the Stck1 and Stck2 superlattices, in order to increase their readability by indicating their compositions for a given example. These indications are not, however, to be interpreted as limiting the nature of the layers thus annotated. Other materials, and in particular those cited in this description, may be used to form these layers.

[0072] Illustrates in (A') a Strc' structure with a possible particularity of the layers surrounding and in direct contact with the Bnd bonding layer.

[0073] In (A) and (A'), the bonding layer Bnd is formed by bonding the covering layer Cap1 to the covering layer Cap2, constituting respectively the last layers formed on the carrier substrate Car and on the donor substrate Don, in direct contact with, respectively, the last sacrificial layer Sac1 or Sac10 formed on the carrier substrate Car and the last sacrificial layer Sac2 or Sac20 formed on the donor substrate Don. The thicknesses of these last sacrificial layers Sac1 (annotated Sac10 for Strc') and Sac2 (annotated Sac20 for Strc') may for example be of the same thickness as the other layers Sac1 and Sac2, respectively.

[0074] In the example shown in (A), all the Sac1 and Sac2 layers are of the same thickness. In this configuration, the distance separating the closest Ch1 and Ch2 layers separated by the Bnd layer is greater than the distances separating two consecutive Ch1 layers or two consecutive Ch2 layers in the stack, since this distance corresponds to the sum of the thicknesses of a Sac1 layer, a Sac2 layer and the Bnd layer.

[0075] In A', the sacrificial layers in direct contact with the bonding layer Bnd, identified as Sac10 and Sac20, are respectively of thicknesses t Sac10 and t Sac20 lower than the thicknesses of the other sacrificial layers Sac1 and Sac2 of respective thicknesses t Sac1 and t Sac2. The layers Sac10 and Sac20 can thus each have a thickness equal to or less than half the thicknesses of the other sacrificial layers Sac1 and Sac2, respectively. In this way, the total thickness t tot separating the Ch1 and Ch2 layers closest to each other and separated by the Bnd layer of thickness t B nd can be close to or even equal to the thicknesses t Sac1 and t Sac2 , as illustrated by the(t tot =t Sac10 +t B nd +t Sac20 ). An interest of this geometry is explained in relation to the.

[0076] As explained above, a Nanosheet or CFET transistor manufacturing process employs a superlattice of semiconductor material with sacrificial layers sandwiched between layers of a semiconductor material to form the transistor channel regions.

[0077] According to the invention, in the present embodiment, the silicon layers Cap1 and Cap2 are sufficiently thin so that germanium from the layers Sac10 and Sac20 has diffused over the entire thickness of the layers Cap1 and Cap2 during the manufacturing process. This diffusion can be ensured by a dedicated heat treatment, by choosing the parameters of a bonding heat treatment during the assembly of the two stacks Stck1 and Stck2, by choosing the parameters of a fracture heat treatment of the donor substrate Don, the heat treatment parameters for consolidating the assembly and repairing the assembled layers, or even by parameterizing these different operations so as to ensure the diffusion of the germanium in the layers Cap1 and Cap2. It is of course advisable not to go beyond the necessary thermal budget so as to prevent the germanium from diffusing throughout the entire thickness of the channel layers.Also, the thickness of the channel layers can be designed to take this diffusion into account. Thus, the layers Cap1 and Cap2 of the structures illustrated by are in fact made of an alloy of silicon and germanium, and can therefore be considered as sacrificial layers with respect to the channel layers Ch1 and Ch2, in the same way as the sacrificial layers Sac1, Sac10, Sac2 and Sac20.

[0078] Laillustrates the Strc' structure of the having been subjected to an attack of the sacrificial layers Sac1, Sac10, Sac2 and Sac20 having left the channel layers Ch1 and Ch2 suspended. In view of the comments in the previous paragraph, it is understood that the layers Cap1 and Cap2 forming the bonding layer have also been attacked. In the general case of the Strct structure, it is possible to obtain a structure of suspended channel layers Ch1 and Ch2, of good crystalline quality over a thickness and / or a number of layers exceeding what is possible from a structure obtained by a conventional epitaxy process, a process limited by the critical epitaxy thickness.

[0079] Furthermore, in the particular case of the Strc' structure, the environment of each of the channel layers Ch1 and Ch2 can be arranged as substantially identical to that of the other channel layers, including with regard to the distances separating them: the distance t totseparating the two channel layers closest to each other and previously separated by the bonding layer Bnd can be brought closer to t Sac1 and t Sac2 of or arranged equal to these distances separating the other channel layers from each other, as illustrated by the. An advantage is the uniformity of the environment of the channel layers of the transistors formed on this basis.

[0080] The bonding layer Bnd, which is the layer bonding the two superlattices to each other, is not in principle limited to being formed of crystalline silicon and amorphous silicon. The layer Bnd may be formed exclusively of crystalline silicon, exclusively of amorphous silicon, or of any other material compatible with the manufacturing processes set forth in this document, and possibly with the envisaged manufacturing processes using as a basis the assembly of the two superlattices Stck1 and Stck2.

[0081] The manufacturing process illustrated in Figures 1 and 2 allows for a superposition of two superlattices. In addition, the process can be repeated to stack an arbitrary number of superlattices. Thus, the critical epitaxy thickness can be exceeded: each of the superlattices taken individually can respect this thickness so as to be formed of high-quality layers, and their stacking allows an assembly of superlattices exceeding the critical thickness while maintaining the quality of the layers composing them. When the stacked superlattices have similar characteristics with regard to the layers (nature, dimension) forming them, it can be considered that a single superlattice is formed, possibly exceeding the critical epitaxy thickness.

[0082] The epitaxial formation of the layers constituting the superlattices involves the reproduction of the crystalline structure from one layer to another, so that the layers Ch1 (or Ch2) and Sac1 (or Sac2), for example in Si and SiGe respectively, have the same crystalline structure. Usually, it is not possible to epitaxially grow a semiconductor layer of acceptable characteristics for the purpose of forming transistors on an amorphous layer. Indeed, the latter does not constitute an adequate basis for the epitaxial growth of a high-quality crystalline semiconductor layer. The bonding layer obtained by the layer transfer of the method according to the invention makes it possible to assemble two superlattices formed from semiconductor layers of sufficient quality to produce transistors for commercial applications.

[0083] Furthermore, the bonding layer can be adapted (composition, thickness of the layer(s) forming it) to the intended use of the stacked superlattices. In particular, it is possible to ensure removal of the bonding layer during a subsequent operation of removing the sacrificial layers by means of an appropriate choice of the nature and thickness of the layers composing it.

[0084] The bonding layer between the two superlattices is formed continuously in a plane parallel to the upper surface of the substrate supporting it, covering substantially the entire surface of the substrate.

[0085] The carrier substrate Car and the donor substrate Don may comprise any semiconductor material. In addition to silicon, the semiconductor material may be germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors or II-VI compound semiconductors, or SOI type substrates for Silicon-On-Insulator in English terminology, and more generally any type of semiconductor substrate comprising a buried or surface layer of dielectric material. Such a dielectric layer may serve as an etch stop layer for the formation of structures on the rear face (on the side of the carrier substrate Car) of the structure obtained by the method described in Figures 1 and 2, or, in the case where it is located on the surface, as insulation in order to prevent the so-called "latch-up" phenomenon of an integrated circuit manufactured on the basis of this structure.

[0086] The Ch1 and Ch2 layers may be formed, for example, from silicon or a III-V type semiconductor compound. The Sac1 and Sac2 layers may be formed, for example, from silicon and germanium alloys generically referred to as SiGe. The Ch1 and Ch2 layers may be of the same composition in both Stck1 and Stck2 superlattices, and similarly, the Sac1 and Sac2 layers may be of the same composition Si 1-x Ge x in the two superlattices Stck1 and Stck2. This last point makes it possible to eliminate the sacrificial layers Sac1 and Sac2 during the same step.

[0087] Alternatively, the superlattices Stck1 and Stck2 may be of different natures and / or orientations. The orientation of the second superlattice with respect to the first superlattice is defined during the assembly step. The layers Sac1 and Sac10 (and Ch1) on the one hand, and the layers Sac2 and Sac20 (and Ch2) on the other hand, may for example have different orientations, for example with crystallographic axes offset by 45°. One may also consider the use of strained silicon, silicon and germanium alloys SiGe or germanium for the channel layers of one or the other of the two superlattices or for both. When the two superlattices comprise silicon and germanium alloys, the proportions of germanium in the alloy may be the same or different for the two superlattices. It is of course appropriate to adapt the nature and characteristics of the sacrificial layers Sac1 and Sac2 to those of the layers Ch1 and Ch2.

[0088] Similarly, the numbers of channel layers and sacrificial layers in the two superlattices may be the same, respectively, or may be different.

[0089] Second embodiment

[0090] A second embodiment of the present invention is described by means of Figures 3, 7, 8 and 9 and the associated description below.

[0091] In the first embodiment, the two superlattices Stck1 and Stck2 illustrated by are formed separately on two respective substrates, then the second superlattice Stck2 is transferred onto the first superlattice Stck1. The second embodiment differs from this first embodiment in that instead of transferring a second superlattice onto the first superlattice Stck1, a seed layer Init is transferred onto the first superlattice Stck1, then the second superlattice Stck2 is formed on this seed layer Init by epitaxy. The seed layer Init is then integrated into the second superlattice Stck2. Apart from this aspect, reference may be made to the description of the first embodiment, the same elements and the same steps being identified by the same references. In particular, the structures obtained by the manufacturing methods of the two embodiments are illustrated in a common manner by the.

[0092] Figures 7, 8 and 9 illustrate a manufacturing process 900 of the Strc and Strc' structures of the, this process being based on the sequential manufacturing of the two superlattices Stck1, the second superlattice Stack2 being formed directly on the first superlattice Stck1. The represents a diagram schematizing the steps of the manufacturing process 900.

[0093] Subsequently, only the steps distinct from the corresponding steps of the first embodiment are commented on. Steps 610 Car , 620 Car , 640 Don , 660, and 670A and their sequences remain unchanged in this second embodiment.

[0094] A 910 step Don replaces step 610 Don : before the formation of the primer layer Init formed during the following step 920 Don , the Stp layer of the first silicon and germanium alloy of formula Si can be formed on the donor substrate Don 1-x Ge xwith a thickness between 5 and 10 nm, then a silicon Cap2' protective layer with a thickness between 1 and 5 nm. These two layers are etch stop layers and are intended to protect the integrity of the Init layer during the manufacturing steps following the fracture of the donor substrate described later and illustrated in (B) and (C) of the.

[0095] A step 920 Don replaces step 620 Don : instead of forming a superlattice on the donor substrate, a seed layer Init is formed. This may be a layer of the same nature and characteristics as one of the sacrificial layers Sac2. Illustrates in (A), (B) and (C) the progress of the manufacturing process after steps 620 Car , 930 Don and 640 Don , respectively.

[0096] A 930Don step is substantially identical to the 630Don step. Simply, instead of training the Cap2 layer on a second superlattice, this Cap2 layer is trained on the Init seed layer.

[0097] The following steps do not change up to step 970 which replaces step 670 of the first embodiment. This is substantially identical to step 670, except that step 670B is replaced by a step 970B during which it is the primer layer Init which is cleared and exposed. Illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Don part a of the donor substrate Don, the etch stop layer Stp, and the protective layer Cap2' during step 970B. Thus, the primer layer Init is released during this step, and accessible for the rest of the manufacturing process.

[0098] The manufacturing process ends with the implementation of a step 980 of forming the second superlattice Stck2 by epitaxy. A preliminary step is to eliminate, within a thin-film deposition frame, any native oxide from the surface of the Init layer, using the “in-situ” etching function available in a large number of epitaxy frames. This operation makes it possible to clean the Init layer and guarantee the quality of its surface in order to ensure the quality of the growth of the layers deposited there. The second superlattice Stck2 is then formed directly on the seed layer Init, during a step 980, according to the methods described for step 620 Don , considering the seed layer Init as one of the sacrificial layers Sac2 of the second superlattice Stck2 and as the starting layer for epitaxial growth. Ch2 layers are thus formed in succession alternating with Sac2 layers.

[0099] The cleaning operation of the Init layer prior to the layer depositions is conventional and is considered as part of the step of formation of the Ch2 and Sac2 layers by epitaxy. Alternatively, other known methods of cleaning the surface of the Init layer could be considered, such as the complete oxidation of the Cap2' layer and its removal by HF directly in the frame. The essential thing is to obtain a clean, non-oxidized surface, before proceeding with the deposition of thin layers on this surface, whether the deposition sequence is started with a Sac2 layer or a Ch2 layer. Following this step, one or the other of the structures illustrated by are obtained.

[0100] The above embodiments have taken as an example associations between layers of silicon alternating with layers of silicon and germanium alloys to form the first superlattice and the second superlattice. However, the invention is not limited to this particular case, and could be applied for example (i) to superlattices consisting of layers of germanium alternating with layers of a silicon and germanium alloy, (ii) to superlattices consisting of layers formed from a first silicon and germanium alloy with a germanium content for example less than 20% alternating with layers formed from a second silicon and germanium alloy with a high germanium content, for example greater than 75%, (iii) to superlattices having layers of different crystallographic orientations, or (iv) to superlattices comprising layers of III-V semiconductor materials.

[0101] The embodiments described above relate to a combination of superlattices intended to form transistors, and more specifically Nanosheet transistors or CFETs. The scope of the invention extends, however, beyond this field, and includes the combination of superlattices in general, not only in the field of semiconductors.

[0102] The invention is not limited to the embodiments described above and variations may be made thereto without departing from the scope of the invention as defined by the claims.

Claims

Method (600; 900) for manufacturing a structure (Strc, Strc') comprising at least one super network, comprising the steps of:- forming (610 Car ) a first super network (Stck1) on a first substrate (Car), by stacking a plurality of first channel layers (Ch1) alternating with a plurality of first sacrificial layers (Sac1);- forming (620 Car ) a first covering layer (Cap1) on the first super network (stck1);- form (620 Don ; 920 Don ) at least one second sacrificial layer (Stck2; Init) on a surface (S Don ) a second substrate (Don);- form (630 Don ; 930 Don ) a second covering layer (Cap2) on the at least one second sacrificial layer (Stck2; Init);- forming (640Don) a weakening plane (Imp) of the carrier substrate by implantation of ions of a light species in the donor substrate (Don) through the surface (S Don) of the second substrate (Don), at least one second sacrificial layer (Stck2; Init) and the second covering layer (Cap2);- assembling (660) the at least one sacrificial layer (Stck2; Init) to the first superlattice (Stck1) by bringing the second covering layer (Cap2) into contact with the first covering layer (Cap1) which together form a bonding layer (Bnd), the first superlattice (Stck1), the bonding layer (Bnd) and the at least one sacrificial layer (Stck2; Init) being stacked in this order; and- fracturing (670A) the donor substrate (Don) at the weakening plane (Imp) and removing a portion (Don b ) of the donor substrate (Don) after the assembly step (660), wherein the first covering layer (Cap1) and the second covering layer (Cap2) each have a thickness of less than 2 nm. The method (600) of claim 1, wherein the step of forming at least one second sacrificial layer on the second substrate (Don) comprises forming (620 Don ) a second superlattice (Stck2) by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2). The method (900) of claim 1, wherein the step of forming at least one second sacrificial layer (Stck2) on the second substrate (Don) comprises forming (920 Don ) a seed layer (Init), the method further comprising a step (980) of forming a second superlattice (Stck2) on the seed layer (Init) after the assembly step (660), by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2). The method of any one of claims 1 to 3, wherein the bonding layer (Bnd) is continuously formed in a plane parallel to a surface (S Car ) of the first substrate (Car) on which the first super network (Stck1) is formed. The method of any one of claims 2 to 4, wherein:- the first channel layers (Ch1) and the second channel layers (Ch2) are each formed of a semiconductor material, and- the first sacrificial layers (Sac1) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Ch1) and the second channel layers (Ch2), respectively. The method of claim 5, wherein the sacrificial layers (Sac1 0 , Bag2 0 ) in direct contact with the bonding layer (Bnd) each have a thickness (t Sac10 , t Sac20) equal to or less than half of the thicknesses (t Sac , t Sac ) of the other sacrificial layers (Sac1, Sac2). The method of any one of claims 1 to 6, further comprising a step of removing (670A) at least a portion (Don b ) of the second substrate (Don) after the assembly step (660). The method according to claim 7, further comprising a step of releasing (670B) a channel layer (Ch2) from the second superlattice (Stck2) after the step of removing (670A) the second substrate (Don). The method of any one of claims 1 to 8, wherein the first covering layer (Cap1) and the second covering layer (Cap2) are each formed of silicon. The method of claim 9, wherein one of the first covering layer and the second covering layer is formed of amorphous silicon and the other is formed of crystalline silicon. The method of claim 3, further comprising a forming step (610 Don ) of at least one etch stop layer (Stp) on the second substrate (Don) before the formation of the primer layer (Init). The method of claim 11, wherein the at least one etch stop layer comprises a layer (Stp) of the same material as the primer layer (Init). The method according to any one of claims 1 to 12, wherein:- the first channel layers (Ch1) are formed of silicon;- the first sacrificial layers (Sac1) are formed of a first alloy of silicon and germanium;- the first capping layer (Cap1) is formed on and in direct contact with one of the sacrificial layers (Sac1) of the first superlattice;- the second sacrificial layer (Stck2; Init) is formed of a second alloy of silicon and germanium;- the second capping layer (Cap2) is formed on and in direct contact with the at least one second sacrificial layer (Stck2; Init); and- the first capping layer (Cap1) and the second capping layer (Cap2) are each formed of silicon. Structure (Strc, Strc') of a superlattice stack, comprising:- a carrier substrate (Car);- a first superlattice (Stck1) on the carrier substrate;- a bonding layer (Bnd) on the first superlattice (Stck1), formed of a first covering layer (Cap1) and a second covering layer (Cap2); and- a second superlattice (Stck2) on the bonding layer (Bnd), wherein:- the first superlattice is formed of a stack of a plurality of first channel layers (Ch1) formed of silicon alternating with a plurality of first sacrificial layers (Sac1) formed of a first alloy of silicon and germanium;- the second superlattice is formed of a stack of a plurality of second channel layers (Ch2) formed of silicon alternating with a plurality of second sacrificial layers (Sac2) formed of a second alloy of silicon and germanium;- the first covering layer (Cap1) and the second covering layer (Cap2) are each formed of silicon, in direct contact with one of the respective sacrificial layers of the first superlattice and the second superlattice, and each have a thickness of less than 2 nm.; The structure of a superlattice stack according to claim 14, wherein the bonding layer (Bnd) is continuously formed in a plane parallel to a surface (S Car ) of the carrier substrate (Car) supporting the first superlattice (Stck1). The structure of a superlattice stack according to claim 14 or 15 wherein:- the first channel layers (Ch1) and the second channel layers (Ch2) are each formed of a semiconductor material, and- the first sacrificial layers (Sac1) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Ch1) and the second channel layers (Ch2), respectively. The superlattice stack structure according to any one of claims 14 to 16, wherein one of the first capping layer (Cap1) and the second capping layer (Cap2) is formed of crystalline silicon and the other of the first capping layer (Cap1) and the second capping layer (Cap2) is formed of amorphous silicon. The structure according to any one of claims 14 to 17, wherein the sacrificial layers (Sac1 0 , Bag2 0 ) in direct contact with the bonding layer (Bnd) each have a thickness (t Sac10 , t Sac20 ) equal to or less than half of the thicknesses (t Sac , t Sac ) of the other sacrificial layers (Sac1, Sac2).

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