Method for evaluating wafer and wafer manufactured using same

Abstract

The present invention provides a method for evaluating a wafer and a wafer manufactured using same, the method including the steps of: preparing a wafer to be evaluated; outputting a flatness image of the wafer by using an optical member; pixelating the flatness image and calculating flatness data corresponding to each pixel; designating a plurality of regions within a radius of 50 mm based on the center of the wafer; calculating a total average value of the flatness data included in the plurality of regions; calculating an average value for each region of the flatness data included in the each region; and calculating a flatness data deviation rate according to equation 1 (see the description of the invention).

Description

Wafer evaluation method and wafer using the same

[0001] The present invention relates to a wafer evaluation method and a wafer using the same.

[0002]

[0003] Silicon carbide (SiC) boasts excellent heat resistance, mechanical strength, and radiation resistance, allowing for production on large-diameter substrates. Furthermore, SiC boasts superior physical strength and chemical resistance, a large energy band gap, and high electron saturation drift velocity and voltage resistance. Therefore, it is widely used in semiconductor devices requiring high power, efficiency, voltage, and capacity, as well as in abrasives, bearings, and refractory plates.

[0004] Typically, to manufacture an epitaxial silicon carbide wafer, a wire saw or the like is used to cut a silicon carbide single crystal ingot to a predetermined thickness, lapping is performed to reduce thickness variation, polishing is performed to reduce the processed layer, and then a chemical mechanical polishing (CMP) process is performed. Thereafter, an epitaxial layer can be grown on the silicon carbide wafer using a thermal chemical vapor deposition (CVD) process to manufacture the wafer.

[0005] The above-mentioned chemical mechanical planarization (CMP) or chemical mechanical polishing (CMP) process is used in various fields for various purposes. The CMP process is performed on a predetermined polishing surface of a polishing target, and can be performed for the purposes of planarizing the polishing surface, removing agglomerated materials, resolving crystal lattice damage, and removing scratches and contaminants.

[0006] In recent years, with the rapid progress in the development of silicon carbide wafers and the increasing demand for handling higher current densities, there is a strong demand for defect reduction in epitaxial silicon carbide wafers.

[0007] The defects of the above epitaxial silicon carbide wafer are highly correlated with the flatness uniformity of the wafer, and depending on the flatness uniformity of the wafer, triangular-shaped stacking defects, carrot defects, comet defects, etc. may occur on the wafer after epitaxial growth.

[0008] Therefore, there is a need for a method that can easily select wafers with a high possibility of defects by evaluating the flatness uniformity of the wafer after processing the wafer by the CMP process.

[0009]

[0010] The present invention provides a method for accurately and quickly evaluating the flatness uniformity of a wafer, which affects wafer quality.

[0011]

[0012] A wafer evaluation method according to the present invention includes the steps of preparing a wafer to be evaluated, the step of outputting a flatness image of the wafer using an optical member, the step of pixelizing the flatness image and calculating flatness data corresponding to each pixel, the step of designating a plurality of areas within a radius of 50 mm based on the center of the wafer, the step of calculating an overall average value of the flatness data included in the plurality of areas, the step of calculating an area-specific average value of the flatness data included in each of the areas, and the step of calculating a flatness data deviation rate according to the following Equation 1.

[0013] [Formula 1]

[0014] Flatness data deviation rate (%) = [(|X - Y|) / Y] ×100

[0015] In the above equation 1, X is the average value for each region, and Y is the overall average value.

[0016] In one embodiment of the present invention, the wafer may be a silicon carbide wafer.

[0017] In one embodiment of the present invention, the wafer may be a product that has undergone a chemical mechanical polishing process.

[0018] In one embodiment of the present invention, the flatness image of the wafer can be output using an interferometer of a laser coming from a light source of the optical member.

[0019] In one embodiment of the present invention, the flatness data may correspond to the total thickness variation of the wafer.

[0020] In one embodiment of the present invention, the plurality of regions may be designated to be spaced apart from each other.

[0021] In one embodiment of the present invention, one of the plurality of regions may include the center of the wafer.

[0022] In one embodiment of the present invention, the plurality of regions may be designated to be symmetrically distributed with respect to a region including the center of the wafer.

[0023] In one embodiment of the present invention, the number of flatness data included in each of the above areas may be 20 to 25.

[0024] In one embodiment of the present invention, a product may be judged as good if the flatness data deviation rate according to the above formula 1 is 15% or less.

[0025] In one embodiment of the present invention, a product may be judged to be good if the flatness data deviation rate according to the above formula 1 is 1% or more and 15% or less.

[0026] The wafer according to the present invention satisfies the flatness data deviation rate of 15% or less according to the above equation 1 using the wafer evaluation method described above.

[0027]

[0028] The evaluation method according to the present invention provides a parameter of a flatness data deviation rate by which the presence or absence of a defect in a wafer can be predicted, so that wafers with a high possibility of defects after a CMP process can be quickly sorted out.

[0029] In addition, the evaluation method according to the present invention not only calculates flatness data of a wafer, but also calculates an average value of flatness data by area distributed over the entire area of ​​the wafer to be evaluated, and by calculating the deviation rate thereof, the accuracy of the evaluation for selecting wafers with a high possibility of defects after the CMP process can be improved.

[0030] In addition, the evaluation method according to the present invention measures the flatness of a wafer by pixelating a flatness image and calculating flatness data corresponding to each pixel, thereby resolving the problem of inconsistency in wafer flatness data depending on conventional equipment conditions, measurement conditions, etc., thereby further improving evaluation reliability.

[0031]

[0032] Figure 1 schematically illustrates a flow chart of a wafer evaluation method according to the present invention.

[0033] Figure 2 illustrates pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Example 1.

[0034] Figure 3 shows pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Example 2.

[0035] Figure 4 shows pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Example 3.

[0036] Figure 5 shows pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Comparative Example 1.

[0037] Figure 6 shows pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Comparative Example 2.

[0038] Figure 7 shows pixelated flatness data and seven regions within a radius of 50 mm of the silicon carbide wafer manufactured in Comparative Example 3.

[0039]

[0040] The structural or functional descriptions of the embodiments disclosed in this specification or application are merely illustrative for the purpose of explaining embodiments according to the technical idea of ​​the present invention, and the embodiments according to the technical idea of ​​the present invention can be implemented in various forms other than the embodiments disclosed in this specification or application, and the technical idea of ​​the present invention is not construed as being limited to the embodiments described in this specification or application.

[0041] When a component is referred to as "including" in this specification or application, unless otherwise specifically stated, this does not exclude other components, but rather implies the inclusion of additional components. Furthermore, all numerical ranges indicating physical properties, dimensions, etc. of the components described in this specification or application should be understood to be modified by the term "about" in all cases unless otherwise specified. Furthermore, "ppm" in this specification or application refers to weight basis.

[0042] The description of "A and / or B" in this specification or application means "A, B, or A and B." In addition, when it is said that a certain component is "connected" to another component, this includes not only the case where it is "directly connected" but also the case where it is "connected with another component in between." In addition, the meaning of B being located on A means that B is located in direct contact with A or that B is located on A with another layer located in between, and is not limited to being located in contact with the surface of A. In addition, the singular expression is interpreted to include the singular or plural as interpreted in the context unless specifically stated otherwise. In addition, each embodiment may be combined with each other unless it is technically opposed to each other. In addition, a unit omitted in this specification or application may mean 'micro (㎛)'.

[0043]

[0044] Figure 1 schematically illustrates a flowchart of a wafer evaluation method according to the present invention. Referring to Figure 1, the evaluation method according to the present invention includes a step (S10) of preparing a wafer to be evaluated.

[0045] The above wafer may be a silicon carbide (SiC) wafer. The silicon carbide may have a larger energy band gap than silicon (Si), and may have improved maximum breakdown field voltage and thermal conductivity.

[0046] The above silicon carbide has excellent electron saturation drift velocity and withstand pressure, and can be applied to devices requiring high efficiency, high withstand pressure, and large capacity.

[0047] The above silicon carbide can be manufactured by processes such as liquid phase epitaxy (LPE) and chemical vapor deposition (CVD), and is preferably manufactured by a physical vapor transport (PVT) process in terms of efficiency of the manufacturing process.

[0048] The above silicon carbide wafer can be obtained from a silicon carbide ingot. The above silicon carbide wafer can be any one of wafers to which an off-angle is applied, which is an angle selected in the range of 0 to 8 degrees with respect to the (0001) plane (SiC (004) plane or (006) plane) of the silicon carbide ingot.

[0049] The above silicon carbide ingot may contain 4H SiC. The silicon carbide ingot may have a convex or flat surface. The silicon carbide ingot may be a substantially single-crystal 4H SiC ingot with minimal defects or polymorphic inclusions. The silicon carbide ingot is substantially composed of 4H SiC, and may have a convex or flat surface.

[0050] The silicon carbide ingot may have a diameter of 4 inches or more, 5 inches or more, or 6 inches or more. The silicon carbide ingot may have a diameter of 4 inches to 12 inches, 4 inches to 10 inches, or 6 inches to 8 inches.

[0051] The above silicon carbide ingot may be grown on the C-plane (0001) of the silicon carbide seed. The silicon carbide ingot may have a convex or flat surface and may have a warpage of 15 mm or less, 12 mm or less, or 0 mm to 10 mm.

[0052] The wafer to be evaluated above can be manufactured by a step of slicing the silicon carbide ingot and a step of polishing the sliced ​​crystal.

[0053] The above slicing step may be a step of slicing the silicon carbide ingot to have a constant off-angle to prepare a sliced ​​crystal.

[0054] The above off-angle may be based on the (0001) plane in 4H SiC. The above off-angle may be any one angle selected from 0 to 15 degrees, 0 to 12 degrees, or 0 to 8 degrees.

[0055] The above slicing may be performed using a slicing method generally used in the manufacture of silicon carbide wafers. For example, cutting using a diamond wire or a wire containing diamond slurry, or cutting using a blade or wheel partially containing diamond, may be used.

[0056] The thickness of the above-mentioned sliced ​​crystal can be adjusted in consideration of the thickness of the silicon carbide wafer to be manufactured. The thickness of the above-mentioned sliced ​​crystal can be sliced ​​to an appropriate thickness in consideration of the thickness after polishing in the polishing step.

[0057] The above polishing step may be a step of polishing the sliced ​​crystal to form a wafer having a thickness reduced to any one selected from 300 ㎛ to 800 ㎛.

[0058] The above polishing step may be performed in a manner such that polishing is performed after a process such as lapping and / or grinding is performed.

[0059] The above polishing may refer to a process of chemical mechanical polishing the wafer.

[0060] In the above polishing step, dressing may be performed using a conditioner to maintain one surface of the polishing pad in a state suitable for polishing before chemical mechanical polishing the wafer. By roughening one surface of the polishing pad with the conditioner, the polishing pad can be maintained in a state suitable for polishing, and foreign substances on the polishing pad can be removed.

[0061] The above polishing pad can be provided on a platen.

[0062] In the dressing process of the above polishing pad, the rotation speed of the platen may be 50 rpm to 150 rpm, 70 rpm to 150 rpm, 80 rpm to 150 rpm, or 80 rpm to 120 rpm.

[0063] In the dressing process of the above polishing pad, the rotation speed of the conditioner may be 70 rpm to 200 rpm, 90 rpm to 200 rpm, 110 rpm to 200 rpm, or 110 rpm to 150 rpm.

[0064] In the dressing process of the above polishing pad, the conditioner can vibrate in a reciprocating path from the center of the polishing pad to the end of the polishing pad.

[0065] When the vibrational motion of the conditioner is calculated as one time of going back and forth from the center of the polishing pad to the end of the polishing pad, the vibrational motion speed of the conditioner may be 10 times / min to 50 times / min, 15 times / min to 50 times / min, 20 times / min to 50 times / min, or 20 times / min to 40 times / min.

[0066] If the above range is satisfied, the phenomenon of defects occurring on the wafer surface can be minimized.

[0067] The above polishing step may include a step of cleaning the polishing head surface of the polishing equipment and a step of cleaning the wafer surface. By the above step, foreign substances on the portion of the polishing equipment where the wafer is loaded and on the wafer surface can be removed.

[0068] The cleaning of the polishing head surface may be performed for 50 seconds to 200 seconds, 70 seconds to 200 seconds, 90 seconds to 200 seconds, or 90 seconds to 150 seconds.

[0069] The wafer surface can be cleaned using a cleaning solution, rinse, etc. The wafer surface can be cleaned using ultrasonic waves. The wafer surface can be cleaned using ultrasonic waves of 80 kHz to 200 kHz, 80 kHz to 180 kHz, 100 kHz to 180 kHz, or 100 kHz to 150 kHz. The cleaning of the wafer surface can be performed for 400 seconds to 800 seconds, 450 seconds to 800 seconds, 500 seconds to 800 seconds, or 500 seconds to 700 seconds.

[0070] The above polishing step may include a step of mounting the wafer on the polishing head and performing chemical mechanical polishing on the wafer. By performing the chemical mechanical polishing process, an appropriate flatness of the wafer surface can be secured, thereby minimizing the occurrence of defects and improving process productivity.

[0071] The above steps can be performed by rotation of the above-mentioned plate, rotation of the polishing head, application of pressure of the polishing head to the above-mentioned polishing pad, and supply of polishing slurry.

[0072] The rotation speed of the above plate may be 100 rpm to 300 rpm, 100 rpm to 250 rpm, 100 rpm to 200 rpm, or 120 rpm to 200 rpm.

[0073] The rotation speed of the polishing head may be 50 rpm to 150 rpm, 50 rpm to 120 rpm, 50 rpm to 100 rpm, or 60 rpm to 80 rpm.

[0074] The pressurized load of the polishing head against the polishing pad may be 3 psi to 10 psi, 4 psi to 10 psi, 5 psi to 10 psi, or 5 psi to 7 psi.

[0075] The polishing slurry may be sprayed onto the polishing pad through a supply nozzle provided in the polishing equipment. The polishing slurry may include polishing particles. The polishing particles may include silica particles or ceria particles, but are not limited thereto. The flow rate of the polishing slurry may be 100 ml / min to 500 ml / min, 100 ml / min to 400 ml / min, 100 ml / min to 300 ml / min, or 150 ml / min to 300 ml / min.

[0076] During the above step, the surface temperature of the polishing pad can be maintained within a range of 50 to 55 degrees. When the above range is satisfied, the flatness deviation rate of the wafer can be minimized, so that the wafer can be processed into a good product with minimized defects after the above process.

[0077] In order to maintain the optimal surface condition of the polishing pad in the above step, a conditioner process having the above-described rotational speed range and vibration operation speed range may be followed.

[0078] By the above steps, a wafer to be evaluated according to the present invention can be prepared.

[0079]

[0080] The evaluation method according to the present invention includes a step (S20) of outputting a flatness image of the wafer using an optical member, and a step (S30) of pixelizing the flatness image and calculating flatness data corresponding to each pixel.

[0081] The flatness image of the above wafer can be output using an interferometer of a laser emitted from a light source of the above optical member. The wavelength of the laser can be 300 nm to 800 nm.

[0082] The above interferometer may utilize information that a laser beam from the light source is split into two light beams that travel different optical paths and are then recombined to create interference.

[0083] Information such as the flatness of the wafer to be evaluated can be generated by the interferometer, and an image for the information can be output by a program capable of outputting an image.

[0084] The above image can be visually expressed as a difference in saturation or brightness corresponding to the flatness of the wafer.

[0085] The above S30 step pixelates the flatness image and calculates flatness data corresponding to each pixel, thereby resolving the problem of inconsistent flatness data of the wafer depending on conventional equipment conditions, measurement conditions, etc., thereby further improving evaluation reliability.

[0086] The above step S30 can increase the magnification of the flatness image of the wafer output in the step S20, and then pixelize it and save it as a text file.

[0087] The magnification of the above image can be increased by 2x, 4x, 8x, 16x, 32x, or 64x, etc. In order to minimize the deviation of the flatness data corresponding to the pixel and to compare the flatness data in the entire area of ​​the wafer to be evaluated, it is preferable to increase it by 16x.

[0088] Fig. 2 illustrates pixelated flatness data of a silicon carbide wafer manufactured in Example 1 described below. Referring to Fig. 2, the pixel values ​​(P) stored in the text file may correspond to flatness data for each position of the wafer. For example, the values ​​of 1.3602, 1.3446, 2.0653, and 2.5615, respectively, indicated by P represent pixelated flatness data corresponding to each position of the wafer, and the unit is μm. By evenly pixelating each position of the wafer, the average flatness data value, the deviation rate thereof, etc. can be calculated based on the representative flatness data at each pixel, so that the characteristics of the wafer related to flatness can be evaluated more quickly and accurately.

[0089] The above flatness data may correspond to the total thickness variation of the wafer. The total thickness variation may be an indicator of the degree of roughness of one surface of the wafer. The total thickness variation may be calculated from the difference between the maximum thickness of the wafer and the minimum thickness of the wafer. Generally, the smaller the total thickness variation of the wafer, the lower the possibility of a defect in the wafer.

[0090]

[0091] The evaluation method according to the present invention includes a step (S40) of designating a plurality of areas within a radius of 50 mm based on the center of the wafer.

[0092] The above step S40 calculates the average value, the deviation rate, etc. from the flatness data that is evenly distributed across the entire area of ​​the wafer, rather than a specific area of ​​the wafer, thereby improving the accuracy of the evaluation for determining the presence or absence of a defect in the wafer using the flatness data. Accordingly, considering the typical size of wafers applied industrially, by designating multiple areas within a radius of 50 mm centered on the wafer, the speed and accuracy of the evaluation can be improved.

[0093] The above-described plurality of regions may be designated to be spaced apart from each other. Referring to FIG. 2, S1 to S7 represent the plurality of regions, and each of the regions S1 to S7 is spaced apart from each other. When the regions are designated to be spaced apart from each other as in S1 to S7, the reliability of the average value of the flatness data for each region, which may serve as an indicator of the flatness of the wafer, may be further improved.

[0094] One of the plurality of regions may include the center of the wafer. In addition, the plurality of regions may be designated to be symmetrically distributed based on the region including the center of the wafer. Generally, the height of the center of the wafer may be relatively higher than the height of the edge. Therefore, the difference between the flatness data at the center of the wafer and the flatness data at the edge of the wafer may be calculated to be the largest. Therefore, if the center of the wafer is included in the region designation, the evaluation reliability may be further improved.

[0095] The number of flatness data included in each of the above areas is not particularly limited, but is preferably 20 to 25 to improve the speed and accuracy of the evaluation.

[0096]

[0097] The evaluation method according to the present invention includes a step (S50) of calculating an overall average value of flatness data included in the plurality of areas, a step (S60) of calculating an area-specific average value of flatness data included in each area, and a step (S70) of calculating a flatness data deviation rate according to the following equation 1.

[0098] [Formula 1]

[0099] Flatness data deviation rate (%) = [(|X - Y|) / Y] ×100

[0100] In the above equation 1, X is the average value for each region, and Y is the overall average value.

[0101] Referring to FIG. 2, step S50 calculates the overall average value of the flatness data included in the S1 to S7 regions distributed over the entire area of ​​the wafer. For example, S1 to S7 include a total of 174 pixels, and include 174 flatness data such as 2.3755, 1.9736, etc. corresponding to the 174 pixels. The overall average value of the S1 to S7 regions is 2.3213, which is the average value of the 174 flatness data.

[0102] In this way, in the above step S50, the average value of the flatness data in the entire area from S1 to S7 can be calculated.

[0103] Also, referring to FIG. 2, step S60 calculates an average value of the flatness data of each of the S1 to S7 regions distributed over the entire area of ​​the wafer. For example, S7 includes 24 pixels and includes 24 flatness data such as 2.7024 and 2.6066 corresponding to the 24 pixels. In addition, S3 includes 25 pixels and includes 25 flatness data such as 2.0313 and 2.554 corresponding to the 25 pixels.

[0104] The average value of the flatness data of the above S7 is 2.55846, which is the average value of the above 24 flatness data. In addition, the average value of the above flatness data of the above S3 is 2.36565, which is the average value of the above 25 flatness data.

[0105] The above 2.55846 value may be an indicator of flatness data corresponding to the S7 region of the wafer, and the above 2.36565 value may be an indicator of flatness data corresponding to the S3 region of the wafer. In this way, in step S60, the average value of flatness data in each of the regions S1 to S7 may be calculated.

[0106] The above step S70 calculates a flatness data deviation rate using the overall average value of the flatness data included in the areas S1 to S7 and the average value of the flatness data in each area S1 to S7.

[0107] In the past, values ​​such as Total Thickness Variation (TTV), Bow (BOW), and Warp (WARP) were used to evaluate the flatness of a wafer after a CMP process or to evaluate the appropriateness of the CMP processing state. The total thickness variation (TTV), degree of warpage (BOW), and degree of warpage (WARP) of a wafer can be a measure for selecting a good wafer. However, the inventors of the present invention confirmed that even if the TTV, BOW, and WARP values ​​are not large, if the deviation of the flatness data of the wafer is large, the frequency of occurrence of triangular stacking defects, caret defects, and comet defects on the wafer after epitaxial growth may increase. In addition, the inventors devised a parameter of the flatness data deviation rate in order to easily select wafers with a high possibility of such defects.

[0108] For example, if the TTV for the wafers after the CMP process is measured and the TTV for the first wafer is 4 μm and the TTV for the second wafer is 5 μm, the first wafer can generally be selected as a good wafer compared to the second wafer.

[0109] However, by introducing the evaluation method according to the present invention, if the flatness data deviation rate of one of the designated areas in the first wafer is 40% and the flatness data deviation rate of one of the designated areas in the second wafer is 20%, the frequency of occurrence of defects in the first wafer selected as a good wafer according to the conventional method may increase compared to the second wafer.

[0110] That is, in order to determine whether a wafer is good quality after the CMP process, not only the TTV, BOW, and WARP values ​​that simply compare flatness using the maximum and minimum values ​​of the flatness data, but also the deviation rate of the flatness data calculated in each area of ​​the wafer must be considered.

[0111] Referring to FIGS. 3 and 6, the flatness data deviation rate means the ratio of the absolute value of the difference between the average value of the flatness data for each area of ​​S1 to S7 and the overall average value of the flatness data included in the areas of S1 to S7.

[0112] For example, the overall average value of the flatness data included in areas S1 to S7 of FIG. 3 is 4.570452. S1 includes 25 flatness data, and the average value of the flatness data in the S1 area is 4.347477. If the value derived in this way is substituted into Equation 1, the flatness data deviation rate of S1 is calculated as 5%, and by the same method, the flatness data deviation rates of S2, S3, S4, S5, S6, and S7 can be calculated as 7%, 6%, 6%, 2%, 8%, and 10%, respectively.

[0113] By the above method, the overall average value of the flatness data included in the S1 to S7 areas of Fig. 6 can be represented as 2.280197. In addition, by the same method, the flatness data deviation rates of 7% for S1, 10% for S2, 8% for S3, 6% for S4, 15% for S5, 5% for S6, and 50% for S7 can be calculated.

[0114] If, according to the conventional method, the overall average value of the flatness data of FIG. 3 is higher than the overall average value of the flatness data of FIG. 6, the wafer of FIG. 6 can be judged to be a good wafer.

[0115] However, according to the evaluation method of the present invention, the wafer of FIG. 3 has a flatness data deviation rate of up to 10%, and the wafer of FIG. 6 has a flatness data deviation rate of up to 50%, so it can be determined that the defect occurrence frequency of the wafer of FIG. 6 is increased compared to the wafer of FIG. 3.

[0116] The evaluation method according to the present invention may include a step (S71) of determining whether the wafer is of good quality based on the flatness data deviation rate according to the above formula 1.

[0117] A product can be judged as good if the flatness data deviation rate according to the above formula 1 is 15% or less.

[0118] Referring to FIGS. 3 and 7, the flatness data deviation rate of 15% or less means that the flatness data deviation rate in all areas from S1 to S7 satisfies 15% or less.

[0119] In the case of the wafer in Fig. 3, the flatness data deviation rate in all areas from S1 to S7 is 15% or less, so it can be judged as a good product.

[0120] In the case of the wafer in Fig. 7, the flatness data deviation rate of the S5 region is 16%, and the flatness data deviation rate of the S7 region is 36%, which does not meet the 15% or less requirement, and thus can be judged as a defective product.

[0121] The flatness data deviation rate according to the above formula 1 may be 1% or more and 15% or less. The lower the flatness data deviation rate, the higher the quality of the product is judged; however, it is more preferable to satisfy the above range in terms of efficiency of the manufacturing process.

[0122] The wafer according to the present invention satisfies the flatness data deviation rate of 15% or less according to the above equation 1 using the wafer evaluation method described above.

[0123] A wafer satisfying the above range can undergo epitaxial growth on the wafer surface through a post-process. The epitaxial growth means that a single crystal film with directionality is grown on the wafer surface.

[0124] After the above epitaxial growth, defects may occur, and the defects are related to the wafer flatness after the CMP process. The types of defects include triangular stacking defects, carrot defects, and comet defects. If the density of carrot defects is 1 / ㎠ or less, and the overall density of epitaxial defects is 2 / ㎠ or less, the wafer can be judged to be a good product.

[0125] That is, if the flatness data deviation rate according to the above formula 1 satisfies 15% or less after the CMP process, the wafer after the epitaxial growth has a carat defect density of 1 / cm2 or less, and the total epitaxial defect density satisfies 2 / cm2 or less, and thus can be judged as a good wafer.

[0126] In this way, the wafer evaluation method according to the present invention can quickly and accurately select wafers with a high possibility of defects after the CMP process.

[0127]

[0128] Hereinafter, the present invention will be described in more detail based on examples and comparative examples. However, the following examples and comparative examples are merely illustrative examples for further explaining the present invention, and the present invention is not limited to the following examples and comparative examples.

[0129]

[0130] Example - Preparation of silicon carbide wafers

[0131] Example 1

[0132] After mounting a polishing pad on a platen of a polishing device (CTS AP300), dressing of the polishing pad was performed under a rotation speed of the platen of about 125 rpm, a rotation speed of the conditioner (CI 45) of about 135 rpm, and a vibration speed of the conditioner of about 28 times / min.

[0133] Afterwards, the surface of the polishing head of the polishing equipment was cleaned for about 120 seconds using a cleaning solution, and the surface of a silicon carbide wafer (SiC wafer) was cleaned using ultrasonic waves of about 133 kHz.

[0134] Thereafter, after mounting the silicon carbide wafer surface on the polishing head, a silicon carbide wafer subjected to a CMP (Chemical Mechanical Polishing) process was manufactured under conditions such that the polishing pad was maintained at a temperature range of 45 to 55 degrees under conditions such as a rotation speed of the platen of about 145 rpm, a rotation speed of the polishing head of about 75 rpm, a pressurized load of the polishing head against the polishing pad of about 5 psi, and a slurry (KMnO4) injection flow rate of 200 ml / min.

[0135]

[0136] Example 2

[0137] In the above Example 1, when dressing the polishing pad, a silicon carbide wafer was manufactured by the same process as Example 1, except that the conditioner (CI 45) was rotated at a rotation speed of about 140 rpm and the conditioner was rotated at a vibration speed of about 25 times / min instead of a rotation speed of about 135 rpm and a vibration speed of about 28 times / min.

[0138]

[0139] Example 3

[0140] When performing the CMP process in Example 1, a silicon carbide wafer was manufactured by the same process as Example 1, except that the process was performed at a rotation speed of about 140 rpm of the platen and a rotation speed of about 80 rpm of the polishing head instead of a rotation speed of about 145 rpm of the platen and a rotation speed of about 75 rpm of the polishing head.

[0141]

[0142] Comparative Example 1

[0143] When performing the CMP process in Example 1, a silicon carbide wafer was manufactured by the same process as Example 1, except that instead of performing the CMP process under the conditions of a pressurized load of 5 psi for the polishing pad, a slurry injection flow rate of 200 ml / min, and a temperature range of 45 to 55 degrees for the polishing pad, the process was performed under the conditions of a pressurized load of 3 psi for the polishing pad, a slurry injection flow rate of 100 ml / min, and a temperature range of 40 to 45 degrees for the polishing pad.

[0144]

[0145] Comparative Example 2

[0146] A silicon carbide wafer was manufactured by the same process as Example 1, except that dressing of the polishing pad was not performed in Example 1.

[0147]

[0148] Comparative Example 3

[0149] After dressing the polishing pad in Example 1, a silicon carbide wafer was manufactured by the same process as Example 1, except that the process of washing the polishing head surface and the silicon carbide wafer surface was not performed.

[0150]

[0151] Experimental example

[0152] Experimental Example 1 - Evaluation of Silicon Carbide Wafer Flatness Uniformity

[0153] For each of the silicon carbide wafers manufactured in Examples 1 to 3 and Comparative Examples 1 to 3, a flatness image of the silicon carbide wafer was output using a laser interferometer (Corning Tropel, Flatmaster 200 XRA, TMS Plot program).

[0154] Afterwards, from the TMS Plot program, the output image was pixelized 16 times, flatness data corresponding to each pixel was calculated, and 7 areas within a radius of 50 mm were designated based on the center of the silicon carbide wafer.

[0155] In FIGS. 2 to 4, flatness data and seven regions within a radius of 50 mm are shown for the silicon carbide wafers of Examples 1 to 3. In addition, in FIGS. 5 to 7, flatness data and seven regions within a radius of 50 mm are shown for the silicon carbide wafers of Comparative Examples 1 to 3.

[0156] Thereafter, using the above flatness data, the average value of the overall flatness data of the seven regions and the average value of the flatness data for each of the seven regions were calculated, and the flatness data deviation rate (%) was calculated according to Equation 1 below. The results are shown in Table 1 below.

[0157] [Formula 1]

[0158] Flatness data deviation rate (%) = [(|X - Y|) / Y] ×100

[0159] In the above equation 1, X is the average value of the flatness data for each of the seven regions, and Y is the average value of the overall flatness data for the seven regions.

[0160]

[0161] Experimental Example 2 - Quality Evaluation of Silicon Carbide Wafers

[0162] Epitaxial growth was performed on each of the silicon carbide wafers manufactured in Examples 1 to 3 and Comparative Examples 1 to 3. Each of the silicon carbide wafers was introduced into a growth furnace, and the inside of the growth furnace was evacuated, and then H2 gas was injected at a rate of 130 L / min while maintaining a pressure of 1.3 × 10 4 It was maintained at ㎩.

[0163] Thereafter, the temperature of the growth furnace was increased to 1,620°C, and SiH4 gas was injected at a rate of 40 cm3 / min, C2H4 gas at a rate of 20 cm3 / min, and N2 gas at a rate of 1 cm3 / min, thereby forming an epitaxial layer of approximately 10 μm in thickness. Thereafter, the temperature of the growth furnace was lowered to room temperature, and the pressure was changed to atmospheric pressure, thereby manufacturing a silicon carbide wafer having an epitaxial layer formed thereon.

[0164] For the epitaxial film manufactured above, the carrot defect density and the total epitaxial defect density were measured using a confocal laser scanning microscope, and the quality of the silicon carbide wafer was evaluated according to the following criteria. The results are shown in Table 1 below.

[0165] - ◎: ​​Carat defect density of 1 / ㎠ or less and total epitaxial defect density of 2 / ㎠ or less

[0166] - Δ: Carat defect density of 1 / ㎠ or less or total epitaxial defect density of 2 / ㎠ or less

[0167] - Х: Carat defect density exceeds 1 / cm2 and total epitaxial defect density exceeds 2 / cm2

[0168]

[0169] Unit Example 1 Example 2 Example 3 Comparative Example 1 Comparative Example 2 Comparative Example 3 S1 1) ㎛2.453274.3474774.4224733.463282.1203353.906623S2 2) 2.048754.2496274.0278773.266792.04513.674865S3 3) 2.365654.8494924.9940124.408232.104453.869777S4 4) 1.976254.8664124.6649234.438412.1396153.764508S5 5) 2.287084.4604654.5163653.920951.9458153.329373S6 6) 2.559654.1889424.5796773.867332.1761273.680915S7 7) 2.558465.0307524.1543124.662383.429945.366236S a 8) 2.32134.5704524.4799484.003912.2801973.941757S1 d 9) %6511471S2 d 10) 1271018107S3 d 11) 26111082S4 d 12) 15641164S5 d 13) 12121516S6 d 14) 1082357S7 d 15)10107165036 Quality Evaluation - ◎◎◎ΔХХ1) S1: Average flatness data of the S1 region in Figs. 2 to 72) S2: Average flatness data of the S2 region in Figs. 2 to 73) S3: Average flatness data of the S3 region in Figs. 2 to 74) S4: Average flatness data of the S4 region in Figs. 2 to 75) S5: Average flatness data of the S5 region in Figs. 2 to 76) S6: Average flatness data of the S6 region in Figs. 2 to 77) S7: Average flatness data of the S7 region in Figs. 2 to 78) S a : Average value of overall flatness data in areas S1 to S79) S1 d : [(|S1 - S a |) / S a ] Х10010) S2 d : [(|S2 - S a |) / S a ] Х10011) S3 d : [(|S3 - S a |) / S a ] Х10012) S4 d : [(|S4 - S a |) / S a ] Х10013) S5 d : [(|S5 - S a |) / S a ] Х10014) S6 d : [(|S6 - S a |) / S a ] Х10015) S7 d : [(|S7 - S a |) / S a ] Х100

[0170]

[0171] Looking at Table 1 above, in the case of Examples 1 to 3, where the flatness data deviation rates of S1 to S7 are all 15% or less, the wafers can be judged to be of good quality, as they exhibit lower defects compared to Comparative Examples 1 to 3.

[0172] In this way, the wafer evaluation method according to the present invention provides a parameter of a flatness data deviation rate by which the presence or absence of a defect in a wafer can be predicted, so that wafers with a high probability of defects after a CMP process can be quickly sorted out, and it was confirmed that the accuracy of the evaluation for sorting out wafers with a high probability of defects is also excellent.

[0173]

[0174] The embodiment can be applied to a wafer evaluation method and a wafer using the same.

Claims

1. Step of preparing the wafer to be evaluated; A step of outputting a flatness image of the wafer using an optical member; A step of pixelating the above flatness image and calculating flatness data corresponding to each pixel; A step of designating multiple areas within a radius of 50 mm based on the center of the wafer; A step of calculating an overall average value of the flatness data included in the above multiple areas; A step of calculating the average value of each area of ​​the flatness data included in each of the above areas; and A wafer evaluation method comprising the step of calculating a flatness data deviation rate according to the following equation 1: [Formula 1] Flatness data deviation rate (%) = [(|X - Y|) / Y] ×100 In the above equation 1, X is the average value for each region, and Y is the overall average value.

2. In paragraph 1, A wafer evaluation method wherein the above wafer is a silicon carbide wafer.

3. In paragraph 1, A wafer evaluation method wherein the above wafer is a product that has undergone a chemical mechanical polishing process.

4. In paragraph 1, A wafer evaluation method wherein the flatness image of the above wafer is output using an interferometer of a laser coming from a light source of the above optical member.

5. In paragraph 1, A wafer evaluation method wherein the above flatness data corresponds to the total thickness variation of the wafer.

6. In paragraph 1, A wafer evaluation method wherein the above plurality of areas are designated to be spaced apart from each other.

7. In paragraph 1, A wafer evaluation method, wherein one of the plurality of regions includes the center of the wafer.

8. In paragraph 7, A wafer evaluation method wherein the plurality of regions are designated to be symmetrically distributed based on a region including the center of the wafer.

9. In paragraph 1, A wafer evaluation method wherein the flatness data included in each of the above areas is 20 to 25.

10. In paragraph 1, A wafer evaluation method in which a wafer having a flatness data deviation rate of 15% or less according to the above formula 1 is judged to be a good product.

11. In paragraph 10, A wafer evaluation method wherein a wafer having a flatness data deviation rate of 1% or more and 15% or less according to the above formula 1 is judged to be a good product.

12. A wafer that satisfies the flatness data deviation rate of 15% or less according to the above formula 1 using the wafer evaluation method according to Article 1.

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