Display panel and display apparatus thereof

Abstract

A display panel and a display apparatus thereof. The display panel comprises a base substrate (100), pixel driving units (10) and a color filter substrate (200), wherein the base substrate (100) comprises a display area (AA), the display area (AA) comprises a plurality of sub-pixels, and the plurality of sub-pixels include first sub-pixels (spx1) and edge virtual sub-pixels (spx2), at least one row of sub-pixels having at least one edge virtual sub-pixel (spx2), and at least one column of sub-pixels having at least one edge virtual sub-pixel (spx2); the pixel driving units (10) are configured to drive the first sub-pixel (spx1) to display a picture; the color filter substrate (200) comprises a black matrix layer (20) and a color resist layer (30), which are formed on the color filter substrate (200); the black matrix layer (20) is provided with a plurality of opening regions (K1); the orthographic projections of a first color resist layer (31), a second color resist layer (32) and a third color resist layer (33) on the color filter substrate (200) overlap the orthographic projections of the opening regions (K1) on the color filter substrate (200); the orthographic projections, on the base substrate (100), of the pixel driving units (10) arranged corresponding to the edge virtual sub-pixels (spx2) do not overlap the orthographic projections of the first color resist layer (31), the second color resist layer (32) and the third color resist layer (33) on the base substrate (100); and the orthographic projections, on the base substrate (100), of the pixel driving units (10) arranged corresponding to the edge virtual sub-pixels (spx2) do not overlap the orthographic projections of the opening regions (K1) on the base substrate (100).

Description

Display panel and display device thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device thereof. Background Art

[0002] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide scanning signals for multiple rows of gate lines in a pixel array, so as to control the multiple rows of gate lines to open in sequence, and at the same time, the data lines provide data signals to the pixel units of the corresponding rows in the pixel array to form the grayscale voltage required for each grayscale of the displayed image in each pixel unit, thereby displaying a frame of image. Current display panels are increasingly using GOA technology to drive the gate lines. GOA technology helps to achieve a narrow frame design for the display panel and can reduce the production cost of the display panel.

[0003] Summary of the Invention

[0004] The display panel provided by the embodiment of the present disclosure includes:

[0005] A base substrate, comprising a display area and a non-display area;

[0006] The display area includes a plurality of sub-pixels; the plurality of sub-pixels include first sub-pixels and edge virtual sub-pixels; at least one row of the sub-pixels includes at least one edge virtual sub-pixel, and at least one column of the sub-pixels includes at least one edge virtual sub-pixel;

[0007] a plurality of pixel driving units, provided in one-to-one correspondence with the first sub-pixels and the edge virtual sub-pixels; wherein the pixel driving units are configured to drive the first sub-pixels to display a picture;

[0008] A color filter substrate, comprising a black matrix layer and a color resist layer formed on the color filter substrate; the black matrix layer having a plurality of opening areas; the color resist layer comprising a plurality of first color resist layers, a plurality of second color resist layers, and a plurality of third color resist layers; the orthographic projections of the first color resist layers, the second color resist layers, and the third color resist layers on the color filter substrate overlap with the orthographic projections of the opening areas on the color filter substrate;

[0009] The orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the base substrate does not overlap with the orthographic projection of the first color resist layer, the second color resist layer, and the third color resist layer on the base substrate; the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the base substrate does not overlap with the orthographic projection of the opening area on the base substrate.

[0010] In some possible embodiments, the edge virtual sub-pixels in the same column of sub-pixels are closer to the corner edge of the display area in the first direction than the first sub-pixel; the edge virtual sub-pixels in the same row of sub-pixels are closer to the corner edge of the display area in the second direction than the first sub-pixel.

[0011] In some possible implementations, the number of the opening areas in each column and the number of the opening areas in each row decreases in a direction approaching a corner edge of the display area;

[0012] The color resist layer includes a plurality of color resist units, each of which includes: the first color resist layer, the second color resist layer, and the third color resist layer; wherein the first color resist layer, the second color resist layer, and the third color resist layer in each color resist unit have the same orthographic projection on the base substrate;

[0013] The area of ​​each color resist unit gradually decreases in a direction approaching a corner edge of the display area.

[0014] In some possible implementations, the pixel driving unit includes: a first sub-driving unit, and / or a second sub-driving unit;

[0015] The first sub-driving unit includes a first driving transistor; a gate of the first driving transistor is coupled to a gate line, a first electrode of the first driving transistor is coupled to a data line, and a second electrode of the first driving transistor is coupled to a pixel electrode.

[0016] The second sub-driving unit includes a second driving transistor; a gate of the second driving transistor is coupled to the gate line, a first electrode of the second driving transistor is coupled to the data line, and a second electrode of the second driving transistor is coupled to the pixel electrode;

[0017] The pixel driving units have the same shape as the orthographic projections on the base substrate.

[0018] In some possible embodiments, a plurality of sub-pixels near the corner edge of the display area are arranged in a stepped manner to form a multi-level pixel ladder, and each level of the pixel ladder is composed of at least one sub-pixel; in some of the pixel ladders, at least one edge virtual sub-pixel is provided for every other level of the pixel ladder.

[0019] In some possible implementations, the substrate further includes: a plurality of cascaded shift register units, a plurality of anti-static units, and at least one common electrode line; wherein each stage of the shift register units corresponds to a row of the sub-pixels;

[0020] The orthographic projection of the anti-static unit on the substrate and the orthographic projection of the cascaded shift register unit on the substrate are respectively located on different sides of the orthographic projection of the common electrode line on the substrate; the orthographic projection of the anti-static unit on the substrate is located between the orthographic projection of the common electrode line on the substrate and the orthographic projection of the sub-pixel on the substrate;

[0021] The sub-pixels in each level of the pixel ladder are respectively electrically connected to at least one of the anti-static units; the anti-static units are located at the ends of the pixel ladder in the first direction and between at most two rows of sub-pixels in the second direction.

[0022] In some possible implementations, the anti-static unit corresponding to the n-th pixel ladder is located at the end of the n-th pixel ladder in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0023] In some possible implementations, the anti-static unit corresponding to the nth pixel ladder is located at the end of the n+ith pixel ladder in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0024] In some possible embodiments, the anti-static unit corresponding to the n-th level pixel ladder includes a first anti-static unit located at the end of the n-th level pixel ladder in the first direction and a first anti-static unit located at the end of the n+i-th level pixel ladder in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0025] In some possible implementations, the base substrate further includes: a plurality of data conduction signal lines; the sub-pixels in each level of the pixel ladder are connected to the corresponding anti-static units via the data conduction signal lines;

[0026] The data conduction signal lines are arranged in an S shape, and / or a zigzag shape, and / or a lightning shape.

[0027] In some possible implementations, the shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0028] The first transistor and the second transistor are arranged opposite to each other along the first direction; the third transistor and the fourth transistor are arranged opposite to each other along the first direction; the orthographic projections of the third transistor and the fourth transistor on the substrate are located between the orthographic projections of the first transistor and the fifth transistor on the substrate; the sixth transistor and the seventh transistor are arranged opposite to each other along the first direction; the orthographic projections of the eighth transistor, the ninth transistor, and the tenth transistor on the substrate are arranged in sequence along the second direction;

[0029] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor each include a plurality of active layers; the plurality of active layers are spaced apart from each other along the second direction; and a spacing between the plurality of active layers along the second direction is no greater than 3 micrometers;

[0030] The width of the plurality of active layers along the second direction is no greater than 5 micrometers.

[0031] In some possible implementations, the non-display area includes: a silver paste area, a data fan-out line area, and a GOA signal line area;

[0032] The data fan-out line area is located between the display area and the GOA signal line area, the GOA signal line area is located between the data fan-out line area and the silver paste area, and the data fan-out line area is adjacent to the GOA signal line area;

[0033] The data fan-out signal line includes: a first extension line and a first lifting line;

[0034] The angle between the first extension line and the first lifting line is a first angle.

[0035] In some possible implementations, the first angle is between 20 degrees and 35 degrees.

[0036] In some possible implementations, the GOA signal line area includes a plurality of GOA signal lines; wherein the GOA signal lines include: a second extension line and a second lifting line;

[0037] The second extension line is arranged in parallel with the first extension line, and the second lifting line is arranged in parallel with the first lifting line.

[0038] In some possible embodiments, the starting end of the data fan-out signal line is located on the lower side of the anti-static unit; the data fan-out signal line includes a first sub-data fan-out signal line and a second sub-data fan-out signal line, wherein the extension direction of the starting end of the first sub-data fan-out signal line and the second direction have an angle not equal to 90 degrees, and / or the extension direction of the starting end of the second sub-data fan-out signal line extends along the first direction.

[0039] In some possible implementations, an orthographic projection of the first sub-data fan-out signal line on the base substrate is closer to the display area than an orthographic projection of the second sub-data fan-out signal line on the base substrate.

[0040] In some possible implementations, the following further comprises:

[0041] A gate conductive layer is located on the substrate;

[0042] a gate insulating layer, located on a side of the gate conductive layer facing away from the substrate;

[0043] a semiconductor layer, located on a side of the gate insulating layer away from the substrate; the semiconductor layer includes a plurality of active layers;

[0044] an etch stop layer, located on a side of the semiconductor layer facing away from the substrate;

[0045] The source and drain layer is located on the side of the etch stop layer away from the substrate, and includes a data line, a data fan-out line, a GOA signal line, and a data conduction signal line;

[0046] a first insulating layer, located on a side of the source / drain layer facing away from the substrate;

[0047] a common electrode layer, located on a side of the first insulating layer facing away from the base substrate;

[0048] a second insulating layer, located on a side of the common electrode layer facing away from the base substrate;

[0049] The pixel electrode layer is located on a side of the second insulating layer away from the base substrate.

[0050] In some possible implementations, the device further includes: a plurality of transfer units; the transfer units include a first transfer hole and a second transfer hole; wherein the first transfer hole exposes the gate conductive layer, and the second transfer hole exposes the source and drain layer;

[0051] The pixel electrode layer is connected to the gate conductive layer via the first transfer hole and is connected to the source and drain layer via the second transfer hole.

[0052] In some possible implementations, the switching unit is further configured to connect a GOA signal line and a shift register unit, and / or the switching unit is located within the shift register unit.

[0053] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a schematic diagram of some structures of a display panel according to an embodiment of the present disclosure;

[0055] FIG2 is a schematic diagram of another structure of a display panel in an embodiment of the present disclosure;

[0056] FIG3 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0057] FIG4 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0058] FIG5 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0059] FIG6 is a schematic diagram of some structures of the color resist unit in an embodiment of the present disclosure;

[0060] FIG7 is a schematic diagram of some structures of a pixel driving unit in an embodiment of the present disclosure;

[0061] FIG8 is a schematic diagram of other structures of a pixel driving unit in an embodiment of the present disclosure;

[0062] FIG9 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0063] FIG10 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0064] FIG11 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0065] FIG12 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0066] FIG13 is a schematic diagram of some structures of a shift register in an embodiment of the present disclosure;

[0067] FIG14 is some equivalent circuit diagrams of the shift register in the embodiment of the present disclosure;

[0068] FIG15 is another schematic diagram of the structure of the shift register in the embodiment of the present disclosure;

[0069] FIG16 is a schematic diagram of some further structures of the shift register in the embodiment of the present disclosure;

[0070] FIG17 is a schematic diagram of some further structures of the shift register in the embodiment of the present disclosure;

[0071] FIG18 is a schematic diagram of some further structures of the shift register in the embodiment of the present disclosure;

[0072] FIG19 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0073] FIG20 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0074] FIG21 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0075] FIG22 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0076] FIG23 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0077] FIG24 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0078] FIG25 is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0080] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0081] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0082] In some embodiments of the present disclosure, the display device may include a display panel and a timing controller. The display panel may include a substrate (i.e., an array substrate), and the substrate may include a display area and a non-display area. The display area may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of multiple different colors. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0083] In some embodiments of the present disclosure, the display area may further include multiple gate lines and multiple data lines. Each sub-pixel may include a transistor and a pixel electrode. Among them, a row of sub-pixels corresponds to a gate line, and a column of sub-pixels corresponds to a data line. The gate of the transistor is coupled to the corresponding gate line, the source of the transistor is coupled to the corresponding data line, and the drain of the transistor is coupled to the pixel electrode. It should be noted that the pixel array structure of the present disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, some data lines are included between two adjacent columns of pixels, and some data lines are not included between two adjacent columns of pixels. The specific pixel arrangement structure and data lines, and the arrangement of the gate lines are not limited.

[0084] In some embodiments of the present disclosure, the non-display area may include a gate drive circuit and a source drive circuit. The gate drive circuit is coupled to the gate line, and the source drive circuit is coupled to the data line. In addition, the timing controller may be coupled to the gate drive circuit and the source drive circuit, respectively. Generally, the gate drive circuit is arranged in the non-display area on the left and right sides of the display panel. For example, the timing controller can obtain the display data of the picture to be displayed in the current display frame, and the timing controller can input a control signal to the gate drive circuit so that the gate drive circuit can output a gate scan signal to each gate line according to the input control signal, thereby driving each gate line to control the transistor conduction in the coupled sub-pixel. In addition, the timing controller inputs the acquired display data to the source drive circuit so that the source drive circuit can input a data voltage to the coupled data line according to the input display data, thereby inputting the voltage on the data line into the sub-pixel through the turned-on transistor to charge the sub-pixel, thereby charging each sub-pixel with the corresponding data voltage to realize the picture display function.

[0085] It should be noted that the display panel in the embodiment of the present disclosure may be a liquid crystal display panel. Exemplarily, the liquid crystal display panel generally includes an upper substrate (e.g., a color filter substrate) and a lower substrate (e.g., a substrate substrate) of the pair of boxes, and liquid crystal molecules encapsulated between the upper substrate (e.g., a color filter substrate) and the lower substrate (e.g., a substrate substrate). When displaying a picture, since there is a voltage difference between the data voltage loaded on the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode, the voltage difference can form an electric field, thereby causing the liquid crystal molecules to deflect under the action of the electric field. Due to different intensities of electric fields, the degree of deflection of the liquid crystal molecules is different, resulting in different transmittances of the sub-pixels, so that the sub-pixels achieve different grayscale brightness, thereby realizing picture display. Of course, the display panel in the embodiment of the present disclosure may also be an OLED display panel, which is not limited here.

[0086] The present disclosure provides a display panel, as shown in FIG1 to FIG5 , including:

[0087] The base substrate 100 includes a display area AA and a non-display area BB;

[0088] The display area AA includes a plurality of sub-pixels; the plurality of sub-pixels include a first sub-pixel spx1 and an edge virtual sub-pixel spx2; at least one row of sub-pixels includes at least one edge virtual sub-pixel spx2, and at least one column of sub-pixels includes at least one edge virtual sub-pixel spx2;

[0089] A plurality of pixel driving units 10 are provided in one-to-one correspondence with the first sub-pixel spx1 and the edge virtual sub-pixel spx2; wherein the pixel driving unit 10 is configured to drive the first sub-pixel spx1 to display a picture;

[0090] The color filter substrate 200 includes a black matrix layer 20 and a color resist layer 30 formed on the color filter substrate 200; the black matrix layer 20 has a plurality of opening areas K1; the color resist layer 30 includes a plurality of first color resist layers 31, a plurality of second color resist layers 32, and a plurality of third color resist layers 33; the orthographic projections of the first color resist layers 31, the second color resist layers 32, and the third color resist layers 33 on the color filter substrate 200 overlap with the orthographic projections of the opening areas K1 on the color filter substrate 200;

[0091] The orthographic projection of the pixel driving unit 10 corresponding to the edge virtual sub-pixel spx2 on the base substrate 100 does not overlap with the orthographic projections of the first color resist layer 31, the second color resist layer 32, and the third color resist layer 33 on the base substrate 100; the orthographic projection of the pixel driving unit 10 corresponding to the edge virtual sub-pixel spx2 on the base substrate 100 does not overlap with the orthographic projection of the opening area K1 on the base substrate 100.

[0092] In the embodiment of the present disclosure, the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; and the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate does not overlap with the orthographic projection of the opening area on the substrate; thereby, the normal display of the display panel is not affected, the space utilization is improved, and the requirement of a narrow bezel of the display panel is met.

[0093] Exemplarily, the orthographic projection of some pixel driving units on the substrate does not overlap with the orthographic projection of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate; the orthographic projection of some pixel driving units on the substrate does not overlap with the orthographic projection of the opening area on the substrate; the orthographic projection of the black matrix layer on the substrate overlaps with the orthographic projection of some pixel driving units on the substrate.

[0094] Exemplarily, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, wherein the orthographic projections of the red sub-pixel, green sub-pixel and blue sub-pixel in the pixel unit on the substrate are the same, and the areas of the opening regions corresponding to the red sub-pixel, green sub-pixel and blue sub-pixel are the same; or, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, wherein the orthographic projections of the red sub-pixel, green sub-pixel, blue sub-pixel and white sub-pixel in the pixel unit on the substrate are the same, and the areas of the opening regions corresponding to the red sub-pixel, green sub-pixel, blue sub-pixel and white sub-pixel are the same.

[0095] In some embodiments of the present disclosure, as shown in Figures 1 and 2, the edge virtual sub-pixel spx2 in the same column of sub-pixels is closer to the corner edge FA1 of the display area than the first sub-pixel spx1 in the first direction F1; the edge virtual sub-pixel spx2 in the same row of sub-pixels is closer to the corner edge FA1 of the display area than the first sub-pixel spx1 in the second direction F2.

[0096] Exemplarily, the edge virtual sub-pixel spx2 in the same column of sub-pixels is aligned with the first sub-pixel spx1 along the first direction F1; the edge virtual sub-pixel spx2 in the same row of sub-pixels is aligned with the first sub-pixel spx1 along the second direction F2.

[0097] In some embodiments of the present disclosure, as shown in Figures 4 to 6, the number of opening areas K1 in each column and the number of opening areas K1 in each row decrease in a direction approaching the corner edge FA1 of the display area; wherein, the color resist layer 30 includes a plurality of color resist units 3, and each color resist unit 3 includes: a first color resist layer 31, a second color resist layer 32, and a third color resist layer 33; wherein, the orthographic projections of the first color resist layer 31, the second color resist layer 32, and the third color resist layer 33 in each color resist unit 3 on the base substrate are the same; wherein, the area of ​​each color resist unit 3 gradually decreases in a direction approaching the corner edge FA1 of the display area.

[0098] Exemplarily, the opening area is arranged corresponding to multiple color resist units, and the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer in each color resist unit on the base substrate overlap with the orthographic projection of the opening area on the base substrate; and the orthographic projections of the opening area corresponding to the first color resist layer, the opening area corresponding to the second color resist layer, and the opening area corresponding to the third color resist layer in the color resist unit on the base substrate are the same; that is, the area and shape of the opening area corresponding to the first color resist layer, the opening area corresponding to the second color resist layer, and the opening area corresponding to the third color resist layer in the color resist unit are substantially the same.

[0099] Exemplarily, as shown in FIG. 4 , the area of ​​each column of the opening region K1 and the area of ​​each row of the opening region K1 gradually decrease in a direction approaching the corner edge FA1 of the display area AA.

[0100] In some embodiments of the present disclosure, as shown in Figure 7, the pixel driving unit 10 includes: a first sub-driving unit 11; the first sub-driving unit 11 includes a first driving transistor T1; wherein the gate of the first driving transistor T1 is coupled to the gate line GA, the first electrode of the first driving transistor T1 is coupled to the data line DA, and the second electrode of the first driving transistor T1 is coupled to the pixel electrode PE.

[0101] Illustratively, the embodiment of the present disclosure enables the pixel driving unit to include only the first sub-driving unit, thereby further reducing space occupancy and saving space, thereby better achieving a narrow frame.

[0102] In some embodiments of the present disclosure, as shown in FIG8 , the pixel driving unit 10 includes: a first sub-driving unit 11 and a second sub-driving unit 12; the second sub-driving unit 12 includes a second driving transistor T2; wherein the gate of the first driving transistor T1 is coupled to the gate line GA, the first electrode of the first driving transistor T1 is coupled to the data line DA, and the second electrode of the first driving transistor T1 is coupled to the pixel electrode PE; the gate of the second driving transistor T2 is coupled to the gate line GA, the first electrode of the second driving transistor T2 is coupled to the data line DA, and the second electrode of the second driving transistor T2 is coupled to the pixel electrode PE; the shape of the orthographic projection of the pixel driving unit 10 on the substrate 100 is the same. For example, generally in the case of a dual-rate drive (Dual-Rate) In a display panel using the Digital Driving (DRD) technology, the sub-pixels on the base substrate are designed to form a pixel unit with two sub-pixels in a group; and the color resist layer on the opposite substrate is designed to form a color resist unit with three color resist layers in a group; wherein each color resist layer corresponds to one sub-pixel; in the prior art, in order to ensure the correspondence between the color resist layers and the sub-pixels and to ensure that the arrangement design is relatively simple, the design is usually based on the least common multiple of the number of sub-pixels in each pixel unit and the number of color resist layers in each color resist unit; that is, the array is arranged in groups of six sub-pixels and in groups of six color resist layers; such a design is relatively simple and easy to arrange, but it will have a relatively large impact on the corner area of ​​the display panel (such as the R corner area, the R corner is the rounded corner of the arc tangent to two intersecting straight lines, for example, the R corner is the rounded corner of the arc tangent to the long side of the display panel and the short side of the display panel.), that is, the border of the corner area of ​​the display panel will become larger, affecting the aesthetics and the realization of a narrow border.

[0103] In the embodiment of the present disclosure, the pixel driving unit includes a first sub-driving unit and / or a second sub-driving unit, wherein each of the first sub-driving unit and the second sub-driving unit corresponds to a sub-pixel setting respectively; the arrangement of the pixel driving unit in an array is equivalent to the arrangement of the sub-pixels in an array; when the pixel driving unit includes only the first sub-driving unit or the second sub-driving unit, the array arrangement design is performed with one sub-pixel as a group; when the pixel driving unit includes the first sub-driving unit and the second sub-driving unit, the array arrangement design is performed with two sub-pixels as a group; in the present disclosure, by setting edge virtual sub-pixels in the border or corner area, the number of sub-pixels arranged in the array can be reduced, and the number of sub-pixels close to the border position can be more easily controlled, thereby facilitating the realization of a narrow border.

[0104] In some embodiments of the present disclosure, as shown in Figures 9 to 12, multiple sub-pixels spx near the corner edges of the display area are arranged in a stepped manner to form a multi-level pixel ladder (for example, J1, J2, J3, J4, J5, J6 in Figure 12), and each level of pixel ladder (for example, J1, J2, J3, J4, J5, J6 in Figure 12) is composed of at least one sub-pixel spx; in some pixel ladders (for example, J10, J11, J12, J13, J14, J15, J16 in Figure 9), at least one edge virtual sub-pixel (for example, spx2_10, spx2_12, spx2_14, spx2_16 in Figure 9) is provided for every other level of pixel ladder.

[0105] For example, as shown in FIG9 , the pixel step J10 is correspondingly provided with an edge virtual sub-pixel spx2_10; the pixel step J12 is correspondingly provided with an edge virtual sub-pixel spx2_12; the pixel step J14 is correspondingly provided with an edge virtual sub-pixel spx2_14; the pixel step J16 is correspondingly provided with an edge virtual sub-pixel spx2_16; wherein, the pixel step J10 and the pixel step J12 are separated by one pixel step J11; the pixel step J12 and the pixel step J14 are separated by one pixel step J13; the pixel step The ladder J14 is separated from the pixel ladder J16 by one pixel ladder J15; exemplarily, as shown in FIG9 , the edge virtual sub-pixel spx2_10 is located at the end of the pixel ladder J10 close to the common electrode line 50; the edge virtual sub-pixel spx2_12 is located at the end of the pixel ladder J12 close to the common electrode line 50; the edge virtual sub-pixel spx2_14 is located at the end of the pixel ladder J14 close to the common electrode line 50; the edge virtual sub-pixel spx2_14 is located at the end of the pixel ladder J14 close to the common electrode line 50.

[0106] In some embodiments of the present disclosure, as shown in FIG9 to FIG12 , the substrate 100 further includes: a plurality of cascaded shift register units 40 , a plurality of anti-static units ESD, and at least one common electrode line 50 ; wherein each stage of the shift register unit 40 corresponds to a row of sub-pixels spx;

[0107] The orthographic projection of the anti-static unit ESD on the substrate 100 and the orthographic projection of the cascaded shift register unit 40 on the substrate 100 are respectively located on different sides of the orthographic projection of the common electrode line 50 on the substrate 100; the orthographic projection of the anti-static unit ESD on the substrate 100 is located between the orthographic projection of the common electrode line 50 on the substrate 100 and the orthographic projection of the sub-pixel spx on the substrate 100;

[0108] The sub-pixels spx in each level of pixel ladder (for example, J1, J2, J3, J4, J5, and J6 in Figure 12) are respectively electrically connected to at least one anti-static unit ESD; the anti-static unit ESD is located at the end of the pixel ladder (for example, J1, J2, J3, J4, J5, and J6 in Figure 12) in the first direction F1, and the anti-static unit ESD is located between at most two rows of sub-pixels spx in the second direction F2.

[0109] For example, as shown in Figures 11 and 12, the anti-static unit ESD1 is located at the end of the pixel ladder J2 in the first direction F1, and the anti-static unit ESD2 is located at the end of the pixel ladder J4 in the first direction F1; the anti-static unit ESD3 is located at the end of the pixel ladder J6 in the first direction F1; the anti-static unit ESD1, the anti-static unit ESD2 and the anti-static unit ESD3 have two upper and lower edges in the second direction F2, and the distance between the two edges does not exceed two rows of sub-pixels; that is, the width of the orthographic projection of the anti-static unit ESD1, the anti-static unit ESD2 and the anti-static unit ESD3 on the substrate along the first direction F1 is less than the width of the orthographic projection of the two rows of sub-pixels on the substrate along the first direction F1.

[0110] In some embodiments of the present disclosure, as shown in FIG9 to FIG12, the substrate 100 further includes: a plurality of data conduction signal lines (for example, 51 in FIG10, 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 in FIG12); the sub-pixels spx in each level of pixel ladder (for example, J1, J2, J3, J4, J5, and J6 in FIG12) are connected to each other through the data conduction signal lines (for example, 51 in FIG10, 12) are connected to corresponding anti-static units (e.g., ESD in FIG10, ESD1, ESD2, ESD3 in FIG11); wherein, the data conduction signal lines (e.g., 51-1, 51-2, 51-3, 51-4, 51-5, 51-6 in FIG12) are arranged in an S shape, and / or a broken line shape, and / or a lightning shape.

[0111] In some embodiments of the present disclosure, the anti-static unit corresponding to the n-th level pixel step is located at the end of the n-th level pixel step in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0112] In some embodiments of the present disclosure, the anti-static unit corresponding to the nth level pixel ladder is located at the end of the n+ith level pixel ladder in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0113] In some embodiments of the present disclosure, the anti-static unit corresponding to the n-th level pixel ladder includes a first anti-static unit located at the end of the n-th level pixel ladder in the first direction and a first anti-static unit located at the end of the n+i-th level pixel ladder in the first direction, where n is an integer not less than , and i is an integer not less than 1.

[0114] For example, as shown in Figures 11 and 12, the anti-static unit ESD1 corresponding to the first-level pixel ladder J1 is located at the end of the second-level pixel ladder J2 in the first direction F1, and the sub-pixels in the first-level pixel ladder J1 are connected to the anti-static unit ESD1 via the data conduction signal line 51-1. The anti-static unit ESD2 corresponding to the second-level pixel ladder J2 is located at the end of the fourth-level pixel ladder J4 in the first direction F1, and the sub-pixels in the second-level pixel ladder J2 are connected to the anti-static unit ESD2 via the data conduction signal line 51-2. The anti-static unit ESD2 corresponding to the third-level pixel ladder J3 is located at the end of the fourth-level pixel ladder J4 in the first direction F1, and the sub-pixels in the third-level pixel ladder J3 are connected to the anti-static unit ESD2 via the data conduction signal line 51-3. The anti-static unit ESD2 corresponding to the fourth-level pixel step J4 is located at the end of the fourth-level pixel step J4 in the first direction F1, and the anti-static unit ESD3 corresponding to the fourth-level pixel step J6 is located at the end of the sixth-level pixel step J6 in the first direction F1. Some sub-pixels in the fourth-level pixel step J4 are connected to the anti-static unit ESD2 via the data conduction signal line 51-4, and some sub-pixels in the fourth-level pixel step J4 are connected to the anti-static unit ESD3 via the data conduction signal line 51-5. The anti-static unit ESD3 corresponding to the fifth-level pixel step J5 is located at the end of the sixth-level pixel step J6 in the first direction F1, and the sub-pixels in the fifth-level pixel step J5 are connected to the anti-static unit ESD3 via the data conduction signal line 51-6.

[0115] Exemplarily, as shown in Figures 9 to 12, the substrate 100 further includes a plurality of data fan-out signal lines 52 and a virtual data fan-out line 53; the data conduction signal line (e.g., 51 in Figure 10, 51-1, 51-2, 51-3, 51-4, 51-5, 51-6 in Figure 12) is electrically connected to the data fan-out signal line 52 through an anti-static unit (e.g., ESD in Figure 10, ESD1, ESD2, ESD3 in Figure 11). It should be noted that the anti-static unit (e.g., ESD in Figure 10, ESD1, ESD2, ESD3 in Figure 11) can avoid electrostatic breakdown caused by a large amount of static electricity accumulation, affecting the display quality and display effect. The orthographic projection of the data-on signal line (e.g., 51 in FIG. 10 , 51-1, 51-2, 51-3, 51-4, 51-5, and 51-6 in FIG. 12 ) on the substrate 100 is located between the orthographic projection of the sub-pixel spx on the substrate 100 and the orthographic projection of the data fan-out signal line 52 on the substrate 100; the orthographic projection of the data fan-out signal line 52 on the substrate 100 is located between the orthographic projection of the anti-static unit (e.g., ESD in FIG. 10 , ESD1, ESD2, and ESD3 in FIG. 11 ) on the substrate 100 and the orthographic projection of the dummy data fan-out line 53 on the substrate 100. It should be noted that the dummy fan-out line can reduce the problem of uneven data fan-out lines near the shift register caused by some process steps (e.g., exposure, etching, etc.), which is mainly due to the size differences between multiple data fan-out lines.

[0116] In some embodiments of the present disclosure, as shown in Figures 13 and 14, the shift register unit 40 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; wherein the first transistor and the second transistor are arranged opposite each other along a first direction F1; the third transistor and the fourth transistor are arranged opposite each other along the first direction F1; the orthographic projections of the third transistor and the fourth transistor on the substrate are located between the orthographic projections of the first transistor and the fifth transistor on the substrate; the sixth transistor and the seventh transistor are arranged opposite each other along the first direction F1; and the orthographic projections of the eighth transistor, the ninth transistor, and the tenth transistor on the substrate are arranged in sequence along a second direction F2. For example, the orthographic projections of the first transistor M1 and the second transistor M2 on the substrate are the same; and the orthographic projections of the sixth transistor M6 and the seventh transistor M7 on the substrate are the same.

[0117] Exemplarily, as shown in Figures 13 and 14, the shift register unit 40 also includes: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18; wherein, the twelfth transistor M12 and the thirteenth transistor M13 have the same orthographic projection on the substrate, and the twelfth transistor M12 and the thirteenth transistor M13 are arranged opposite to each other along the second direction F2; the fifteenth transistor M15 and the sixteenth transistor M16 have the same orthographic projection on the substrate, and the fifteenth transistor M15 and the sixteenth transistor M16 are arranged opposite to each other along the first direction F1; the seventeenth transistor M17 and the eighteenth transistor M18 have the same orthographic projection on the substrate, and the seventeenth transistor M17 and the eighteenth transistor M18 are arranged opposite to each other along the first direction F1.

[0118] For example, in the equivalent circuit diagram of the shift register unit shown in FIG14 , the gate of the third transistor M3 is coupled to the first electrode of the third transistor M3, the gate of the first transistor M1 is coupled to the third node PU, the first electrode of the first transistor M1 is coupled to the first node PD1, and the second electrode of the first transistor M1 is coupled to the first level signal terminal LVGL; the gate of the second transistor M2 is coupled to the first electrode of the first capacitor C1, the first electrode of the second transistor M2 is coupled to the second node PD2, and the second electrode of the second transistor M2 is coupled to the first level signal terminal LVGL; the first electrode of the third transistor M3 is coupled to the first output control signal terminal Out_C(n-1), and the second electrode of the third transistor M3 is coupled to the eighth transistor The first electrode of M8 is coupled to the fourth transistor M4; the gate of the fourth transistor M4 is coupled to the second node PD2, the first electrode of the fourth transistor M4 is coupled to the second electrode of the third transistor M3, and the second electrode of the fourth transistor M4 is coupled to the first level signal terminal LVGL; the gate of the fifth transistor M5 is coupled to the first node PD1, the first electrode of the fifth transistor M5 is coupled to the second electrode of the third transistor M3, and the second electrode of the fifth transistor M5 is coupled to the first level signal terminal LVGL; the gate of the sixth transistor M6 is coupled to the first node PD1, the first electrode of the thirteenth transistor M13A is coupled to the first cascade output terminal Gout(n), and the second electrode of the sixth transistor M6 is coupled to the second level signal terminal VGL; the gate of the seventh transistor M7 is coupled to the first node PD1, the first electrode of the fifth transistor M5 is coupled to the second electrode of the third transistor M3, and the second electrode of the fifth transistor M5 is coupled to the first level signal terminal LVGL. The first electrode of the seventh transistor M7 is coupled to the first cascade output terminal Gout(n), and the second electrode of the seventh transistor M7 is coupled to the second level signal terminal VGL; the gate of the eighth transistor M8 is coupled to the third output control signal terminal Out_C(n+1), and the second electrode of the eighth transistor M8 is coupled to the first level signal terminal LVGL; the gate of the ninth transistor M9 is coupled to the first electrode of the first capacitor C1, the first electrode of the ninth transistor M9 is coupled to the first clock signal terminal CLK, and the second electrode of the ninth transistor M9 is coupled to the first cascade output terminal Gout(n); the second electrode of the first capacitor C1 is coupled to the first cascade output terminal Gout(n); the gate of the tenth transistor M10 ... first capacitor C1 is coupled to the first clock signal terminal CLK, and the second electrode of the ninth transistor M9 is coupled to the first cascade output terminal Gout(n); the gate of the tenth transistor M10 is coupled to the first electrode of the first capacitor C1, the first electrode of the first capacitor C1 is coupled to the first clock signal terminal CLK, and the second electrode of the ninth transistor M9 is coupled to the first cascade output terminal Gout(n); the gate of the tenth transistor M10 is coupled to the first electrode of the first capacitor C1, the first electrode of the first capacitor C1 is coupled to the first clock signal terminal CLK, and the second electrode of the ninth transistor M9 is coupled to the first cascade output terminal Gout(n); the gate of the tenth transistor M10 is coupled to the first electrode of the first capacitor C1, the first electrode of the A first electrode of a capacitor C1 is coupled to the first clock signal terminal CLK, a first electrode of the tenth transistor M10 is coupled to the first clock signal terminal CLK, and a second electrode of the tenth transistor M10 is coupled to the second output control signal terminal Out_C(n); a gate of the eleventh transistor M11 is coupled to the second cascade output terminal Gout(n+1), a first electrode of the eleventh transistor M11 is coupled to the second electrode of the ninth transistor M9, and a second electrode of the eleventh transistor M11 is coupled to the second level signal terminal VGL; a gate of the twelfth transistor M12 is coupled to the second node PD2, a first electrode of the twelfth transistor M12 is coupled to the second output control signal terminal Out_C(n), and a second electrode of the twelfth transistor M12 is coupled to the first level signal terminal LVGL;The gate of the thirteenth transistor M13 is coupled to the first node PD1, the first electrode of the thirteenth transistor M13 is coupled to the second output control signal terminal Out_C(n), and the second electrode of the thirteenth transistor M13 is coupled to the first level signal terminal LVGL; the gate of the fourteenth transistor M14 is coupled to the reset signal terminal T_RST, the first electrode of the fourteenth transistor M14 is coupled to the second electrode of the first transistor M1, and the second electrode of the fourteenth transistor M14 is coupled to the first level signal terminal LVGL; the gate of the fifteenth transistor M15 is coupled to the first output control signal terminal Out_C(n-1), the first electrode of the fifteenth transistor M15 is coupled to the first node PD1, and the second electrode of the fifteenth transistor M15 is coupled to the first level signal terminal L VGL; a gate of the sixteenth transistor M16 is coupled to the first output control signal terminal Out_C(n-1), a first electrode of the sixteenth transistor M16 is coupled to the second node PD2, and a second electrode of the sixteenth transistor M16 is coupled to the first level signal terminal LVGL; a gate of the seventeenth transistor M17 is coupled to the first electrode of the seventeenth transistor M17, a first electrode of the seventeenth transistor M17 is coupled to the second clock signal terminal CLKB, and a second electrode of the seventeenth transistor M17 is coupled to the first node PD1; a gate of the eighteenth transistor M18 is coupled to the first electrode of the eighteenth transistor M18, a first electrode of the eighteenth transistor M18 is coupled to the first clock signal terminal CLK, and a second electrode of the eighteenth transistor M18 is coupled to the second node PD2.

[0119] Exemplarily, the first electrode of the transistor is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode; this is not limited here.

[0120] In some embodiments of the present disclosure, as shown in Figures 15 to 18, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor respectively include multiple active layers 60; the multiple active layers 60 are arranged at intervals along the second direction F2; the spacing d between the multiple active layers 60 and the intervals d between the multiple active layers 60 along the second direction F2 is not greater than 3 microns.

[0121] In some embodiments of the present disclosure, as shown in FIG. 17 and FIG. 18 , a width c of the plurality of active layers 60 along the second direction F2 is not greater than 5 micrometers.

[0122] Illustratively, the disclosed embodiment controls the position of transistors in the shift register unit, controls the spacing between the active layers of the transistors along the second direction F2, and controls the width of the active layers, thereby reducing the size of the shift register unit, further saving space, and making it easier to achieve a narrow frame.

[0123] In some embodiments of the present disclosure, as shown in Figures 19 to 21, the non-display area BB includes: a silver paste area 70, a data fan-out line area 80 and a GOA signal line area 90; wherein, the data fan-out line area 80 is located between the display area AA and the GOA signal line area 90, the GOA signal line area 90 is located between the data fan-out line area 80 and the silver paste area 70, and the data fan-out line area 80 is adjacent to the GOA signal line area 90.

[0124] Exemplarily, as shown in FIG. 19 and FIG. 20 , the distance d′ between the edge of the GOA signal line region 90 and the edge of the adjacent silver paste region 70 is not less than 150 μm.

[0125] In some embodiments of the present disclosure, as shown in Figures 19 to 21, the data fan-out signal line 52 includes a first extension line 52-1 and a first elevated line 52-2; wherein the angle between the first extension line 52-1 and the first elevated line 52-2 is a first angle e. The GOA signal line area 90 includes multiple GOA signal lines 91; wherein the GOA signal lines 91 include a second extension line 91-1 and a second elevated line 91-2; the second extension line 91-1 is arranged parallel to the first extension line 52-1, and the second elevated line 91-2 is arranged parallel to the first elevated line 52-2.

[0126] Exemplarily, the first angle e is between 20 degrees and 35 degrees. For example, the first angle e can be 20 degrees, 23 degrees, 26 degrees, 29 degrees, 30 degrees, 35 degrees, etc., which is not limited here.

[0127] Exemplarily, as shown in FIG21 , f represents the distance that the plurality of data fan-out signal lines can be raised upward.

[0128] For example, the required signals can be respectively input to the first level signal terminal LVGL, the second level signal terminal VGL, the first output control signal terminal Out_C(n-1), the second output control signal terminal Out_C(n), the third output control signal terminal Out_C(n+1), the first clock signal terminal CLK and the second clock signal terminal CLKB in the shift register unit through multiple GOA signal lines in the GOA signal line area.

[0129] In some embodiments of the present disclosure, as shown in 21, the starting ends of the data fan-out signal lines (such as Q1 and Q2 in Figure 21) are located on the lower side of the anti-static unit ESD; the data fan-out signal lines include a first sub-data fan-out signal line 52_q1 and a second sub-data fan-out signal line 52_q2, wherein the extension direction of the starting end Q1 of the first sub-data fan-out signal line 52_q1 and the second direction F2 have an angle not equal to 90 degrees, and / or the extension direction of the starting end Q2 of the second sub-data fan-out signal line 52_q2 extends along the first direction F1.

[0130] In some embodiments of the present disclosure, as shown in FIG21 , the orthographic projection of first sub-data fan-out signal line 52_q1 on substrate 100 is closer to the display area than the orthographic projection of second sub-data fan-out signal line 52_q2 on the substrate. Optionally, first sub-data fan-out signal line 52_q1 is electrically connected to an electrostatic discharge (ESD) device closest to the data fan-out signal line along first direction F1.

[0131] In the embodiment of the present disclosure, the extension direction of the starting end Q2 of the second sub-data fan-out signal line is extended along the first direction F1, and / or the extension direction of the starting end Q1 of the first sub-data fan-out signal line and the second direction F2 have an angle not equal to 90 degrees, wherein the projection of the first sub-data fan-out signal line on the base substrate is closer to the display area than the projection of the second sub-data fan-out signal line on the base substrate, so that signal lines such as the common electrode signal line, the data fan-out signal line, and the GOA signal line have space for setting the lifting line portion, and the distance requirement between the silver paste area and the signal line is met under the narrow frame restriction condition, thereby avoiding short circuit of the signal line.

[0132] In some embodiments of the present disclosure, as shown in FIG22 , the following further comprises:

[0133] The gate conductive layer 110 is located on the base substrate 100;

[0134] The gate insulating layer 120 is located on a side of the gate conductive layer 110 facing away from the base substrate 100 ;

[0135] The semiconductor layer 130 is located on the side of the gate insulating layer 120 away from the substrate 100; the semiconductor layer 130 includes a plurality of active layers;

[0136] The etch stop layer 140 is located on a side of the semiconductor layer 130 facing away from the substrate 100;

[0137] The source and drain layer 150 is located on the side of the etch stop layer 140 facing away from the substrate 100;

[0138] A first insulating layer 160 is located on a side of the source / drain layer 150 facing away from the substrate 100;

[0139] The common electrode layer 170 is located on a side of the first insulating layer 160 away from the base substrate 100;

[0140] The second insulating layer 180 is located on a side of the common electrode layer 170 facing away from the base substrate 100;

[0141] The pixel electrode layer 190 is located on a side of the second insulating layer 180 facing away from the base substrate 100 .

[0142] Exemplarily, the gate conductive layer may include gate lines and the gates of the above-mentioned transistors; the source and drain layer may include data lines, virtual data fan-out signal lines, data fan-out signal lines, GOA signal lines, data turn-on signal lines and the sources and drains of the above-mentioned transistors; the common electrode layer may include common electrode lines; and the pixel electrode layer may include pixel electrodes.

[0143] Exemplarily, the gate conductive layer, source / drain layer, common electrode layer, and pixel electrode layer may be made of a conductive material. For example, the conductive material may include a metal material or alloy material such as aluminum, molybdenum, or titanium, or may include a metal oxide such as indium tin oxide (ITO). The embodiments of the present disclosure do not limit the materials of the functional layers.

[0144] For example, the material of the semiconductor layer may include oxide, amorphous silicon, low-temperature polysilicon, etc., which is not limited here.

[0145] Illustratively, the gate insulating layer, the etch stop layer, the first insulating layer, and the second insulating layer are all formed of insulating materials. As needed, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0146] In some embodiments of the present disclosure, as shown in Figures 23 to 25, it also includes: a plurality of transfer units (for example, K1 and K2 in the figures); wherein the transfer unit includes a first transfer hole K1 and a second transfer hole K2; wherein the first transfer hole K1 exposes the gate conductive layer 110, and the second transfer hole K2 exposes the source and drain layer 150; the pixel electrode layer 190 jumps over the gate conductive layer 110 through the first transfer hole K1 and jumps over the source and drain layer 150 through the second transfer hole K2.

[0147] Exemplarily, as shown in FIG23 , the width of the first transfer hole in the second direction is not greater than 7 microns; the width of the second transfer hole in the second direction is not less than 5 microns.

[0148] For example, the present disclosure controls the sizes of the first through hole K1 and the second through hole K2 and uses an ICP etching process to reduce the overall size of all through holes to about 12.5 μm, thereby further achieving a narrow frame.

[0149] In some embodiments of the present disclosure, as shown in Figures 24 and 25, the switching unit (for example, K1 and K2 in the figures) is also used to connect the GOA signal line with the shift register unit 40, and / or, the switching unit (for example, K1 and K2 in the figures) is located inside the shift register unit 40.

[0150] Illustratively, the GOA signal line is connected to the second clock signal terminal CLKB in the shift register unit 40 through a transfer hole, so that the second clock signal terminal CLKB provides the required signal for the seventeenth transistor M17; the GOA signal line is connected to the first clock signal terminal CLK in the shift register unit 40 through a transfer hole, so that the first clock signal terminal CLK provides the required signal for the eighteenth transistor M18.

[0151] Illustratively, the first transfer hole K1 located in the shift register unit 40 bridges the gate of the sixteenth transistor in the gate conductive layer 110 with the pixel electrode in the pixel electrode layer 190; the second transfer hole K2 located in the shift register unit 40 bridges the source and drain of the sixteenth transistor M16 in the source and drain layer 150 with the pixel electrode in the pixel electrode layer 190.

[0152] Based on the same disclosed concept, the present disclosure also provides a display device, including the display panel provided in the present disclosure. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated here.

[0153] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, an electronic watch, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0154] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0155] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein, comprising: a substrate substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels; the plurality of sub-pixels include a first sub-pixel and edge virtual sub-pixels; at least one of the edge virtual sub-pixels is included in at least one row of the sub-pixels, and at least one of the edge virtual sub-pixels is included in at least one column of the sub-pixels; a plurality of pixel driving units, which are arranged in one-to-one correspondence with the first sub-pixel and the edge virtual sub-pixels; wherein, the pixel driving unit is configured to drive the first sub-pixel to display an image; a color filter substrate, including a black matrix layer and a color resist layer formed on the color filter substrate; the black matrix layer has a plurality of opening areas; the color resist layer includes a plurality of first color resist layers, a plurality of second color resist layers, and a plurality of third color resist layers; the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the color filter substrate overlap with the orthographic projection of the opening area on the color filter substrate; the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate substrate does not overlap with the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer on the substrate substrate; the orthographic projection of the pixel driving unit corresponding to the edge virtual sub-pixel on the substrate substrate does not overlap with the orthographic projection of the opening area on the substrate substrate.

2. The display panel according to claim 1, wherein, the edge virtual sub-pixels in the same column of sub-pixels are closer to the corner edge of the display area than the first sub-pixel in a first direction; the edge virtual sub-pixels in the same row of sub-pixels are closer to the corner edge of the display area than the first sub-pixel in a second direction.

3. The display panel according to claim 1, wherein, the number of opening areas in each column and the number of opening areas in each row are reduced in a direction approaching the corner edge of the display area; wherein, the color resist layer includes a plurality of color resist units, and each color resist unit includes: the first color resist layer, the second color resist layer, and the third color resist layer; wherein, the orthographic projections of the first color resist layer, the second color resist layer, and the third color resist layer in each color resist unit on the substrate substrate are the same; wherein, the area of each color resist unit gradually decreases in a direction approaching the corner edge of the display area.

4. The display panel according to claim 1, wherein, the pixel driving unit includes: a first sub-driving unit, and / or, a second sub-driving unit; the first sub-driving unit includes a first driving transistor; the gate of the first driving transistor is coupled to a gate line, the first pole of the first driving transistor is coupled to a data line, and the second pole of the first driving transistor is coupled to a pixel electrode; the second sub-driving unit includes a second driving transistor; the gate of the second driving transistor is coupled to the gate line, the first pole of the second driving transistor is coupled to the data line, and the second pole of the second driving transistor is coupled to the pixel electrode; the shapes of the orthographic projections of the pixel driving units on the substrate substrate are the same.

5. The display panel according to any one of claims 1-4, wherein, a plurality of sub-pixels near the corner edge of the display area are arranged in a stepped manner to form a multi-level pixel step, and each level of the pixel step is composed of at least one sub-pixel; in some of the pixel steps, at least one of the edge virtual sub-pixels is arranged at every other level of the pixel step.

6. The display panel according to claim 5, wherein, the substrate further includes: a plurality of cascaded shift register units, a plurality of anti-static units, and at least one common electrode line; wherein each shift register unit corresponds to one row of the sub-pixels; the orthographic projection of the anti-static unit on the substrate and the orthographic projection of the cascaded shift register units on the substrate are respectively located on different sides of the orthographic projection of the common electrode line on the substrate; the orthographic projection of the anti-static unit on the substrate is located between the orthographic projection of the common electrode line on the substrate and the orthographic projection of the sub-pixels on the substrate; the sub-pixels in each level of the pixel step are respectively electrically connected to at least one of the anti-static units; the anti-static unit is located at the end of the pixel step in the first direction, and the anti-static unit is located between at most two rows of sub-pixels in the second direction.

7. The display panel according to claim 6, wherein, the anti-static unit corresponding to the nth level of the pixel step is located at the end of the nth level of the pixel step in the first direction, where n is an integer not less than, and i is an integer not less than 1.

8. The display panel according to claim 6, wherein, the anti-static unit corresponding to the nth level of the pixel step is located at the end of the (n + i)th level of the pixel step in the first direction, where n is an integer not less than, and i is an integer not less than 1.

9. The display panel according to claim 6, wherein, the anti-static unit corresponding to the nth level of the pixel step includes a first anti-static unit located at the end of the nth level of the pixel step in the first direction and a first anti-static unit located at the end of the (n + i)th level of the pixel step in the first direction, where n is an integer not less than, and i is an integer not less than 1.

10. The display panel according to claim 6, wherein, the substrate further includes: a plurality of data conduction signal lines; the sub-pixels in each level of the pixel step are connected to the corresponding anti-static units through the data conduction signal lines; the data conduction signal lines are arranged in an S shape, and / or a zigzag shape, and / or a lightning shape.

11. The display panel according to any one of claims 5-10, wherein, the shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; Wherein, the first transistor and the second transistor are arranged opposite to each other along the first direction; the third transistor and the fourth transistor are arranged opposite to each other along the first direction; the orthographic projections of the third transistor and the fourth transistor on the substrate are located between the orthographic projections of the first transistor and the fifth transistor on the substrate; the sixth transistor and the seventh transistor are arranged opposite to each other along the first direction; the orthographic projections of the eighth transistor, the ninth transistor and the tenth transistor on the substrate are arranged in sequence along the second direction; The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor respectively include a plurality of active layers; the plurality of active layers are arranged in a spaced relationship along the second direction; and the spacing between the plurality of active layers in the second direction is not greater than 3 micrometers; The width of the plurality of active layers along the second direction is no greater than 5 micrometers.

12. The display panel according to claim 11, in, The non-display area includes: a silver paste area, a data fan-out line area and a GOA signal line area; The data fan-out line area is located between the display area and the GOA signal line area, the GOA signal line area is located between the data fan-out line area and the silver paste area, and the data fan-out line area is adjacent to the GOA signal line area; The data fan-out signal line includes: a first extension line and a first lift line; An angle between the first extension line and the first lifting line is a first angle.

13. The display panel according to claim 12, in, The first angle is between 20 degrees and 35 degrees.

14. The display panel according to claim 12, in, The GOA signal line area includes a plurality of GOA signal lines; wherein the GOA signal line includes: a second extension line and a second lifting line; The second extension line is arranged in parallel with the first extension line, and the second lifting line is arranged in parallel with the first lifting line.

15. The display panel according to claim 12, in, The starting end of the data fan-out signal line is located at the lower side of the anti-static unit; the data fan-out signal line includes a first sub-data fan-out signal line and a second sub-data fan-out signal line, wherein an extension direction of the starting end of the first sub-data fan-out signal line and the second direction have an angle not equal to 90 degrees, and / or an extension direction of the starting end of the second sub-data fan-out signal line extends along the first direction.

16. The display panel according to claim 15, in, An orthographic projection of the first sub-data fan-out signal line on the base substrate is closer to the display area than an orthographic projection of the second sub-data fan-out signal line on the base substrate.

17. The display panel according to any one of claims 1 to 16, in, Also includes: A gate conductive layer, located on the substrate; A gate insulating layer, located on a side of the gate conductive layer away from the substrate; A semiconductor layer, located on a side of the gate insulating layer away from the substrate; The semiconductor layer includes a plurality of active layers; An etching stop layer, located on a side of the semiconductor layer away from the substrate; The source-drain layer is located on the side of the etching stop layer away from the substrate, and includes a data line, a data fan-out line, a GOA signal line, and a data conduction signal line; A first insulating layer, located on a side of the source / drain layer away from the substrate; A common electrode layer, located on a side of the first insulating layer away from the base substrate; A second insulating layer is located on a side of the common electrode layer away from the base substrate; The pixel electrode layer is located on a side of the second insulating layer away from the base substrate.

18. The display panel according to claim 17, in, Also included: a plurality of transfer units; the transfer unit includes a first transfer hole and a second transfer hole; wherein the first transfer hole exposes the gate conductive layer, and the second transfer hole exposes the source and drain layer; The pixel electrode layer is connected to the gate conductive layer via the first transfer hole and is connected to the source and drain layer via the second transfer hole.

19. The display panel according to claim 18, in, The switching unit is further used to connect the GOA signal line and the shift register unit, and / or the switching unit is located in the shift register unit.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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