LED chip fan-out wafer level packaging structure and packaging method

Abstract

An LED chip fan-out wafer level packaging structure and packaging method. The packaging structure comprises three LED chips (3) with colors of R, G, and B grouped together as one unit, wherein the light-emitting sides of the LED chips (3) are fitted and arranged on a substrate (1), the substrate (1) is filled with an insulating light-shielding layer (5) wrapping the side surfaces of the substrate (1) and the side surfaces of the LED chips (3), and the surface layer of the insulating light-shielding layer (5) is flush with the surface layer of the substrate (1).

Description

LED chip fan-out wafer-level packaging structure and packaging method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311620881.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and for example, to a fan-out wafer-level packaging structure for an LED chip and a packaging method thereof. Background Art

[0003] Light-emitting diode (LED) displays are a new type of information display media that developed rapidly around the world in the late 1980s. They utilize dot matrix modules or pixel units composed of light-emitting diodes to form large-area display screens. They offer stable performance, long service life, strong environmental adaptability, high cost-performance, and low operating costs. In a short period of time, they have rapidly grown into a mainstream product for various display types and have been widely used in the information display field.

[0004] With the gradual development of LEDs, wafer-level LED packaging finally emerged and developed rapidly. Wafer-level LEDs are characterized by their small size and the integration of multiple electronic components in a chip-sized package structure, which has led to some problems.

[0005] Common issues include crosstalk between LED pixels, which results in brightness loss and poor uniformity, hindering the continued development of wafer-level LEDs. However, prior art wafer-level LED packaging solutions for addressing optical crosstalk often rely on the driver substrate, resulting in complex and costly packaging processes that urgently need improvement.

[0006] Summary of the Invention

[0007] The present application provides an LED chip fan-out wafer-level packaging structure and a packaging method thereof, which adopts wafer-level packaging technology to achieve hexagonal encapsulation of the LED chip to solve the lateral crosstalk problem.

[0008] An embodiment of the present application provides an LED chip fan-out wafer-level packaging structure, comprising three LED chips of R, G, and B colors in a group, wherein the light-emitting sides of the LED chips are bonded to a substrate, and an insulating light-shielding layer is filled between the substrates to wrap the side surfaces of the substrates and the side surfaces of the LED chips, and the surface layer of the insulating light-shielding layer is flush with the surface layer of the substrates.

[0009] The present embodiment provides a fan-out wafer-level packaging method for an LED chip, which is used to prepare the above-mentioned fan-out wafer-level packaging structure for an LED chip, comprising:

[0010] Prepare a substrate, and cover the front surface of the substrate with a light-transmitting transparent bonding adhesive layer;

[0011] The positive electrode of the LED chip faces upwards, and the LED chip is adhered to the substrate through the transparent bonding adhesive layer;

[0012] On the substrate, a through groove is provided along the circumference of the arrangement position of the LED chip;

[0013] An insulating light-shielding layer is prepared on the entire substrate to cover the entire LED chip, and a window is opened on the insulating light-shielding layer at the position where the electrode of the LED chip is located to expose the electrode of the LED chip;

[0014] preparing interconnecting metal in the window to lead out the electrodes of the LED chip;

[0015] The back side of the substrate is thinned until the insulating light shielding layer in the through groove is exposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic structural diagram of a substrate in this application;

[0017] FIG2 is a schematic structural diagram of the through slot in this application;

[0018] FIG3 is a top view of the through slot in the present application;

[0019] FIG4 is a schematic structural diagram of the insulating light-shielding layer in the present application;

[0020] FIG5 is a schematic diagram of the structure of the interconnect metal in this application;

[0021] FIG6 is a top view of the interconnect metal in this application;

[0022] FIG7 is a schematic structural diagram of a fan-out wafer-level packaging structure for an LED chip in the present application;

[0023] FIG8 is a flow chart of a fan-out wafer-level packaging method for LED chips in the present application.

[0024] In the figure: 1. Substrate; 2. Transparent solid crystal adhesive layer; 3. LED chip; 4. Through groove; 5. Insulation shading layer; 6. Window; 7. Interconnect metal; 8. Surface shading layer. DETAILED DESCRIPTION

[0025] The present application is described below in conjunction with the accompanying drawings and embodiments. The embodiments described herein are only used to explain the relevant content and are not intended to limit the present application. It should also be noted that, for ease of description, only the parts relevant to the present application are shown in the accompanying drawings.

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described below with reference to the accompanying drawings and in combination with the embodiments.

[0027] Example

[0028] This embodiment first provides an LED chip fan-out wafer-level packaging structure, see Figure 7, including three LED chips 3 of R, G, and B colors in a group, and the light-emitting side of the LED chip 3 is bonded to the substrate 1. The substrate 1 is filled with an insulating shading layer 5 that wraps the side of the substrate 1 and the side of the LED chip 3. The surface of the insulating shading layer 5 is flush with the surface of the substrate 1.

[0029] 7 , in some embodiments, a surface light-shielding layer 8 is disposed on the insulating light-shielding layer 5 between adjacent LED chips 3, and the surface light-shielding layer 8 covers the edges of the adjacent LED chips 3. In other embodiments, a surface light-shielding layer 8 is disposed on the insulating light-shielding layer 5 between adjacent groups of LED chips 3, and the surface light-shielding layer 8 covers the edges of the adjacent groups of LED chips 3.

[0030] 7 , the insulating light-shielding layer 5 defines a window 6 at the electrode of the LED chip 3 , and an interconnecting metal 7 for leading out the electrode of the LED chip 3 is provided in the window 6 .

[0031] In a second aspect, this embodiment further provides a fan-out wafer-level packaging method for an LED chip, as shown in FIG8 , for preparing the above-mentioned fan-out wafer-level packaging structure for an LED chip. The method includes the following steps.

[0032] Step S1: prepare a substrate 1 and cover the front surface of the substrate 1 with a light-transmitting transparent bonding adhesive layer 2.

[0033] Step S1 involves wafer preparation and the fabrication of a transparent bonding adhesive layer 2. Referring to Figure 1 , a wafer-level substrate 1 is prepared and thinned to an appropriate thickness. The transparent bonding adhesive layer 2 is then formed by coating or laminating the substrate 1 with a transparent bonding adhesive layer 2. The thickness of the transparent bonding adhesive layer can be adjusted freely based on production requirements. The substrate can be made of sapphire, glass, or other transparent materials, depending on the specific processing requirements.

[0034] Step S2: With the positive electrode of the LED chip 3 facing upward, the LED chip 3 is adhered to the substrate 1 through the transparent bonding adhesive layer 2 .

[0035] Step S2 is chip reconstruction. Referring to Figure 1 , the LED chips 3 to be packaged are attached to the substrate 1 using a technique such as SMT or mass transfer, and permanently bonded using a transparent die-bonding adhesive layer 2. The electrodes of the LED chips 3 face upward, and the three R / G / B chips form a group.

[0036] Step S3: On the substrate 1 , a through groove 4 is provided along the circumference of the location where the LED chip 3 is provided.

[0037] Step S3 is to make the through groove 4. Referring to FIG. 2 and FIG. 3 , a through groove 4 is made on the substrate 1 by using a mechanical or laser grooving process to prepare for the subsequent side encapsulation.

[0038] There is no particular order for steps S1, S2, and S3. In some embodiments, a through groove 4 may be firstly formed on the substrate 1 at the position where the LED chip is to be arranged, and then a transparent bonding adhesive layer 2 may be prepared, and then the LED chip 3 may be fixedly arranged.

[0039] Step S4: preparing an insulating light-shielding layer 5 covering the entire LED chip 3 on the entire substrate 1, and opening a window 6 on the insulating light-shielding layer 5 at the position where the electrode of the LED chip 3 is located to expose the electrode of the LED chip 3.

[0040] Step S4 is the production of the insulating light-shielding layer 5. Referring to FIG4 , an insulating light-shielding layer 5 is coated on the entire substrate 1 to wrap the entire LED chip 3 through spraying, coating, lamination, dispensing, and plastic packaging processes, and the windowing of the LED chip 3 electrode is achieved through a photolithography process.

[0041] Step S5: preparing interconnect metal 7 in the window 6 to lead out the electrodes of the LED chip 3 .

[0042] Step S5 is the fabrication of the interconnect metal 7. Referring to Figures 5 and 6, the redistribution layer (RDL) is fabricated by processes such as 3D printing, printing, physical vapor deposition (PVD), photolithography, and electroplating to achieve fan-out fabrication of the redistribution layer (RDL) and lead-out of the electrodes of the LED chip 3.

[0043] Step S6: thinning the back side of the substrate 1 until the insulating light shielding layer 5 in the through groove 4 is exposed.

[0044] Step S6 is thinning. Referring to FIG7 , the substrate 1 is thinned by a grinding process to expose the insulating light shielding layer 5 in the through groove 4 from the back. The thinning thickness is not limited and can be adjusted freely according to production requirements.

[0045] In some embodiments, the method further comprises: preparing a surface light-shielding layer 8 covering the substrate 1 on the back side of the substrate 1, and opening a window in the surface light-shielding layer 8 at the light-emitting position of each LED chip 3 to allow the LED light to pass through. In other embodiments, the method further comprises: preparing a surface light-shielding layer 8 covering the substrate 1 on the back side of the substrate 1, and opening a window in the surface light-shielding layer 8 for each group of LED chips 3 to expose each group of LED chips 3.

[0046] In some embodiments, as shown in FIG7 , after substrate 1 is thinned, a surface light-shielding layer 8 is formed on the back side of substrate 1. This layer is applied to the non-chip side of substrate 1 through processes such as photolithography, metal deposition, or etching, while simultaneously revealing the location where the corresponding LED chip 3 emits light. The locations of the openings in surface light-shielding layer 8 are not limited; individual windows for G / R / B can be provided, or a group of windows can be provided. The material of surface light-shielding layer 8 is not limited and can include polymers, metals, and the like.

[0047] The packaging structure and packaging method provided in the present application solve the problem of lateral light crosstalk between different chips in LED wafer-level packaging by opening a through groove on the substrate, filling the through groove with an insulating light-shielding layer, and then thinning the substrate to expose the insulating light-shielding layer in the through groove. Compared with the solutions in related technologies, the process is simple, the cost is low, and the thickness of the obtained packaging structure is greatly reduced.

[0048] Those skilled in the art will appreciate that the above embodiments are merely intended to illustrate the present application and are not intended to limit the scope of the present application. Other variations or modifications may be made based on the above application, and these variations or modifications are still within the scope of the present application.

Claims

1. A fan-out wafer-level packaging structure for a light-emitting diode (LED) chip, comprising three LED chips of three colors, R, G, and B, in a group, wherein a substrate is bonded to the light-emitting side of the LED chip, and an insulating light-shielding layer is filled between the substrates to wrap the side surfaces of the substrate and the side surfaces of the LED chip, and the surface layer of the insulating light-shielding layer is flush with the surface layer of the substrate.

2. The LED chip fan-out wafer-level packaging structure according to claim 1, wherein: A surface light-shielding layer is arranged on the insulating light-shielding layer between adjacent LED chips, and the surface light-shielding layer covers the edges of adjacent LED chips.

3. The LED chip fan-out wafer-level packaging structure according to claim 1, wherein: A surface light-shielding layer is arranged on the insulating light-shielding layer between adjacent groups of LED chips, and the surface light-shielding layer covers the edges of the adjacent groups of LED chips.

4. The LED chip fan-out wafer level packaging structure according to claim 1, wherein: The insulating light-shielding layer has windows at the electrodes of the LED chip, and interconnecting metals for leading out the electrodes of the LED chip are arranged in the windows.

5. A fan-out wafer-level packaging method for a light-emitting diode (LED) chip, used to prepare the fan-out wafer-level packaging structure of an LED chip according to any one of claims 1 to 5, comprising: Prepare a substrate, and cover the front side of the substrate with a light-transmitting transparent bonding adhesive layer; The positive electrode of the LED chip faces upward, and the LED chip is adhered to the substrate through the transparent bonding adhesive layer; On the substrate, a through groove is provided along the circumference of the location where the LED chip is arranged; An insulating light-shielding layer covering the entire LED chip is prepared on the entire substrate, and a window is opened on the insulating light-shielding layer at the position where the electrode of the LED chip is located to expose the electrode of the LED chip; Preparing interconnect metal in the window to lead out the electrodes of the LED chip; The back side of the substrate is thinned until the insulating light-shielding layer in the through groove is exposed.

6. The method according to claim 5, further comprising: A surface light shielding layer covering the substrate is prepared on the back side of the substrate, and a window is opened on the surface light shielding layer at the light emitting position of each LED chip to allow the LED light to pass through.

7. The method according to claim 5, further comprising: A surface light shielding layer covering the substrate is prepared on the back side of the substrate, and windows are opened on the surface light shielding layer for each group of LED chips to expose each group of LED chips.

8. The method according to claim 5, wherein: The through groove is prepared by a mechanical grooving process or a laser grooving process.

9. The method according to claim 5, wherein: The insulating light-shielding layer is prepared by at least one method selected from the group consisting of spraying, coating, lamination, dispensing and plastic sealing.

10. The method according to claim 6 or 7, wherein: The interconnect metal is prepared by at least one of three-dimensional 3D printing, printing, physical vapor deposition PVD, photolithography and electroplating, and the surface light shielding layer is prepared by at least one of photolithography, metal deposition and etching.

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