Display panel, display screen, and electronic device

Abstract

A display panel, comprising a hole area (22), a winding area (24), a display area (21), and a non-display area (23). The winding area (24) is arranged around the hole area (22), and the display area (21) is arranged around at least part of the winding area (24). The display panel further comprises a first gate driving circuit (231), wherein the first gate driving circuit (231) is located in the non-display area (23) on one side of the display area (21). The first gate driving circuit (231) comprises a plurality of cascaded first gate driving units (2311), wherein each first gate driving unit (2311) provides a first scan signal to two adjacent rows of pixel circuits (210) by means of two first signal transmission lines (211), the first scan signal affects gate potentials of driving transistors (T3) in the pixel circuits (210), the first signal transmission lines (211) are partially located in the winding area (24), and the parts of the first signal transmission lines (211) located in the winding area (24) are independent of each other.

Description

Display panels, displays, and electronic devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 2023116495111 and invention name “Display panel, display screen and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a display panel, a display screen, and an electronic device. Background Art

[0004] The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

[0005] Existing electronic device display panels are often provided with a hole area for arranging functional devices such as a camera, a winding area arranged around the hole area, and a display area arranged around at least a portion of the winding area. Summary of the Invention

[0006] According to various embodiments of the present application, a display panel, a display screen, and an electronic device are provided.

[0007] In a first aspect, an embodiment of the present application provides a display panel comprising: a hole area, a winding area, a display area, and a non-display area, wherein the winding area is arranged around the hole area, and the display area is arranged around at least a portion of the winding area; wherein the display panel further comprises a first gate drive circuit, and the first gate drive circuit is located in the non-display area on one side of the display area; wherein,

[0008] The first gate driving circuit includes a plurality of cascaded first gate driving units;

[0009] The first gate driving unit provides a first scanning signal to two adjacent rows of pixel circuits through two first signal transmission lines; wherein the first scanning signal affects the gate potential of the driving transistor in the pixel circuit;

[0010] Part of the first signal transmission line is located in the winding area, and parts of the first signal transmission lines located in the winding area are independent of each other.

[0011] In one embodiment, the first signal transmission line includes a first line segment A, a first winding line, and a first line segment B that are electrically connected in sequence; wherein, the first winding line is located in the winding area, and the first line segment A and the first line segment B are respectively located in the display area on both sides of the winding area.

[0012] In one embodiment, the display panel further includes a second gate driving circuit, the second gate driving circuit is located in a non-display area on the other side of the display area, and the second gate driving circuit includes a plurality of cascaded second gate driving units.

[0013] The second gate driving unit at the same level as the first gate driving unit provides a second scanning signal to the two adjacent rows of pixel circuits through two second signal transmission lines, wherein the second scanning signal is different from the first scanning signal and affects the gate potential of the driving transistor in the pixel circuit.

[0014] Part of the second signal transmission line is located in the winding area, and parts of the second signal transmission lines located in the winding area are independent of each other.

[0015] In one embodiment, the second signal transmission line includes a second line segment A, a second winding line, and a second line segment B electrically connected in sequence; wherein, the second winding line is located in the winding area, and the second line segment A and the second line segment B are respectively located in the display area on both sides of the winding area.

[0016] In one embodiment, a portion of the first signal transmission line located in the winding area and a portion of the second signal transmission line located in the winding area are located in different layers.

[0017] In one embodiment, the display panel further includes:

[0018] A third gate driving circuit, the third gate driving circuit comprising a plurality of cascaded third-A gate driving units and a plurality of cascaded third-B gate driving units; wherein the third-A gate driving units and the third-B gate driving units are respectively located in non-display areas on both sides of the display area; wherein,

[0019] The third gate driving unit A and the third gate driving unit B arranged at the same level provide a third scanning signal to the pixel circuits in the same row through a third signal transmission line, wherein the third scanning signal affects the data writing of the pixel circuits.

[0020] In one embodiment, the third signal transmission line includes a third A line segment connected to the third A gate driving unit, and a third B line segment connected to the third B gate driving unit; the third A line segment and the third B line segment are connected, and the third A line segment and the third B line segment are respectively located in the display area on both sides of the winding area.

[0021] In one embodiment, the third signal transmission line includes a third A segment, a third winding and a third B segment electrically connected in sequence, and also includes a third winding connected to the third A segment and the third B segment respectively, wherein the third A segment and the third B segment are respectively located in the display area on both sides of the winding area, and the third winding is located in the winding area.

[0022] In one embodiment, a portion of the first signal transmission line located in the winding area and a portion of the third signal transmission line located in the winding area are located in different layers.

[0023] In one embodiment, the portion of the third signal transmission line located in the winding area is arranged in the same layer as the portion of the second signal transmission line located in the winding area, wherein:

[0024] The second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

[0025] In one embodiment, the non-display area further includes:

[0026] a fourth gate driving circuit, the fourth gate driving circuit comprising a plurality of cascaded fourth gate driving units;

[0027] Each of the fourth gate driving units provides a fourth scanning signal to two rows of pixel circuits respectively through two fourth signal transmission lines; wherein the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element.

[0028] In one embodiment, the two fourth signal transmission lines respectively include a fourth A line segment and a fourth B line segment, and one of the two fourth signal transmission lines also includes a fourth winding; wherein, the two fourth A line segments are respectively connected to the corresponding two fourth B line segments through a fourth winding, the fourth winding is located in the winding area, and the fourth A line segment and the fourth B line segment are respectively located in the display area on both sides of the winding area.

[0029] In one embodiment, one of the second winding and the first winding is located on the same layer as the fourth winding, and the other of the second winding and the first winding is located on a different layer from the fourth winding.

[0030] Wherein, the first winding is the portion of the first signal transmission line located in the winding area;

[0031] The second winding is a portion of the second signal transmission line located in the winding area. The second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

[0032] In one embodiment, the non-display area further includes:

[0033] a fifth gate driving circuit, the fifth gate driving circuit comprising a plurality of cascaded fifth gate driving units;

[0034] Each of the fifth gate driving units provides light-emitting control signals to two rows of pixel circuits via two fifth signal transmission lines, wherein the light-emitting control signals affect the light-emitting of the light-emitting elements.

[0035] In one embodiment, the two fifth signal transmission lines respectively include a fifth A line segment and a fifth B line segment, and one of the two fifth signal transmission lines also includes a fifth winding; the two fifth A line segments are respectively connected to the two fifth B line segments through a fifth winding, wherein the fifth winding is located in the winding area, and the fifth A line segment and the fifth B line segment are respectively located in the display area on both sides of the winding area.

[0036] In one embodiment, the fifth gate driving circuit and the second gate driving circuit are located in the non-display area on the same side of the display area, and the second gate driving circuit is used to provide a second scanning signal; wherein, the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

[0037] In one embodiment, one of the second winding and the first winding is located on the same layer as the fifth winding, and the other of the second winding and the first winding is located on a different layer from the fifth winding; wherein, the first winding is the portion of the first signal transmission line located in the winding area, and the second winding is the portion of the second signal transmission line located in the winding area.

[0038] In one embodiment, a portion of the first signal transmission line located in the winding area and a portion of the second signal transmission line located in the winding area are located in different layers.

[0039] In one embodiment, a portion of the first signal transmission line located in the winding area and a portion of the third signal transmission line located in the winding area are located in different layers.

[0040] In one embodiment, the display panel includes:

[0041] substrate and;

[0042] A driving circuit layer, the driving circuit layer comprising a first gate layer and a second gate layer;

[0043] The portion of the first signal transmission line located in the winding area is located in the second gate layer, and the portion of the second signal transmission line located in the winding area is located in the first gate layer.

[0044] In one embodiment, the third signal transmission line includes a third line segment A and a third line segment B connected in sequence, and the third line segment A and the third line segment B are respectively located in the display area on both sides of the winding area, and the third signal transmission line is used to transmit a third scanning signal, and the third scanning signal affects the data writing of the pixel circuit;

[0045] One of the fourth winding and the fifth winding is located in the first gate layer, and the other of the fourth winding and the fifth winding is located in the second gate layer;

[0046] The fourth winding is a portion of the fourth signal transmission line located in the winding area, and the fourth signal transmission line is used to transmit a fourth scanning signal, and the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element;

[0047] The fifth winding is a portion of the fifth signal transmission line located in the winding area, and the fifth signal transmission line is used to transmit a light-emitting control signal.

[0048] In one embodiment, the third signal transmission line includes a third line segment A, a third winding line, and a third line segment B electrically connected in sequence; the third signal line is used to transmit a third scanning signal, and the third scanning signal affects data writing of the pixel circuit;

[0049] The second winding and the third winding are respectively located on the first gate layer, and the first winding, the fourth winding and the fifth winding are respectively located on the second gate layer;

[0050] The first winding is a portion of the first signal transmission line located in the winding area;

[0051] The second winding is a portion of the second signal transmission line located in the winding area, the second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit;

[0052] The third winding is a portion of the third signal transmission line located in the winding area, the third signal transmission line is used to transmit a third scanning signal, and the second scanning signal affects the data writing of the pixel circuit;

[0053] The fourth winding is a portion of the fourth signal transmission line located in the winding area, and the fourth signal transmission line is used to transmit a fourth scanning signal, and the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element;

[0054] The fifth winding is a portion of the fifth signal transmission line located in the winding area, and the fifth signal transmission line is used to transmit a light-emitting control signal.

[0055] In one embodiment, the display panel includes a substrate and a driving circuit layer, the driving circuit layer includes multiple rows of pixel circuits arranged in a column direction, wherein the number of winding projections in the first area is the same as the number of winding projections in the second area, and the first area and the second area are respectively the projection areas of two rows of pixel circuits in the target area on the substrate.

[0056] In one embodiment, the pixel circuit comprises:

[0057] a driving transistor for providing a driving current to the light emitting element;

[0058] a storage capacitor, wherein a first end of the storage capacitor is used to receive a first power supply signal, and a second end of the storage capacitor is connected to the gate of the driving transistor;

[0059] a threshold compensation module, wherein a first end of the threshold compensation module is connected to the second end of the driving transistor, a second end of the threshold compensation module is connected to the gate of the driving transistor, and a control end of the threshold compensation module is used to receive the first scanning signal;

[0060] A first initialization module, wherein the first end of the first initialization module is used to receive a first initialization signal, the second end of the first initialization module is connected to the gate of the driving transistor or the first end of the threshold compensation module, and the control end of the first initialization module is used to receive a second scanning signal.

[0061] In one embodiment, the pixel circuit comprises:

[0062] a driving transistor for providing a driving current to the light emitting element;

[0063] a storage capacitor, wherein a first end of the storage capacitor is used to receive a first power supply signal, and a second end of the storage capacitor is connected to the gate of the driving transistor;

[0064] a threshold compensation module, wherein a first end of the threshold compensation module is connected to the second end of the driving transistor, a second end of the threshold compensation module is connected to the gate of the driving transistor, and a control end of the threshold compensation module is used to receive the first scanning signal;

[0065] A first initialization module, wherein the first end of the first initialization module is used to receive a first initialization signal, the second end of the first initialization module is connected to the first end of the threshold compensation module, and the control end of the first initialization module is used to receive a second scanning signal.

[0066] In one embodiment, the pixel circuit further includes:

[0067] A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to the first electrode of the driving transistor, and a control end of the data writing module is used to receive a third scanning signal.

[0068] In one embodiment, the pixel circuit further includes:

[0069] a second initialization module, wherein a first end of the second initialization module is used to receive a second initialization signal, a second end of the second initialization module is connected to the gate of the driving transistor, and a control end of the second initialization module is used to receive a fourth scanning signal;

[0070] a third initialization module, wherein a first end of the third initialization module is used to receive a third initialization signal, a second end of the third initialization module is connected to the first end of the driving transistor, and a control end of the third initialization module is used to receive a fourth scanning signal;

[0071] a first light-emitting control module, wherein a first terminal of the first light-emitting control module is used to receive a first power supply signal, a second terminal of the first light-emitting control module is connected to the first terminal of the driving transistor, and a control terminal of the first light-emitting control module is used to receive a light-emitting control signal;

[0072] A second light-emitting control module, wherein the first end of the second light-emitting control module is connected to the second end of the driving transistor, the second end of the second light-emitting control module is connected to the anode of the light-emitting element, and the control end of the second light-emitting control module is used to receive a light-emitting control signal.

[0073] In a second aspect, an embodiment of the present application further provides a display screen, comprising a cover plate and the display panel provided in the first aspect.

[0074] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the display screen provided in the second aspect.

[0075] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0077] FIG1 is a schematic diagram of a planar structure of a display panel in the related art;

[0078] FIG2 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application;

[0079] FIG3 is a schematic diagram of the planar structure of the area surrounding the hole area in FIG2 ;

[0080] FIG4 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0081] FIG5 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0082] FIG6 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0083] FIG7 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0084] FIG8 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0085] FIG9 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0086] FIG10 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0087] FIG11 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0088] FIG12 is a schematic diagram of the structure of a display screen provided in an embodiment of the present application;

[0089] FIG13 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0090] Description of reference numerals: 11 - display area, 12 - aperture area, 21 - display area, 210 - pixel circuit, 2101 - threshold compensation module, 2102 - first initialization module, 2103-data writing module, 2104-second initialization module, 2105-third initialization module, 2106-first light control module, 2107-second light control module, 211-first signal transmission line, 2111-first line segment A, 2112-first winding, 2113-first line segment B, 2121-second line segment A, 2122-second winding, 2123-second line segment B, 2131-third line segment A, 2132-third line segment B, 2133-third winding, 2141-fourth line segment A, 2142-fourth winding, 2143-fourth line segment B, 2151-fifth line segment A, 2152-fifth winding, 2153-fifth line segment B, 22 -hole area, 23-non-display area, 24-winding area, 25-target area, 251-first tangent, 252-second tangent, 231-first gate drive circuit, 2311-first gate drive circuit unit, 232-second gate drive circuit, 2321-second gate drive circuit unit, 233-third gate drive circuit, 2331-third gate drive circuit unit A, 2332-third gate drive circuit unit B, 234-fourth gate drive circuit, 2341-fourth gate drive circuit unit, 235-fifth gate drive circuit, 2351-fifth gate drive circuit unit, 200-display screen, 2100-cover, 20-display panel, 30-electronic device. DETAILED DESCRIPTION

[0091] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0093] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, when a layer is referred to as being "under" another layer, it can be directly under or one or more intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening elements may also be present.

[0094] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0095] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0096] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately," "approximately," or "substantially" can mean within one or more standard deviations, and is not limited here.

[0097] Furthermore, in the specification, the phrase “planar distribution diagram” refers to a drawing when the target portion is viewed from above, and the phrase “cross-sectional diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0098] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0099] Figure 1 is a schematic diagram of the planar structure of a display panel in the related art. As shown in Figure 1, the display panel in the related art includes a hole area 12, a winding area (not shown) and a display area 11. The winding area is arranged around the hole area 12, and the display area 11 is arranged around at least part of the winding area. A camera, an earpiece and other structures can be arranged in the hole area 12 to reduce the area of ​​the border area.

[0100] Due to the presence of the hole area 12 , the signal lines that should be arranged at the hole area 12 need to be routed in the routing area around the hole area 12 . There is a difference in routing loading between the routing area and the display area 11 , resulting in uneven display of the display panel.

[0101] Based on the above technical problems, the inventors have found that by adjusting the winding of the winding area, it is beneficial to reduce the load difference of the wiring between the secondary screen area and the main screen area, thereby improving the display uniformity of the display panel. Based on this, the inventors have further studied the technical solution of the embodiment of the present application. The display panel provided by the embodiment of the present application includes a hole area, a winding area, a display area and a non-display area, the winding area is arranged around the hole area, and the display area is arranged around at least part of the winding area; wherein, the display panel also includes a first gate drive circuit, and the first gate drive circuit is located in the non-display area on one side of the display area; wherein, the first gate drive circuit includes a plurality of cascaded first gate drive units; the first gate drive unit provides a first scanning signal to two adjacent rows of pixel circuits through two first signal transmission lines respectively; wherein, the first scanning signal affects the gate potential of the driving transistor in the pixel circuit; the first signal transmission line is partially located in the winding area, and the parts of each first signal transmission line located in the winding area are independent of each other.

[0102] By adopting the above technical solution, the routing distribution of the first signal transmission line in the display area and the winding area can be made close, thereby reducing the load difference of the first signal transmission line in the display area and the winding area. Since the first signal transmission line can transmit the first scanning signal, the first scanning signal affects the gate potential of the driving transistor in the pixel circuit. Therefore, the gate potential difference of the driving transistor in the winding area and the display area can be reduced, thereby improving display uniformity.

[0103] The above is the core concept of this application. The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0104] Figure 2 is a schematic diagram of the planar structure of a display panel provided by an exemplary embodiment of the present application; Figure 3 is a schematic diagram of the planar structure of the area around the hole area in Figure 2; and Figure 4 is a schematic diagram of the planar structure of another display panel provided by an embodiment of the present application. As shown in Figures 2 and 3, the display panel provided by the embodiment of the present application includes: a hole area 22, a winding area 24, a display area 21 and a non-display area 23. The winding area 24 is arranged around the hole area 22, and the display area 21 is arranged around at least part of the winding area 24. A winding is provided in the winding area 24 to avoid the hole area 22 connecting the signal lines on both sides of the winding area 24. As shown in Figure 4, the display panel also includes a first gate drive circuit 231. The first gate drive circuit 231 is located in the non-display area 23 on one side of the display area 21.

[0105] The first gate driving circuit 231 includes a plurality of cascaded first gate driving units 2311. It should be noted that the cascade connection can be understood as a stage-by-stage connection along the column direction, with the number of stages increasing from top to bottom.

[0106] Each first gate driving unit 2311 provides a first scanning signal to two rows of pixel circuits 210 via two first signal transmission lines 211. For example, the i-th level first gate driving unit 2311 provides a first scanning signal to the 2i-1 and 2i-th rows of pixel circuits 210 via two first signal transmission lines 211, where i is a positive integer greater than or equal to 1. Thus, the first gate driving units 2311 employ a 1-drive-2 design, reducing the number of first gate driving units 2311 in the non-display area 23 and thus reducing the area occupied by the gate driving units in the border, thereby achieving a narrow border.

[0107] The first scanning signal affects the gate potential of the driving transistor in the pixel circuit 210. The first scanning signal can be provided to the threshold compensation control terminal in the pixel circuit 210 to control the threshold compensation process and data writing process of the driving transistor.

[0108] In the embodiment of the present application, the first signal transmission lines 211 are partially located in the winding area 24, and the portions of the first signal transmission lines 211 located in the winding area 24 are independent of each other. In the related art, however, the portions of the first signal transmission lines located in the winding area are shared. As a result, the routing methods of the winding area and the display area are significantly different, resulting in uneven display on the display panel.

[0109] In the display panel of the embodiment of the present application, the portions of the first signal transmission lines 211 located in the winding area 211 are independent of each other, so that the routing distribution of the first signal transmission lines 211 in the display area 21 and the winding area 24 are close, thereby reducing the load difference between the first signal transmission lines 211 and the second signal transmission lines in the display area 21 and the target area 25. Among them, the target area 25 is the area between the first tangent line 251 and the second tangent line 252. The first tangent line 251 and the second tangent line 252 are different line segments. The first tangent line 251 and the second tangent line 252 both extend in the row direction and are tangent to the winding area 24 respectively. Since the first signal transmission line 211 can transmit the first scanning signal, the first scanning signal affects the gate potential of the driving transistor in the pixel circuit 210. Therefore, the gate potential difference between the driving transistor in the target area 25 and the display area 21 can be reduced, thereby improving display uniformity.

[0110] The display panel includes a hole area 22, a winding area 24, a display area 21 and a non-display area 23, the winding area 24 is arranged around the hole area 22, and the display area 21 is arranged around at least part of the winding area 24; wherein the display panel further includes a first gate driving circuit 231, the first gate driving circuit 231 is located in the non-display area 23 on one side of the display area 21, and the first gate driving circuit 231 includes a plurality of cascaded first gate driving units 2311; since each first gate driving unit 2311 provides a first scanning signal to two rows of pixel circuits 210 respectively through two first signal transmission lines 211, each first signal The portions of the first signal transmission lines 211 located in the winding area 24 are independent of each other, and there is no common line segment among the first signal transmission lines 211 in the winding area 24. The routing distributions of the first signal transmission lines 211 in the display area 21 and the winding area 24 are close, thereby reducing the load difference of the first signal transmission lines 211 in the display area 21 and the winding area 24. Since the first signal transmission lines 211 can transmit the first scanning signal, the first scanning signal affects the gate potential of the driving transistor in the pixel circuit 210. Therefore, the gate potential difference of the driving transistor in the target area 25 and the display area 21 can be reduced, thereby improving display uniformity.

[0111] In one embodiment, as shown in FIG4 , the first signal transmission line 211 of the target area includes a first line segment A 2111, a first winding line 2112, and a first line segment B 2113, which are electrically connected in sequence. The first winding line 2112 is located in the winding area 24 , and the first line segment A 2111 and the first line segment B 2113 are respectively located in the display area 21 on both sides of the winding area 24 . The first line segment A 2111 and the first line segment B 2113 are connected via the first winding line 2112 , so that the first scanning signal output by the first gate driving unit 2311 can be transmitted to the pixel circuits 210 on both sides of the winding area 24 .

[0112] FIG5 is a schematic diagram of a planar structure of another display panel provided in an exemplary embodiment of the present application. As shown in FIG5 , the display panel further includes a second gate driver circuit 232 , which is located in the non-display area 23 on the other side of the display area 21 . That is, the first gate driver circuit 231 and the second gate driver circuit 232 are located in the non-display area 23 on both sides of the display area 21 .

[0113] The second gate driving circuit 232 includes a plurality of cascaded second gate driving units 2321 .

[0114] The second gate driving unit 2321 at the same level as the first gate driving unit 2311 provides a second scanning signal to two rows of pixel circuits 210 via two second signal transmission lines. For example, the first gate driving unit 2311 at the i-th level provides a first scanning signal to the pixel circuits 210 in the 2i-1 and 2i rows via two first signal transmission lines 211; the second gate driving unit 2321 at the i-th level provides a second scanning signal to the pixel circuits 210 in the 2i-1 and 2i rows via two second signal transmission lines, where i is a positive integer greater than or equal to 1. In this way, both the first gate driving unit 2311 and the second gate driving unit 2321 adopt a 1-drive-2 design, reducing the number of first gate driving units 2311 and second gate driving units 2321 in the non-display area 23, thereby reducing the area occupied by the gate driving units in the frame and achieving a narrow frame.

[0115] The second scanning signal is different from the first scanning signal and affects the gate potential of the driving transistor in the pixel circuit 210. The second scanning signal can be provided to the initialization control terminal of the gate potential of the driving transistor in the pixel circuit 210 to control the initialization process of the gate potential of the driving transistor.

[0116] The second signal transmission lines 212 are partially located in the winding area 24, and the portions of the second signal transmission lines 212 located in the winding area 24 are independent of each other. In the related art, however, the portions of the second signal transmission lines located in the winding area are shared. As a result, the routing methods of the winding area and the display area are significantly different, resulting in uneven display on the display panel.

[0117] The above-mentioned arrangement is adopted in this embodiment, which can make the routing distribution of the second signal transmission line 212 in the display area 21 and the winding area 24 close, thereby reducing the load difference of the second signal transmission line 212 in the display area 21 and the winding area 24. In addition, the second signal transmission line 212 can transmit the second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit 210. Therefore, the gate potential difference of the driving transistor in the target area 25 and the display area 21 can be reduced, thereby improving display uniformity.

[0118] In one embodiment, as shown in Figure 5, the second signal transmission line of the target area 25 includes a second line segment A 2121, a second winding 2122 and a second line segment B 2123 that are electrically connected in sequence; wherein, the second winding 2122 is located in the winding area 24, and the second line segment A 2121 and the second line segment B 2123 are respectively located in the display area 21 on both sides of the winding area 24, so that the second line segment A 2121 and the second line segment B 2123 are connected through the second winding 2122, so that the second scanning signal output by the second gate driving unit 2321 can be transmitted to the pixel circuits 210 on both sides of the winding area 24.

[0119] FIG6 is a schematic diagram of the structure of a pixel circuit provided in an exemplary embodiment of the present application; FIG7 is a schematic diagram of the structure of another pixel circuit provided in an exemplary embodiment of the present application. In one embodiment, as shown in FIG6 and FIG7, the pixel circuit 210 includes: a driving transistor T3, a storage capacitor Cst, a threshold compensation module 2101 and a first initialization module 2102. It should be noted that in FIG6, N_Gate is the first scan signal, N_Reset is the second scan signal, P_Gate is the third scan signal, H_Reset is the fourth scan signal, EM is the light-emitting control signal, ELVDD is the first power signal, and ELVSS is the second power signal. In FIG7, NGate is the first scan signal, P_Reset is the second scan signal, PGate is the third scan signal, H_Reset is the fourth scan signal, EM is the light-emitting control signal, ELVDD is the first power signal, and ELVSS is the second power signal.

[0120] The driving transistor T3 is used to provide a driving current to the light emitting element.

[0121] A first terminal of the storage capacitor Cst is used to receive a first power signal, and a second terminal of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0122] The first end of the threshold compensation module 2101 is connected to the second end of the driving transistor T3, the second end of the threshold compensation module 2101 is connected to the gate of the driving transistor T3, the control end of the threshold compensation module 2101 is connected to the second signal transmission line, and the control end of the threshold compensation module 2101 is used to receive the first scanning signal.

[0123] The first end of the first initialization module 2102 is used to receive a first initialization signal, the second end of the first initialization module 2102 is connected to the gate of the driving transistor T3 or the first end of the threshold compensation module 2101, the control end of the first initialization module 2102 is connected to the first signal transmission line 211, and the control end of the first initialization module 2102 is used to receive a second scanning signal.

[0124] If the second end of the first initialization module 2102 is connected to the gate of the driving transistor T3, then in the first initialization stage, the first initialization module 2102 is turned on in response to the second scanning signal, and the first initialization signal is written into the gate of the driving transistor T3 through the first end and the second end of the first initialization module 2102 to initialize the gate potential of the driving transistor T3.

[0125] If the second end of the first initialization module 2102 is connected to the first end of the threshold compensation module 2101, then in the first initialization stage, the first initialization module 2102 is turned on in response to the second scanning signal, and the threshold compensation module 2101 is turned on in response to the first scanning signal. The first initialization signal is written into the gate of the driving transistor T3 through the first and second ends of the first initialization module 2102 and the first and second ends of the threshold compensation module 2101, thereby initializing the gate potential of the driving transistor T3.

[0126] In the data writing phase, the threshold compensation module 2101 is turned on in response to the first scanning signal, and the data signal is written into the gate of the driving transistor T3 via the first terminal and the second terminal of the threshold compensation module 2101 .

[0127] It can be understood that both the second scanning signal and the first scanning signal affect the gate potential of the driving transistor T3 in the pixel circuit 210. Therefore, reducing the load difference between the first signal transmission line 211 and the second signal transmission line in the display area 21 and the winding area 24 can reduce the gate potential difference of the driving transistor T3 in the winding area 24 and the display area 21, thereby improving display uniformity.

[0128] 5 , the first signal transmission line 211 and the second signal transmission line 212 are located in different layers in the winding area 24 , that is, the second winding 2122 and the first winding 2112 are located in different layers.

[0129] It can be understood that by setting the second winding 2122 and the first winding 2112 in different layers, the windings in the same film layer can be avoided from being too dense, thereby providing a compressed space for the border area corresponding to the hole area 22, which is conducive to narrowing the border corresponding to the hole area 22 and improving the screen-to-body ratio of the display panel.

[0130] FIG8 is a schematic diagram of a planar structure of another display panel provided in an exemplary embodiment of the present application. As shown in FIG8 , in one embodiment, the display panel further includes a third gate drive circuit 233. The third gate drive circuit 233 includes a plurality of cascaded third-A gate drive units 2331 and a plurality of cascaded third-B gate drive units 2332. The third-A gate drive units 2331 and the third-B gate drive units 2332 are respectively located in the non-display area 23 on either side of the display area 21.

[0131] The third-A gate driving unit 2331 and the third-B gate driving unit 2332 provided at the same level provide a third scanning signal to the pixel circuits 210 in the same row via a third signal transmission line, wherein the third scanning signal affects the writing of data into the pixel circuits 210. Exemplarily, the third-A gate driving unit 2331 of the i-th level and the third-B gate driving unit 2332 of the i-th level provide the third scanning signal to the pixel circuits 210 in the i-th row via a third signal transmission line.

[0132] It can be understood that the display area 21 can be divided into two display sub-areas, one adjacent to the non-display area 23 on either side of the display area 21. The third gate driver unit 2331 provides the third scan signal to the pixel circuit 210 in the adjacent display sub-area. The third gate driver unit 2332 provides the third scan signal to the pixel circuit 210 in the other display sub-area. The third gate driver unit 2331 and the third gate driver unit 2332 can achieve bilateral drive, reducing the transmission distance of the third scan signal, thereby reducing the impact of signal line voltage drop and improving display uniformity.

[0133] In one embodiment, as shown in FIG6 and FIG7 , the pixel circuit 210 further includes a data writing module 2103. A first terminal of the data writing module 2103 is used to receive a data signal, a second terminal of the data writing module 2103 is connected to the first electrode of the driving transistor T3, and a control terminal of the data writing module 2103 is used to receive a third scanning signal.

[0134] It can be understood that during the data writing phase, the data writing module 2103 is turned on in response to the third scanning signal, the threshold compensation module 2101 is turned on in response to the first scanning signal, and the data signal is written to the gate of the driving transistor T3 via the first and second terminals of the data writing module 2103, the first and second terminals of the driving transistor T3, and the first and second terminals of the threshold compensation module 2101. The third scanning signal output by the third gate driving circuit 233 controls the data writing phase of the pixel circuit 210.

[0135] In the above embodiment, the third gate driver circuit 233 includes a plurality of cascaded third-A gate driver units 2331 and a plurality of cascaded third-B gate driver units 2332. The third-A gate driver units 2331 and the third-B gate driver units 2332 are respectively located in the non-display area 23 on either side of the display area 21. The third-A gate driver units 2331 and the third-B gate driver units 2332, which are arranged in the same level, provide the third scanning signal to the pixel circuits 210 in the same row via the third signal transmission line. Therefore, the third-A gate driver units 2331 and the third-B gate driver units 2332 can achieve bilateral driving. Furthermore, the third-A gate driver units 2331 and the third-B gate driver units 2332 both adopt a one-drive-one design, thereby minimizing the load difference of the third signal transmission line in the winding area 24 and the display area 21. This, in turn, helps reduce the gate potential difference of the driving transistor T3 in the winding area 24 and the display area 21, thereby improving display uniformity.

[0136] In one embodiment, as shown in Figure 8, the third signal transmission line of the target area 25 includes a third A line segment 2131 connected to the third A gate driving unit 2331, and a third B line segment 2132 connected to the third B gate driving unit 2332; the third A line segment 2131 and the third B line segment 2132 are respectively located in the display area 21 on both sides of the winding area 24.

[0137] It can be understood that the third A gate driving unit 2331 is connected to the third A line segment 2131, and the third B gate driving unit 2332 is connected to the third B line segment 2132. Then, the third A gate driving unit 2331 can provide a third scanning signal to the pixel circuit 210 on the side of the winding area 24 close to the third A gate driving unit 2331 through the third A line segment 2131, and the third B gate driving unit 2332 can provide a third scanning signal to the pixel circuit 210 on the other side of the winding area 24 through the third B line segment 2132. For a specific display panel (for example, a display panel in which the hole area 22 does not need to emit light), there is no need to connect the third A line segment 2131 and the third B line segment 2132 by winding, which is conducive to reducing the number of windings in the winding area 24, facilitating the narrowing of the frame corresponding to the hole area 22, and improving the screen-to-body ratio of the display panel.

[0138] FIG9 is a schematic diagram of a planar structure of another display panel provided in accordance with an exemplary embodiment of the present application. In one embodiment, as shown in FIG9 , the third signal transmission line in the target area 25 further includes a third winding 2133 connected to the third line segment A 2131 and the third line segment B 2132 , respectively. The third winding 2133 is located in the winding area 24 .

[0139] It can be understood that for the hole area 22 to serve as a secondary screen area, that is, the display panel that the hole area 22 needs to emit light, a third winding 2133 is required to connect the third A line segment 2131 and the third B line segment 2132, so as to provide a third scanning signal for the pixel circuit 210 of the hole area 22 to support the hole area 22 to emit light.

[0140] In one embodiment, as shown in FIG9 , the portion of the first signal transmission line 211 located in the winding area 24 is located on a different layer than the portion of the third signal transmission line 213 located in the winding area 24. That is, the third winding line 2133 and the first winding line 2112 can be located on different layers, and the third winding line 2133 can be located on the same layer as the second winding line 2122.

[0141] In the related art, the first scan signal and the third scan signal are often respectively provided to different types of transistors, and the signal lines providing the first scan signal and the third scan signal are often located in different layers.

[0142] In this embodiment, by arranging the third winding 2133 and the first winding 2112 in different layers and arranging the third winding 2133 and the second winding 2122 in the same layer, excessive changes in the manufacturing process of the display panel are avoided, thereby reducing the cost of improving the manufacturing process.

[0143] Figure 10 is a schematic diagram of the planar structure of another display panel provided in an exemplary embodiment of the present application; Figure 11 is a schematic diagram of the planar structure of another display panel provided in an exemplary embodiment of the present application. In one embodiment, as shown in Figures 10 and 11, the non-display area 23 further includes: a fourth gate drive circuit 234. The fourth gate drive circuit 234 can be located in the non-display area 23 on the same side of the display area 21 as the first gate drive circuit 231. The fourth gate drive circuit 234 includes a plurality of cascaded fourth gate drive units 2341.

[0144] Each fourth gate driving unit 2341 provides a fourth scanning signal to two rows of pixel circuits 210 via two fourth signal transmission lines. For example, the i-th stage fourth gate driving unit 2341 provides a fourth scanning signal to the 2i-1 and 2i-th rows of pixel circuits 210 via two fourth signal transmission lines. Thus, the fourth gate driving unit 2341 employs a 1-drive-2 design, reducing the number of fourth gate driving units 2341 in the non-display area 23 and thus reducing the area occupied by the gate driving units in the border, thereby achieving a narrow border.

[0145] The fourth scanning signal affects the first electrode potential of the driving transistor and the anode potential of the light-emitting element in the pixel circuit 210. The fourth scanning signal can control the initialization process of the first electrode potential of the driving transistor and the initialization process of the anode potential of the light-emitting element, thereby controlling the initialization process of the first electrode potential of the driving transistor and the initialization process of the anode potential of the light-emitting element through the fourth gate driving unit 2341.

[0146] In one embodiment, as shown in Figures 10 and 11, the fourth signal transmission line 214 of the target area 25 includes a fourth line segment A 2141 and a fourth line segment B 2143. One of the two fourth signal transmission lines 214 connected to each fourth gate driving unit 2341 further includes a fourth winding line 2142. The two fourth line segments 2141 are respectively connected to two fourth line segments B 2143 via a fourth winding line 2142. The fourth winding line 2142 is located in the winding area 24, and the fourth line segment A 2141 and the fourth line segment B 2143 are respectively located in the display area 21 on both sides of the winding area 24.

[0147] It can be understood that since the fourth scan signal affects the first electrode potential of the driving transistor in the pixel circuit 210 and the anode potential of the light-emitting element, the fourth scan signal has a relatively low impact on the gate potential of the driving transistor. Therefore, there may be a certain difference in the load of the fourth signal transmission line between the target area 25 and the normal area (the display area 21 excluding the target area 25). The two fourth A line segments 2141 can be connected to the two fourth B line segments 2143 via a fourth winding 2142, that is, the two fourth signal transmission lines can share a fourth winding 2142. This reduces the number of windings in the winding area 24, helps to narrow the frame corresponding to the hole area 22, and improves the screen-to-body ratio of the display panel.

[0148] In one embodiment, as shown in FIG. 10 and FIG. 11 , one of the second winding 2122 and the first winding 2112 and the fourth winding 2142 are located on the same layer, and the other of the second winding 2122 and the first winding 2112 and the fourth winding 2142 are located on different layers.

[0149] It can be understood that by arranging one of the second winding 2122 and the first winding 2112 on the same layer as the fourth winding 2142, and arranging the other of the second winding 2122 and the first winding 2112 on a different layer from the fourth winding 2142, it is possible to avoid the windings on the same film layer being too dense, thereby providing a compressed space for the border area corresponding to the hole area 22, which is conducive to narrowing the border corresponding to the hole area 22 and improving the screen-to-body ratio of the display panel.

[0150] In one embodiment, as shown in Figures 10 and 11, the non-display area 23 further includes a fifth gate driving circuit 235. The fifth gate driving circuit 235 and the second gate driving circuit 232 may be located in the non-display area 23 on the same side of the display area 21. The fifth gate driving circuit 235 includes a plurality of cascaded fifth gate driving units 2351.

[0151] Each fifth gate driving unit 2351 provides light-emitting control signals to two rows of pixel circuits 210 through two fifth signal transmission lines. For example, the i-th stage fifth gate driving unit 2351 provides light-emitting control signals to the 2i-1 and 2i-th rows of pixel circuits 210 through two fifth signal transmission lines.

[0152] The fifth gate driving unit 2351 adopts a 1-drive-2 design, which reduces the number of the fifth gate driving units 2351 in the non-display area 23 , thereby reducing the area occupied by the gate driving unit in the frame and achieving a narrow frame.

[0153] The light emitting control signal affects the light emitting element. The light emitting control signal can control the process of the pixel circuit 210 driving the light emitting element to emit light, thereby achieving light emitting control through the fifth gate driving unit 2351.

[0154] In one embodiment, as shown in Figures 10 and 11, the fifth signal transmission line of the target area 25 includes a fifth line segment A 2151 and a fifth line segment B 2153, wherein one of the two fourth signal transmission lines 214 connected to each fourth gate driving unit 2341 further includes a fourth winding line 2142. The two fifth line segments A 2151 are respectively connected to the two fifth line segments B 2153 via a fifth winding line 2152, wherein the fifth winding line 2152 is located in the winding area 24, and the fifth line segment A 2151 and the fifth line segment B 2153 are respectively located in the display area 21 on both sides of the winding area 24.

[0155] It can be understood that since the light-emitting control signal affects the light emission of the light-emitting element, the light-emitting control signal has a relatively low impact on the gate potential of the driving transistor. Therefore, there can be a certain difference in the load of the fifth signal transmission line between the target area 25 and the normal area (the display area 21 excluding the target area 25). The two fifth A line segments 2151 can be connected to the two fifth B line segments 2153 via a fifth winding 2152, that is, the two fifth signal transmission lines can share a fifth winding 2152. This reduces the number of windings in the winding area 24, helps to narrow the frame corresponding to the hole area 22, and improves the screen-to-body ratio of the display panel.

[0156] In one embodiment, as shown in FIG. 6 and FIG. 7 , the pixel circuit 210 further includes: a second initialization module 2104 , a third initialization module 2105 , a first light emission control module 2106 , and a second light emission control module 2107 .

[0157] A first terminal of the second initialization module 2104 is used to receive a second initialization signal, a second terminal of the second initialization module 2104 is connected to the gate of the driving transistor T3 , and a control terminal of the second initialization module 2104 is used to receive a fourth scanning signal.

[0158] In the second initialization stage, the second initialization module 2104 is turned on in response to the fourth scanning signal, and the second initialization signal is written into the anode of the light emitting element via the first and second terminals of the second initialization module 2104 to initialize the anode potential of the light emitting element.

[0159] A first terminal of the third initialization module 2105 is used to receive a third initialization signal, a second terminal of the third initialization module 2105 is connected to the first terminal of the driving transistor T3, and a control terminal of the third initialization module 2105 is used to receive a fourth scanning signal.

[0160] Before and after the data writing stage, the third initialization module 2105 is turned on in response to the fourth scanning signal, and the third initialization signal is written into the first electrode of the driving transistor T3 through the first end and the second end of the third initialization module 2105 to initialize the first electrode potential of the driving transistor T3.

[0161] A first terminal of the first light emitting control module 2106 is used to receive a first power supply signal, a second terminal of the first light emitting control module 2106 is connected to the first terminal of the driving transistor T3, and a control terminal of the first light emitting control module 2106 is used to receive a light emitting control signal.

[0162] A first end of the second light emitting control module 2107 is connected to the second end of the driving transistor T3 , a second end of the second light emitting control module 2107 is connected to the anode of the light emitting element, and a control end of the second light emitting control module 2107 is used to receive a light emitting control signal.

[0163] In the light emitting stage, the first light emitting control module 2106 and the second light emitting control module 2107 are turned on in response to the light emitting control signal, and the driving transistor T3 provides a driving current to the light emitting element, driving the light emitting element to emit light.

[0164] It can be understood that the fourth scanning signal and the light-emitting control signal have a relatively low impact on the data writing process. The fourth transmission line in the target area 25 and the normal area can have certain differences, and the load of the fifth signal transmission line in the target area 25 and the normal area can also have certain differences. Therefore, the two fourth A line segments 2141 can be connected to the two fourth B line segments 2143 via a fourth winding 2142, that is, the two fourth signal transmission lines can share a fourth winding 2142. The two fifth A line segments 2151 can be connected to the two fifth B line segments 2153 via a fifth winding 2152, that is, the two fifth signal transmission lines can share a fifth winding 2152. This reduces the number of windings in the winding area 24, which is conducive to narrowing the frame corresponding to the hole area 22 and improving the screen-to-body ratio of the display panel.

[0165] In one embodiment, as shown in FIG. 10 and FIG. 11 , one of the second winding 2122 and the first winding 2112 and the fifth winding 2152 are located on the same layer, and the other of the second winding 2122 and the first winding 2112 and the fifth winding 2152 are located on a different layer.

[0166] It can be understood that by arranging one of the second winding 2122 and the first winding 2112 on the same layer as the fifth winding 2152, and arranging the other of the second winding 2122 and the first winding 2112 on a different layer from the fifth winding 2152, it is possible to avoid the windings on the same film layer being too dense, thereby providing a compressed space for the border area corresponding to the hole area 22, which is conducive to narrowing the border corresponding to the hole area 22 and improving the screen-to-body ratio of the display panel.

[0167] In one embodiment, a display panel includes a substrate and a drive circuit layer, the drive circuit layer including a first gate layer CE1 and a second gate layer CE2. The second winding 2122 is located on the first gate layer CE1, and the first winding 2112 is located on the second gate layer CE2. Placing the second winding 2122 and the first winding 2112 on different layers prevents excessive density of windings on the same layer, providing space for compressing the border area corresponding to the aperture area 22. This helps narrow the border corresponding to the aperture area 22 and improves the screen-to-body ratio of the display panel.

[0168] Based on the above embodiment, as shown in FIG10 , in one example, if the third signal transmission line in the target area 25 includes a third A segment 2131 connected to the third A gate driver unit 2331, and a third B segment 2132 connected to the third B gate driver unit 2332; the third A segment 2131 and the third B segment 2132 are respectively located in the display area 21 on either side of the winding area 24. That is, the third A segment 2131 and the third B segment 2132 are not connected by a winding. Then, the second winding 2122 is located on the first gate layer CE1, the first winding 2112 is located on the second gate layer CE2, and the fourth winding 2142 and the fifth winding 2152 are located on different layers. For example, the fourth winding 2142 is located on the first gate layer CE1, and the fifth winding 2152 is located on the second gate layer CE2. For another example, the fifth winding 2152 is located on the first gate layer CE1, and the fourth winding 2142 is located on the second gate layer CE2. Since the number of the second winding 2122 and the first winding 2112 is substantially the same, and the number of the fourth winding 2142 and the fifth winding 2152 is substantially the same, the above setting can make the film layer of the winding distribution more uniform, which is conducive to narrowing the frame corresponding to the hole area 22.

[0169] Based on the above embodiment, as shown in FIG11 , in another example, if the third signal transmission line of the target area 25 includes a third A segment 2131, a third winding 2133, and a third B segment 2132 electrically connected in sequence, and the third winding 2133 is located in the winding area 24 , then the second winding 2122 and the third winding 2133 are located in the first gate layer CE1, and the first winding 2112, the fourth winding 2142, and the fifth winding 2152 are located in the second gate layer CE2. Since the number of second windings 2122 and the first winding 2112 is substantially the same, and the sum of the number of fourth windings 2142 and the fifth winding 2152 is substantially the same as the number of third windings 2133, this arrangement can achieve a more uniform distribution of windings across the film layer, facilitating a narrowing of the border corresponding to the aperture area 22.

[0170] In one embodiment, the display panel includes a substrate and a driving circuit layer, the driving circuit layer includes multiple rows of pixel circuits 210 arranged in a column direction, wherein the number of winding projections in the first area is the same as the number of winding projections in the second area, and the first area and the second area are respectively the projection areas of two rows of pixel circuits 210 in the target area 25 on the substrate.

[0171] It can be understood that by making the number of winding projections in the first area the same as the number of winding projections in the second area, the winding distribution in the winding area 24 can be made uniform, avoiding the mura (uneven display) problem caused by uneven winding distribution in the winding area 24.

[0172] Based on the above embodiments, as shown in Figure 6, in one example, the threshold compensation module 2101 may include a threshold compensation transistor T2, the first initialization module 2102 may include a first initialization transistor T1, the data writing module 2103 may include a data writing transistor T4, the second initialization module 2104 may include a second initialization transistor T7, the third initialization module 2105 may include a third initialization transistor T8, the first light-emitting control module 2106 may include a first light-emitting control transistor T5, and the second light-emitting control module 2107 may include a second light-emitting control transistor T6.

[0173] The pixel circuit 210 includes a driving transistor T3, a storage capacitor Cst, a threshold compensation transistor T2, a first initialization transistor T1, a data writing transistor T4, a second initialization transistor T7, a third initialization transistor T8, a first emission control transistor T5 and a second emission control transistor T6.

[0174] The driving transistor T3 is used to provide a driving current to the light emitting element.

[0175] A first terminal of the storage capacitor Cst is used to receive a first power signal, and a second terminal of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0176] The first electrode of the threshold compensation transistor T2 is connected to the second end of the driving transistor T3, the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, the gate of the threshold compensation transistor T2 is connected to the second signal transmission line, and the gate of the threshold compensation transistor T2 is used to receive the first scanning signal.

[0177] The first electrode of the first initialization transistor T1 is used to receive the first initialization signal, the second electrode of the first initialization transistor T1 is connected to the gate of the driving transistor T3, the gate of the first initialization transistor T1 is connected to the first signal transmission line 211, and the gate of the first initialization transistor T1 is used to receive the second scanning signal.

[0178] A first electrode of the data writing transistor T4 is used to receive a data signal, a second electrode of the data writing transistor T4 is connected to a first electrode of the driving transistor T3 , and a gate of the data writing transistor T4 is used to receive a third scanning signal.

[0179] A first electrode of the second initialization transistor T7 is used to receive a second initialization signal, a second electrode of the second initialization transistor T7 is connected to the gate of the driving transistor T3 , and a gate of the second initialization transistor T7 is used to receive a fourth scan signal.

[0180] A first electrode of the third initialization transistor T8 is used to receive a third initialization signal, a second electrode of the third initialization transistor T8 is connected to the first end of the driving transistor T3 , and a gate of the third initialization transistor T8 is used to receive a fourth scan signal.

[0181] The first electrode of the first light emitting control transistor T5 is used to receive the first power supply signal, the second electrode of the first light emitting control transistor T5 is connected to the first end of the driving transistor T3, and the gate of the first light emitting control transistor T5 is used to receive the light emitting control signal.

[0182] A first electrode of the second light emitting control transistor T6 is connected to the second end of the driving transistor T3 , a second electrode of the second light emitting control transistor T6 is connected to the anode of the light emitting element, and a gate of the second light emitting control transistor T6 is used to receive a light emitting control signal.

[0183] Based on the above embodiments, as shown in Figure 7, in another example, the pixel circuit 210 includes a driving transistor T3, a storage capacitor Cst, a threshold compensation transistor T2, a first initialization transistor T1, a data writing transistor T4, a second initialization transistor T7, a third initialization transistor T8, a first light-emitting control transistor T5 and a second light-emitting control transistor T6.

[0184] The driving transistor T3 is used to provide a driving current to the light emitting element.

[0185] A first terminal of the storage capacitor Cst is used to receive a first power signal, and a second terminal of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0186] The first electrode of the threshold compensation transistor T2 is connected to the second end of the driving transistor T3, the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, the gate of the threshold compensation transistor T2 is connected to the second signal transmission line, and the gate of the threshold compensation transistor T2 is used to receive the first scanning signal.

[0187] The first electrode of the first initialization transistor T1 is used to receive the first initialization signal, the second electrode of the first initialization transistor T1 is connected to the first electrode of the threshold compensation transistor T2, the gate of the first initialization transistor T1 is connected to the first signal transmission line 211, and the gate of the first initialization transistor T1 is used to receive the second scan signal.

[0188] A first electrode of the data writing transistor T4 is used to receive a data signal, a second electrode of the data writing transistor T4 is connected to a first electrode of the driving transistor T3 , and a gate of the data writing transistor T4 is used to receive a third scanning signal.

[0189] A first electrode of the second initialization transistor T7 is used to receive a second initialization signal, a second electrode of the second initialization transistor T7 is connected to the gate of the driving transistor T3 , and a gate of the second initialization transistor T7 is used to receive a fourth scan signal.

[0190] A first electrode of the third initialization transistor T8 is used to receive a third initialization signal, a second electrode of the third initialization transistor T8 is connected to the first end of the driving transistor T3 , and a gate of the third initialization transistor T8 is used to receive a fourth scan signal.

[0191] The first electrode of the first light emitting control transistor T5 is used to receive the first power supply signal, the second electrode of the first light emitting control transistor T5 is connected to the first end of the driving transistor T3, and the gate of the first light emitting control transistor T5 is used to receive the light emitting control signal.

[0192] A first electrode of the second light emitting control transistor T6 is connected to the second end of the driving transistor T3 , a second electrode of the second light emitting control transistor T6 is connected to the anode of the light emitting element, and a gate of the second light emitting control transistor T6 is used to receive a light emitting control signal.

[0193] FIG12 is a schematic diagram of the structure of a display screen 200 provided in an embodiment of the present application. This embodiment of the present application further provides a display screen 200. Referring to FIG12 , the display screen 200 includes a cover plate 2100 and the display panel 20 provided in the aforementioned embodiment. The cover plate 2100 can be disposed on the light-emitting side of the display panel 10 to protect the display panel 20.

[0194] Based on the same application concept, an embodiment of the present application further provides an electronic device. Figure 13 is a schematic structural diagram of an electronic device 30 provided in an embodiment of the present application. As shown in Figure 13, the electronic device 30 includes the display screen 200 of the above embodiment. Because the display screen 200 includes a cover plate 2100 and the display panel 20 provided in the above embodiment, the electronic device 30 also has the beneficial effects of the display panel 20 of the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 20, and will not be repeated below.

[0195] The electronic device 30 provided in the embodiment of the present application can be the mobile phone shown in Figure 13, or it can be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiment of the present application does not specifically limit this.

[0196] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0197] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A display panel, wherein: include: A hole area, a winding area, a display area and a non-display area, wherein the winding area is arranged around the hole area, and the display area is arranged around at least a part of the winding area; wherein the display panel further comprises a first gate driving circuit, and the first gate driving circuit is located in the non-display area on one side of the display area; wherein, The first gate driving circuit includes a plurality of first gate driving units; The first gate driving unit provides a first scanning signal to two adjacent rows of pixel circuits through two first signal transmission lines respectively; wherein the first scanning signal affects the gate potential of the driving transistor in the pixel circuit; The first signal transmission line portion is located in the winding area, and the first signal transmission line portions located in the winding area are independent of each other.

2. The display panel according to claim 1, wherein: The first signal transmission line includes a first line segment A, a first winding line and a first line segment B which are electrically connected in sequence; wherein the first winding line is located in the winding area, and the first line segment A and the first line segment B are respectively located in the display area on both sides of the winding area.

3. The display panel according to claim 1, wherein: The display panel further includes a second gate driving circuit, the second gate driving circuit is located in a non-display area on the other side of the display area, and the second gate driving circuit includes a plurality of cascaded second gate driving units. The second gate driving unit at the same level as the first gate driving unit provides second scanning signals to the two adjacent rows of pixel circuits through two second signal transmission lines; wherein the second scanning signal is different from the first scanning signal, the second scanning signal affects the gate potential of the driving transistor in the pixel circuit, and the second signal transmission line is partially located in the winding area, and the parts of each second signal transmission line located in the winding area are independent of each other.

4. The display panel according to claim 3, wherein: The second signal transmission line includes a second A line segment, a second winding line, and a second B line segment electrically connected in sequence; wherein the second winding line is located in the winding area, and the second A line segment and the second B line segment are respectively located in the display area on both sides of the winding area.

5. The display panel according to claim 3, wherein: The portion of the first signal transmission line located in the winding area is located in a different layer from the portion of the second signal transmission line located in the winding area.

6. The display panel according to claim 1, wherein: The display panel further includes: A third gate driving circuit, the third gate driving circuit comprising a plurality of cascaded third A gate driving units and a plurality of cascaded third B gate driving units; wherein the third A gate driving units and the third B gate driving units are respectively located in non-display areas on both sides of the display area; wherein, The third gate driving unit A and the third gate driving unit B arranged at the same level provide a third scanning signal for the pixel circuits in the same row through a third signal transmission line, wherein the third scanning signal affects the data writing of the pixel circuits.

7. The display panel according to claim 6, wherein: The third signal transmission line includes a third A line segment connected to the third A gate driving unit, and a third B line segment connected to the third B gate driving unit; the third A line segment and the third B line segment are connected, and the third A line segment and the third B line segment are respectively located in the display area on both sides of the winding area.

8. The display panel according to claim 6, wherein: The third signal transmission line includes a third A line segment, a third winding line and a third B line segment electrically connected in sequence, wherein the third A line segment and the third B line segment are respectively located in the display area on both sides of the winding area, and the third winding line is located in the winding area.

9. The display panel according to claim 6, wherein: The portion of the first signal transmission line located in the winding area and the portion of the third signal transmission line located in the winding area are located in different layers.

10. The display panel according to claim 6, wherein: The portion of the third signal transmission line located in the winding area is arranged in the same layer as the portion of the second signal transmission line located in the winding area, wherein: The second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

11. The display panel according to claim 1, wherein: The non-display area also includes: a fourth gate driving circuit, the fourth gate driving circuit comprising a plurality of cascaded fourth gate driving units; Each of the fourth gate driving units provides fourth scanning signals to two rows of pixel circuits respectively through two fourth signal transmission lines; wherein the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element.

12. The display panel according to claim 11, wherein: The two fourth signal transmission lines respectively include a fourth A line segment and a fourth B line segment, and one of the two fourth signal transmission lines also includes a fourth winding wire; wherein the two fourth A line segments are respectively connected to the corresponding two fourth B line segments through a fourth winding wire, the fourth winding wire is located in the winding area, and the fourth A line segment and the fourth B line segment are respectively located in the display area on both sides of the winding area.

13. The display panel according to claim 12, wherein: One of the second winding and the first winding is located at the same layer as the fourth winding, and the other of the second winding and the first winding is located at a different layer from the fourth winding; Wherein, the first winding is the portion of the first signal transmission line located in the winding area; The second winding is a portion of the second signal transmission line located in the winding area, and the second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

14. The display panel according to claim 1, wherein: The non-display area also includes: a fifth gate driving circuit, the fifth gate driving circuit comprising a plurality of cascaded fifth gate driving units; Each of the fifth gate driving units provides light-emitting control signals for two rows of pixel circuits through two fifth signal transmission lines, wherein the light-emitting control signals affect the light-emitting of the light-emitting elements.

15. The display panel according to claim 14, wherein: The two fifth signal transmission lines respectively include a fifth A line segment and a fifth B line segment, and one of the two fifth signal transmission lines also includes a fifth winding; the two fifth A line segments are respectively connected to the two fifth B line segments through a fifth winding, wherein the fifth winding is located in the winding area, and the fifth A line segment and the fifth B line segment are respectively located in the display area on both sides of the winding area.

16. The display panel according to claim 14, wherein: The fifth gate driving circuit and the second gate driving circuit are located in the non-display area on the same side of the display area, and the second gate driving circuit is used to provide a second scanning signal; wherein the second scanning signal affects the gate potential of the driving transistor in the pixel circuit.

17. The display panel according to claim 14, wherein: One of the second winding and the first winding is located at the same layer as the fifth winding, and the other of the second winding and the first winding is located at a different layer from the fifth winding; wherein, the first winding is the portion of the first signal transmission line located in the winding area, and the second winding is the portion of the second signal transmission line located in the winding area.

18. The display panel according to claim 1, wherein: The display panel comprises: substrate; and A driving circuit layer, the driving circuit layer comprising a first gate layer and a second gate layer; The portion of the first signal transmission line located in the winding area is located in the second gate layer, and the portion of the second signal transmission line located in the winding area is located in the first gate layer.

19. The display panel according to claim 18, wherein: The third signal transmission line includes a third line segment A and a third line segment B connected in sequence, and the third line segment A and the third line segment B are respectively located in the display area on both sides of the winding area, and the third signal transmission line is used to transmit a third scanning signal, and the third scanning signal affects the data writing of the pixel circuit; One of the fourth winding and the fifth winding is located at the first gate layer, and the other of the fourth winding and the fifth winding is located at the second gate layer; The fourth winding is a portion of the fourth signal transmission line located in the winding area, and the fourth signal transmission line is used to transmit a fourth scanning signal, and the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element; The fifth winding is a portion of the fifth signal transmission line located in the winding area, and the fifth signal transmission line is used to transmit a light emitting control signal.

20. The display panel according to claim 18, wherein: The third signal transmission line comprises a third line segment A, a third winding line and a third line segment B which are electrically connected in sequence; the third signal line is used to transmit a third scanning signal, and the third scanning signal affects the data writing of the pixel circuit; The second winding and the third winding are respectively located at the first gate layer, and the first winding, the fourth winding and the fifth winding are respectively located at the second gate layer; The first winding is a portion of the first signal transmission line located in the winding area; The second winding is a portion of the second signal transmission line located in the winding area, the second signal transmission line is used to transmit a second scanning signal, and the second scanning signal affects the gate potential of the driving transistor in the pixel circuit; The third winding is a portion of the third signal transmission line located in the winding area, the third signal transmission line is used to transmit a third scanning signal, and the second scanning signal affects the data writing of the pixel circuit; The fourth winding is a portion of the fourth signal transmission line located in the winding area, and the fourth signal transmission line is used to transmit a fourth scanning signal, and the fourth scanning signal affects the first electrode potential of the driving transistor in the pixel circuit and the anode potential of the light-emitting element; The fifth winding is a portion of the fifth signal transmission line located in the winding area, and the fifth signal transmission line is used to transmit a light emitting control signal.

21. The display panel according to any one of claims 1 to 20, wherein: The display panel includes a substrate and a driving circuit layer, the driving circuit layer includes multiple rows of pixel circuits arranged in a column direction, wherein the number of winding projections in the first area is the same as the number of winding projections in the second area, and the first area and the second area are respectively the projection areas of two rows of pixel circuits in the target area on the substrate.

22. The display panel according to claim 21, wherein: The pixel circuit comprises: A driving transistor, used for providing a driving current to the light emitting element; A storage capacitor, wherein a first end of the storage capacitor is used to receive a first power supply signal, and a second end of the storage capacitor is connected to the gate of the driving transistor; a threshold compensation module, wherein a first end of the threshold compensation module is connected to a second end of the driving transistor, a second end of the threshold compensation module is connected to a gate of the driving transistor, and a control end of the threshold compensation module is used to receive the first scanning signal; A first initialization module, wherein a first end of the first initialization module is used to receive a first initialization signal, a second end of the first initialization module is connected to the gate of the driving transistor, and a control end of the first initialization module is used to receive a second scanning signal.

23. The display panel according to claim 21, wherein: The pixel circuit comprises: A driving transistor, used for providing a driving current to the light emitting element; A storage capacitor, wherein a first end of the storage capacitor is used to receive a first power supply signal, and a second end of the storage capacitor is connected to the gate of the driving transistor; a threshold compensation module, wherein a first end of the threshold compensation module is connected to a second end of the driving transistor, a second end of the threshold compensation module is connected to a gate of the driving transistor, and a control end of the threshold compensation module is used to receive the first scanning signal; A first initialization module, wherein a first end of the first initialization module is used to receive a first initialization signal, a second end of the first initialization module is connected to a first end of the threshold compensation module, and a control end of the first initialization module is used to receive a second scanning signal.

24. The display panel according to claim 22 or 23, wherein: The pixel circuit further includes: A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to a first electrode of the driving transistor, and a control end of the data writing module is used to receive a third scanning signal.

25. The display panel according to claim 24, wherein: The pixel circuit further includes: A second initialization module, wherein a first end of the second initialization module is used to receive a second initialization signal, a second end of the second initialization module is connected to the gate of the driving transistor, and a control end of the second initialization module is used to receive a fourth scanning signal; a third initialization module, wherein a first end of the third initialization module is used to receive a third initialization signal, a second end of the third initialization module is connected to the first end of the driving transistor, and a control end of the third initialization module is used to receive a fourth scanning signal; a first light-emitting control module, wherein a first end of the first light-emitting control module is used to receive a first power supply signal, a second end of the first light-emitting control module is connected to the first end of the driving transistor, and a control end of the first light-emitting control module is used to receive a light-emitting control signal; A second light-emitting control module, wherein a first end of the second light-emitting control module is connected to a second end of the driving transistor, a second end of the second light-emitting control module is connected to an anode of the light-emitting element, and a control end of the second light-emitting control module is used to receive a light-emitting control signal.

26. A display screen, wherein: The invention comprises a cover plate and the display panel according to any one of claims 1 to 25.

27. An electronic device, wherein: Comprising the display screen as claimed in claim 26.

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