Semiconductor integrated circuit device

Abstract

In the present invention, a standard cell comprises: power supply wiring (11, 21) formed in a back surface wiring layer; and a via (61) that is formed in a region where a region serving as a source of a transistor (P1) in an active region (2P1) and the power supply wiring (11) overlap, and that connects the source in the active region (2P1) and the power supply wiring (11). A surface on one side in a Y direction of a nanosheet (21) is exposed from gate wiring (31). A surface on the other side in the Y direction of a nanosheet (22) is exposed from gate wiring (32). The via (61) is disposed in a central portion in the Y direction of the active region (2P1) in plan view.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, also simply referred to as a cell, as appropriate) that includes a fork-sheet transistor.

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a gate electrode in a fork shape, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 1 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0005] US Patent Application Publication No. 2022 / 0246644 US Patent Application Publication No. 2022 / 0375761

[0006] Incidentally, Japanese Patent Application Laid-Open No. 2003-144999 discloses a standard cell in which a backside wiring is provided on the backside immediately below a transistor in order to reduce the area of ​​the semiconductor integrated circuit device, and the source and drain of the transistor are connected to this wiring.

[0007] However, no specific study has been done on standard cells using fork-sheet transistors and backside wiring.

[0008] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including standard cells using fork-sheet transistors and backside wiring.

[0009] A first aspect of the present disclosure is a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises a first active region including a first nanosheet extending in a first direction as the channel, the first nanosheet constituting the channel, source, and drain of a first transistor of a first conductivity type, the channel being a different conductivity type from the first conductivity type; a second active region including a second nanosheet extending in the first direction as the channel, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; and a second gate wiring extending in the second direction and surrounding an outer periphery of the first nanosheet in the second direction and in the third direction. a first power supply wiring formed on the back side of the first transistor and extending in the first direction; a second power supply wiring formed on the back side of the second transistor and extending in the first direction; and a first via formed in a region of the first active region where a region serving as a source of the first transistor and the first power supply wiring overlap, connecting the source in the first active region to the first power supply wiring, wherein the second nanosheet is arranged on a first side that is one side of the first nanosheet in the second direction, a surface of the first nanosheet on the first side being exposed from the first gate wiring, and a surface of the second nanosheet on the other side in the second direction being exposed from the second gate wiring, and the first via is arranged in a center of the first active region in the second direction.

[0010] According to the present disclosure, the first and second nanosheets have their surfaces facing the second direction exposed from the first and second gate wirings, respectively. This reduces the distance in the second direction between the first and second active regions within the first standard cell. Furthermore, the first via connecting the first power supply wiring to the portion of the first active region that serves as the source of the first transistor is positioned in the center of the first active region in the second direction in a plan view. This makes the distances from the first via to both ends of the portion of the first active region that serves as the source of the first transistor in the second direction equal, thereby equalizing the current flowing through the first transistor on both sides in the second direction. This allows for a smaller area and higher speed of the semiconductor integrated circuit device.

[0011] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in a first direction; a second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel including a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; a second gate wiring extending in the second direction and surrounding an outer periphery of the first nanosheet in the second direction and in the third direction; the second nanosheet is disposed on a first side, which is one side in the second direction, of the first nanosheet, a surface on the first side of the first nanosheet being exposed from the first gate wiring, and a surface on the second side, which is the other side in the second direction, of the second nanosheet being exposed from the second gate wiring, and an overlap amount of the first active region with the first via is greater than an overlap amount of the first power supply wiring with the first via in the second direction.

[0012] A third aspect of the present disclosure is a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises a first active region including a first nanosheet extending in a first direction as the channel, constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a channel, a source, and a drain of a second nanosheet extending in the first direction, the channel being a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a channel, a source, and a drain of a second nanosheet extending in the first direction, a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction, and a second gate wiring extending in the second direction and surrounding an outer periphery of the second nanosheet in the second direction and in the third direction. a first power supply wiring formed on the back side of the first transistor and extending in the first direction; a second power supply wiring formed on the back side of the second transistor and extending in the first direction; and a first via formed in a region of the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, connecting the source in the first active region to the first power supply wiring, wherein the second nanosheet is arranged on a first side that is one side of the first nanosheet in the second direction, and a surface of the first nanosheet on a second side that is the other side in the second direction is exposed from the first gate wiring, and a surface of the second nanosheet on the first side is exposed from the second gate wiring, and the first via is arranged in a center of the first active region in the second direction in a plan view.

[0013] According to the present disclosure, it is possible to reduce the area and increase the speed of a semiconductor integrated circuit device.

[0014] 7 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. FIG. 8 is a plan view showing an example of the layout structure of an inverter cell according to the first embodiment. FIG. 9 is a cross-sectional view of the inverter cell of FIG. 2. FIG. 10 is a circuit diagram of the inverter cell of FIG. 2. FIG. 11 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. FIG. 12 is a plan view showing an example of the layout structure of an inverter cell according to a modified example of the first embodiment. FIG. 13 is a plan view showing an example of the layout structure of a standard cell included in a first semiconductor integrated circuit device. FIG. 14 is a circuit diagram of the standard cell of FIG. 15. FIG. 16 is a plan view showing an example of the layout structure of a standard cell included in a first semiconductor integrated circuit device.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells, and at least some of the plurality of standard cells include fork sheet transistors, which are nanosheet FETs and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] (First Embodiment) (Circuit Block Configuration) Fig. 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. The block layout in Fig. 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a wiring layer provided on the back surface of a semiconductor chip on which transistors are formed.

[0018] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0019] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0020] In the layout of FIG. 1, a plurality of cells aligned in the X direction constitute a cell column CR (CR1 to CR3). A plurality of cell columns CR (three columns in FIG. 1) are aligned in the Y direction. The plurality of cells include cells with logic functions such as inverters, NAND gates, and NOR gates. For example, the cell column CR includes inverter cells C1 and C4, two-input NAND cells C2 and C5, and two-input NOR cells C3 and C6, which will be described later.

[0021] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0022] Each cell is configured with an active region 2P that forms the channel, source, and drain of a P-type transistor, and an active region 2N that forms the channel, source, and drain of an N-type transistor. In a cell row CR, the active regions 2P are arranged side by side in the X direction, and the active regions 2N are arranged side by side in the X direction. In cell rows CR adjacent in the Y direction, the active regions 2P are arranged facing each other, and the active regions 2N are arranged facing each other. The distance d1 in the Y direction between the active regions 2P and 2N within a cell is smaller than the distance d2 between the active regions 2P (2N) between cell rows CR.

[0023] In addition, in cell rows CR1 and CR3, the bottom ends of the active regions 2P in the Y direction on the drawing are aligned in the X direction, and the top ends of the active regions 2N in the Y direction on the drawing are aligned in the X direction in each cell. In cell row CR2, the bottom ends of the active regions 2N in the Y direction on the drawing are aligned in the X direction, and the top ends of the active regions 2P in the Y direction on the drawing are aligned in the X direction in each cell. That is, in cell row CR, the ends of the active regions 2P and 2N on opposing sides within the cell are aligned in the X direction so that they form a straight line.

[0024] (Configuration of inverter cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C4 according to the first embodiment, Fig. 3 is a cross-sectional view showing an example of the layout structure of the inverter cell according to the first embodiment, and Fig. 4 is a circuit diagram configured in the inverter cell according to the first embodiment. Specifically, Fig. 2(a) is a plan view of inverter cell C1, Fig. 2(b) is a plan view of inverter cell C4, Fig. 3(a) is a cross-section taken along X1-X1' in Fig. 2, Fig. 3(b) is a cross-section taken along Y1-Y1' in Fig. 2, and Fig. 3(c) is a cross-section taken along Y2-Y2' in Fig. 2.

[0025] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 3 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0026] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit having an input A and an output Y is configured.

[0027] 2, a wiring layer BM0 is formed on the back surface of the semiconductor chip on which the transistors are formed. Power supply wirings 11 and 12 are shared with other cells in the cell row CR including the inverter cell C1, and serve as power supply wirings extending in the X direction.

[0028] In the BM0 wiring layer, power supply wirings 11 and 12 are formed on both ends of the cell in the Y direction in the drawing, extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0029] An active region constituting the channel, source, and drain of the P-type transistor is formed in a P-type transistor region on an N-type well (NWell). Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0030] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2P1, the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0031] An active region constituting the channel, source, and drain of the N-type transistor is formed in an N-type transistor region on a P-type substrate (PSub) (not shown). Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 overlaps with the power supply wiring 12 in a plan view.

[0032] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a channel made of a nanosheet 22 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2N1, the source of the transistor N1 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in the region where the power supply wiring 12 and the active region 2N1 overlap in a planar view.

[0033] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0034] Gate wirings 31 and 32 extending in the Y direction are formed in the center of the cell in the X direction. The nanosheet 21 overlaps with the gate wiring 31 in a planar view. The nanosheet 22 overlaps with the gate wiring 32 in a planar view. The gate wiring 31 corresponds to the gate of the transistor P1. The gate wiring 32 corresponds to the gate of the transistor N1.

[0035] As shown in FIG. 3C, the gate wiring 31 covers the outer periphery of the nanosheet 21 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 21 is exposed. The gate wiring 32 covers the outer periphery of the nanosheet 22 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 22 is exposed. Specifically, the right side of the nanosheet 21 in the drawing is not covered by the gate wiring 31. The left side of the nanosheet 22 in the drawing is not covered by the gate wiring 32. That is, the right side of the nanosheet 21 in the drawing is exposed from the gate wiring 31. The left side of the nanosheet 22 in the drawing is exposed from the gate wiring 32. Therefore, in FIG. 2, the lower surface of the nanosheet 21 in the Y direction is exposed from the gate wiring 31, and the upper surface of the nanosheet 22 in the Y direction is covered by the gate wiring 31. The upper surface of the nanosheet 22 in the Y direction is exposed from the gate wiring 32, and the lower surface of the nanosheet 22 in the Y direction is covered by the gate wiring 32.

[0036] The gate wirings 31 and 32 are connected via a bridge portion 33 extending in the Y direction.

[0037] 2, dummy gate wirings 34 and 35 are formed on both sides of the cell frame in the X direction. The dummy gate wiring 34 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 35 is shared with other cells arranged on the right side of the drawing.

[0038] The local interconnect layer has a local interconnect (LI) 41 extending in the Y direction. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1 and a portion of the active region 2N1 that serves as the drain of the transistor N1.

[0039] Wirings 51 and 52 extending in the X direction are formed in the M0 wiring layer, which is a metal wiring layer above the local wiring layer. Wiring 51 is connected to gate wiring 32 through a via. Wiring 52 is connected to local wiring 41 through a via. Wiring 51 corresponds to input A, and wiring 52 corresponds to output Y.

[0040] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0041] As shown in FIG. 2A, the active regions 2P1 and 2N1 in the inverter cell C1 have a width of w2 in the Y direction in plan view.

[0042] 2, the surface of the nanosheet 21 on the lower side in the Y direction in the drawing is exposed from the gate wiring 31. The surface of the nanosheet 22 on the upper side in the Y direction in the drawing is exposed from the gate wiring 32. That is, the surfaces of the nanosheets 21 and 22 that face each other in the Y direction are exposed from the gate wiring 31 and 32, respectively. This makes it possible to reduce the distance d1 in the Y direction between the active regions 2P1 and 2N1 within the inverter cell C1. This therefore makes it possible to reduce the area of ​​the semiconductor integrated circuit device.

[0043] Furthermore, the upper surface of the nanosheet 21 in the Y direction in the drawing is covered by the gate wiring 31. The lower surface of the nanosheet 22 in the Y direction in the drawing is covered by the gate wiring 32. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have surfaces facing each other in the Y direction that are not exposed from the gate wiring. Therefore, the distance d2 in the Y direction between the active regions of cells adjacent to each other in the Y direction is greater than the distance d1 in the Y direction between the active regions 2P1 and 2N1 in the inverter cell C1.

[0044] Furthermore, the distance d3 in the Y direction between the power supply wiring 11 and 12 formed in the BM0 wiring layer is greater than the distance d1 in the Y direction between the active regions 2P1 and 2N1. That is, in a plan view, the bottom end of the power supply wiring 11 in the Y direction is located above the bottom end of the active region 2P1 in the Y direction. In a plan view, the top end of the power supply wiring 12 in the Y direction is located below the top end of the active region 2N1 in the Y direction. In other words, in a plan view, the bottom end of the active region 2P1 and the top end of the active region 2N1 are located between the bottom end of the power supply wiring 11 and the top end of the power supply wiring 12 (i.e., inside the power supply wirings 11 and 12).

[0045] Furthermore, the via 61 connecting the power supply wiring 11 and the portion of the active region 2P1 that will serve as the source of the transistor P1 is located at the center of the active region 2P1 in the Y direction in a plan view. Specifically, the distance from the center of the via 61 in the Y direction to the top of the active region 2P1 is the same as the distance d4 from the center of the via 61 in the Y direction to the bottom of the active region 2P1. Furthermore, the via 62 connecting the power supply wiring 12 and the portion of the active region 2N1 that will serve as the source of the transistor N1 is located at the center of the active region 2N1 in the Y direction in a plan view. Specifically, the distance from the center of the via 62 in the Y direction to the top of the active region 2N1 is the same as the distance d5 from the center of the via 62 in the Y direction to the bottom of the active region 2N1. This makes the distances from the via 61 to the top and bottom ends of the portion of the active region 2P1 that will serve as the source of the transistor P1 in the Y direction equal. The distances from the via 62 to both the top and bottom ends of the Y direction in the figure at the portion of the active region 2N1 that serves as the source of the transistor N1 are equalized, so that the currents flowing through the transistors P1 and N1 are equalized in the Y direction, up and down in the figure, thereby increasing the speed of the semiconductor integrated circuit device.

[0046] Furthermore, in a plan view, the amount of overlap of the active region 2P1 with the via 61 in the Y direction is greater than the amount of overlap of the power supply wiring 11 with the via 61 in the Y direction. Specifically, in a plan view, a distance d6 from the lower end of the via 61 in the Y direction to the lower end of the active region 2P1 in the Y direction is greater than a distance d7 from the lower end of the via 61 in the Y direction to the lower end of the power supply wiring 11 in the Y direction. Furthermore, in a plan view, the amount of overlap of the active region 2N1 with the via 62 in the Y direction is greater than the amount of overlap of the power supply wiring 12 with the via 62 in the Y direction. Specifically, in a plan view, a distance d8 from the upper end of the via 62 in the Y direction to the upper end of the active region 2N1 in the Y direction is greater than a distance d9 from the upper end of the via 62 in the Y direction to the upper end of the power supply wiring 12 in the Y direction.

[0047] (Configuration of Inverter Cell C4) The inverter cell C4 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0048] As shown in FIG. 2B, in comparison with the inverter cell C1 shown in FIG. 2A, the inverter cell C4 has active regions 2P4 and 2N4 having different widths in the Y direction arranged therein instead of the active regions 2P1 and 2N1.

[0049] Specifically, the active regions 2P4 and 2N4 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the inverter cell C4 is greater than the drive capability of the inverter cell C1.

[0050] As shown in FIG. 2 , the bottom edge of the active region 2P4 in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1. The top edge of the active region 2N4 in the Y direction is located at the same position in the Y direction as the top edge of the active region 2N1. That is, the bottom edge of the active region 2P1 of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P4 of the inverter cell C4 in the Y direction are aligned in the Y direction. The top edge of the active region 2N1 of the inverter cell C1 in the Y direction and the top edge of the active region 2N4 of the inverter cell C4 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 of the inverter cells C1 and C4 have their lower surfaces exposed from the gate wiring 31. The nanosheets 22 of the inverter cells C1 and C4 have their upper surfaces exposed from the gate wiring 32. That is, in the inverter cells C1 and C4, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row in which standard cells are arranged in the X direction, as in the configuration of Figure 1, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction, thereby making the shape of the structure, i.e., its size and layout area in the Y direction, uniform. This facilitates the manufacture of semiconductor integrated circuit devices.

[0051] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0052] Fig. 5(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0053] 5B shows a cross section of the inverter cell of FIG. 2 taken along line Y1-Y1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 that supplies VDD and a power supply wiring 12 that supplies VSS are formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region 2P1 of chip A via via 61. Power supply wiring 12 is connected to active region 2N1 of chip A via via 62.

[0054] This configuration example also provides the same effects as the inverter cell described above.

[0055] 6 is a plan view showing an example of the layout structure of an inverter cell according to a modification of the first embodiment. Compared to FIG. 2, in FIG. 6, vias 63 and 64 are arranged instead of the vias 61 and 62.

[0056] 6, the vias 63 and 64 have a rectangular cross section in a plan view. Specifically, the vias 63 and 64 each have a length d11 in the Y direction that is longer than a length d12 in the X direction.

[0057] The via 63 has a length d11 in the Y direction that is approximately the same as the length from the top to the bottom of the active region 2P1 in the drawing. The via 64 has a length d11 in the Y direction that is approximately the same as the length from the top to the bottom of the active region 2P1 in the drawing.

[0058] According to the configuration of Figure 6, the resistance value of via 63 connecting power supply wiring 11 and the portion that becomes the source of transistor P1 in active region 2P1, and via 64 connecting power supply wiring 12 and the portion that becomes the source of transistor N1 in active region 2N1 can be reduced, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration.

[0059] In addition, in Figure 6, it is preferable that via 63 is arranged in the center of active region 2P1 in the Y direction when viewed in a plane, and via 64 is arranged in the center of active region 2N1 in the Y direction when viewed in a plane.

[0060] 7A and 7B are plan views showing examples of layout structures of cells included in the semiconductor integrated circuit device according to the first embodiment, with Fig. 7A(a) showing a two-input NAND cell C2, Fig. 7A(b) showing a two-input NAND cell C5, Fig. 7B(a) showing a two-input NOR cell C3, and Fig. 7B(b) showing a two-input NOR cell C6. Fig. 8(a) is a circuit diagram of a two-input NAND cell, and Fig. 8(b) is a circuit diagram of a two-input NOR cell.

[0061] The layout structure of FIGS. 7A and 7B can be easily inferred from the above description of the inverter cell and the circuit diagram of FIG. 8, and therefore will not be described further.

[0062] 7A(a), an active region 2P2 is formed in the P-type transistor region. The active region 2P2 overlaps with the power supply wiring 11 in plan view.

[0063] Transistors P11 and P12 are configured in the active region 2P2. The transistors P11 and P12 have nanosheets 23 and 24, respectively, extending in the X direction. In the active region 2P2, the portions that serve as the sources of the transistors P11 and P12 are connected to the power supply wiring 11 via vias 65. The vias 65 are formed in a region where the power supply wiring 11 and the active region 2P2 overlap in a plan view.

[0064] An active region 2N2 is formed in the N-type transistor region. The active region 2N2 overlaps with the power supply wiring 12 in plan view.

[0065] Transistors N11 and N12 are configured in the active region 2N2. The transistors N11 and N12 have nanosheets 25 and 26, respectively, extending in the X direction. In the active region 2N2, the portion that serves as the source of the transistor N11 is connected to the power supply wiring 12 via a via 66. The via 66 is formed in a region where the power supply wiring 12 and the active region 2N2 overlap in a plan view.

[0066] Gate wirings 131 to 134 are formed extending in the Y direction. The nanosheets 23 to 26 overlap the gate wirings 131 to 134 in plan view. The gate wirings 131 to 134 correspond to the gates of the transistors P11, P12, N11, and N12, respectively.

[0067] The gate wirings 131 and 133 are connected via a bridge portion 135 extending in the Y direction. The gate wirings 132 and 134 are connected via a bridge portion 136 extending in the Y direction.

[0068] Gate wiring 131 covers the periphery of nanosheet 23 in the Y and Z directions so that a portion of the periphery of nanosheet 23 is exposed. Gate wiring 132 covers the periphery of nanosheet 24 in the Y and Z directions so that a portion of the periphery of nanosheet 24 is exposed. Gate wiring 133 covers the periphery of nanosheet 25 in the Y and Z directions so that a portion of the periphery of nanosheet 25 is exposed. Gate wiring 134 covers the periphery of nanosheet 26 in the Y and Z directions so that a portion of the periphery of nanosheet 26 is exposed. Specifically, the lower surfaces of nanosheets 23 and 24 in the Y direction in the drawing are exposed from gate wirings 131 and 132, respectively, and the upper surfaces of nanosheets 23 and 24 in the Y direction in the drawing are covered by gate wirings 131 and 132, respectively. The upper surfaces of the nanosheets 25 and 26 in the Y direction are exposed from the gate wirings 133 and 134, respectively, and the lower surfaces of the nanosheets 25 and 26 in the Y direction are covered by the gate wirings 133 and 134, respectively.

[0069] As described above, the two-input NAND cell C2 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and realizes a NAND circuit with inputs A and B and an output Y.

[0070] As shown in FIG. 7A(a), the active regions 2P2 and 2N2 in the two-input NAND cell C2 have a width of w2 in the Y direction in plan view.

[0071] In the two-input NAND cell C2 of FIG. 7A(a), the nanosheets 23 and 24 have their lower surfaces in the Y direction exposed from the gate wirings 131 and 132, respectively. The nanosheets 25 and 26 have their upper surfaces in the Y direction exposed from the gate wirings 133 and 134, respectively. That is, the surfaces of the nanosheets 23 and 25 facing each other in the Y direction are exposed from the gate wirings 131 and 133, respectively. The surfaces of the nanosheets 24 and 26 facing each other in the Y direction are exposed from the gate wirings 132 and 134, respectively. This allows the distance d1 in the Y direction between the active regions 2P2 and 2N2 to be reduced. This allows the area of ​​the semiconductor integrated circuit device to be reduced.

[0072] Furthermore, the upper sides of nanosheets 23 and 24 in the Y direction are covered by gate wiring 131 and 132, respectively. The lower sides of nanosheets 25 and 26 in the Y direction are covered by gate wiring 133 and 134, respectively. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent in the Y direction, the nanosheets in the active regions facing each other in the Y direction have surfaces facing each other in the Y direction that are not exposed from the gate wiring. Therefore, the distance d2 in the Y direction between the active regions of cells adjacent in the Y direction is greater than the distance d1 in the Y direction between the active regions 2P2 and 2N2 in the 2NAND cell C2.

[0073] Furthermore, the distance d3 in the Y direction between the power supply wiring 11 and 12 formed in the BM0 wiring layer is greater than the distance d1 in the Y direction between the active regions 2P2 and 2N2. That is, in a plan view, the bottom end of the power supply wiring 11 in the Y direction is located above the bottom end of the active region 2P2 in the Y direction. In a plan view, the top end of the power supply wiring 12 in the Y direction is located below the top end of the active region 2N2 in the Y direction. In other words, in a plan view, the bottom end of the active region 2P2 and the top end of the active region 2N2 are located between the bottom end of the power supply wiring 11 and the top end of the power supply wiring 12 (i.e., inside the power supply wirings 11 and 12).

[0074] Furthermore, via 65, which connects power supply wiring 11 and the portions of active region 2P2 that serve as the sources of transistors P11 and P12, is disposed at the center of active region 2P2 in the Y direction in plan view. Specifically, the distance from the center of via 65 in the Y direction to the top of active region 2P2 is the same as the distance d4 from the center of via 65 in the Y direction to the bottom of active region 2P2. Furthermore, via 66, which connects power supply wiring 12 and the portions of active region 2N2 that serve as the source of transistor N11, is disposed at the center of active region 2N2 in the Y direction in plan view. Specifically, the distance from the center of via 66 in the Y direction to the top of active region 2N2 is the same as the distance d5 from the center of via 66 in the Y direction to the bottom of active region 2N2. As a result, the distances from via 65 to both the top and bottom of the Y direction in the drawing at the portion in active region 2P2 that serves as the source of transistors P11 and P12 are equal. The distances from via 66 to both the top and bottom of the Y direction in the drawing at the portion in active region 2N2 that serves as the source of transistor N11 are equal. Therefore, the currents flowing through transistors P11, P12, and N11 are equalized in the Y direction, up and down, on the drawing, thereby increasing the speed of the semiconductor integrated circuit device.

[0075] Furthermore, in a plan view, the amount of overlap of the active region 2P2 with the via 65 in the Y direction is greater than the amount of overlap of the power supply wiring 11 with the via 65 in the Y direction. Specifically, in a plan view, a distance d6 from the lower end of the via 65 in the Y direction to the lower end of the active region 2P2 in the Y direction is greater than a distance d7 from the lower end of the via 65 in the Y direction to the lower end of the power supply wiring 11 in the Y direction. Furthermore, in a plan view, the amount of overlap of the active region 2N2 with the via 66 in the Y direction is greater than the amount of overlap of the power supply wiring 12 with the via 66 in the Y direction. Specifically, in a plan view, a distance d8 from the upper end of the via 66 in the Y direction to the upper end of the active region 2N2 in the Y direction is greater than a distance d9 from the upper end of the via 66 in the Y direction to the upper end of the power supply wiring 12 in the Y direction.

[0076] (Configuration of Two-Input NAND Cell C5) The two-input NAND cell C5 has a configuration similar to that of the two-input NAND cell C2. Specifically, the two-input NAND cell C5 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and implements a NAND circuit with inputs A and B and an output Y.

[0077] As shown in FIG. 7A(b), in comparison with the two-input NAND cell C2 shown in FIG. 7A(a), the two-input NAND cell C5 has active regions 2P5 and 2N5, each having a different width in the Y direction, arranged in place of the active regions 2P2 and 2N2.

[0078] Specifically, the active regions 2P5 and 2N5 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the two-input NAND cell C5 is greater than the drive capability of the two-input NAND cell C2.

[0079] As shown in FIG. 7A , the bottom edge of the active region 2P5 in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P2 in the Y direction. The top edge of the active region 2N5 in the Y direction is located at the same position in the Y direction as the top edge of the active region 2N2 in the Y direction. That is, the bottom edge of the active region 2P2 of the two-input NAND cell C2 in the Y direction is aligned with the bottom edge of the active region 2P5 of the two-input NAND cell C5 in the Y direction. The top edge of the active region 2N2 of the two-input NAND cell C2 in the Y direction is aligned with the top edge of the active region 2N5 of the two-input NAND cell C5 in the Y direction. Furthermore, the nanosheets 23 and 24 of the two-input NAND cells C2 and C5 have their lower surfaces exposed from the gate wiring 131 and 132, respectively. The surfaces of the nanosheets 25 and 26 of the two-input NAND cells C2 and C5 on the upper side in the Y direction in the drawing are exposed from the gate wiring 133 and 134, respectively. That is, in the two-input NAND cells C2 and C5, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0080] 7B(a), an active region 2P3 is formed in the P-type transistor region. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0081] Transistors P21 and P22 are configured in the active region 2P3. The transistors P21 and P22 have nanosheets 27 and 28, respectively, extending in the X direction. In the active region 2P3, the portion that serves as the source of the transistor P21 is connected to the power supply wiring 11 via a via 67. The via 67 is formed in a region where the power supply wiring 11 and the active region 2P3 overlap in a plan view.

[0082] An active region 2N3 is formed in the N-type transistor region. The active region 2N3 overlaps with the power supply wiring 12 in plan view.

[0083] Transistors N21 and N22 are configured in the active region 2N3. The transistors N21 and N22 have nanosheets 29 and 30, respectively, extending in the X direction. In the active region 2N3, the portions that serve as the sources of the transistors N21 and N22 are connected to the power supply wiring 12 via vias 68. The vias 68 are formed in a region where the power supply wiring 12 and the active region 2N3 overlap in a plan view.

[0084] Gate wirings 137 to 140 are formed extending in the Y direction. The nanosheets 27 to 30 overlap the gate wirings 137 to 140 in plan view. The gate wirings 137 to 140 correspond to the gates of the transistors P21, P22, N21, and N22, respectively.

[0085] The gate wirings 137 and 139 are connected via a bridge portion 141 extending in the Y direction. The gate wirings 138 and 140 are connected via a bridge portion 142 extending in the Y direction.

[0086] The gate wiring 137 covers the outer periphery of the nanosheet 27 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 27 is exposed. The gate wiring 138 covers the outer periphery of the nanosheet 28 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 28 is exposed. The gate wiring 139 covers the outer periphery of the nanosheet 29 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 29 is exposed. The gate wiring 140 covers the outer periphery of the nanosheet 30 in the Y and Z directions so that a portion of the outer periphery of the nanosheet 30 is exposed. Specifically, the lower surfaces of the nanosheets 27 and 28 in the Y direction in the drawing are exposed from the gate wirings 137 and 138, respectively, and the upper surfaces of the nanosheets 27 and 28 in the Y direction in the drawing are covered by the gate wirings 137 and 138, respectively. The upper surfaces of the nanosheets 29 and 30 in the Y direction are exposed from the gate wirings 139 and 140, respectively, and the lower surfaces of the nanosheets 29 and 30 in the Y direction are covered by the gate wirings 139 and 140, respectively.

[0087] As described above, the two-input NOR cell C3 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and an output Y.

[0088] As shown in FIG. 7B(a), the active regions 2P3 and 2N3 of the two-input NOR cell C3 have a width of w2 in the Y direction in plan view.

[0089] 7B(a), the nanosheets 27 and 28 are exposed at their lower Y-direction sides from the gate wirings 137 and 138, respectively. The nanosheets 29 and 30 are exposed at their upper Y-direction sides from the gate wirings 139 and 140, respectively. That is, the surfaces of the nanosheets 27 and 29 that face each other in the Y direction are exposed from the gate wirings 137 and 139, respectively. The surfaces of the nanosheets 28 and 30 that face each other in the Y direction are exposed from the gate wirings 138 and 140, respectively. This allows the distance d1 in the Y direction between the active regions 2P3 and 2N3 to be reduced.

[0090] Furthermore, the upper surfaces of nanosheets 27 and 28 in the Y direction are covered by gate wiring 137 and 138, respectively. The lower surfaces of nanosheets 29 and 30 in the Y direction are covered by gate wiring 139 and 140, respectively. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent in the Y direction, the nanosheets in the active regions facing each other in the Y direction have surfaces facing each other in the Y direction that are not exposed from the gate wiring. Therefore, the distance d2 in the Y direction between the active regions of cells adjacent in the Y direction is greater than the distance d1 in the Y direction between the active regions 2P3 and 2N3 in the 2NOR cell C3.

[0091] Furthermore, the distance d3 in the Y direction between the power supply wiring 11 and 12 formed in the BM0 wiring layer is greater than the distance d1 in the Y direction between the active regions 2P3 and 2N3. That is, in a plan view, the bottom end of the power supply wiring 11 in the Y direction is located above the bottom end of the active region 2P3 in the Y direction. In a plan view, the top end of the power supply wiring 12 in the Y direction is located below the top end of the active region 2N3 in the Y direction. In other words, in a plan view, the bottom end of the active region 2P3 and the top end of the active region 2N3 are located between the bottom end of the power supply wiring 11 and the top end of the power supply wiring 12 (i.e., inside the power supply wirings 11 and 12).

[0092] Furthermore, via 67, which connects power supply wiring 11 to the portion of active region 2P3 that serves as the source of transistor P21, is located at the center of active region 2P3 in the Y direction in plan view. Specifically, the distance from the center of via 67 in the Y direction to the top of active region 2P3 is the same as the distance d4 from the center of via 67 in the Y direction to the bottom of active region 2P3. Also, via 68, which connects power supply wiring 12 to the portions that serve as the sources of transistors N21 and N22 in active region 2N3, is located at the center of active region 2N3 in the Y direction in plan view. Specifically, the distance from the center of via 68 in the Y direction to the top of active region 2N3 is the same as the distance d5 from the center of via 68 in the Y direction to the bottom of active region 2N3. This makes the distances from via 67 to both the top and bottom of the portion of active region 2P3 that serves as the source of transistor P21 in the Y direction equal. The distances from via 68 to both the top and bottom ends of the Y direction of the source portions of transistors N21 and N22 in active region 2N3 are equalized, so that the currents flowing through transistors P21, N21, and N22 are equalized in the Y direction of the drawing, thereby increasing the speed of the semiconductor integrated circuit device.

[0093] Furthermore, in a plan view, the amount of overlap of the active region 2P3 with the via 67 in the Y direction is greater than the amount of overlap of the power supply wiring 11 with the via 67 in the Y direction. Specifically, in a plan view, a distance d6 from the lower end of the via 67 in the Y direction to the lower end of the active region 2P3 in the Y direction is greater than a distance d7 from the lower end of the via 67 in the Y direction to the lower end of the power supply wiring 11 in the Y direction. Furthermore, in a plan view, the amount of overlap of the active region 2N3 with the via 68 in the Y direction is greater than the amount of overlap of the power supply wiring 12 with the via 68 in the Y direction. Specifically, in a plan view, a distance d8 from the upper end of the via 68 in the Y direction to the upper end of the active region 2N3 in the Y direction is greater than a distance d9 from the upper end of the via 68 in the Y direction to the upper end of the power supply wiring 12 in the Y direction.

[0094] (Configuration of 2-input NOR cell C6) The 2-input NOR cell C6 has almost the same configuration as the 2-input NOR cell C3. Specifically, the 2-input NOR cell C6 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and output Y.

[0095] As shown in FIG. 7B(b), in comparison with the two-input NOR cell C3 shown in FIG. 7B(a), the two-input NOR cell C6 has active regions 2P6 and 2N6, each having a different width in the Y direction, arranged in place of the active regions 2P3 and 2N3.

[0096] Specifically, the active regions 2P6 and 2N6 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the two-input NOR cell C6 is greater than the drive capability of the two-input NOR cell C3.

[0097] As shown in FIG. 7B , the bottom edge of the active region 2P6 in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P3. The top edge of the active region 2N6 in the Y direction is located at the same position in the Y direction as the top edge of the active region 2N3. That is, the bottom edge of the active region 2P3 of the two-input NOR cell C3 in the Y direction is aligned with the bottom edge of the active region 2P6 of the two-input NOR cell C6 in the Y direction. The top edge of the active region 2N3 of the two-input NOR cell C3 in the Y direction is aligned with the top edge of the active region 2N6 of the two-input NOR cell C6 in the Y direction. Furthermore, the nanosheets 27 and 28 of the two-input NOR cells C3 and C6 have their lower surfaces exposed from the gate wiring 137 and 138, respectively. The surfaces of the nanosheets 29 and 30 of the two-input NOR cells C3 and C6 facing upward in the Y direction are exposed from the gate wiring 139 and 140, respectively. That is, in the two-input NOR cells C3 and C6, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0098] Second Embodiment (Circuit Block Configuration) FIG. 9 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment.

[0099] 9 is configured by arranging standard cells. In this embodiment, too, the power supply wiring is formed in the BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0100] In the layout of FIG. 1, a plurality of cells aligned in the X direction constitute a cell column CR (CR4 to CR6). A plurality of cell columns CR (three columns in FIG. 1) are aligned in the Y direction. The cells include cells with logic functions such as inverters, NAND gates, and NOR gates. For example, the cell column CR includes inverter cells C7 and C10, two-input NAND cells C8 and C11, and two-input NOR cells C9 and C12, which will be described later.

[0101] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0102] Each cell is configured with an active region 2P that forms the channel, source, and drain of a P-type transistor, and an active region 2N that forms the channel, source, and drain of an N-type transistor. In a cell row CR, the active regions 2P are arranged side by side in the X direction, and the active regions 2N are arranged side by side in the X direction. In cell rows CR adjacent in the Y direction, the active regions 2P are arranged facing each other, and the active regions 2N are arranged facing each other. The distance d21 in the Y direction between the active regions 2P and 2N within a cell is greater than the distance d22 between the active regions 2P (2N) between cell rows CR.

[0103] In addition, in cell rows CR4 and CR6, the upper ends of the active regions 2P in the Y direction on the drawing are aligned in the X direction, and the lower ends of the active regions 2N in the Y direction on the drawing are aligned in the X direction. In cell row CR5, the upper ends of the active regions 2N in the Y direction on the drawing are aligned in the X direction, and the lower ends of the active regions 2P in the Y direction on the drawing are aligned in the X direction. That is, in cell row CR, the active regions 2P and 2N in the cells aligned in the Y direction are aligned so that the ends of the active regions on opposing sides form a straight line in the X direction.

[0104] (Configuration of inverter cell C7) Figure 10 is a plan view showing an example of the layout structure of inverter cells C7 and C10 according to the second embodiment. Specifically, Figure 10(a) shows inverter cell C7, and Figure 10(b) shows inverter cell C10. Note that the inverter circuits shown in Figure 4 are configured in the inverter cells C7 and C10 in Figure 10, respectively.

[0105] 10A, power supply wirings 11 and 12 extending in the X direction are formed on both ends of the cell in the Y direction in the drawing in the BM0 wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wiring 12 supplies a power supply voltage VSS.

[0106] An active region 2P7 is formed in the P-type transistor region. The active region 2P7 overlaps with the power supply wiring 11 in plan view.

[0107] A transistor P1 is configured in the active region 2P7. The transistor P1 has a nanosheet 221 extending in the X direction. In the active region 2P7, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 261. The via 261 is formed in a region where the power supply wiring 11 and the active region 2P7 overlap in a plan view.

[0108] An active region 2N7 is formed in the N-type transistor region. The active region 2N7 overlaps with the power supply wiring 12 in plan view.

[0109] A transistor N1 is configured in the active region 2N7. The transistor N1 has a nanosheet 222 extending in the X direction. In the active region 2N7, a portion that serves as the source of the transistor N1 is connected to the power supply wiring 12 via a via 262. The via 262 is formed in a region where the power supply wiring 12 and the active region 2N7 overlap in a plan view.

[0110] A gate wiring 231 extending in the Y direction is formed in the center of the cell in the X direction. The nanosheets 221 and 222 overlap the gate wiring 231 in plan view. The gate wiring 231 corresponds to the gates of the transistors P1 and N1.

[0111] Gate wiring 231 covers the outer peripheries of nanosheets 221 and 222 in the Y and Z directions, respectively, so as to expose part of the outer peripheries of nanosheets 221 and 222. Specifically, the upper surface of nanosheet 221 in the Y direction in the drawing is exposed from gate wiring 231, and the lower surface of nanosheet 221 in the Y direction in the drawing is covered by gate wiring 231. The lower surface of nanosheet 222 in the Y direction in the drawing is exposed from gate wiring 231, and the upper surface of nanosheet 222 in the Y direction in the drawing is covered by gate wiring 231.

[0112] Dummy gate wirings 232 and 233 are formed on both sides of the cell frame in the X direction. The dummy gate wiring 232 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 233 is shared with other cells arranged on the right side of the drawing.

[0113] The local wiring layer is formed with a local wiring 241 extending in the Y direction. The local wiring 241 is connected to a portion of the active region 2P7 that serves as the drain of the transistor P1 and a portion of the active region 2N7 that serves as the drain of the transistor N1.

[0114] In the M0 wiring layer, wirings 251 and 252 extending in the X direction are formed. The wiring 251 is connected to the gate wiring 231 through a via. The wiring 252 is connected to the local wiring 241 through a via. The wiring 251 corresponds to the input A, and the wiring 252 corresponds to the output Y.

[0115] As described above, the inverter cell C7 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0116] As shown in FIG. 10A, the active regions 2P7 and 2N7 in the inverter cell C7 have a width of w2 in the Y direction in plan view.

[0117] In the inverter cell C7 of FIG. 10( a), the upper surface of the nanosheet 221 in the Y direction is exposed from the gate wiring 231. The lower surface of the nanosheet 222 in the Y direction is exposed from the gate wiring 231. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring facing each other in the Y direction. This allows the distance d22 between the active regions facing each other in the Y direction to be reduced in cells adjacent to each other in the Y direction. Therefore, the area of ​​the semiconductor integrated circuit device can be reduced.

[0118] Furthermore, the surface of nanosheet 221 on the lower side in the Y direction in the drawing is covered by gate wiring 231. The surface of nanosheet 222 on the upper side in the Y direction in the drawing is covered by gate wiring 231. That is, in inverter cell C7, the opposing surfaces of nanosheets 221 and 222 are covered by gate wiring 231. Therefore, the distance d21 in the Y direction between active regions 2P7 and 2N7 in inverter cell C10 is greater than the distance d22 in the Y direction between active regions in cells adjacent in the Y direction.

[0119] Furthermore, the via 261 connecting the power supply wiring 11 and the portion of the active region 2P7 that will serve as the source of the transistor P1 is located at the center of the active region 2P7 in the Y direction in a plan view. Specifically, the distance from the center of the via 261 in the Y direction to the top of the active region 2P7 is the same as the distance d24 from the center of the via 261 in the Y direction to the bottom of the active region 2P7. Furthermore, the via 262 connecting the power supply wiring 12 and the portion of the active region 2N7 that will serve as the source of the transistor N1 is located at the center of the active region 2N7 in the Y direction in a plan view. Specifically, the distance from the center of the via 262 in the Y direction to the top of the active region 2N7 is the same as the distance d25 from the center of the via 262 in the Y direction to the bottom of the active region 2N7. This makes the distances from the via 261 to the top and bottom ends of the portion of the active region 2P7 that will serve as the source of the transistor P1 in the Y direction equal. The distances from the via 262 to both the top and bottom ends of the Y direction in the drawing of the portion of the active region 2N7 that serves as the source of the transistor N1 are equalized. Therefore, the currents flowing through the transistors P1 and N1 are equalized in the Y direction, that is, up and down in the drawing, thereby increasing the speed of the semiconductor integrated circuit device.

[0120] (Configuration of Inverter Cell C10) The inverter cell C10 has a configuration similar to that of the inverter cell C7. Specifically, the inverter cell C10 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0121] As shown in FIG. 10B, in comparison with the inverter cell C7 shown in FIG. 10A, the inverter cell C10 has active regions 2P10 and 2N10 having different widths in the Y direction arranged therein instead of the active regions 2P7 and 2N7.

[0122] Specifically, the active regions 2P10 and 2N10 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the inverter cell C10 is greater than the drive capability of the inverter cell C7.

[0123] As shown in FIG. 10 , the upper end of the active region 2P10 in the Y direction is located at the same position in the Y direction as the upper end of the active region 2P7 in the Y direction. The lower end of the active region 2N10 in the Y direction is located at the same position in the Y direction as the lower end of the active region 2N7 in the Y direction. That is, the upper end of the active region 2P7 of the inverter cell C7 in the Y direction and the upper end of the active region 2P10 of the inverter cell C10 in the Y direction are aligned in the Y direction. The lower end of the active region 2N7 of the inverter cell C7 in the Y direction and the lower end of the active region 2N10 of the inverter cell C10 in the Y direction are aligned in the Y direction. Furthermore, the upper surfaces of the nanosheets 221 of the inverter cells C7 and C10 in the Y direction are exposed from the gate wiring 231. The nanosheets 222 of inverter cells C7 and C10 have their lower surfaces in the Y direction exposed from the gate wiring 231. That is, in inverter cells C7 and C10, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0124] (Other layout structures of standard cells) Figures 11A and 11B are plan views showing examples of layout structures of cells included in a semiconductor integrated circuit device according to the second embodiment, where Figure 11A(a) shows a two-input NAND cell C8, Figure 11A(b) shows a two-input NAND cell C11, Figure 11B(a) shows a two-input NOR cell C9, and Figure 11B(b) shows a two-input NOR cell C12.

[0125] The layout structure of FIGS. 11A and 11B can be easily inferred from the above description of the inverter cell and the circuit diagram of FIG. 8, and therefore will not be described further.

[0126] 11A(a), an active region 2P8 is formed in the P-type transistor region. The active region 2P8 overlaps with the power supply wiring 11 in plan view.

[0127] Transistors P11 and P12 are configured in the active region 2P8. The transistors P11 and P12 have nanosheets 223 and 224, respectively, extending in the X direction. In the active region 2P8, the portions that serve as the sources of the transistors P11 and P12 are connected to the power supply wiring 11 via vias 265. The vias 265 are formed in a region where the power supply wiring 11 and the active region 2P8 overlap in a planar view.

[0128] An active region 2N8 is formed in the N-type transistor region. The active region 2N8 overlaps with the power supply wiring 12 in plan view.

[0129] Transistors N11 and N12 are configured in the active region 2N8. The transistors N11 and N12 have nanosheets 225 and 226, respectively, extending in the X direction. In the active region 2N8, the portion that serves as the source of the transistor N11 is connected to the power supply wiring 12 via a via 266. The via 266 is formed in a region where the power supply wiring 12 and the active region 2N8 overlap in a plan view.

[0130] Gate wirings 234 and 235 are formed extending in the Y direction. The nanosheets 223 and 225 overlap the gate wiring 234 in a planar view. The nanosheets 224 and 226 each overlap the gate wiring 235 in a planar view. The gate wiring 234 corresponds to the gates of the transistors P11 and N11, respectively. The gate wiring 235 corresponds to the gates of the transistors P12 and N12, respectively.

[0131] Gate wiring 234 covers the outer peripheries of nanosheets 223 and 225 in the Y and Z directions so that portions of the outer peripheries of nanosheets 223 and 225 are exposed. Gate wiring 235 covers the outer peripheries of nanosheets 224 and 226 in the Y and Z directions so that portions of the outer peripheries of nanosheets 224 and 226 are exposed. Specifically, the upper surfaces of nanosheets 223 and 224 in the Y direction are exposed from gate wirings 234 and 235, respectively, and the lower surfaces of nanosheets 225 and 226 in the Y direction are covered by gate wirings 234 and 235, respectively. The lower surfaces of nanosheets 225 and 226 in the Y direction are exposed from gate wirings 234 and 235, respectively, and the upper surfaces of nanosheets 225 and 226 in the Y direction are covered by gate wirings 234 and 235, respectively.

[0132] As described above, the two-input NAND cell C8 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and realizes a NAND circuit with inputs A and B and an output Y.

[0133] As shown in FIG. 11A(a), the active regions 2P8 and 2N8 in the two-input NAND cell C8 have a width of w2 in the Y direction in plan view.

[0134] In the two-input NAND cell C8 of FIG. 11A(a), the surfaces of the nanosheets 223 and 224 on the upper side in the Y direction are exposed from the gate wiring 234 and 235, respectively. The surfaces of the nanosheets 225 and 226 on the lower side in the Y direction are exposed from the gate wiring 234 and 235, respectively. That is, in cells adjacent to each other in the Y direction, the surfaces of the nanosheets in the active regions facing each other in the Y direction that are exposed from the gate wiring face each other in the Y direction. This allows the distance d22 between the active regions facing each other in the Y direction to be reduced in cells adjacent to each other in the Y direction. This allows the area of ​​the semiconductor integrated circuit device to be reduced.

[0135] Furthermore, the nanosheets 223 and 224 are covered at their lower sides in the Y direction by gate wiring 234 and 235, respectively. The nanosheets 225 and 226 are covered at their upper sides in the Y direction by gate wiring 234 and 235, respectively. That is, in the two-input NAND cell C8, the opposing surfaces of the nanosheets 223 and 225 are covered by gate wiring 234. The opposing surfaces of the nanosheets 224 and 226 are covered by gate wiring 235. Therefore, the distance d21 in the Y direction between the active regions 2P8 and 2N8 in the two-input NAND cell C8 is greater than the distance d22 in the Y direction between the active regions of cells adjacent in the Y direction.

[0136] Furthermore, via 265, which connects power supply wiring 11 and the portions of active region 2P8 that serve as the sources of transistors P11 and P12, is disposed at the center of active region 2P8 in the Y direction in plan view. Specifically, the distance from the center of via 265 in the Y direction to the top edge of active region 2P8 is the same as the distance d24 from the center of via 265 in the Y direction to the bottom edge of active region 2P8. Furthermore, via 266, which connects power supply wiring 12 and the portions of active region 2N8 that serve as the source of transistor N11, is disposed at the center of active region 2N8 in the Y direction in plan view. Specifically, the distance from the center of via 266 in the Y direction to the top edge of active region 2N8 is the same as the distance d25 from the center of via 266 in the Y direction to the bottom edge of active region 2N8. As a result, the distances from via 265 to both the top and bottom of the Y-direction in the drawing at the portion of active region 2P8 that serves as the source of transistors P11 and P12 are equal. The distances from via 266 to both the top and bottom of the Y-direction in the drawing at the portion of active region 2N8 that serves as the source of transistor N11 are equal. Therefore, the currents flowing through transistors P11, P12, and N11 are equalized in the Y-direction in the top and bottom of the drawing, thereby increasing the speed of the semiconductor integrated circuit device.

[0137] (Configuration of the 2-input NAND cell C11) The 2-input NAND cell C11 has a configuration similar to that of the 2-input NAND cell C8. Specifically, the 2-input NAND cell C11 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and implements a NAND circuit with inputs A and B and an output Y.

[0138] As shown in FIG. 11A(b), compared to the two-input NAND cell C8 shown in FIG. 11A(a), the two-input NAND cell C11 has active regions 2P11 and 2N11 with different widths in the Y direction arranged therein instead of the active regions 2P8 and 2N8.

[0139] Specifically, the active regions 2P11 and 2N11 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the two-input NAND cell C11 is greater than the drive capability of the two-input NAND cell C8.

[0140] As shown in FIG. 11A, the top edge of the active region 2P11 in the Y direction is located at the same position in the Y direction as the top edge of the active region 2P8 in the Y direction. The bottom edge of the active region 2N11 in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2N8 in the Y direction. That is, the top edge of the active region 2P8 of the two-input NAND cell C8 in the Y direction and the top edge of the active region 2P11 of the two-input NAND cell C11 in the Y direction are aligned in the Y direction. The bottom edge of the active region 2N8 of the two-input NAND cell C8 in the Y direction and the bottom edge of the active region 2N11 of the two-input NAND cell C11 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 223 and 224 of the two-input NAND cells C8 and C11 have their upper surfaces in the Y direction exposed from the gate wiring 234 and 235, respectively. The nanosheets 225 and 226 of the two-input NAND cells C8 and C11 have their lower surfaces in the Y direction exposed from the gate wiring 234 and 235, respectively. That is, in the two-input NAND cells C8 and C11, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0141] 11B(a), an active region 2P9 is formed in the P-type transistor region. The active region 2P9 overlaps with the power supply wiring 11 in plan view.

[0142] Transistors P21 and P22 are configured in the active region 2P9. The transistors P21 and P22 have nanosheets 227 and 228, respectively, extending in the X direction. In the active region 2P9, the portion that serves as the source of the transistor P21 is connected to the power supply wiring 11 via a via 267. The via 267 is formed in a region where the power supply wiring 11 and the active region 2P9 overlap in plan view.

[0143] An active region 2N9 is formed in the N-type transistor region. The active region 2N9 overlaps with the power supply wiring 12 in plan view.

[0144] Transistors N21 and N22 are configured in the active region 2N9. The transistors N21 and N22 have nanosheets 229 and 230, respectively, extending in the X direction. In the active region 2N9, the portions that serve as the sources of the transistors N21 and N22 are connected to the power supply wiring 12 via vias 268. The vias 268 are formed in a region where the power supply wiring 12 and the active region 2N9 overlap in a planar view.

[0145] Gate wiring 236, 237 extending in the Y direction are formed. Nanosheets 227, 229 overlap with gate wiring 236 in plan view. Nanosheets 228, 230 overlap with gate wiring 237 in plan view. Gate wiring 236 corresponds to the gates of transistors P21, N21. Gate wiring 237 corresponds to the gates of transistors P22, N22.

[0146] Gate wiring 236 covers the outer peripheries of nanosheets 227 and 229 in the Y and Z directions so that portions of the outer peripheries of nanosheets 227 and 229 are exposed. Gate wiring 237 covers the outer peripheries of nanosheets 228 and 230 in the Y and Z directions so that portions of the outer peripheries of nanosheets 228 and 230 are exposed. Specifically, the upper surfaces of nanosheets 227 and 228 in the Y direction are exposed from gate wirings 236 and 237, respectively, and the lower surfaces of nanosheets 227 and 228 in the Y direction are covered by gate wirings 236 and 237, respectively. The lower surfaces of nanosheets 229 and 230 in the Y direction are exposed from gate wirings 236 and 237, respectively, and the upper surfaces of nanosheets 229 and 230 in the Y direction are covered by gate wirings 236 and 237, respectively.

[0147] As described above, the two-input NOR cell C9 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and an output Y.

[0148] As shown in FIG. 11B(a), the active regions 2P9 and 2N9 of the two-input NOR cell C9 have a width of w2 in the Y direction in plan view.

[0149] In the two-input NOR cell C9 of FIG. 11B(a), the surfaces of nanosheets 227 and 228 on the upper side in the Y direction are exposed from gate wiring 236 and 237, respectively. The surfaces of nanosheets 229 and 230 on the lower side in the Y direction are exposed from gate wiring 236 and 237, respectively. That is, in cells adjacent to each other in the Y direction, the surfaces of nanosheets in active regions facing each other in the Y direction that are exposed from the gate wiring face each other in the Y direction. This allows the distance d22 between active regions facing each other in the Y direction to be reduced in cells adjacent to each other in the Y direction. This allows the area of ​​the semiconductor integrated circuit device to be reduced.

[0150] Furthermore, the lower sides of nanosheets 227 and 228 in the Y direction are covered by gate wirings 236 and 237, respectively. The upper sides of nanosheets 229 and 230 in the Y direction are covered by gate wirings 236 and 237, respectively. That is, in two-input NOR cell C9, the opposing surfaces of nanosheets 227 and 229 are covered by gate wiring 236. The opposing surfaces of nanosheets 228 and 230 are covered by gate wiring 237. Therefore, the distance d21 in the Y direction between active regions 2P9 and 2N9 in two-input NOR cell C9 is greater than the distance d22 in the Y direction between active regions in cells adjacent in the Y direction.

[0151] Furthermore, via 267, which connects power supply wiring 11 to the portion of active region 2P9 that serves as the source of transistor P21, is located at the center of active region 2P9 in the Y direction in plan view. Specifically, the distance from the center of via 267 in the Y direction to the top of active region 2P9 is the same as the distance d24 from the center of via 267 in the Y direction to the bottom of active region 2P9. Furthermore, via 268, which connects power supply wiring 12 to the portions that serve as the sources of transistors N21 and N22 in active region 2N9, is located at the center of active region 2N9 in the Y direction in plan view. Specifically, the distance from the center of via 268 in the Y direction to the top of active region 2N9 is the same as the distance d25 from the center of via 268 in the Y direction to the bottom of active region 2N9. As a result, the distance from via 267 to both the top and bottom of the Y-direction in the drawing at the portion of active region 2P9 that serves as the source of transistor P21 is equalized. The distance from via 268 to both the top and bottom of the Y-direction in the drawing at the portion of active region 2N9 that serves as the sources of transistors N21 and N22 is equalized. Therefore, the currents flowing through transistors P21, N21, and N22 are equalized in the Y-direction in the top and bottom of the drawing, thereby increasing the speed of the semiconductor integrated circuit device.

[0152] (Configuration of 2-input NOR cell C12) The 2-input NOR cell C12 has almost the same configuration as the 2-input NOR cell C9. Specifically, the 2-input NOR cell C12 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and output Y.

[0153] As shown in FIG. 11B(b), compared to the two-input NOR cell C9 shown in FIG. 11B(a), the two-input NOR cell C12 has active regions 2P12 and 2N12 with different widths in the Y direction arranged therein instead of the active regions 2P9 and 2N9.

[0154] Specifically, the active regions 2P12 and 2N12 have a width w1 in the Y direction. w2 is smaller than w1. That is, the drive capability of the two-input NOR cell C12 is greater than the drive capability of the two-input NOR cell C9.

[0155] As shown in FIG. 11B , the upper end of the active region 2P12 in the Y direction is located at the same position in the Y direction as the upper end of the active region 2P9 in the Y direction. The lower end of the active region 2N12 in the Y direction is located at the same position in the Y direction as the lower end of the active region 2N9 in the Y direction. That is, the upper end of the active region 2P9 of the two-input NOR cell C9 in the Y direction and the upper end of the active region 2P12 of the two-input NOR cell C12 in the Y direction are aligned in the Y direction. The lower end of the active region 2N9 of the two-input NOR cell C9 in the Y direction and the lower end of the active region 2N12 of the two-input NOR cell C12 in the Y direction are aligned in the Y direction. Furthermore, the upper surfaces of the nanosheets 227 and 228 of the two-input NOR cells C9 and C12 in the Y direction are exposed from the gate wiring 236 and 237, respectively. The nanosheets 229 and 230 of the two-input NOR cells C9 and C12 have their lower surfaces in the Y direction exposed from the gate wiring 236 and 237, respectively. That is, in the two-input NOR cells C9 and C12, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0156] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0157] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0158] In the two-input NAND cells C2 and C5, vias 65 and 66 may be replaced with vias whose length in the Y direction is greater than that in the X direction, such as vias 63 and 64 shown in the modified example of FIG. 6 . Similarly, in the two-input NOR cells C3 and C6, vias 63 and 64 may be used instead of vias 67 and 68. In the inverter cell C4, vias 63 and 64 may be used instead of vias 61 and 62. In the two-input NAND cells C8 and C11, vias 63 and 64 may be used instead of vias 265 and 266. In the two-input NOR cells C9 and C12, vias 63 and 64 may be used instead of vias 267 and 268.

[0159] According to the present disclosure, in a semiconductor integrated circuit device including a standard cell using a fork sheet transistor and backside wiring, it is possible to reduce the area and increase the speed of the semiconductor integrated circuit device.

[0160] 11, 12 Power supply wiring 21-30, 221-230 Nanosheet 31, 32, 131-134, 137-140, 231-235 Gate wiring 51, 52, 251, 252 Wiring 61-68, 261-268 Via 2P, 2P1-2P12, 2N, 2N1-2N12 Active area P1, P11, P12, P21, P22, N1, N11, N12, N21, N22 Transistor C1, C4, C7, C10 Inverter cell C2, C5, C8, C11 2-input NAND cell C3, C6, C9, C12 2-input NOR cell

Claims

1. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region including a first nanosheet extending in a first direction as the channel, the first standard cell forming a channel, a source, and a drain of a first transistor of a first conductivity type; a second active region including a second nanosheet extending in the first direction as the channel, the second nanosheet forming a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the second active region including a second nanosheet extending in the first direction as the channel; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction; a second gate wiring extending in the second direction and surrounding an outer periphery of the second nanosheet in the second direction and in the third direction; a first power supply wiring formed on a back side of the first transistor and extending in the first direction; and a second power supply wiring formed on a back side of the second transistor and extending in the first direction. a first via formed in a region in the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, connecting the source in the first active region to the first power supply wiring; the second nanosheet is arranged on a first side that is one side of the first nanosheet in the second direction, a surface of the first nanosheet on the first side being exposed from the first gate wiring, a surface of the second nanosheet on the other side in the second direction being exposed from the second gate wiring, and the first via is arranged in a center of the first active region in the second direction in a planar view.

2. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell is formed in a region in the second active region where a region serving as the source of the second transistor overlaps with the second power supply wiring, and further comprises a second via connecting the source in the second active region to the second power supply wiring, and the second via is positioned in the center of the second active region in the second direction in a plan view.

3. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells include a second standard cell arranged adjacent to the second side of the first standard cell, the second standard cell constituting a channel, source and drain of a third transistor of the first conductivity type, and comprising: a third active region including a third nanosheet extending in the first direction as the channel; and a third gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions, the surface of the third nanosheet on the second side being exposed from the third gate wiring, and the distance between the first active region and the third active region in the second direction being greater than the distance between the first active region and the second active region in the second direction.

4. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the first side end of the first active area and the second side end of the second active area are disposed between the first side end of the first power supply wiring and the second side end of the second power supply wiring.

5. A semiconductor integrated circuit device according to claim 1, wherein the length of said first via in said second direction is longer than the length of said first via in said first direction.

6. A semiconductor integrated circuit device according to claim 1, wherein the first active region constitutes a channel, source and drain of a fourth transistor of the first conductivity type, and includes a fourth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a fifth transistor of the second conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the first standard cell comprises: a fourth gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the third direction; and a fifth gate wiring extending in the second direction and surrounding the periphery of the fifth nanosheet in the second direction and the third direction; the first power supply wiring is formed on the back side of the fourth transistor; the second power supply wiring is formed on the back side of the fifth transistor; the fifth nanosheet is disposed on the first side of the fourth nanosheet; and the surface of the fourth nanosheet on the first side is exposed from the fourth gate wiring; A semiconductor integrated circuit device, wherein the fifth nanosheet has a second side surface exposed from the fifth gate wiring.

7. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells include a third standard cell arranged alongside the first standard cell in the first direction, the third standard cell comprising: a fourth active region constituting a channel, source and drain of a sixth transistor of the first conductivity type and including a sixth nanosheet extending in the first direction as the channel; a fifth active region constituting a channel, source and drain of a seventh transistor of the second conductivity type and including a seventh nanosheet extending in the first direction as the channel; a sixth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; and a seventh gate wiring extending in the second direction and surrounding the periphery of the seventh nanosheet in the second direction and the third direction, the seventh nanosheet being arranged on the first side of the sixth nanosheet, the surface of the sixth nanosheet on the first side being exposed from the sixth gate wiring, and the surface of the seventh nanosheet on the second side being exposed from the seventh gate wiring, A semiconductor integrated circuit device, wherein, in a planar view, the width of the sixth nanosheet in the second direction is greater than the width of the first nanosheet in the second direction, and, in a planar view, the end of the first side of the first nanosheet and the end of the first side of the sixth nanosheet are arranged at the same position in the second direction.

8. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region forming a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region forming a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction; a second gate wiring extending in the second direction and surrounding an outer periphery of the first nanosheet in the second direction and in the third direction; a first power supply wiring formed on a back side of the first transistor and extending in the first direction; and a second power supply wiring formed on a back side of the second transistor and extending in the first direction. a first via formed in a region in the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, connecting the source in the first active region to the first power supply wiring; the second nanosheet is arranged on a first side which is one side of the first nanosheet in the second direction, a surface of the first nanosheet on the first side being exposed from the first gate wiring, and a surface of the second nanosheet on the second side which is the other side in the second direction being exposed from the second gate wiring, and an overlap amount of the first side of the first active region with the first via in the second direction is greater than an overlap amount of the first side of the first power supply wiring with the first via in the second direction.

9. A semiconductor integrated circuit device according to claim 8, wherein the first standard cell is formed in a region in the second active region where a region serving as the source of the second transistor overlaps with the second power supply wiring, and further comprises a second via connecting the source in the second active region to the second power supply wiring, and an overlap amount of the second side of the second active region in the second direction with the second via is greater than an overlap amount of the second side of the second power supply wiring in the second direction with the second via.

10. A semiconductor integrated circuit device according to claim 8, wherein the plurality of standard cells include a second standard cell arranged adjacent to the second side of the first standard cell, the second standard cell constituting a channel, source and drain of a third transistor of the first conductivity type, and comprising: a third active region including a third nanosheet extending in the first direction as the channel; and a third gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second and third directions, the second side surface of the third nanosheet being exposed from the third gate wiring, and the distance between the first active region and the third active region in the second direction being greater than the distance between the first active region and the second active region in the second direction.

11. A semiconductor integrated circuit device according to claim 8, wherein the first via has a length in the second direction longer than a length in the first direction.

12. A semiconductor integrated circuit device according to claim 8, wherein the first active region constitutes a channel, source and drain of a fourth transistor of the first conductivity type, and includes a fourth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a fifth transistor of the second conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the first standard cell comprises: a fourth gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the third direction; and a fifth gate wiring extending in the second direction and surrounding the periphery of the fifth nanosheet in the second direction and the third direction; the first power supply wiring is formed on the back side of the fourth transistor; the second power supply wiring is formed on the back side of the fifth transistor; the fifth nanosheet is disposed on the first side of the fourth nanosheet; and the surface of the fourth nanosheet on the first side is exposed from the fourth gate wiring; A semiconductor integrated circuit device, wherein the fifth nanosheet has a second side surface exposed from the fifth gate wiring.

13. A semiconductor integrated circuit device according to claim 8, wherein the plurality of standard cells include a third standard cell arranged alongside the first standard cell in the first direction, the third standard cell comprising: a fourth active region constituting a channel, source and drain of a sixth transistor of the first conductivity type and including a sixth nanosheet extending in the first direction as the channel; a fifth active region constituting a channel, source and drain of a seventh transistor of the second conductivity type and including a seventh nanosheet extending in the first direction as the channel; a sixth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; and a seventh gate wiring extending in the second direction and surrounding the periphery of the seventh nanosheet in the second direction and the third direction, the seventh nanosheet being arranged on the first side of the sixth nanosheet, the surface of the sixth nanosheet on the first side being exposed from the sixth gate wiring, and the surface of the seventh nanosheet on the second side being exposed from the seventh gate wiring, A semiconductor integrated circuit device, wherein, in a planar view, the width of the sixth nanosheet in the second direction is greater than the width of the first nanosheet in the second direction, and, in a planar view, the end of the first side of the first nanosheet and the end of the first side of the sixth nanosheet are arranged at the same position in the second direction.

14. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region forming a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region forming a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and surrounding an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first direction and the second direction; a second gate wiring extending in the second direction and surrounding an outer periphery of the second nanosheet in the second direction and in the third direction; a first power supply wiring formed on a back side of the first transistor and extending in the first direction; and a second power supply wiring formed on a back side of the second transistor and extending in the first direction. a first via formed in a region in the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, connecting the source in the first active region to the first power supply wiring; the second nanosheet is arranged on a first side that is one side of the first nanosheet in the second direction; a surface of the first nanosheet on a second side that is the other side in the second direction is exposed from the first gate wiring; and a surface of the second nanosheet on the first side is exposed from the second gate wiring; and the first via is arranged in a center of the first active region in the second direction in a planar view.

15. A semiconductor integrated circuit device according to claim 14, wherein the first standard cell is formed in a region in the second active region where a region serving as the source of the second transistor overlaps with the second power supply wiring, and further comprises a second via connecting the source in the second active region to the second power supply wiring, and the second via is positioned in the center of the second active region in the second direction in a planar view.

16. A semiconductor integrated circuit device according to claim 14, wherein the plurality of standard cells include a second standard cell arranged adjacent to the second side of the first standard cell, the second standard cell constituting a channel, source and drain of a third transistor of the first conductivity type, and comprising: a third active region including a third nanosheet extending in a first direction as the channel; and a third gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second direction and the third direction, the surface of the third nanosheet on the first side being exposed from the third gate wiring, and the distance between the first active region and the third active region in the second direction is smaller than the distance between the first active region and the second active region in the second direction.

17. A semiconductor integrated circuit device according to claim 14, wherein the first via has a length in the second direction longer than a length in the first direction.

18. A semiconductor integrated circuit device according to claim 14, wherein the first active region constitutes a channel, source and drain of a fourth transistor of the first conductivity type, and includes a fourth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a fifth transistor of the second conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the first standard cell comprises: a fourth gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the third direction; and a fifth gate wiring extending in the second direction and surrounding the periphery of the fifth nanosheet in the second direction and the third direction; the first power supply wiring is formed on the back side of the fourth transistor; the second power supply wiring is formed on the back side of the fifth transistor; the fifth nanosheet is disposed on the first side of the fourth nanosheet; and the second side surface of the fourth nanosheet is exposed from the fourth gate wiring; A semiconductor integrated circuit device, wherein the fifth nanosheet has a surface on the first side exposed from the fifth gate wiring.

19. A semiconductor integrated circuit device according to claim 14, wherein the plurality of standard cells include a third standard cell arranged alongside the first standard cell in the first direction, the third standard cell comprising: a fourth active region constituting a channel, source and drain of a sixth transistor of the first conductivity type and including a sixth nanosheet extending in the first direction as the channel; a fifth active region constituting a channel, source and drain of a seventh transistor of the second conductivity type and including a seventh nanosheet extending in the first direction as the channel; a sixth gate wiring extending in the second direction and surrounding the periphery of the sixth nanosheet in the second direction and the third direction; and a seventh gate wiring extending in the second direction and surrounding the periphery of the seventh nanosheet in the second direction and the third direction, the seventh nanosheet being arranged on the first side of the sixth nanosheet, the second side surface of the sixth nanosheet being exposed from the sixth gate wiring, and the first side surface of the seventh nanosheet being exposed from the seventh gate wiring, A semiconductor integrated circuit device, wherein, in a planar view, the width of the sixth nanosheet in the second direction is greater than the width of the first nanosheet in the second direction, and, in a planar view, the end of the first nanosheet on the second side and the end of the sixth nanosheet on the second side are arranged at the same position in the second direction.

Images