Multi-planar static random-access memory

Abstract

A novel SRAM cell employs two or more MBT transistors formed on a plane of a semiconductor die over the plane of the die on which CMOS logic circuitry is formed. By using MBT transistors formed over the CMOS logic plane of the die, the area required on that CMOS logic plane is reduced. Reducing the required area provides several advantages, including increased memory cell densities, reduced length of signal and power leads to the SRAM cells with a commensurate decrease in power losses, thermal heating and parasitic capacitances.

Description

Multi-Planar Static Random-Access MemoryCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of US provisional patent app. no. 63 / 606,199, filed, Dec. 5, 2023, which is incorporated herein by reference.FIELD OF THE INVENTION

[0002] The present invention relates to static random-access memory (SRAM). More specifically, the present invention relates to an SRAM cell with components formed on at least two different planes of a semiconductor SRAM device and to arrays of such SRAM cells and to semiconductor devices, such as computational devices, which employ them.BACKGROUND OF THE INVENTION

[0003] Static random-access memory (SRAM) is a type of digital memory which offers faster performance and simpler access than dynamic random-access memory (DRAM) but at the cost of requiring more silicon area than DRAM memory. SRAM is often preferably employed as memory in embedded devices and as cache memories in computational devices, etc.[ooo4] Typically, SRAM is fabricated as a complementary metal-oxide-semiconductor (CMOS) semiconductor device comprising a large array of repeated SRAM cells, each cell being capable of storing one bit of information, and a set of ancillary components, such as sense amplifiers, address decoders, timing units, etc. For many applications / use cases where the SRAM is to be integrated onto the same die as the other circuitry, such as the above-mentioned computational devices, SRAM is the memory structure of choice due to its speed performance and simpler manufacturing, as well as its reliable operation over a wide range of voltages and temperatures.[ooos] As demand for memory increases, it is desired to decrease the area of the semiconductor die occupied by each SRAM cell to increase the density of the cells, and thus the amount of memory that can be provided in an area of the semiconductor die.

[0006] To date, efforts to reduce the area required by SRAM cells have concentrated on reducing feature sizes of the circuit elements in the cell (i.e. - making smaller transistors, etc.) and / or developing circuit designs which require fewer transistors to operate. While these two approaches have improved SRAM cell densities, they each have various disadvantages including increased fabrication costs, decreased noise tolerance, decreased yield, reduced operational margins, etc. and they both have obvious limitations; specifically feature sizes cannot continue to be easily reduced and transistor counts for functional SRAM designs have minimum numbers, which appear to have already been reached.

[0007] It is desired to have a novel SRAM cell, SRAM device and semiconductor devices including SRAM memory, which employ SRAM cells with a reduced area requirement.SUMMARY OF THE INVENTION

[0008] It is an object of the present invention to provide novel static random-access memory cells and devices that obviate or mitigate at least one disadvantage of the prior art.

[0009] According to an aspect of the present invention, a static random-access memory cell includes a first inverter including a first pair of serially connected transistors including an n-type semiconductor thin-film transistor (TFT) and a second inverter including a second pair of serially connected transistors including an n-type semiconductor TFT. An input of the second inverter is connected to an output of the first inverter and an input of the first inverter is connected to an output of the second inverter. The static random-access memory cell further includes a first access transistor connected between a bit line and the output of the first inverter and a second access transistor connected between an inverted bit line and the output of the second inverter.The n-type semiconductor TFT of each inverter are formed on at least one TFT plane that is formed over a complementary metal-oxide-semiconductor (CMOS) plane of a semiconductor die.

[0010] According to another aspect of the present invention, a method of making a static random-access memory cell includes forming an n-type semiconductor TFT of the static random-access memory cell at a TFT plane over a CMOS plane of a semiconductor die, and connecting the n-type semiconductor TFT to a device at the CMOS plane. toon] According to another aspect of the present invention, a static random-access memory cell includes an arrangement of transistors forming two cross coupled inverters at a semiconductor die. At least one of the transistors of the arrangement of transistors is an n-type semiconductor TFT formed by a Back End of Line (BEOL) process, a Middle of Line (MOL) process, or a combination thereof. The n-type semiconductor TFT is positioned at a plane different to a CMOS plane of the semiconductor die.

[0012] According to an another aspect of the present invention, there is provided a static random-access memory cell on a semiconductor die, including a word line to select the cell and a bit line and a logic inverse of the bit line and comprising: a first inverter comprising a serially connected p-type transistor and an n-type transistor, the first inverter connected between a voltage source and an electrical ground; a second inverter comprising a second serially connected p-type transistor and an n-type transistor, the second inverter also being connected between the voltage source and the electrical ground and wherein the input of the second inverter is connected to the output of the first inverter and the input of the first inverter is connected to the output of the second inverter; a first access transistor connected between the bit line and the output of the first inverter; a second access transistor connected between the logic inverse bit line and the output of the second inverter, the first and second access transistors responsive to the word line to connect the first and second inverters to the respective bit line and logic inverse bit line; and wherein the n-type transistors of each inverter are MBTs, which are transistors formed by MOL and / or BEOL processes (discussed in detail below), that are formed on a plane of the semiconductor die over aCMOS plane on which the p-type transistors of each inverter are formed, the MBTs being formed after FEOL processing is complete.

[0013] According to another aspect of the present invention, there is provided a static random-access memory cell on a semiconductor die, including a word line to select the cell and a bit line and a logic inverse of the bit line and comprising: a first inverter comprising a serially connected p-type transistor and an n-type transistor, the first inverter connected between a voltage source and an electrical ground; a second inverter comprising a second serially connected p-type transistor and an n-type transistor, the second inverter also being connected between the voltage source and the electrical ground and wherein the input of the second inverter is connected to the output of the first inverter and the input of the first inverter is connected to the output of the second inverter; a first access transistor connected between the bit line and the output of the first inverter; a second access transistor connected between the logic inverse bit line and the output of the second inverter, the first and second access transistors responsive to the word line to connect the first and second inverters to the respective bit line and logic inverse bit line; and wherein each n-type transistors of each inverter is an MBT comprising: an insulator formed on a plane of the semiconductor die over a CMOS plane on which the p-type transistors of each inverter are formed; a source formed on the insulator; a drain formed on the insulator; an n-type semiconductor member; a source-channel interfacial member formed on the insulator and extending between at least the n-type semiconductor member and the source; a gate dielectric formed over the n-type semiconductor member; a gate formed on the gate dielectric; an n-type semiconductor carrier reservoir formed on the source; a source electrode formed on the carrier reservoir; a gate electrode formed on the gate; and a drain electrode formed on the drain; and wherein a channel is formed in the n- type semiconductor member when a threshold voltage is applied to the gate electrode, the channel conducting charge carriers through the n-type semiconductor member and wherein the carrier reservoir provides a reservoir of negative charge carriers to mitigate carrier starvation through the channel of the n-type semiconductor member and wherein the source-channel interfacial member provides a repository of complimentary excess negative charge that functions to deplete the channel in at least the region of the n-typesemiconductor member adjacent the source and the carrier reservoir when the threshold voltage is not applied to the gate electrode.

[0014] According to another aspect of the present invention, there is provided a static random-access memory cell on a semiconductor die, the memory cell including transistors formed on at least two planes of the semiconductor die and including a word line to select the cell and a bit line and a logic inverse of the bit line to read from and write to the cell and comprising: a first inverter comprising a serially connected p-type transistor and an n-type transistor, the first inverter connected between a voltage source and an electrical ground; a second inverter comprising a second serially connected p- type transistor and an n-type transistor, the second inverter also being connected between the voltage source and the electrical ground and wherein the input of the second inverter is connected to the output of the first inverter and the input of the first inverter is connected to the output of the second inverter; a first access transistor connected between the bit line and the output of the first inverter; a second access transistor connected between the logic inverse bit line and the output of the second inverter, the first and second access transistors responsive to the word line to connect the first and second inverters to the respective bit line and logic inverse bit line; and wherein the p-type transistors are formed on a first plane of the semiconductor die on which CMOS logic circuitry is formed and the n-type transistors of each inverter are MBTs formed on a second plane of the semiconductor die over the plane on which the CMOS logic circuitry has been formed in FEOL processes.

[0015] The present invention provides a static random-access memory cell which employs transistors, at least one of which is formed by a Back End of Line process, Middle of Line process, or combination thereof on a plane of a semiconductor die over a plane of the semiconductor die on which the CMOS transistors are formed, so as to reduce the required area for the cell in that CMOS plane on the die.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:[oo ] Figure 1 is a schematic diagram of a circuit of a prior art six-transistor SRAM cell;

[0018] Figure 2 is a schematic diagram of an SRAM cell in accordance with an aspect of the present invention;

[0019] Figure 3 is a cross-sectional view through a semiconductor die in accordance with another aspect of the present invention;

[0020] Figure 4 is a schematic diagram of a circuit of an SRAM cell in accordance with another aspect of the present invention;

[0021] Figure 5 is a cross-sectional view through another semiconductor die in accordance with another aspect of the present invention;

[0022] Figure 6 is a schematic diagram of a circuit of another SRAM cell in accordance with an aspect of the present invention;

[0023] Figure 7 is a schematic diagram of a circuit of another SRAM cell in accordance with an aspect of the present invention;

[0024] Figure 8 is a schematic diagram of a circuit of another SRAM cell in accordance with an aspect of the present invention;

[0025] Figure 9 is a cross-sectional view of a thin-film transistor (TFT) in accordance with an aspect of the present invention;

[0026] Figure 10 is a cross-sectional view of a primary current path through the TFT of Figure 10 when the TFT is in the ON state;

[0027] Figure 11 is a cross-sectional view of another TFT in accordance with an aspect of the present invention;

[0028] Figure 12 is a cross-sectional view of another TFT in accordance with an aspect of the present invention;

[0029] Figure 13 is a cross-sectional view through another semiconductor die inaccordance with another aspect of the present invention.

[0030] Figure 14 is a flowchart of a method of making an SRAM cell in accordance with another aspect of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0031] A widely employed prior art circuit for an SRAM cell is indicated generally at 20 in Figure 1. The illustrated circuit is a six-transistor design (6T SRAM) wherein transistors M1 and M2 form a first inverter which is cross linked to a second inverter, formed by transistors M3 and M4. In each inverter, the n-type transistor (M2 and M4) is commonly referred to as the “drive” transistor and the p-type transistor (M1 and M3) is referred to as the “load” transistor.

[0032] The inverters, which are connected between a voltage source VDD and ground, store one data bit in cell 20 and, to improve the read and write margins of cell 20, the data is written and read as a differential signal across the two inverters. As is well understood, the n-type transistors are designed to have sufficient strength to maintain their state during a read operation, thus enabling a non-destructive read of data stored in the cell.

[0033] Each inverter is connected, via a respective access transistor (M5 and M6) to a respective bit line, BL and BL , and each access transistor M5 and M6 is controlled by a word line WL. Both read and write operations are performed through the bit lines, via access transistors M5 and M6.

[0034] As is well known by those of skill in the art, a variety of other SRAM cell designs are known and used, including eight and ten transistor designs (8T SRAM and 10T SRAM, etc.) and the present invention, as described below, is applicable to other designs, such as 8T SRAM, 10T SRAM, etc. and is not limited to use with 6T SRAM.

[0035] The present inventors have determined that a reduction in area of SRAM cells can be achieved by fabricating the cell with at least two different, stacked, planes of transistors on the semiconductor die. In particular, it has been determined thattransistors such as those described in published PCT application WO 2023 / 285936 to Barlage et al., which is assigned to the assignee of the present invention and is incorporated herein by reference, and / or those described below with respect to Figures 9 - 12, can be employed. Such a transistor, herein referred to as a thin-film transistor (TFT) with an n-type semiconductor, an n-type semiconductor TFT, an n-type transistor, an n-type TFT, or an “MBT”, can be fabricated over CMOS logic on a die, after the CMOS logic has been fabricated in Front End of Line (FEOL) processes. MBTs are fabricated in Middle of Line (MOL) and / or Back End of Line (BEOL) processes and can be fabricated on planes of a semiconductor die over CMOS logic previously formed thereon, and over other planes of MBTs (i.e. - enabling a stacked arrangement of MBTs) and MBTs can be formed in lateral (horizontal) and vertical (+Z-axis) configurations.

[0036] For sake of explanation, a “plane” may be considered a base layer at which transistors or other semiconductor devices may be formed, with the understanding that such transistors / devices may include doped regions, layers of deposited material, and similar structures. A stack of layers of a TFT may be said to be located at a plane. The terms “plane” and “layer” are used interchangeably where appropriate.

[0037] Figure 2 shows an example of a 6T SRAM cell 100 in accordance with one aspect of the present invention. In cell 100, n-type transistors M11 and M13 are formed as MBTs transistors (as indicated by the different schematic symbol, with the offset gate, used for these transistors in the Figures) on a plane of the semiconductor device atop the plane of CMOS logic on which p-type transistors M10 and M12 are formed. Transistors M11 and M13 are connected to the other components and to signal and control lines of cell 100 by vias, as will be understood by those of ordinary skill in the art given the benefit of this disclosure.

[0038] By forming transistors M11 and M13 on a plane atop the remainder of cell 100, the area required for cell 100, compared to prior art cell 20, is significantly reduced and it is contemplated that a reduction in required area on the CMOS logic plane for cell 100 of at least 20% can be obtained compared to that required for cell 20.

[0039] It is also contemplated that, in some circumstances, access transistors M14 and M15 can also be formed as MBTs transistors on a plane of the semiconductor device atop the plane of CMOS logic and on, or atop, the plane on which transistors M11 and M13 are formed. In such a case, a further reduction in the required area for cell 100 in the CMOS plane will be obtained.

[0040] Figure 3 shows a schematic representation, not to scale, of a cross section through a semiconductor die 200, such as a memory device, a computational device with onboard SRAM or any other semiconductor device which includes SRAM memory, on which SRAM cell 100 has been formed.

[0041] Die 200 includes a substrate 204, such as a silicon wafer, upon which the semiconductor device is fabricated. Substrate 204 is not limited to being a silicon wafer and, depending on the semiconductor device being fabricated; substrate 204 can be glass, plastic, sapphire, diamond or any suitable substance as will be apparent to those of ordinary skill in the art given the benefit of this disclosure.

[0042] An insulating layer 208, such as a layer of silicon dioxide or another suitable material, is formed over substrate 204 and CMOS logic 212 is then formed over insulating layer 208, for example using well known FEOL manufacturing techniques and processes. The insulating layers discussed herein may be interlayer dielectric (ILD).

[0043] After the plane containing the CMOS logic 212 has been formed, a layer 216 of insulating material is formed over CMOS logic 212 and Back End of Line processes are used to form a plane of one or more metalization layers 220, which act as interconnects and supply and ground connections, to carry power and signals between circuit elements of CMOS logic layers 212 and which are connected thereto by vias through insulating layer 216.

[0044] Another insulating layer 224 is then formed atop the metalization layers 220, and MBT transistors, as described above, are formed in a plane 228. The transistors of plane 228 are then appropriately connected to circuit elements in CMOS logic layers 212, and / or to the metalization layers of plane 220, as appropriate, by vias throughinsulating layer 224, metalization layers 220 and insulating layer 216, to complete SRAM cell 100. An appropriate encapsulation layer 232 can then be formed over the MBT transistor plane 228 to complete the semiconductor device in a conventional manner.

[0045] As will be apparent to those of ordinary skill in the art, a typical semiconductor device will often employ many millions of SRAM cells, typically arranged in arrays to obtain the necessary rows and columns of memory storage required by the device. Accordingly, while the area saved with a single SRAM cell 100 of the present invention is relatively insignificant, when multiplied by the millions, or more commonly billions, of instances of SRAM cell 100 on a semiconductor device, a significant reduction in the required area for the SRAM memory subsystem is obtained.

[0046] Further, in addition to saving area, the reduced area of SRAM cell 100 reduces the length of the signal lines and power connections to and between SRAM cells 100. By reducing those lengths, the inherent power loss in those lines and interconnects is reduced, saving power and reducing the related thermal losses and effects. Reducing the line lengths also reduces parasitic capacitance in those lines, to allow faster switching of SRAM cells 100.

[0047] Figure 4 shows another SRAM cell 300, in accordance with an aspect of the present invention, which is similar to that shown in Figure 2, and discussed above, and wherein like components to those of Figure 2 are indicated with like reference numerals In cell 300, the access transistors M16 and M17 are now p-type transistors. In this configuration, bit lines BL are pre-charged to a logic low (zero) before a read operation, rather than being pre-charged to a logic high (one) as was the case for the prior art cell of Figure 1 and the embodiment of Figure 2.

[0048] In cell 300, the use of p-type transistors for access transistors M16 and M17 improves the read and write margins for p-type drive transistors M10 and M12.

[0049] As mentioned above, it is also contemplated that, if desired, two or more planes of MBT transistors can be formed over a CMOS logic plane. Figure 5 shows a crosssection of a semiconductor die 400, similar to that of die 200 of Figure 3, but further comprising an insulating layer 236 formed over the first plane 228 of MBT transistors and including a second plane 240 of MBT transistors formed on insulating layer 236. In such a configuration, plane 228 could include the n-type transistors of the inverters formed on it while n-type access transistors are formed on plane 240, etc.

[0050] As will be apparent, a variety of circuit arrangements can be employed to take advantage of the multiple planes of MBT transistors of Figure 5, with commensurate reductions in the area required for an SRAM cell in accordance with the present invention. Additionally, flexibility of realizing an SRAM cell on multiple planes enables it to have a greater flexibility to improve read and / or write margins without increasing its footprint in X and Y domains.

[0051] As was also discussed above, it will now be apparent to those of ordinary skill in the art, given the benefit of this disclosure, that the present invention is not limited to use with 6T SRAM cells and other SRAM cell designs can benefit from the present invention by replacing one or more CMOS n-type transistors of the cell with MBT transistors formed on one or more planes over the CMOS logic planes and metalization planes.

[0052] Figure 6 shows an eight transistor (8T) SRAM cell 500 in accordance with an aspect of the present invention. In cell 500, components which are similar to those described above with respect to Figure 2 are indicated with like reference numerals.Cell 500 is written to as described above for cell 100, using Write Bit Line (WBL) and its logical inverse, Write Bit Line Bar ( WBL ), with transistors M14 and M15 turned on by Write Line (WL).

[0053] The read operation of cell 500 differs from that of the 6T cell 100 in that It involves two additional transistors M18 and M19, which are n-type MOS transistors. To perform the read, the read word line (RWL) is set high to turn on transistor M18. If the contents of cell 500 are a logic “0”, transistor M19 will be on, as the output of the inverter formed by M12 and M13 will be high, and RBL will be connected to ground through M18 and M19, resulting in RBL being “0”. Conversely, if the contents of cell 500are a logic “1”, then transistor M19 is off and RBL is not connected to ground and RBL remains at its pre-charge value of “1”.

[0054] In the embodiment illustrated in Figure 6, transistors M11 and M13 are both MBT transistors and are formed on a plane of the die, such as plane 228 of Figure 5, over the plane 212 on which the CMOS transistors are formed. The access transistors M14 and M15 are also MBT transistors formed on a plane over the plane 212 on which the CMOS transistors are formed. The plane on which access transistors M14 and M15 are formed can be the same plane 228 on which transistors M11 and M13 are formed, or transistors M14 and M15 can be formed on another plane, such as plane 240, over the plane 228 on which transistors M11 and M13 are formed, or vice-versa. It will be further understood that, in some circumstances, n-type transistors M18 and M19 can also be MBTs formed on a plane, such as plane 228 and / or 240 of Figure 5, over the plane 212 on which the CMOS transistors are formed, whether on a plane with one or both of transistors M11 and M13 and / or transistors M14 and M15, or on a plane over another plane of the die.

[0055] Figure 7 shows a ten transistor (10T) SRAM cell 600 in accordance with another aspect of the present invention. In the embodiment illustrated in the Figure, transistors M11 , M13, M14 and M15 are MBT transistors, while transistors M10 and M12 are p- type CMOS transistors and transistors M22, M23, M24 and M25 are n-type CMOS transistors. As will be apparent to those of ordinary skill in the art given the benefit of this disclosure, any or all of the n-type transistors of cell 600 can be MBT transistors and those transistors can be formed on a single plane (e.g. plane 228) over the plane (e.g. 212) on which the CMOS logic is formed, or the n-type transistors can be formed on two or more planes (e.g. 228, 240, etc.) over the plane (e.g. 212) on which the CMOS logic is formed. loose] Figure 8 shows a six transistor (6T) SRAM cell 800 in accordance with another aspect of the present invention. The SRAM cell 800 is similar to the SRAM cell 100 discussed above, and only differences will be discussed in detail. In this embodiment, all transistors M11 , M13, M14, M15, M30 and M32 are MBT transistors and the twotransistors M30 and M32 connected to the voltage source VDD have their gates connected to a DC bias voltage Vbias. The bias voltage Vbias is kept at lower voltage under static condition to reduce the leakage current through the cell. For example, it could be set to the threshold voltage of the MBT transistor. On the other hand, the bias voltage Vbias should be sufficiently large to maintain the stability of the cell. Under read and / or write conditions, the bias voltage Vbias is increased to enhance read and / or write margins. Since all transistors are MBTs, they may be provided at one or more BEOL / MOL planes 228, 240, etc. (see Figures 3 and 5) that are disposed over a FEOL plane 212 that has CMOS devices. Any one or combination of transistors M11 , M13, M14, M15, M30 and M32 may be provided to a given BEOL / MOL plane 228, 240, etc., as may be determined by implementation requirements. Accordingly, the entire memory cell 800 may be situated above CMOS devices, which may also include memory cells or may implement other devices. This may further increase the spatial efficiency and other advantages of the present invention.

[0057] In the SRAM cell 800, a bias voltage Vbias may be programable as voltage Vprog. The programmable bias voltage Vprog allows for read, write, and hibernation operations under varying process conditions. For example, when MBT transistors are processed at the best “process corner” (“process corner” refers to variations in manufacturing parameters when forming an integrated circuit design on a semiconductor wafer, in that process comers represent extremes of parameter variations within which the circuit should function as intended), the programmable voltage Vprog can be reduced or optimized to provide an enhanced read and / or write margin. Similarly, when MBT transistors are processed at the worst process corner, the programmable voltage Vprag can be increased or optimized differently. As will be apparent to one of ordinary skill in the art given the benefit of this disclosure, the programmable bias voltage provides a way to compensate for process variations.

[0058] With reference to Figures 9 - 12, examples of MBTs, which are suitable for use with the embodiments of SRAM cells described above, will now be discussed. As mentioned, MBTs are made using BEOL and / or MOL processes.

[0059] A TFT in accordance with an aspect of the present invention is indicated generally at 900 in Figure 9. TFT 900 is formed on an insulating substrate 24, such as a layer of a suitable dielectric such as silicon dioxide, etc. Substrate 24 may be ILD.

[0060] All TFTs, including TFT 900, have the basic structure of a field effect transistor and include a source 28, a drain 32 and a gate 36. In TFT 900, source 28 and drain 32 can be elemental materials or compounds of materials with conducting properties, such as a metal or a degenerate (highly doped) semiconductor. Examples of suitable materials that can be used as source 28 or drain 32 include: nickel, tungsten, molybdenum, aluminum; gold; copper; cobalt; ruthenium; titanium nitride; tantalum nitride; ruthenium, silicon; and / or any lll-V compound semiconductor with a high conductivity. The specific selection of material for source 28 is made in conjunction with the selected material for gate 36 and the selection of these two materials results in the primary determination of the threshold voltage of TFT 900.

[0061] Source 28 is connected to a source electrode 40 through a carrier reservoir 28a. Carrier reservoir 28a is preferably formed of an n-type semiconductor material which is much more heavily n-type than semiconductor member 48, discussed below. Examples of suitable materials for carrier reservoir 28a include heavily n-doped poly-silicon or germanium, tin oxide, zirconium, molybdenum, tungsten, etc.

[0062] Similarly, in TFT drain 32 is connected to drain electrode 44 through a drain reservoir 32a. The materials of which drain reservoir 32a and drain 32 are formed are preferably selected to provide effective conduction of carriers out of the channel of semiconductor member 48 and they can be the same material or, more commonly, different materials.

[0063] Drain electrode 44 can be any suitable material to form a desired electrical connection between drain reservoir 32a and other circuitry that connects to TFT 900.

[0064] An n-type semiconductor member 48 is formed to extend between source 28 and drain 32, and to contact carrier reservoir 28a and drain reservoir 32a. Semiconductor member 48 comprises any suitable metal oxide, such as: zinc oxide; tin oxide; indiumgallium zinc oxide (IGZO); gallium oxide; germanium oxide; etc. The n-type semiconductor material of which semiconductor member 48 is formed is preferably selected such that it can be formed and annealed at temperatures not exceeding about 400 °C.

[0065] A gate dielectric member 52, which can be any suitable dielectric material, such as silicon dioxide, hafnium oxide, etc., is formed over semiconductor member 48 and gate 36 is formed on gate dielectric member 52. Gate 36, which can be any suitable material, such as titanium, titanium nitride, chromium, tungsten, hafnium, tantalum nitride or any other single element or bimetal element or compound, as will occur to those of ordinary skill in the art, is connected to a gate electrode 58 which is selected to optimize the electrical connection between gate 36 and other circuitry that connects to TFT 900.

[0066] As is known to those of ordinary skill in the art, when an electric field is applied to gate 36, a conductive channel is formed through semiconductor member 48, allowing current to flow through this channel, from carrier reservoir 28a and source 28 to drain reservoir 32a and drain 32.

[0067] Source electrode 40 is electrically insulated from gate 36 and gate electrode 58 by a source dielectric member 62 and drain electrode 44 is electrically insulated from gate 36 and gate electrode 58 by drain dielectric member 66. Source dielectric member 62 and drain dielectric member 66 can be any suitable dielectric material, such as silicon dioxide, etc. In some cases, source dielectric member 62 and drain dielectric member 66 will be low-K dielectrics, while gate dielectric member 52 will be a high-K dielectric, but in other cases source dielectric member 62, drain dielectric member 66 and gate dielectric member 52 can be formed of the same material.

[0068] In order to enhance the OFF state performance of TFT 900, a source-channel interfacial member 70 may be provided to increase the threshold voltage at which TFT 900 turns ON, making the transistor operate in enhancement mode, and can reduce the leakage current through TFT 900 in the OFF state.

[0069] Specifically, source-channel interfacial member 70 is provided to create a repository of complimentary excess negative charge that functions to deplete the channel in at least the region of semiconductor member 48 adjacent source 28 and carrier reservoir 28a. In this manner, source-channel interfacial member 70 serves as an electron transport barrier, resulting in substantially no current flow through semiconductor member 48 when TFT 900 is in an ‘OFF’ state.

[0070] The operation of source-channel interfacial member 70 can be achieved when source-channel interfacial member 70 is formed in a variety of configurations, including a p-type semiconductor, an induced piezoelectric dipole, a controllable tunneling barrier, combinations thereof or other mechanisms to modulate injected current by an external applied field.

[0071] For example, when implemented as a p-type semiconductor, source-channel interfacial member 70 can include elemental germanium or source-channel interfacial member 70 can be formed by using a p-type dopant in a relevant portion of semiconductor member 48. In other cases, source-channel interfacial member 70 can include an oxide, nitride, or sulfide, or another element corresponding to group VI (A) of the periodic table, such as ruthenium oxide, silicon nitride, nickel oxide, copper oxide, molybdenum oxide, iridium oxide, or the chalcogens, such as oxygen, sulfur, selenium, tellurium or polonium. In various examples, source-channel interfacial member 70 is formed by applying oxygen plasma to the material that forms the source 28.

[0072] Source-channel interfacial member 70 can also be formed by a catalytic growth of the material that forms source 28. In such cases, oxygen can preferentially traverse to the source-channel interface, creating source-channel interfacial member 70. In other cases, source-channel interfacial member 70 can be formed by depositing a p-type material, such as a p-type metal oxide or another semiconductor, by way of a deposition technique, such as atomic layer deposition, sputtering physical vapor deposition or chemical vapor deposition.

[0073] It has been found, due to the efficacy of source-channel interfacial member 70 in TFT 900, that TFT 900 can experience carrier starvation when in the ON state. Toprovide a reservoir of negative charge carriers to mitigate carrier starvation, charge carrier reservoir 28a and drain reservoir 32a are formed at each respective end of semiconductor member 48.

[0074] In the example of Figure 9, and as mentioned above, carrier reservoir 28a is formed between source 28 and source electrode 40, adjacent semiconductor member 48. Carrier reservoir 28a can be formed from the same material as source 28, while in other implementations, carrier reservoir 28a is preferably formed of other suitable materials which are selected such that the electron barrier between the channel formed in semiconductor member 48 and carrier reservoir 28a and source 28 is minimized, or forms a slowly increasing gradient, so that electrons do not experience a significant reflection probability when traversing the boundary between reservoir 28a, source 28 and semiconductor member 48

[0075] Carrier reservoir 28a preferably has an effective electron mass, or density, of available electronic states that are at a similar level as the channel material of semiconductor member 48 itself. Carrier reservoir 28a can be a monoatomic semiconductor such as silicon, germanium, or tin that is degenerately doped or can be a binary, ternary quaternary, etc., semiconductor material that is doped to produce a high degree of electrons.

[0076] Generally, carrier reservoir 28a should not be a metal because the large density of states in the metal can give rise to a reflection at the interface to the channel formed in semiconductor member 48 and the pre-channel of semiconductor member 48 due to the disparity between available electron states.

[0077] In the example of Figure 9, drain reservoir 32a is formed between drain 32 and drain electrode 44, adjacent semiconductor member 48. Drain reservoir 32a serves as an electron receiver to enhance the flow of electrons out of the channel formed in semiconductor member 48.

[0078] As shown in Figure 10, when a sufficient voltage is applied to gate 36 to place TFT 900 into the ON state, (i.e. - a voltage equal to, or exceeding the threshold voltageis applied to gate 36), the majority of current flows from source electrode 40, through carrier reservoir 28a, into the channel formed in semiconductor member 48, as indicated by the thick arrow in Figure 10. A comparably small amount of current also flows from source electrode 40, through carrier reservoir 28a into source 28 and then into the channel formed in semiconductor member 48, as indicated by the thin arrow in Figure 10.

[0079] TFT 900 can be manufactured with a wide variety of BEOL and / or MOL processes.

[0080] The manufacture of members and / or features of the TFTs discussed herein is referred to herein as “forming.” Unless otherwise mentioned, “forming” is intended to include all semiconductor manufacturing techniques suitable and applicable therefor including, without limitation, deposition (e.g., chemical vapor deposition or CVD, atomic layer deposition or ALD, physical vapor deposition or PVD, etc.), plasma- enhanced / assisted atomic layer deposition (PEALD / PAALD), thermal ALD (T-ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, lithography / photolithography, etching, implantation, annealing, oxidation, and similar processes. While examples of specific types of forming are given below, it should be understood that comparable methods of forming may be alternatively or additionally used, unless otherwise mentioned, without departing from the present invention.

[0081] Figure 11 shows another TFT 1100 in accordance with an aspect of the present invention and wherein like elements to those discussed above with reference to Figure 9 are indicated with like reference numerals.

[0082] Specifically, in TFT 1100, drain reservoir 32a has been omitted. TFT 1100 still offers enhanced threshold voltage levels, as described with reference to TFT 900 above, but will have a different, higher, breakdown voltage.

[0083] Figure 12 shows another TFT 1200 in accordance with an aspect of the present invention and wherein like elements to those discussed above with reference to Figure 9 are indicated with like reference numerals. In this example, the performancecharacteristics of TFT 1200 have been established by further forming interface metals 94 and 98 respectively between carrier reservoir 28a and source electrode 40 and between drain reservoir 32a and drain electrode 44. Interface metals 94 and 98 can be titanium, tin, hafnium, zirconium and other metals that form a conducting oxide in small forms. When annealed, interface metals 94 and 98 function to draw oxygen out of carrier reservoir 28a and / or drain reservoir 32a as oxygen deficiencies accumulate, thus making the underlying semiconductor materials of carrier reservoir 28a and / or drain reservoir 32a more heavily n-type. It is contemplated that a layer of 1 to 2 nm of these interface metals is sufficient. It is also contemplated that interface metal 98 can be omitted from TFT 1200, if desired.

[0084] A particular advantage of the TFTs 900, 1100 and 1200 is that the materials and forming processes may be limited to those usable at the MOL and / or BEOL. This provides for the stacking of TFTs over CMOS devices, as discussed above with respect to Figures 2 - 8.

[0085] For example, annealing of TFTs in accordance with aspects of the present invention can be performed at temperatures below about 400 °C. Thus, in the illustrated examples, insulating layer 24 can be, for example, a layer of silicon dioxide formed on top of logic circuitry otherwise fabricated by FEOL fabrication processes.

[0086] Figure 13 shows a schematic representation, not to scale, of a cross section through a semiconductor die 1300, such as a memory device, a computational device with onboard SRAM or any other semiconductor device which includes SRAM memory, on which an array of SRAM cells, such as those cells discussed herein, has been formed. The die 1300 is similar to the dies 200 and 400 of Figures 3 and 5, which may be referenced for details not repeated here.

[0087] Die 1300 includes a substrate 1302 with an insulating layer formed thereon. A CMOS plane 1304 resides over the substrate 1302. The CMOS plane 1304 includes CMOS devices, such as CMOS transistors. Subsequently formed planes / layers over the CMOS plane 1304 may include, in order, ILD 1306, metalization 1308, ILD 1310, a TFT plane 1312, ILD 1314, metalization 1316, ILD 1318, a TFT plane 1320, ILD 1322. Thepattern ILD, TFT, ILD, and metalization may be repeated any suitable number of times. In the exampled depicted, two such repetitions are shown, as an example.

[0088] Various SRAM cells 1330 and 1332 are illustrated generally for sake of explanation. An SRAM cells 1330 and 1332 may include transistors in any combination of the TFT planes 1312, 1320, and the CMOS plane 1304, where transistors at the TFT planes 1312, 1320 are n-type, e.g., MBTs as discussed above, and transistors at the CMOS plane are conventional and may be p-type. Vias 1334 may be provided through ILD 1306, 1310, 1314, 1318 to electrically connect transistors at the TFT planes 1312, 1320 and the CMOS plane 1304 to metalization planes 1308 and 1316 that include conductors, so that transistor / device interconnections may be realized.

[0089] The SRAM cells 1330 and 1332 are merely generalized examples to illustrate the principles discussed herein. SRAM cell 1330 includes transistors on the CMOS plane 1304 and one of the TFT planes 1312. SRAM cell 1332 includes transistors on the CMOS plane 1304 and two of the TFT planes 1312, 1320. Another example SRAM cell (not shown) includes transistors only on one or more TFT planes 1312, 1320 and not on the CMOS plane 1304.

[0090] Figure 14 shows a method 1400 of making an SRAM cell, such those discussed herein. Reference may be made to the above description of various SRAM cells for details not repeated here.

[0091] At block 1402, a CMOS plane is formed over a substrate and CMOS devices, which may include transistors such as one or more p-type transistors of the SRAM cell, are formed at the CMOS plane. FEOL processes are to form the CMOS devices.

[0092] At block 1404, intermediate layers, such ILD and metalization, are formed over the CMOS plane. Metalization may is patterned to provide the desired electrical connections. Electrical connections between layers, such as vias, may also be formed.

[0093] At block 1406, a TFT plane is formed over the CMOS plane and the intermediate layers, and at least one n-type semiconductor TFT (e.g., an MBT) of the SRAM cell is formed at the TFT plane using BEOL and / or MOL processes. An n-type semiconductorTFT may be connected to a device at the CMOS plane, such as a p-type transistor of the SRAM cell, through the intermediate layers by a suitable configuration of one or more vias.

[0094] Blocks 1404 and 1406 may be repeated any suitable number of times to form additional n-type semiconductor TFTs of the SRAM cell and / or other SRAM cells, as well as the interconnections therebetween.

[0095] The resulting structure may undergo further processes, such as encapsulation, etc.

[0096] As is well understood by those of ordinary skill in the art given the benefit of this disclosure, an array of numerous SRAM cells may be formed simultaneously by the method 1400.

[0097] As will now be apparent, the present invention can be employed to obtain a variety of other SRAM cell designs wherein some, or all, of the n-type transistors can be MBT transistors formed on one or more planes over the plane on which the CMOS logic is formed, thus reducing the area of that CMOS logic plane occupied by the cell.

[0098] As will also now be apparent, the present invention relates to a novel SRAM cell that employs two or more n-type MBT transistors formed, on a plane of a semiconductor die over the plane of the die on which CMOS logic circuitry is formed. By using transistors formed over the CMOS logic plane of the die, the area required on that CMOS logic plane is reduced. Reducing the required area provides several advantages, including increased memory cell densities, reduced length of signal and power leads to the SRAM cells with a commensurate decrease in power losses, reduced thermal heating and reduced parasitic capacitances.

[0099] Regarding interpretation of the above description, the following notes are provided.

[0100] Auxiliary verbs “can” and “may” are used interchangeably herein to denote components, features, and / or aspects of the present invention that are capable,configurable, operable, selectable, modifiable, or optional, as would be apparent to one of ordinary skill in the art given the benefit of this disclosure. These terms should not be taken as limiting the present invention, unless otherwise specified.

[0101] Spatial prepositions, such as “over”, “under”, “above”, “below”, “up”, “down”, “beside”, etc., are provided for sake of explanation and should not be taken as limiting the present invention to an absolute spatial orientation or arrangement, unless otherwise specified. For example, one of ordinary skill in the art would understand that a first element is “above” or “below” a second element depending on the perspective of the observer.

[0102] The articles “a”, “an”, “the”, “said”, etc. indicate singular and plural, unless otherwise specified.

[0103] The conjunction “or” is used inclusively and should be understood to mean “and / or”, unless otherwise specified.

[0104] Sets of elements A, B, C described as A, B, or C; A, B, and C; A, B, and / or C; or A, B, C should be considered open sets from which one or more elements or a combination of one or more elements may be selected, unless otherwise specified. Sets of elements are open, unless specified to be closed, for example, by use of the term “consist”, “consisting”, or similar closed language.

[0105] The above clarifications apply to both the specification and claims.

[0106] The figures are not to scale, unless otherwise specified.

[0107] The above-described embodiments of the invention are intended to be examples of the present invention and alterations and modifications may be effected thereto, by those of skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.

Claims

CLAIMS1 . A static random-access memory cell comprising: a first inverter including a first pair of serially connected transistors including an n-type semiconductor thin-film transistor (TFT); a second inverter including a second pair of serially connected transistors including an n-type semiconductor TFT, wherein an input of the second inverter is connected to an output of the first inverter and an input of the first inverter is connected to an output of the second inverter; a first access transistor connected between a bit line and the output of the first inverter; and a second access transistor connected between an inverted bit line and the output of the second inverter; wherein the n-type semiconductor TFT of each inverter are formed on at least one TFT plane that is formed over a complementary metal-oxide-semiconductor (CMOS) plane of a semiconductor die.

2. The static random-access memory cell of claim 1 , wherein at least another transistor of the first and second pairs of serially connected transistors is a p-type transistor formed on the CMOS plane.

3. The static random-access memory cell of claim 1 , wherein all transistors of the first and second pairs of serially connected transistors are n-type semiconductor TFTs formed on the at least one TFT plane.

4. The static random-access memory cell of claim 1 , wherein at least two of the n-type semiconductor TFTs are formed on different TFT planes.

5. The static random-access memory cell of claim 1 , wherein at least one of the first and second access transistors is a p-type transistor formed on the CMOS plane.

6. The static random-access memory cell of claim 1 , wherein at least one of the first and second access transistors is an n-type transistor formed on the at least one TFT plane.

7. The static random-access memory cell of claim 1 , wherein the n-type semiconductor TFT comprises: an insulator formed at the at least one TFT plane that is formed over the CMOS plane; a source formed on the insulator; a drain formed on the insulator; an n-type semiconductor member; a source-channel interfacial member formed between at least the n-type semiconductor member and the source; a gate dielectric formed over the n-type semiconductor member; and a gate formed on the gate dielectric; wherein a channel is formed in the n-type semiconductor member when a threshold voltage is applied to the gate electrode, the channel conducting charge carriers through the n-type semiconductor member.

8. The static random-access memory cell of claim 7, wherein the source-channel interfacial member comprises a plasma treated portion of the source.

9. A memory device comprising an array of static random-access memory cells of claim 1.

10. A method of making a static random-access memory cell, the method comprising: forming an n-type semiconductor thin-film transistor (TFT) of the static randomaccess memory cell at a TFT plane over a complementary metal-oxide-semiconductor (CMOS) plane of a semiconductor die; andconnecting the n-type semiconductor TFT to a device at the CMOS plane.11 . The method of claim 10, wherein the component is a p-type transistor of the static random-access memory cell.

12. The method of claim 10, further comprising connecting the n-type semiconductor TFT to another n-type semiconductor TFT of the static random-access memory cell at another TFT plane.

13. The method of claim 10, wherein the component at the CMOS plane is made with a Front End of Line process, the method further comprising: forming the n-type semiconductor TFT at the TFT plane using a Back End of Line process, Middle of Line process, or combination thereof.

14. The method of claim 10, further comprising forming the n-type semiconductor TFT at the TFT plane at a temperature not exceeding about 400 °C.

15. A static random-access memory cell comprising: an arrangement of transistors forming two cross coupled inverters at a semiconductor die; wherein at least one of the transistors of the arrangement of transistors is an n- type semiconductor thin-film transistor (TFT) formed by a Back End of Line (BEOL) process, a Middle of Line (MOL) process, or a combination thereof; wherein the n-type semiconductor TFT is positioned at a plane different to a complementary metal-oxide-semiconductor (CMOS) plane of the semiconductor die.

16. The static random-access memory cell of claim 15: wherein at least another of the transistors of the arrangement of transistors is another n-type semiconductor TFT formed by the BEOL process, the MOL process, or the combination thereof;wherein the at least another n-type semiconductor TFT is positioned at another plane different to the CMOS plane of the semiconductor die.

17. The static random-access memory cell of claim 15: wherein at least another of the transistors of the arrangement of transistors is a p-type transistor formed at the CMOS plane.

18. The static random-access memory cell of claim 15 wherein: two transistors of the arrangement of transistors, which are connected to a source voltage, have gates connected to a bias voltage.

19. The static random-access memory cell of claim 15 wherein: the bias voltage is programmable to compensate for process variations in forming the static random-access memory cell.

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