Semiconductor device and method for manufacturing same

Abstract

In a first step S101, a first metal layer composed of V is formed in contact with a semiconductor layer composed of AlxGa1–xN (0.62<x). In a second step S102, a second metal layer composed of Al is formed in contact with the first metal layer. In a third step S103, a third metal layer composed of Pt is formed on the second metal layer. In a fourth step S104, a fourth metal layer composed of Au is formed on the third metal layer. In a fifth step S105, a semiconductor layer, on which there is formed a metal layered body in which the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are layered in the stated order, is heated to form an electrode that is formed in ohmic contact with the semiconductor layer.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Nitride semiconductors, such as AlN, GaN, InN, and their alloys, are characterized by their large bandgap energy and direct transition type semiconductor materials. For this reason, these nitride semiconductors have attracted attention as materials for semiconductor light-emitting devices such as light-emitting diodes (LEDs) and laser diodes (LDs), which can cover a wide range of emission wavelengths from ultraviolet to infrared.

[0003] Nitride semiconductors have also attracted attention as materials that have a large breakdown field and can contribute to ultra-low loss in power devices, and research into them is being actively pursued. x Ga 1-x N (0.62<x) is a promising material for deep ultraviolet light emitting devices with emission wavelengths of 300 nm or less and for next-generation high-voltage power devices.

[0004] To fabricate these devices, electrodes that achieve ohmic characteristics with sufficiently low contact resistance with the nitride semiconductor layer are required. x Ga 1-x Since the electron affinity of N (0.62<x) is very small, at 3 eV or less, there is no metal with a work function small enough not to form a Schottky barrier. x Ga 1-x The occurrence of a Schottky barrier between Al and N (0.62<x) is unavoidable. x Ga 1-x To achieve ohmic contact between an N (0.62<x) layer and a metal, it is necessary to devise a method for controlling the interface state between the nitride semiconductor and the electrode to make the width of the electron depletion layer sufficiently thin and generate an effective tunneling effect.

[0005] For example, n-type Al x Ga 1-xIn order to obtain ohmic characteristics with metals in N (0.62<x), techniques related to electrode configuration and heat treatment have been disclosed (Non-Patent Documents 1 and 2). In these conventional techniques, electrodes with metal laminated structures such as V / Al / V / Au or V / Al / Ni / Au are used, and heat treatment at 800°C or higher is performed to achieve ohmic characteristics with the electrodes and Al. x Ga 1-x It forms an ohmic contact with the N layer.

[0006] Ryan France et al., "Vanadium-based Ohmic contacts to n-AlGaN in the entire alloy composition", Applied Physics Letters, vol. 90, 062115, 2007.Luca Sulmoni et al., "Electrical properties and microstructureformation of V / Al-based n-contacts onhigh Al mole fraction n-AlGaN layers", Photonics Research, vol. 8, no. 8, pp. 1381-1387, 2020.

[0007] However, the electrodes fabricated by the above-mentioned techniques have the problem that they are unable to achieve ohmic contact with AlGaN, which has a high Al composition, with a sufficiently low contact resistance.

[0008] The present invention has been made to solve the above-mentioned problems, and has as its object to form an electrode that makes ohmic contact with AlGaN having a high Al composition with sufficiently low contact resistance.

[0009] The semiconductor device according to the present invention is x Ga 1-xThe semiconductor device comprises a semiconductor layer made of N (0.62<x), an electrode containing V, Al, and Au and formed in ohmic contact with the semiconductor layer, a group of first crystal grains made of V with an average grain size of 1.8 μm or less dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, a group of second crystal grains made of an alloy of V and Au dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, and Al diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, and the region occupied by the second crystal grains in which the atomic ratio of Au is greater is 72% or less of the group of second crystal grains.

[0010] The method for manufacturing a semiconductor device according to the present invention includes the steps of: x Ga 1-x A first step of forming a first metal layer made of V in contact with a semiconductor layer made of N (0.62<x), a second step of forming a second metal layer made of Al in contact with the first metal layer, a third step of forming a third metal layer made of Pt on the second metal layer, a fourth step of forming a fourth metal layer made of Au on the third metal layer, and a semiconductor layer having a metal laminate formed thereon, in which the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are laminated in this order, is heated to form a metal laminate in ohmic contact with the semiconductor layer. and a fifth step of forming an electrode formed by the V-type semiconductor layer, in which a group of first crystal grains made of V with an average grain size of 1.8 μm or less is formed and dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, a group of second crystal grains made of an alloy of V and Au is formed and dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, and Al is diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, and the region occupied by the second crystal grains in which the atomic ratio of Au is greater is 72% or less of the group of second crystal grains.

[0011] As described above, according to the present invention, by the above-described means, an electrode that is in ohmic contact with AlGaN having a high Al composition can be formed with a sufficiently low contact resistance.

[0012] FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a characteristic diagram showing the results of measuring the IV characteristics of a semiconductor device actually fabricated. FIG. 3 is a photograph showing the results of SEM-EDS measurement of an electrode of a semiconductor device according to an embodiment actually fabricated. FIG. 4 is a photograph showing HAADF-STEM images and EDS images of a cross section of an electrode of a semiconductor device according to an embodiment actually fabricated. FIG. 5 is a photograph showing the results of SEM-EDS measurement of an electrode of a semiconductor device fabricated as a comparative example. FIG. 6 is a photograph showing HAADF-STEM images and EDS images of a cross section of an electrode of a semiconductor device fabricated as a comparative example.

[0013] A method for manufacturing a semiconductor device according to an embodiment of the present invention will now be described with reference to FIG.

[0014] First, in the first step S101, Al x Ga 1-x A first metal layer made of V is formed on and in contact with a semiconductor layer made of N (0.62<x). The semiconductor layer is, for example, an n-type Al x Ga 1-x In the following, unless otherwise specified, the term "semiconductor layer" refers to a layer made of AlN (0.62<x). x Ga 1-x N (0.62<x) layers.

[0015] Next, in a second step S102, a second metal layer made of Al is formed on and in contact with the first metal layer. Next, in a third step S103, a third metal layer made of Pt is formed on the second metal layer. Next, in a fourth step S104, a fourth metal layer made of Au is formed on the third metal layer.

[0016] The above-described metal layers can be formed by, for example, electron beam vacuum deposition. In a deposition apparatus for performing electron beam vacuum deposition, the pressure in the chamber when depositing the metal layers is set to 1.0×10 to reduce the influence of impurities, etc. -4 The pressure can be set to not more than Pa. In addition to the electron beam vacuum deposition method, the above-mentioned metal layers can also be formed by resistance heating deposition or sputtering.

[0017] Next, in a fifth step S105, a semiconductor layer (e.g., an n-type semiconductor layer) having a metal laminate formed by laminating a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer in this order is heated to form an electrode in ohmic contact with the semiconductor layer. For example, the heating can be performed under the following conditions: in a nitrogen atmosphere, the temperature is increased to 720°C to 835°C at a rate of 67 to 98°C / sec, and the temperature is maintained for 14 seconds to 2 minutes and 10 seconds.

[0018] The heat treatment in the fifth step S105 first forms a group of first crystal grains composed of V with an average grain size of 1.8 μm or less dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode. Also, a group of second crystal grains composed of an alloy of V and Au (a compound containing V and Au) dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode is formed. Furthermore, Al (such as a group of crystal grains of an alloy with V or a group of crystal grains of Al alone) diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode is formed. Here, the heat treatment in the fifth step S105 is performed under conditions such that the region occupied by second crystal grains in which the atomic ratio of Au is greater occupies 72% or less of the second crystal grain group.

[0019] By the above-mentioned manufacturing method, Al x Ga 1-x A semiconductor device is obtained which comprises: a semiconductor layer made of N (0.62<x); an electrode containing V, Al, and Au and formed in ohmic contact with the semiconductor layer; a group of first crystal grains made of V with an average grain size of 1.8 μm or less dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode; a group of second crystal grains made of an alloy of V and Au dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode; and Al diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, wherein the region occupied by the second crystal grains in which the atomic ratio of Au is greater is 72% or less of the group of second crystal grains.

[0020] The method may further include a sixth step of forming a fifth metal layer made of at least one of V, Ti, and Ni on the second metal layer before forming the third metal layer. The fifth metal layer may be a single layer made of any one of V, Ti, and Ni. Alternatively, the fifth metal layer may have a stacked structure made of two metal layers made of any one of V, Ti, and Ni. Alternatively, the fifth metal layer may have a stacked structure made of a V layer, a Ti layer, and a Ni layer. In this case, the fifth step involves heating the semiconductor layer on which a metal stack formed by stacking the first metal layer, the second metal layer, the fifth metal layer, the third metal layer, and the fourth metal layer in this order is formed, to form an electrode in ohmic contact with the semiconductor layer.

[0021] This will be explained in more detail below. First, the inventors discovered that the contact resistance of electrodes fabricated by conventional techniques did not decrease to the target value. This led to extensive research by the inventors, who discovered that the reasons for the failure to reduce the contact resistance were that Au diffuses to the interface between the semiconductor layer and the electrode during heat treatment at 800°C or higher, and that V reacts with Au to form an alloy, making it difficult for V to be distributed on the surface of the semiconductor layer, leading to an increase in contact resistance. Based on this discovery, extensive research led to the present invention.

[0022] In Non-Patent Document 1, n-type Al x Ga 1-x The ohmic contact of the electrode to N is explained, and the electrode configuration is V / Al / V / Au. x Ga 1-x It has been reported that the contact resistance can be reduced by forming an electrode on the N (0.62<x) layer and then performing a heat treatment at 850° C. or higher.

[0023] However, as a result of intensive research by the inventors, it was found that when a V / Al / V / Au electrode structure is formed on a semiconductor layer and a heat treatment is performed at 850°C, Au, which has a work function of about 5 eV, diffuses to the interface between the semiconductor layer and the electrode, forming a V-Au alloy with an average crystal grain size of more than 1.8 μm, and the contact resistance increases.

[0024] In addition, in Non-Patent Document 2, n-type Al x Ga1-x For N (0.62<x), an electrode is formed by heat treatment using an electrode configuration of V / Al / Ni / Au. The inventors have studied this technology and confirmed that using a Ni layer as a diffusion prevention layer can prevent Au from diffusing into the surface of the semiconductor layer after heat treatment. However, it was confirmed that V is easily diffused toward the Au layer in the upper layer of the electrode, making it difficult for V to disperse on the surface of the semiconductor layer, and therefore a sufficiently low contact resistance cannot be obtained.

[0025] Based on the above findings, the present inventors arrived at the present invention described above, which states that in order to obtain ohmic contact with the semiconductor layer, the contact resistance can be reduced by suppressing the diffusion of Au to the interface between the semiconductor layer and the electrode and by sufficiently dispersing V in the semiconductor layer.

[0026] Next, the roles of the first, second, third, and fourth metal layers will be explained. It is believed that V, which constitutes the first metal layer, extracts nitrogen from the semiconductor layer through heat treatment, forming vanadium nitride (VN) at the interface between the electrode and the semiconductor layer. While the work function of V is 4.30 eV, the work function of VN is as low as 3.56 eV.

[0027] Here, Al x Ga 1-x Since the electron affinity of N (0.62<x) is very small, at 3 eV or less, a metal with a small work function is required as the electrode material for the contact portion in order to reduce the contact resistance. VN, which has a low work function, is suitable for this requirement. Furthermore, it is believed that nitrogen vacancies are formed on the surface of the semiconductor layer, which makes the width of the electron depletion layer sufficiently thin, resulting in an effective tunneling effect and reducing the contact resistance.

[0028] The Al constituting the second metal layer has a low work function of approximately 4 eV and a low melting point of 660° C., and by heat treatment, Al diffuses into the surface of, for example, an n-type semiconductor layer. Together with V, Al plays a role in lowering the Schottky barrier at the metal / semiconductor interface.

[0029] The fourth metal layer, which is the final layer, is made of Au as an oxidation prevention layer, but a third metal layer made of Pt is inserted between the second metal layer made of Al and the fourth metal layer made of Au as a diffusion prevention layer. Inserting the third metal layer made of Pt can prevent Au from diffusing from the fourth metal layer to the surface of the semiconductor layer during heat treatment.

[0030] Next, the thickness of each electrode will be described.

[0031] First, the first metal layer can be formed to a thickness of, for example, 6 to 32 nm. More preferably, the thickness of the first metal layer can be 9 to 21 nm. Even more preferably, the thickness of the first metal layer can be 12 to 19 nm. If the thickness of the first metal layer is less than 6 nm, it may be difficult to form a VN with a low work function after heat treatment. Furthermore, if the thickness of the first metal layer exceeds 32 nm, it may react with the upper Au layer after heat treatment, resulting in an increase in contact resistance.

[0032] The second metal layer can be formed to a thickness of, for example, 28 to 110 nm. More preferably, the thickness of the second metal layer can be 39 to 102 nm. Even more preferably, the thickness of the second metal layer can be 41 to 90 nm. If the thickness of the second metal layer is less than 28 nm, Al may not diffuse sufficiently into the surface of the semiconductor layer after heat treatment, potentially reducing the contribution of Al to lowering the Schottky barrier. If the thickness of the second metal layer exceeds 110 nm, it may react with Au in the upper layer after heat treatment, increasing contact resistance.

[0033] The third metal layer may have a thickness of, for example, 12 nm to 83 nm. More preferably, the third metal layer may have a thickness of 14 nm to 52 nm. Even more preferably, the third metal layer may have a thickness of 18 nm to 45 nm. If the thickness of the third metal layer is less than 12 nm, its function as a diffusion prevention layer may be reduced, and the Au of the fourth metal layer thereon may diffuse onto the semiconductor layer. If the thickness of the third metal layer exceeds 83 nm, Pt may diffuse to the surface of the semiconductor layer after heat treatment, increasing contact resistance.

[0034] The fourth metal layer may have a thickness of, for example, 26 nm to 118 nm. More preferably, the third metal layer may have a thickness of 35 nm to 107 nm. Even more preferably, the third metal layer may have a thickness of 41 nm to 83 nm. If the thickness of the fourth metal layer is less than 26 nm, the anti-oxidation function may be reduced, and the electrode may become more susceptible to oxidation. If the thickness of the fourth metal layer is more than 118 nm, Au may diffuse after heat treatment and react with V or Al to form a V-Au alloy or an Al-Au alloy, which may inhibit the diffusion of V or Al onto the semiconductor layer and increase contact resistance.

[0035] In the above-described embodiment, by suppressing the diffusion of Au into the surface of the semiconductor layer, the region occupied by second crystal grains in which the atomic ratio of Au is greater among the second crystal grains made of an alloy of V and Au (a compound containing V and Au) on the surface of the fourth metal layer is 72% or less of the group of second crystal grains. The proportion of the region occupied by second crystal grains in which the atomic ratio of Au is greater than V on the surface of the semiconductor layer can be more preferably 63% or less, and even more preferably 54% or less. By reducing the proportion of the region occupied by second crystal grains in which the atomic ratio of Au is greater than V in the group of second crystal grains, ohmic contact of the electrode with the semiconductor layer can be achieved, thereby reducing contact resistance.

[0036] Next, a heat treatment will be described. After forming a metal stack on a semiconductor layer, the temperature is raised to 720°C to 835°C at a heating rate of 67 to 98°C / sec in a nitrogen atmosphere and maintained at that temperature for 14 seconds to 2 minutes and 10 seconds, thereby dispersing V having an average crystal grain size of 1.8 μm or less on the surface of the semiconductor layer, and the proportion of the area occupied by second crystal grains in which the atomic ratio in the group of second crystal grains is Au>V can be set to 72% or less on the surface of the semiconductor layer.

[0037] Under the above-described heat treatment conditions, a more preferable heating rate is 71 to 98°C / sec, and even more preferably 76 to 98°C / sec. If the heating rate is less than 67°C / sec, V and Au may react at the interface between the semiconductor layer and the electrode to form a V-Au alloy with an average crystal grain size exceeding 1.8 μm, which may result in an increase in contact resistance. Furthermore, on the surface of the semiconductor layer, the proportion of the region occupied by second crystal grains in which the atomic ratio within the group of second crystal grains is Au > V may exceed 72%. On the other hand, if the heating rate exceeds 98°C / sec, the reaction between the semiconductor layer and the metal constituting the metal laminate may be insufficient, which may inhibit the production of a metal with a low work function, such as VN.

[0038] The heat treatment temperature and heat treatment time are preferably 740°C to 820°C, 17 seconds to 1 minute 40 seconds, and even more preferably 760°C to 810°C, 23 seconds to 1 minute 15 seconds. If the heat treatment temperature is less than 720°C and the holding time is less than 14 seconds, the reaction between the semiconductor layer and the metal constituting the metal laminate will be insufficient, which may inhibit the production of metals with low work functions such as VN. Furthermore, if the heat treatment temperature is higher than 835°C and the holding time is longer than 2 minutes 10 seconds, V and Au will react at the interface between the semiconductor layer and the metal laminate to produce a V-Au alloy with an average crystal grain size of more than 1.8 μm. Furthermore, the proportion of the region occupied by second crystal grains in which the atomic ratio of Au > V in the group of second crystal grains on the surface of the semiconductor layer exceeds 72%, which may lead to an increase in contact resistance.

[0039] The following describes the observation results of semiconductor devices that were actually fabricated. First, the average crystal grain size of each metal in the electrode obtained by heat treatment was determined by observing from above using a scanning ion microscope (SIM) or a scanning electron microscope (SEM). The area of ​​each crystal grain observed within a 25 μm square frame was measured, and the average diameter when the shape of the crystal grain was converted into a circle was calculated. In addition, an energy dispersive X-ray analyzer (EDS) was connected to the SEM and X-ray analysis was performed to determine the element distribution in the electrode.

[0040] The cross-sectional structure of the semiconductor layer and the electrode is clearly confirmed in a high-angle electron scattering (HAADF) image. An HAADF image is a mapping image of the integrated intensity of electrons inelastically scattered at high angles, obtained by a scanning transmission electron microscope (STEM). In an HAADF image, the image intensity is proportional to the square of the atomic number, and the areas where atoms with higher atomic numbers are present appear brighter (whiter). The elemental distribution is also identified by elemental analysis using EDS. EDS is measured using an EDS measurement device attached to the STEM device.

[0041] The distribution of V and Au diffused into the surface of the semiconductor layer can be investigated by using TEM-EDS. When a 3 μm square cross section including V crystal grains is examined using TEM-EDS, the proportion of compounds containing V and Au in which Au has a larger atomic ratio within the field of view is defined as the proportion of the region occupied by second crystal grains in which Au has a larger atomic ratio (the proportion of the region occupied by the atomic ratio Au>V).

[0042] The performance of an ohmic electrode can be expressed by the specific contact resistance ρc. The TLM (Transmission Line Model) method is widely used to measure the specific contact resistance. There are patterns with linear electrodes and patterns with circular electrodes, but in both cases, electrode patterns with different inter-electrode distances are formed, and the resistance between the electrodes is measured to calculate the specific contact resistance.

[0043] The semiconductor layer can be formed by epitaxial growth. For example, metal organic vapor phase epitaxy (MOVPE) is preferably used as the epitaxial growth method. The epitaxial growth method is not limited to MOVPE, and can also be, for example, hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), sputtering, or the like.

[0044] Crystal growth of a semiconductor layer is performed by preparing a growth substrate, then loading the growth substrate into an epitaxial growth apparatus and performing epitaxial growth. When an MOVPE apparatus is used as the epitaxial growth apparatus, trimethylaluminum (TMAl) can be used as the source gas for Al. Trimethylgallium (TMGa) can be used as the source gas for Ga. NH can be used as the source gas for N. Silane (SiH) can be used as the source gas for Si, which is an impurity that contributes to n-type conductivity. Examples of carrier gases that can be used include H gas, N gas, and a mixture of H gas and N gas.

[0045] Furthermore, each source gas is not particularly limited, and for example, triethylgallium (TEGa) can be used as a source gas for Ga, and a hydrazine derivative can be used as a source gas for N. The n-type impurity means a donor impurity, and can be, for example, Si or Ge.

[0046] In the following, a buffer layer made of AlN is crystal-grown on the surface of SiC whose main surface is the (0001) plane, and n-type AlN is grown on the buffer layer. x Ga 1-x The following describes an example in which a semiconductor layer made of N (0.62<x) is grown as a crystal and an electrode is formed on the crystal. Note that these configurations are merely examples, and similar effects can be obtained with semiconductor layers grown on other crystal planes such as (000-1) and (1-102).

[0047] Furthermore, the substrate is not limited to a SiC substrate, and other substrates such as an AlN substrate, a sapphire substrate, a GaN substrate, an MgAlO substrate, a SiO substrate, an MgO substrate, a ZnO substrate, an NdGaO, a ScAlMgO, a ZnS substrate, a GaAs substrate, or a Si substrate can be used.

[0048] Example 1 An AlN buffer layer was grown to a thickness of 1.3 μm on a semi-insulating 4H—SiC (0001) substrate by MOVPE, and Si-doped Al 0.7 Ga 0.3N was grown to a thickness of 250 nm to form a semiconductor layer. SIMS revealed that the doping amount of Si in the semiconductor layer was 1.5×10 19 cm -3 The SIMS used was ADEPT1010 (manufactured by ULVAC PHI).

[0049] For the purpose of limiting the current path for measuring the specific contact resistance, a mesa structure was formed on the surface of the semiconductor layer, and rectangular electrode patterns measuring 100 μm × 190 μm in plan view were linearly formed on this mesa structure at intervals of 4, 8, 12, 18, and 24 μm. The mesa structure was formed by dry etching the semiconductor layer using a mask pattern prepared by photolithography, for example.

[0050] Each electrode pattern was formed using a well-known lift-off method. First, a lift-off mask with openings corresponding to the electrode patterns was formed on the mesa structure. Next, a metal stack was formed by depositing a first metal layer of 15 nm thick V, a second metal layer of 80 nm thick Al, a third metal layer of 30 nm thick Pt, and a fourth metal layer of 50 nm thick Au using electron beam vacuum deposition. The lift-off mask was then removed, leaving the electrode patterns formed by the metal stack linearly spaced at intervals of 4, 8, 12, 18, and 24 μm. A heat treatment was then performed in a nitrogen atmosphere, raising the temperature from room temperature to 800°C at a rate of 91°C / sec and maintaining the temperature for 30 seconds.

[0051] Based on the above, IV characteristics were measured using a TLM pattern with linearly formed electrode patterns spaced at intervals of 4, 8, 12, 18, and 24 μm. The results of the IV characteristics measurement are shown in Figure 2. As shown in Figure 2, ohmic contact was obtained. The specific contact resistance was calculated by the TLM method, and the specific contact resistance ρc was 9.7 × 10 -5 Ω cm 2 It was.

[0052] Figure 3 shows the results of SEM-EDS measurements of an electrode obtained after heat treatment at 800°C of a metal stack consisting of a 15 nm thick first metal layer, an 80 nm thick second metal layer, a 30 nm thick third metal layer, and a 50 nm thick fourth metal layer. The SEM used was a Carl Zeiss ULTRA 55. The EDS connected to the SEM was a Bruker Quantax. As shown in Figure 2, the diffusion of Au is suppressed in the region where Pt is present, indicating the presence of V in that region. Furthermore, the average grain size of V crystal grains observed within a 25 μm square frame was examined, and the average grain size of V was found to be 1.2 μm.

[0053] Next, Figure 4 shows HAADF-STEM and EDS images of the cross section of an electrode obtained after heat treatment at 800°C of a metal laminate consisting of a 15 nm thick first metal layer, an 80 nm thick second metal layer, a 30 nm thick third metal layer, and a 50 nm thick fourth metal layer. For this observation, a JEM-2100F manufactured by JEOL Ltd. was used. Comparison of the images showing the Pt distribution, the Au distribution, and the V distribution reveals that in the Pt distribution region, Au diffusion is suppressed and V is present at the bottom of the electrode. Taking the SEM-EDS results into account, V with an average crystal grain size of 1.2 μm is distributed on the surface of the semiconductor layer, and Au diffusion is suppressed in this region. Furthermore, the image showing the Al distribution reveals that Al, which has a small work function, is diffused onto the surface of the semiconductor layer. It is believed that this diffusion of Al into the surface of the semiconductor layer contributes to the lowering of the Schottky barrier.

[0054] Furthermore, a 3 μm square cross section including V crystal grains was examined by TEM-EDS, and the proportion of compounds (second crystal grains) with an atomic ratio of Au>V among the distribution of compounds (second crystal grains) containing V and Au (group of second crystal grains) in the surface portion of the semiconductor layer within the field of view was examined, and it was found to be 46%.

[0055] [Examples 2 to 8] In Examples 2, 3, 4, 5, 6, 7, and 8, TLM patterns were fabricated by changing the Al composition in the semiconductor layer and the electrode configuration as shown in Tables 1, 2, and 3. In Examples 2 and 7, a 30-nm-thick fifth metal layer made of V was inserted between the second and third metal layers. In Examples 3 and 8, a 30-nm-thick fifth metal layer made of Ti was inserted between the second and third metal layers. In Example 5, a 30-nm-thick fifth metal layer made of Ni was inserted between the second and third metal layers. The TLM patterns were heat-treated in a nitrogen atmosphere under the conditions (temperature rise measurement, heat treatment temperature, and holding time) shown in Tables 1, 2, and 3 below. Similar to Example 1, excellent ohmic characteristics were obtained. Tables 1, 2, and 3 show the results of determining the specific contact resistance ρc using the TLM method. In the table below, the "percentage of atomic ratio Au / V" indicates the "percentage of compounds (second crystal grains) with an atomic ratio of Au > V among the distribution (group of second crystal grains) of compounds (second crystal grains) containing V and Au."

[0056]

[0057]

[0058]

[0059] Furthermore, from SEM-EDS measurement and cross-sectional TEM measurement (HAADF-STEM, EDS), it was found that the diffusion of Au was suppressed in the region where Pt was distributed, and that V crystal grains with an average crystal grain size of 1.8 μm or less were present on the surface of the semiconductor layer, as in Example 1. Furthermore, a 3 μm square cross section including the V crystal grains was examined by TEM measurement, and the proportion of compounds (second crystal grains) in which the atomic ratio was Au>V was examined among the distribution of compounds containing V and Au (second crystal grains) in the surface portion of the semiconductor layer within the field of view, and all were found to be 72% or less.

[0060] Next, comparative examples will be described using Comparative Example 1, Comparative Example 2, and Comparative Example 3. In Comparative Example 1, Comparative Example 2, and Comparative Example 3, TLM patterns were fabricated by changing the Al composition of the semiconductor layer and the electrode configuration as shown in Table 4 below. The TLM patterns were heat-treated in a nitrogen atmosphere under the conditions in Table 4 (temperature rise measurement, heat treatment temperature, and holding time). Measurement of the I-V characteristics of the TLM patterns after heat treatment confirmed that in Comparative Example 1, Comparative Example 2, and Comparative Example 3, no ohmic contact was obtained, but a Schottky junction was obtained.

[0061]

[0062] The results of SEM-EDS measurement of the electrode after heat treatment in Comparative Example 1 are shown in Figure 5. Unlike the results of the Example in which Pt was used as the diffusion prevention layer, it was found that Au was present in the region where V was distributed. The average crystal grain size of V observed within a 25 μm square frame was examined, and the average crystal grain size was found to be 1.9 μm.

[0063] FIG. 6 shows the results of HAADF-STEM and EDS images of the electrode after heat treatment in Comparative Example 1. It can be seen from FIG. 6 that Au diffused through the V and was distributed on the surface of the semiconductor layer. It is believed that the ohmic characteristics were degraded because Au, which has a high work function of approximately 5 eV, was in contact with the surface of the semiconductor layer. Furthermore, a 3 μm square cross section including V crystal grains was examined using TEM-EDS, and the proportion of compounds (second crystal grains) with an atomic ratio of Au > V was examined within the distribution of compounds containing V and Au (second crystal grains) in the surface portion of the semiconductor layer within the field of view. The proportion was found to be 96%.

[0064] Similarly to Comparative Example 1, SEM-EDS and cross-sectional TEM (HAADF-STEM, EDS) measurements were also performed on Comparative Example 2 and Comparative Example 3. In Comparative Example 2, similar to Comparative Example 1, Au was diffused on the semiconductor layer surface, and the average crystal grain size of V was 2.1 μm. In Comparative Example 3, the average crystal grain size of V was 1.8 μm or less, but V diffused toward the Au side of the upper layer, making it difficult for V to be distributed on the semiconductor layer surface. Furthermore, similar to Comparative Example 1, the proportion of compounds (second crystal grains) in which the atomic ratio was Au > V was investigated within the distribution of compounds (second crystal grains) containing V and Au in the surface portion of the semiconductor layer. The results are shown in Table 4.

[0065] As described above, according to the present invention, a group of first crystal grains made of V and having an average grain size of 1.8 μm or less is dispersed on the surface of a semiconductor layer at the interface between the semiconductor layer and an electrode, the group of second crystal grains made of an alloy of V and Au dispersed on the surface of the semiconductor layer occupies 72% or less of the region of the group of second crystal grains in which Au has a larger atomic ratio, and furthermore, Al is diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, so that an electrode can be formed that makes ohmic contact with AlGaN having a high Al composition with sufficiently low contact resistance.

[0066] Al with a high Al composition x Ga 1-x When forming an electrode for ohmic contact with a semiconductor layer made of N, there is a risk that Au constituting the electrode will diffuse to the interface between the semiconductor layer and the electrode after heat treatment at 800°C or higher, and V constituting the electrode will react with Au to form an alloy, which may lead to an increase in contact resistance because V, which has a small work function, is difficult to distribute on the surface of the semiconductor layer. According to the present invention, the above-mentioned problems can be suppressed and the contact resistance can be reduced. The present invention is capable of suppressing the above-mentioned problems and reducing the contact resistance. x Ga 1-x The present invention can be suitably applied to deep ultraviolet light emitting devices and high voltage power devices using N (0.62<x).

[0067] It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by a person skilled in the art within the technical concept of the present invention. For example, Al x Ga 1-x The semiconductor layer made of N (0.62<x) can be p-type.

Claims

1. Al x Ga 1-x A semiconductor layer composed of N(0.62 < x), an electrode formed by ohmic contact with the semiconductor layer and composed of V, Al, and Au, a group of first crystal grains composed of V having an average particle size of 1.8 μm or less dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, a group of second crystal grains composed of an alloy of V and Au dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, and Al diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode, wherein, among the second crystal grains, the region occupied by the second crystal grains in which the atomic ratio of Au is larger is 72% or less among the group of second crystal grains.

2. The semiconductor device according to claim 1, wherein the electrode further contains Pt.

3. The semiconductor device according to claim 2, wherein the electrode further contains at least one of Ti and Ni.

4. Al x Ga 1-x A first step of forming a first metal layer made of V in contact with a semiconductor layer composed of AlGaN (0.62 < x); a second step of forming a second metal layer made of Al in contact with the first metal layer; a third step of forming a third metal layer made of Pt on the second metal layer; a fourth step of forming a fourth metal layer made of Au on the third metal layer; and a fifth step of heating the semiconductor layer on which a metal laminate in which the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are laminated in this order is formed, to form an electrode formed in ohmic contact with the semiconductor layer. In the fifth step, a group of first crystal grains made of V having an average particle size of 1.8 μm or less dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode; a group of second crystal grains made of an alloy of V and Au dispersed on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode; and Al diffused on the surface of the semiconductor layer at the interface between the semiconductor layer and the electrode are formed. A method of manufacturing a semiconductor device, wherein in the second crystal grains, a region occupied by the second crystal grains in which the atomic ratio of Au is larger is 72% or less in the group of the second crystal grains.

5. In the method for manufacturing a semiconductor device according to claim 4, a sixth step of forming a fifth metal layer made of at least one of V, Ti, and Ni on the second metal layer before forming the third metal layer is provided, and the fifth step is heating the semiconductor layer in which a metal laminate in which the first metal layer, the second metal layer, the fifth metal layer, the third metal layer, and the fourth metal layer are laminated in this order is formed, to form the electrode formed by ohmic contact with the semiconductor layer. A method for manufacturing a semiconductor device.

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