Photodetection element

Abstract

The present technology relates to a photodetection element capable of suppressing an increase in power consumption and reducing the dead time of a counter. This photodetection element comprises: a photodiode that performs avalanche amplification in response to incidence of a photon, and that outputs a signal; and an output destination-switching unit that switches an output destination of the signal so that the signal output from the photodiode is sequentially output to each of a plurality of counters. The present technology can be applied to a photodetection element.

Description

Photodetector element

[0001] The present technology relates to a photodetector element, and more particularly to a photodetector element that can shorten the dead time of a counter while suppressing an increase in power consumption.

[0002] 2. Description of the Related Art Conventionally, a technique for measuring distance using a single photon avalanche diode (SPAD) is known as a technique related to Direct-ToF (Time of Flight).

[0003] This technology makes it possible to detect single photon signals incident on a pixel by avalanche amplifying the signal inside the pixel, which has a SPAD. The signal obtained by avalanche amplification in the pixel is converted into distance information via a TDC (Time to Digital Counter), which is a counter. The general configuration is one TDC connected to one SPAD (pixel).

[0004] Furthermore, as a technology relating to SPADs, a technology has been proposed in which one TDC is provided for a plurality of SPADs to improve counting accuracy (see, for example, Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2022-69202

[0006] In a configuration in which one TDC is connected to one SPAD, the TDC switching period, i.e., the TDC dead time, can sometimes be longer than the time during which the SPAD cannot respond, i.e., the recharge period called the SPAD dead time.

[0007] In such a case, if a new signal corresponding to the incident photon is output from a pixel while the signal is being passed from the TDC to the downstream histogram builder, the new signal will not be counted by the TDC and will not be used to generate a histogram in the histogram builder. This will result in an inaccurate count value, i.e., a lower count rate, which will result in a decrease in ranging accuracy and a lower signal-to-noise ratio (SNR).

[0008] One possible solution is to shorten the TDC dead time by increasing the drive frequency of the TDC, but this would increase the leakage current depending on the drive frequency, resulting in increased power consumption.

[0009] The present technology has been made in view of such circumstances, and makes it possible to shorten the dead time of a counter while suppressing an increase in power consumption.

[0010] A photodetector element according to one aspect of the present technology includes a photodiode that performs avalanche amplification in response to incident photons and outputs a signal, and an output destination switching unit that switches the output destination of the signal so that the signal output from the photodiode is output in sequence to each of a plurality of counters.

[0011] In one aspect of the present technology, avalanche amplification is performed in a photodiode in response to the incidence of a photon, and a signal is output, and the output destination of the signal is switched so that the signal output from the photodiode is output in sequence to each of a plurality of counters.

[0012] FIG. 1 is a diagram illustrating an example of the configuration of a photodetector. FIG. 2 is a diagram illustrating an example of the configuration of a photodetector. FIG. 3 is a diagram illustrating an example of the configuration of a photodetector. FIG. 4 is a diagram illustrating an example of the configuration of a photodetector. FIG. 5 is a diagram illustrating an example of the configuration of a TDC. FIG. 6 is a diagram illustrating an example of the configuration of a photodetector. FIG. 7 is a diagram illustrating an example of the arrangement of a pixel array unit and a discrimination pixel array unit. FIG. 8 is a diagram illustrating an example of the configuration of a photodetector. FIG. 9 is a diagram illustrating an example of the configuration of a photodetector. FIG. 10 is a diagram illustrating an example of the operation timing of a photodetector. FIG. 11 is a diagram illustrating an example of the configuration of an imaging device. FIG. 12 is a block diagram illustrating an example of the schematic configuration of a vehicle control system. FIG. 13 is an explanatory diagram illustrating an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0013] Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.

[0014] First Embodiment Example of Configuration of Photodetector Element The present technology is to connect two or more TDCs (counters) to one pixel that performs avalanche amplification in response to incident photons, thereby making it possible to reduce the dead time of the TDCs while suppressing an increase in power consumption.

[0015] In this technology, an output destination switching unit consisting of a flip-flop circuit or the like is provided between a pixel having a photodiode such as a SPAD and multiple TDCs connected to the pixel. This output destination switching unit sequentially distributes signals obtained from the pixel to the multiple TDCs. This reduces leakage current caused by the TDC drive frequency, thereby suppressing increases in power consumption, while shortening the TDC dead time (hereinafter also referred to as DT).

[0016] This technology can be applied to, for example, a photodetector element that performs distance measurement using Direct-ToF, and a distance measurement system that has such a photodetector element.

[0017] FIG. 1 is a diagram showing an example of the configuration of an embodiment of a photodetector element to which the present technology is applied.

[0018] The photodetector element 11 shown in Fig. 1 is, for example, an imaging element itself such as an image sensor for distance measurement, a semiconductor chip having such an imaging element, etc. For ease of explanation, Fig. 1 shows the configuration corresponding to one pixel of the photodetector element 11.

[0019] The photodetector element 11 includes a photodiode 21, an inverter 22, a flip-flop circuit section 23, and TDCs (Time to Digital Counters) 24-1 and 24-2.

[0020] The photodiode 21 corresponds to one pixel, performs avalanche amplification (avalanche multiplication) in response to the incidence of photons, and outputs a signal in response to the incidence of photons.

[0021] For example, the photodiode 21 is a single photon avalanche diode (SPAD) that detects a single photon. Note that the photodiode 21 may be any type, such as an avalanche photodiode (APD) that detects multiple photons, as long as it outputs a signal corresponding to an incident photon by avalanche multiplication or the like.

[0022] The photodiode 21 is connected to a predetermined power supply and an input terminal of an inverter 22. As an example, the power supply and the input terminal of the inverter 22 are connected to the cathode of the photodiode 21.

[0023] For example, when the photodiode 21 is connected to a power supply, the photodiode 21 enters a recharge state. In the recharge state, the potential of the photodiode 21 becomes a potential corresponding to the power supply, and the photodiode 21 is charged (recharged).

[0024] Furthermore, for example, when the photodiode 21 is disconnected from the power supply, the recharging is completed and the photodiode 21 enters a standby state. In the standby state, it is possible to detect the incidence of photons on the photodiode 21.

[0025] When a photon is input to the photodiode 21 while the photodiode 21 is in a standby state, avalanche amplification occurs in the photodiode 21, changing the potential on the output side of the photodiode 21. In other words, when a photon is input to the photodiode 21, the photodiode 21 outputs a signal corresponding to the input of the photon.

[0026] The inverter 22 inverts the signal supplied from the photodiode 21 and supplies the inverted signal to the flip-flop circuit unit 23. Hereinafter, the signal supplied from the inverter 22 to the flip-flop circuit unit 23, more specifically, the signal output from the inverter 22 and latched by the flip-flop circuit unit 23, will also be referred to as a latch signal.

[0027] The flip-flop circuit unit 23 functions as an output destination switching unit that alternately distributes and supplies the latch signal supplied from the inverter 22 to the TDC 24-1 and TDC 24-2 connected downstream. In other words, the flip-flop circuit unit 23 switches the output destination of the latch signal so that the latch signal is alternately supplied to the TDC 24-1 and TDC 24-2.

[0028] The flip-flop circuit section 23 includes a flip-flop circuit 31 and an inverter 32 .

[0029] The flip-flop circuit 31 is made up of a D-flip-flop circuit, and the signal (latch signal) output from the inverter 22 is input to the clock input terminal of the flip-flop circuit 31 .

[0030] The output terminal (Q terminal) of the flip-flop circuit 31 is connected to the input terminal of the inverter 32 and the TDC 24-1, and the inverting output terminal of the flip-flop circuit 31 is connected to the TDC 24-2. The inverting output terminal of the flip-flop circuit 31 is a terminal that inverts the output from the output terminal of the flip-flop circuit 31 and outputs the inverted output.

[0031] Furthermore, the input terminal (D terminal) of the flip-flop circuit 31 is connected to the output terminal of the inverter 32 .

[0032] For example, when the inverter 22 supplies the flip-flop circuit 31 with an H-level signal as a latch signal, the flip-flop circuit 31 supplies the latch signal, more specifically, an H-level signal corresponding to the latch signal, to the TDC 24-1.

[0033] Then, when an H-level signal is next supplied as a latch signal from the inverter 22, the flip-flop circuit 31 supplies that latch signal, or more specifically, an H-level signal corresponding to the latch signal, from its inverting output terminal to the TDC 24-2. This is because the signal previously output to the TDC 24-1 is inverted by the inverter 32 and supplied to the input terminal of the flip-flop circuit 31.

[0034] Furthermore, when the inverter 22 supplies the flip-flop circuit 31 with an H-level signal as a latch signal, the flip-flop circuit 31 supplies the TDC 24-1 with an H-level signal corresponding to the latch signal.

[0035] Therefore, in the photodetector element 11, every time a photon is incident on the photodiode 21, i.e., every time the incident photon is detected by the photodiode 21, a signal corresponding to the incident photon is supplied alternately from the flip-flop circuit 31 (flip-flop circuit section 23) to the TDC 24-1 and the TDC 24-2.

[0036] Hereinafter, the signals supplied from the flip-flop circuit 31 to the TDC 24-1 and TDC 24-2 will also be referred to as output signals.

[0037] The TDCs 24-1 and 24-2 are counter circuits (counters) that perform counting operations according to the output signal supplied from the flip-flop circuit 31 for a predetermined period of time, and output data indicating the count results as count data to the subsequent stage.

[0038] Hereinafter, when there is no need to particularly distinguish between the TDC 24-1 and the TDC 24-2, they will also be simply referred to as the TDC 24.

[0039] As described above, the photodetector element 11 has a circuit structure in which the photodiode 21 and the TDC 24 are connected via the flip-flop circuit section 23 and one photodiode 21 is shared by two TDCs 24 .

[0040] This doubles the period during which the TDC 24 can count photons detected by the photodiode 21 without missing any, i.e., the slew rate, compared to when only one TDC 24 is connected to one photodiode 21. In other words, when the two TDCs 24 for the entire photodetector element 11 are viewed as one counter, the dead time of the counter (TDC 24) can be halved.

[0041] Moreover, since the dead time can be shortened without increasing the drive frequency of the TDC 24, it is possible to suppress the occurrence of leakage current and the increase in power consumption compared to when only one TDC 24 is connected to the photodiode 21.

[0042] In addition, it becomes possible to continuously receive and transfer the signal output from the photodiode 21 in response to the incidence (detection) of photons, and when the dead time of the TDC 24 is set to be accordingly shorter, it is possible to expect an improvement in the count rate under high background light conditions.

[0043] The photodetector element 11 can be configured as a semiconductor chip having multiple pixels. In this case, two TDCs 24 can be connected to one pixel (photodiode 21), but two TDCs 24 can also be connected to a unit of multiple pixels.

[0044] For example, when each pixel is connected to two TDCs 24 in units of a pixel row consisting of a plurality of pixels arranged in the row direction, the photodetector element 11 can be configured as shown in Figure 2. Note that in Figure 2, parts corresponding to those in Figure 1 are assigned the same reference numerals, and their explanation will be omitted as appropriate. Also, in Figure 2, some reference numerals have been omitted to make the figure easier to understand.

[0045] The photodetector element 11 shown in FIG. 2 is configured as a semiconductor chip made up of one or more semiconductor substrates, and the semiconductor substrate that configures the photodetector element 11 is provided with an upper substrate region 61 and a lower substrate region 62 .

[0046] In more detail, the upper substrate region 61 and the lower substrate region 62 are arranged side by side in a direction perpendicular to the surface of the semiconductor substrate, but here, for ease of viewing, the upper substrate region 61 and the lower substrate region 62 are shown arranged side by side. For example, the upper substrate region 61 and the lower substrate region 62 may be arranged on the upper and lower surfaces of the same semiconductor substrate, or the upper substrate region 61 and the lower substrate region 62 may be arranged on different semiconductor substrates, and these semiconductor substrates may be bonded together.

[0047] A pixel array section 71 having a plurality of pixels arranged in a matrix is ​​provided in the upper substrate region 61. Hereinafter, in the drawing, a plurality of pixels arranged in the horizontal direction, i.e., the row direction, will also be referred to as a pixel row, and a plurality of pixels arranged in the vertical direction, i.e., the column direction, will also be referred to as a pixel column.

[0048] 2, a plurality of pixels including pixels 81-1, 81-2, and 81-3 are arranged in a matrix in the pixel array section 71. Hereinafter, when there is no need to particularly distinguish between the pixels provided in the pixel array section 71, such as pixel 81-1 and pixel 81-2, they will also be simply referred to as pixel 81.

[0049] Each pixel 81 has one photodiode 21, and when a photon is incident on the pixel 81 (photodiode 21), avalanche amplification occurs, and a signal indicating the photon detection result is output from the pixel 81. Also, an inverter 22 connected to the photodiode 21 in the pixel 81 is provided inside or outside the pixel 81 in the pixel array unit 71, but is not shown here.

[0050] The lower substrate area 62 is provided with a switching unit 91, a counting unit 92, and a generating unit 93.

[0051] The switching section 91 is provided with a flip-flop circuit section 23 for each pixel row made up of pixels 81 arranged in the row direction.

[0052] For example, each of the plurality of pixels 81 constituting a pixel row made up of pixel 81-1 and pixel 81-2 is connected to the same signal line, and the signal line is connected to one flip-flop circuit unit 23. More specifically, an inverter 22 is connected between the signal line and the flip-flop circuit unit 23 or between the signal line and the photodiode 21.

[0053] The counting unit 92 is provided with a TDC 24-1 and a TDC 24-2 for each pixel row. That is, the TDC 24-1 and the TDC 24-2 are connected to one flip-flop circuit unit 23 connected to one pixel row.

[0054] The generation unit 93 is provided with a histogram builder 101 for each pixel row. That is, one histogram builder 101 is connected to the TDC 24-1 and TDC 24-2 provided for one pixel row.

[0055] The histogram builder 101 generates a histogram showing the number of incident photons at each time (period) in a predetermined period such as one frame, i.e., the photon detection results, based on the count data supplied from the TDC 24, and outputs the histogram to a subsequent stage. In other words, the period for which the histogram is generated is one frame period. During one frame period, the photodiode 21 is recharged and the incident photons are detected multiple times.

[0056] By using the histogram obtained by the histogram builder 101, distance information indicating the distance from the light detection element 11 to the object to be measured (measured) can be obtained.

[0057] 2, it is possible to set whether or not to drive each of the plurality of pixels 81 constituting a pixel row for each pixel 81. In other words, it is possible to dynamically set the drive settings of the pixels 81 so that any number of the plurality of pixels 81 constituting a pixel row are driven.

[0058] Of the pixels 81, the pixels 81 that are driven are also particularly referred to as driven pixels, and the pixels 81 that are not driven are also referred to as non-driven pixels.

[0059] When a photon is incident on the photodiode 21 in a pixel 81 that is set as a driven pixel, a signal corresponding to the incident photon is output from the pixel 81. In contrast, even if a photon is incident on a pixel 81 that is set as a non-driven pixel, the pixel 81 does not output a signal corresponding to the incident photon.

[0060] For example, suppose that a setting is made so that only one pixel 81 constituting a pixel row is driven. In other words, among the pixels 81 constituting a pixel row, only one pixel 81 is set as a driven pixel, and the remaining pixels 81 are set as non-driven pixels.

[0061] In such a case, when a photon is incident on one pixel 81 designated as a driven pixel, a signal corresponding to the incident photon is output from the pixel 81 and is supplied via a signal line or the like to the flip-flop circuit unit 23. An output signal is then supplied from the flip-flop circuit unit 23 to the TDC 24, and the TDC 24 reflects the incident photon on the driven pixel, i.e., the detection of the photon at the driven pixel, in a count value (count data).

[0062] In contrast, even if a photon is incident on a non-driven pixel, no signal is output from pixel 81, which is a non-driven pixel, and therefore the incidence of a photon on a non-driven pixel is not reflected in the count data held in TDC 24.

[0063] Therefore, the histogram indicating the photon detection results at one pixel 81 designated as a driven pixel is obtained in the histogram builder 101 at the subsequent stage of the TDC 24 .

[0064] Also, for example, it is assumed that a setting is made so that a predetermined number of pixels 81, two or more, of the plurality of pixels 81 that make up a pixel row are driven.

[0065] In such a case, when a photon is incident on any of the pixels 81 designated as the driving pixel, a signal corresponding to the incident photon is output from the pixel 81 and supplied to the flip-flop circuit section 23 via a signal line or the like.

[0066] Therefore, in the TDC 24, the detection of photons in each of the plurality of pixels 81 designated as driven pixels is reflected in the count value (count data). As a result, the histogram builder 101 obtains a histogram indicating the detection results of photons incident on a driven pixel group made up of the plurality of pixels 81.

[0067] Although an example in which two TDCs 24 are connected to one pixel row has been described here, two TDCs 24 may be connected to multiple pixel rows, or two TDCs 24 may be connected to one pixel 81.

[0068] Second Embodiment Example of the Configuration of the Photodetector Element The photodetector element 11 may be configured such that two pixels (photodiodes) are connected to two TDCs, and the slew rate of the counter (TDC) connected to the pixels may be made variable.

[0069] In such a case, the photodetector element 11 is configured, for example, as shown in Fig. 3. In Fig. 3, parts corresponding to those in Fig. 1 are given the same reference numerals, and their explanation will be omitted as appropriate.

[0070] The photodetector element 11 shown in FIG. 3 includes a photodiode 141, an inverter 142, a photodiode 21, an inverter 22, a MUX (Multiplexer) circuit 143, a flip-flop circuit section 23, MUX circuits 144-1 and 144-2, a TDC 24-1, and a TDC 24-2.

[0071] 1, and includes a flip-flop circuit 31 and an inverter 32. However, in this example, the photodiode 21 and the photodiode 141 are connected to the flip-flop circuit 23 via a MUX circuit 143 and the like.

[0072] The photodiode 141 is a photodiode similar to the photodiode 21, and performs avalanche amplification in response to incident photons. A predetermined power supply and an input terminal of an inverter 142 are connected to the photodiode 141. The inverter 142 inverts the signal supplied from the photodiode 141 and outputs the inverted signal.

[0073] In FIG. 3, the output terminal of the inverter 142 is connected to the MUX circuit 143 and the MUX circuit 144-1, and the output terminal of the inverter 22 is connected to the MUX circuit 143 and the MUX circuit 144-2.

[0074] The MUX circuit 143 is a multiplexer circuit arranged between the photodiodes 21 and photodiodes 141 corresponding to a plurality of pixels and the flip-flop circuit unit 23. In particular, the MUX circuit 143 is arranged immediately before (preceding) the flip-flop circuit 31, and functions as a switch unit (switch circuit) that turns on and off the input of a signal to the flip-flop circuit unit 23. For example, the operation of the MUX circuit 143, i.e., the on / off of the MUX circuit 143, is controlled by a register.

[0075] The MUX circuit 143 switches between supplying the signals from the photodiode 21 and the photodiode 141 to the TDC 24 via the flip-flop circuit unit 23, or supplying the signals output from the photodiode 21 and the photodiode 141 to the TDC 24-1 and the TDC 24-2, respectively, without passing through the flip-flop circuit unit 23.

[0076] Specifically, when the MUX circuit 143 is turned on, i.e., when the MUX circuit 143 is in a driving state, the MUX circuit 143 supplies the signal supplied from the inverter 22 or the inverter 142 to the clock input terminal of the flip-flop circuit 31.

[0077] For example, when the MUX circuit 143 is turned on (driven), only one of the pixel having the photodiode 21 and the pixel having the photodiode 141 is set as a driven pixel, and the other pixel is set as a non-driven pixel.

[0078] Therefore, when the MUX circuit 143 is in the on state, the signal output from the photodiode of the pixel designated as the driven pixel, out of the photodiode 21 and the photodiode 141, is input to the flip-flop circuit 31 via the inverter and the MUX circuit 143.

[0079] On the other hand, when the MUX circuit 143 is turned off, that is, when the MUX circuit 143 is in a non-driven state, even if a signal is supplied from the inverter 22 or the inverter 142, the MUX circuit 143 does not output the supplied signal to the flip-flop circuit 31. Furthermore, the signal output from the photodiode 21 is supplied to the TDC 24-2 via the inverter 22 and the MUX circuit 144-2, and the signal output from the photodiode 141 is supplied to the TDC 24-1 via the inverter 142 and the MUX circuit 144-1.

[0080] From the above, it can be said that turning the MUX circuit 143 on and off controls whether or not to use the flip-flop circuit unit 23 when generating a histogram, that is, when measuring distance.

[0081] The MUX circuits 144-1 and 144-2 are multiplexer circuits with a switching function, and selectively output input signals to the TDC 24 in response to external control.

[0082] One input terminal of the MUX circuit 144-1 is connected to the output terminal of the inverter 142, and the other input terminal of the MUX circuit 144-1 is connected to the output terminal (Q terminal) of the flip-flop circuit 31. The output terminal of the MUX circuit 144-1 is connected to the TDC 24-1.

[0083] One input terminal of the MUX circuit 144-2 is connected to the output terminal of the inverter 22, and the other input terminal of the MUX circuit 144-2 is connected to the inverting output terminal of the flip-flop circuit 31. The output terminal of the MUX circuit 144-2 is connected to the TDC 24-2.

[0084] Hereinafter, when there is no need to particularly distinguish between the MUX circuits 144-1 and 144-2, they will also be simply referred to as MUX circuits 144.

[0085] The photodetector element 11 has a configuration in which two photodiodes 21 and 141 are shared by two TDCs 24 .

[0086] 3, the photodetector element 11 can select either a normal TDC slew rate mode or a high TDC slew rate mode as the drive mode. That is, it is possible to dynamically switch between the normal TDC slew rate mode and the high TDC slew rate mode. For example, the drive mode can be switched for each frame.

[0087] The normal TDC slew rate mode is a mode in which the slew rate of the TDC 24 is slow.

[0088] In the normal TDC slew rate mode, the MUX circuit 143 is turned off. That is, the flip-flop circuit 31 is not used, and no signal is output from the flip-flop circuit 31 to the MUX circuit 144.

[0089] In the normal TDC slew rate mode, at least one of the pixel having the photodiode 21 and the pixel having the photodiode 141 is set as a driving pixel. Here, it is assumed that both pixels are set as driving pixels.

[0090] Therefore, in the normal TDC slew rate mode, for example, when a photon is incident on the photodiode 141, a signal corresponding to the incident photon is supplied from the photodiode 141 to the TDC 24-1 via the inverter 142 and the MUX circuit 144-1. When the TDC 24-1 receives the signal output from the photodiode 141, it performs a counting operation and generates count data. In this case, the MUX circuit 144-1 is controlled to output the signal supplied from the inverter 142.

[0091] Similarly, in the normal TDC slew rate mode, when a photon is incident on the photodiode 21, a signal corresponding to the incident photon is supplied from the photodiode 21 to the TDC 24-2 via the inverter 22 and the MUX circuit 144-2. When the TDC 24-2 receives the signal output from the photodiode 21, it performs a counting operation and generates count data. In this case, the MUX circuit 144-2 is controlled to output the signal supplied from the inverter 22.

[0092] From the above, in the normal TDC slew rate mode, TDC 24-1 generates count data indicating the result of photon detection by photodiode 141, and TDC 24-2 generates count data indicating the result of photon detection by photodiode 21.

[0093] Therefore, one TDC 24 is connected to one pixel (photodiode), in other words, one pixel has one TDC output.

[0094] In contrast, the high TDC slew rate mode is a mode in which the slew rate of the TDC 24 is higher than in the normal TDC slew rate mode.

[0095] When the high TDC slew rate mode is selected, the MUX circuit 143 is turned on. That is, the flip-flop circuit 31 is enabled, and a signal is output from the flip-flop circuit 31 to the MUX circuit 144. In this case, each MUX circuit 144 is controlled to output a signal supplied from the flip-flop circuit 31. In other words, each MUX circuit 144 is controlled to receive a signal from the flip-flop circuit 31.

[0096] In the high TDC slew rate mode, either the pixel having the photodiode 21 or the pixel having the photodiode 141 is set as a driven pixel, and the other pixel is set as a non-driven pixel.

[0097] Here, for example, a pixel having the photodiode 141 is considered to be a driven pixel, and a pixel having the photodiode 21 is considered to be a non-driven pixel.

[0098] Therefore, in the high TDC slew rate mode, for example, when a photon is incident on the photodiode 141, a signal corresponding to the incident photon is supplied from the photodiode 141 to the flip-flop circuit 31 via the inverter 142 and the MUX circuit 143.

[0099] In this case, the flip-flop circuit 31 outputs an output signal corresponding to the supplied latch signal while switching the output destination each time a signal (latch signal) is supplied from the MUX circuit 143, as in the case of FIG. 1 .

[0100] That is, the flip-flop circuit 31 alternately supplies an output signal to the TDC 24-1 via the MUX circuit 144-1 and to the TDC 24-2 via the MUX circuit 144-2. As a result, the output signal from the flip-flop circuit 31 is alternately distributed to the TDC 24-1 and the TDC 24-2. At this time, the MUX circuit 144 does not output the signal supplied from the inverter 142 or the inverter 22, but selectively supplies the output signal supplied from the flip-flop circuit 31 to the TDC 24.

[0101] When the output signals from the MUX circuits 144-1 and 144-2 are supplied to the TDCs 24-1 and 24-2, the TDCs 24-1 and 24-2 perform counting operations and generate count data, thereby enabling the histogram builder 101 at the subsequent stage to obtain the same histogram as in FIG.

[0102] In this example, the pixel having the photodiode 21 is a non-driven pixel, and therefore no signal is output from the photodiode 21.

[0103] As a result, in the high TDC slew rate mode, two TDCs 24 are connected to and driven for one photodiode. Therefore, similar to the example in FIG. 1, the dead time of the TDCs 24 can be shortened while suppressing the occurrence of leakage current and the increase in power consumption. This improves the ranging accuracy and the signal-to-noise ratio.

[0104] 3 and each pixel in each pixel row is connected to two TDCs 24, the photodetector element 11 may have the configuration shown in Fig. 4. In Fig. 4, the same reference numerals are used to designate parts corresponding to those in Fig. 2 or 3, and descriptions thereof will be omitted where appropriate.

[0105] 4, the pixel array section 71 is provided with a pixel row including pixels 171-1, 171-2, and 171-3, which are similar to pixel 81, adjacent to a pixel row including pixel 81 having a photodiode 21. Hereinafter, the pixels that make up the pixel row including pixel 171-1 and pixel 171-2 will also be simply referred to as pixel 171.

[0106] Each pixel 171 has one photodiode 141. An inverter 142 connected to the photodiode 141 in the pixel 171 is also provided inside or outside the pixel 171 in the pixel array unit 71, but the inverter 142 is not shown here.

[0107] Furthermore, one MUX circuit 143 is provided for every two adjacent pixel rows in the photodetector element 11. The MUX circuits 143 may be provided in either the upper substrate region 61 or the lower substrate region 62.

[0108] For example, each pixel constituting one pixel row, such as a pixel row consisting of pixel 81 or a pixel row consisting of pixel 171, is connected to the same signal line, and that signal line is connected to the flip-flop circuit section 23 via one MUX circuit 143.

[0109] Furthermore, although not shown here, a MUX circuit 144-1 and a MUX circuit 144-2 are provided in the subsequent stage of each flip-flop circuit unit 23 in the switching unit 91.

[0110] As explained with reference to FIG. 3, the photodiode 141 in the pixel 171 is connected to the MUX circuit 144-1 via an inverter 142 and a signal line (not shown), and the photodiode 21 in the pixel 81 is connected to the MUX circuit 144-2 via an inverter 22 and a signal line (not shown).

[0111] In this example, two pixel rows are shared by two TDCs 24, and whether or not to use the flip-flop circuit 31 can be determined by switching the on / off state of the MUX circuit 143. In other words, the drive mode can be switched. In particular, since drive in a normal TDC slew rate mode, in which one pixel outputs one TDC, is also possible, the generation unit 93 is provided with a histogram builder 101 for each TDC 24.

[0112] When driving in any drive mode, it is possible to set each pixel constituting a pixel row, such as pixel 171 or pixel 81, as a driven pixel or a non-driven pixel, as in the example of FIG.

[0113] <First Modification of Second Embodiment> <Configuration Example of Photodetector> The photodetector 11 shown in FIG. 4 may further be provided with a circuit control unit that controls the on / off switching of the flip-flop circuit 31, i.e., switching between use and non-use.

[0114] In such a case, the photodetector element 11 may have, for example, the configuration shown in Fig. 5. In Fig. 5, parts corresponding to those in Fig. 4 are given the same reference numerals, and their explanation will be omitted as appropriate.

[0115] The configuration of the photodetector element 11 shown in FIG. 5 is configured by adding a circuit control unit 201 to the configuration of the photodetector element 11 shown in FIG.

[0116] The circuit control unit 201 receives the histograms obtained by each histogram builder 101 from the generation unit 93, and controls the operations of the MUX circuit 143 and the pixel array unit 71 based on the histograms. That is, the circuit control unit 201 controls whether or not the flip-flop circuit 31 is used by the MUX circuit 143, and controls the amount of recharge current at the pixels of the pixel array unit 71.

[0117] For example, the histogram builder 101 generates a histogram in which a predetermined time within one frame period, more specifically, a predetermined short period, is defined as a bin, and the bin value is a count value corresponding to the number of photons incident on a pixel (photodiode) at the time (period) corresponding to that bin. The histogram is made up of bin values ​​corresponding to multiple times within one frame period.

[0118] The circuit control unit 201 performs threshold processing based on the histograms obtained by each histogram builder 101, and, depending on the results of the threshold processing, controls the MUX circuit 143 and the pixels of the pixel array unit 71. For example, the circuit control unit 201 controls the MUX circuit 143 and the pixels of the pixel array unit 71 for each predetermined period, such as each frame period.

[0119] As a specific example, a case where the pixel 81 and the MUX circuit 143 are controlled for each frame will be described.

[0120] The circuit control unit 201 performs threshold processing based on the histogram obtained by the histogram builder 101 corresponding to the pixel row made up of the pixels 81 .

[0121] In threshold processing, the value (count value) of a predetermined bin in the histogram may be the target of threshold determination, or the sum of the values ​​of all bins in the histogram, or the sum of the values ​​of a predetermined number of bins in the histogram. Here, the value (count value) of one predetermined bin is compared with the threshold.

[0122] For example, when the value (count value) of a specific bin in the histogram is equal to or greater than a predetermined threshold, the circuit control unit 201 turns on the MUX circuit 143 connected to the pixel row made up of the pixels 81 and sets the drive mode to the high TDC slew rate mode. This is because when the bin value (count value) is large, photons are incident on the pixel 81 with a high frequency, and therefore the high TDC slew rate mode, which has a higher slew rate, is suitable for performing distance measurement with sufficient accuracy.

[0123] In contrast, when the value of a specific bin in the histogram is less than a predetermined threshold, the circuit control unit 201 turns off the MUX circuit 143 connected to the pixel row consisting of the pixels 81, and sets the drive mode to the normal TDC slew rate mode.

[0124] Furthermore, in accordance with the result of the threshold processing, the circuit control unit 201 switches the setting of the recharge current of the pixel 81, more specifically, the photodiode 21. In other words, the circuit control unit 201 controls the amount of the recharge current in accordance with the result of the threshold processing.

[0125] For example, when the value of a specific bin in the histogram is equal to or greater than a predetermined threshold, the circuit control unit 201 sets a larger recharge current amount for the photodiode 21. This shortens the dead time of the photodiode 21, allowing it to count up to a larger count value.

[0126] In response to this, when the value of a specific bin in the histogram is less than a predetermined threshold, the circuit control unit 201 sets the amount of recharge current of the photodiode 21 to be smaller. Note that the threshold used to control the amount of recharge current may be different from the threshold used to switch the drive mode. Furthermore, the amount of recharge current may be switched in three or more stages depending on the histogram.

[0127] As described above, the circuit control unit 201 controls the switching of the drive mode and the amount of recharge current based on the histogram. Since the histogram is generated from the count data, it can be said that the circuit control unit 201 controls the switching of the drive mode and the amount of recharge current based on the count data.

[0128] The switching of the drive mode and the control of the recharge current amount may be performed for all MUX circuits 143 or pixels, or may be performed for each MUX circuit 143 or for each pixel group connected to one MUX circuit 143. For example, when the value of a predetermined bin in one histogram or a predetermined number of histograms out of all the histograms is equal to or greater than a threshold, it may be possible to set the drive mode for the entire pixel array unit 71 to the high TDC slew rate mode or to set the recharge current amount to a larger amount.

[0129] <Modification 2 of Second Embodiment> <Configuration Example of Photodetector Element> When the circuit control unit 201 controls the MUX circuit 143, that is, the on / off of the flip-flop circuit 31, and the recharge current of the pixels in the pixel array unit 71, the photodetector element 11 can also be configured as shown in Fig. 6. Note that in Fig. 6, parts corresponding to those in Fig. 5 are assigned the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0130] The configuration of the photodetector element 11 shown in FIG. 6 is basically the same as the configuration of the photodetector element 11 shown in FIG. 5, but differs from the example in FIG. 5 in that the circuit control unit 201 does not receive a histogram from the generation unit 93, but receives detection signals for each TDC 24 from the counting unit 92.

[0131] In the example of FIG. 6, each TDC 24 and the circuit control unit 201 are connected by a signal line for notifying (transmitting) the detection signal to the circuit control unit 201 on the logic side.

[0132] The detection signal is a signal indicating that a new latch signal is supplied while the latch signal, more specifically, while the output signal, is being latched by the TDC 24. In other words, the detection signal is a signal indicating that a new incident photon has been detected during the dead time period of the TDC 24.

[0133] The term "during latching" here refers to the period from when the TDC 24 latches a latch signal until the next latch operation becomes possible, i.e., the dead time period of the TDC 24. Even if a further latch signal is supplied during the dead time of the TDC 24, the TDC 24 cannot perform a count operation (update the count data) based on that latch signal.

[0134] Therefore, the circuit control unit 201 controls the MUX circuit 143 based on the detection signal supplied from the TDC 24 to switch the driving mode and control the amount of recharge current for the pixels of the pixel array unit 71 .

[0135] For example, when a detection signal is supplied from the TDC 24, the circuit control unit 201 controls the MUX circuit 143 to turn it on, sets the drive mode to a high TDC slew rate mode, and sets the recharge current amount to a larger value.

[0136] In the example shown in Figure 6, as in the example of Figure 5, switching of drive modes and control of the amount of recharge current may be performed for all MUX circuits 143 or pixels, or may be performed for each MUX circuit 143 or for each pixel group connected to one MUX circuit 143, etc.

[0137] When the photodetector element 11 has the configuration shown in FIG. 6, the TDC 24 has the configuration shown in FIG. 7, for example.

[0138] The TDC 24 shown in FIG. 7 includes a TDC circuit unit 211 and a detection unit 212 .

[0139] The TDC circuit unit 211 is a circuit having the same configuration as a general TDC, and latches the signal (latch signal) supplied from the MUX circuit 144, and outputs a code signal corresponding to the latch result as count data.

[0140] The detection unit 212 generates a detection signal based on the signal (latch signal) supplied from the MUX circuit 144 and a signal supplied from an internal circuit of the TDC circuit unit 211 (a flip-flop circuit 231 described later) indicating whether or not the latch is in progress, i.e., whether or not the dead time of the TDC 24 is in progress, and supplies the detection signal to the circuit control unit 201.

[0141] For example, the signal supplied from the MUX circuit 144-1 to the TDC circuit unit 211 and detection unit 212 of the TDC 24-1 is the signal output from the photodiode 141 via the inverter 142, or the signal (output signal) output from the output terminal of the flip-flop circuit 31. Also, the signal supplied from the MUX circuit 144-2 to the TDC circuit unit 211 and detection unit 212 of the TDC 24-2 is the signal output from the photodiode 21 via the inverter 22, or the signal output from the inverting output terminal of the flip-flop circuit 31.

[0142] The TDC circuit section 211 includes a flip-flop circuit 231 , a flip-flop circuit 232 , a flip-flop circuit 233 , a flip-flop circuit 234 , an AND circuit 235 , a flip-flop circuit 236 , a pulse shortening section 237 , and an inverter 238 .

[0143] The detection unit 212 includes an AND circuit 241 and a flip-flop circuit 242 .

[0144] In the TDC circuit unit 211, the signal (latch signal) output from the MUX circuit 144 is input to the clock input terminal of the flip-flop circuit 231, and the signal TIEH of a fixed voltage is supplied to the input terminal of the flip-flop circuit 231.

[0145] Furthermore, the output terminal (Q terminal) of the flip-flop circuit 231 is connected to the input terminal of an AND circuit 241 in the detection unit 212 , the clock input terminal of the flip-flop circuit 232 , and the input terminal of the flip-flop circuit 234 .

[0146] The output terminal of the flip-flop circuit 233 is connected to the input terminal of the flip-flop circuit 233, and the clock input terminal of the flip-flop circuit 233 is connected to the output terminal of the AND circuit 235. The flip-flop circuit 233 outputs a code signal as count data from its output terminal. This code signal (count data) is supplied to the histogram builder 101.

[0147] In the TDC circuit section 211 , a clock signal for synchronization is inverted and input to the clock input terminal of the flip-flop circuit 234 , and is also supplied to the clock input terminal of the flip-flop circuit 236 and the input terminal of the AND circuit 235 .

[0148] The output terminal of the flip-flop circuit 234 is connected to the input terminal of the AND circuit 235 and the input terminal of the flip-flop circuit 236, and the flip-flop circuit 236 outputs a validity determination signal from its output terminal. This validity determination signal indicates whether the code signal (count data) is valid or not.

[0149] AND circuit 235 outputs a signal corresponding to the signal from flip-flop circuit 234 and a clock signal for synchronization to the clock input terminal of flip-flop circuit 233 and to pulse shortening unit 237. Pulse shortening unit 237 is a one-shot circuit, and supplies an output (signal) corresponding to the signal input from AND circuit 235 to the reset terminal of flip-flop circuit 231 via inverter 238.

[0150] In the detection unit 212, the signal (latch signal) output from the MUX circuit 144 and the signal output from the output terminal of the flip-flop circuit 231 in the TDC circuit unit 211 are supplied to the input terminal of an AND circuit 241. The signal supplied from the MUX circuit 144 to the AND circuit 241 is the same as the signal supplied from the MUX circuit 144 to the TDC circuit unit 211.

[0151] The output terminal of the AND circuit 241 is connected to the clock input terminal of a flip-flop circuit 242, and a fixed voltage signal TIEH is supplied to the input terminal of the flip-flop circuit 242. The output terminal of the flip-flop circuit 242 is connected to the circuit control unit 201 via a signal line (not shown).

[0152] For example, when a photon is incident on a pixel of the pixel array unit 71, i.e., the photodiode 21 or the photodiode 141, and a signal is supplied from the MUX circuit 144 to the flip-flop circuit 231 of the TDC circuit unit 211, the TDC circuit unit 211 enters a latching state. In other words, this is the dead time period of the TDC 24.

[0153] When the TDC circuit unit 211 is in a latching state (holding a signal), that is, when the signal held by the TDC circuit unit 211 has not yet been handed over (before output) to the downstream histogram builder 101, the signal output from the flip-flop circuit 231 to the AND circuit 241 is a signal indicating that the TDC 24 is currently in a dead time period. When the dead time period of the TDC 24 ends, the signal output from the flip-flop circuit 231 to the AND circuit 241 is a signal indicating that the dead time period is not in progress.

[0154] While a signal indicating that a dead time period is in progress is being supplied from the flip-flop circuit 231 to the AND circuit 241, a photon is detected incident on a pixel (photodiode) of the pixel array section 71, and a new signal (latch signal) is supplied to the clock input terminal of the flip-flop circuit 231 and the input terminal of the AND circuit 241.

[0155] In such a case, a signal serving as a clock is input from the AND circuit 241 to the flip-flop circuit 242, and the flip-flop circuit 242 outputs (supplies) to the circuit control unit 201 a detection signal indicating that a new photon has been detected entering during the dead time of the TDC 24. Specifically, in the example of Fig. 7, the detection signal becomes H level.

[0156] By providing such a detection unit 212, it is possible to detect that a new photon has been detected at a pixel (photodiode) during the dead time of the TDC 24, that is, that a new signal has been supplied to the TDC 24, and notify (feed back) the detection result to the circuit control unit 201.

[0157] The detection unit 212 may be provided inside the TDC 24 or outside the TDC 24 .

[0158] <Third Modification of the Second Embodiment> <Configuration Example of Photodetector Element> Apart from the pixel array unit 71 for distance measurement, a pixel array unit for discrimination may be provided for switching the drive mode and controlling the amount of recharge current.

[0159] In such a case, the photodetector element 11 is configured, for example, as shown in Fig. 8. In Fig. 8, the same reference numerals are used to designate parts corresponding to those in Fig. 5, and the description thereof will be omitted where appropriate.

[0160] The configuration of the photodetector element 11 shown in Fig. 8 is the same as the configuration of the photodetector element 11 shown in Fig. 5, but with a new determination pixel array section 281, count section 282, and generation section 283. In this example, the determination pixel array section 281, count section 282, and generation section 283 are configured to allow the circuit control section 201 to switch the drive mode and control the amount of recharge current.

[0161] Here, an example will be described in which the circuit control unit 201 performs both the switching of the drive mode and the control of the recharge current amount, but it is sufficient if at least one of the switching of the drive mode and the control of the recharge current amount is performed.

[0162] The discrimination pixel array section 281 is made up of a plurality of pixels arranged in a matrix, including, for example, a pixel 291. Hereinafter, when there is no need to particularly distinguish the pixels provided in the discrimination pixel array section 281, they will also be simply referred to as pixels 291.

[0163] The pixel 291 is provided with a photodiode similar to the photodiode 21 of the pixel 81. Furthermore, a pixel row is formed by the pixels 291 arranged in the row direction in the discrimination pixel array section 281, and each pixel 291 constituting one pixel row is connected to the count section 282 via an inverter (not shown) or one signal line.

[0164] In the discrimination pixel array section 281 as well, as in the pixel array section 71, it is possible to set each pixel 291 as either a driven pixel or a non-driven pixel.

[0165] The counting unit 282 has a TDC 292, which is a counter provided for each pixel row, and the generating unit 283 has a histogram builder 293 provided for each pixel row.

[0166] When a photon is incident on a pixel 291 that is a driving pixel and that constitutes a pixel row, a signal corresponding to the incident photon is supplied to the TDC 292 from the pixel 291. The TDC 292 performs a counting operation similar to that of the TDC 24, and supplies the resulting count data to a histogram builder 293.

[0167] The histogram builder 293 generates a histogram similar to that in the histogram builder 101 based on the count data supplied from the TDC 292 , and supplies the histogram to the circuit control unit 201 .

[0168] 5 based on the histogram supplied from the histogram builder 293, and controls the MUX circuit 143 and the pixels of the pixel array unit 71 according to the result of the threshold processing, thereby switching the drive mode and controlling the amount of recharge current.

[0169] In the example of FIG. 8, a pixel array section 281 for determination, which is dedicated to switching the drive mode and controlling the amount of recharge current, is provided separately from the pixel array section 71 for distance measurement.

[0170] Since the discrimination pixel array unit 281 does not require switching of the drive mode, a MUX circuit corresponding to the MUX circuit 143 is not provided between the pixels 291 of the discrimination pixel array unit 281 and the TDC 292. However, the present invention is not limited to this, and a MUX circuit may be provided between the pixels 291 and the TDC 292.

[0171] Alternatively, in the photodetector element 11 shown in FIG. 8, the TDC 292 may have the configuration shown in FIG. 7, and the circuit control unit 201 may switch the drive mode and control the amount of recharge current based on the detection signal supplied from the TDC 292.

[0172] When the photodetection element 11 has the configuration shown in FIG. 8, for example, as shown in FIG. 9, the pixel array section 71 and the discrimination pixel array section 281 are arranged at different positions on the surface (top surface) of the semiconductor chip that constitutes the photodetection element 11, more specifically, the semiconductor substrate 321.

[0173] 9, the discrimination pixel array section 281 is arranged near the pixel array section 71, at the lower right position in the drawing of the pixel array section 71. However, there are no particular restrictions on the arrangement of the pixel array section 71 and the discrimination pixel array section 281, and they may be arranged in any manner, not limited to the example shown in FIG.

[0174] Third Embodiment Example of the Configuration of the Photodetector Element When the photodetector element 11 is configured to be capable of switching the drive mode, a configuration for reducing the transfer time difference of signals to each TDC 24, i.e., skew, may be provided.

[0175] In such a case, the photodetector element 11 is configured, for example, as shown in Fig. 10. In Fig. 10, parts corresponding to those in Fig. 3 are given the same reference numerals, and their explanation will be omitted as appropriate.

[0176] The configuration of the photodetector element 11 shown in FIG. 10 is the same as the configuration of the photodetector element 11 shown in FIG. 3, except that delay elements 361-1, 361-2, AND circuits 362-1, and 362-2 are newly added.

[0177] In the example of FIG. 10, the output terminal of the MUX circuit 143 is connected to the clock input terminal of the flip-flop circuit 31, the delay element 361-1, and the delay element 361-2.

[0178] The delay elements 361-1 and 361-2 delay the signal (latch signal) output from the MUX circuit 143 and then supply the delayed signal to the AND circuits 362-1 and 362-2. Hereinafter, when there is no need to particularly distinguish between the delay elements 361-1 and 361-2, they will also be simply referred to as delay elements 361.

[0179] The AND circuit 362-1 supplies a signal corresponding to the signal supplied from the delay element 361-1 and the signal (output signal) supplied from the output terminal of the flip-flop circuit 31 to the MUX circuit 144-1.

[0180] The AND circuit 362-2 supplies a signal corresponding to the signal supplied from the delay element 361-2 and the signal supplied from the inverting output terminal of the flip-flop circuit 31 to the MUX circuit 144-2.

[0181] Hereinafter, when there is no need to particularly distinguish between the AND circuit 362-1 and the AND circuit 362-2, they will also be simply referred to as the AND circuit 362.

[0182] In the example of Fig. 10, skew can be reduced by providing a delay element 361 and an AND circuit 362. Skew reduction will be described below with reference to Fig. 11. In Fig. 11, the horizontal direction represents time, and the vertical direction represents signal level.

[0183] 11, the broken line L11 indicates the latch signal, i.e., the output (pixel output) of the MUX circuit 143, and the broken line L12 indicates the output (output signal) from the output terminal of the flip-flop circuit 31. The broken line L13 indicates the output of the delay element 361, i.e., the signal supplied from the delay element 361 to the AND circuit 362.

[0184] The broken line L14 indicates the output of the AND circuit 362-1, i.e., the signal supplied from the AND circuit 362-1 to the TDC 24-1 via the MUX circuit 144-1. The broken line L15 indicates the output of the AND circuit 362-2, i.e., the signal supplied from the AND circuit 362-2 to the TDC 24-2 via the MUX circuit 144-2.

[0185] For example, when the incident photon is detected at the driving pixel at the timing indicated by the arrow W11 in FIG. 11 and a signal is output from the MUX circuit 143, that is, when the output of the MUX circuit 143 becomes H level, the output (output signal) of the flip-flop circuit 31 also becomes H level accordingly.

[0186] Thereafter, the signal output from the MUX circuit 143 at the timing indicated by arrow W11 is delayed by the delay element 361-1 and supplied to the AND circuit 362-1 at the timing indicated by arrow W12, causing the output of the AND circuit 362-1 to go high. As a result, as indicated by broken line L14, a signal corresponding to the incidence of a photon is supplied to the TDC 24-1, and the TDC 24-1 performs a counting operation.

[0187] Furthermore, thereafter, when the next incident photon is detected at the driven pixel at the timing indicated by arrow W13, a signal is output from the MUX circuit 143, and accordingly the output (output signal) of the flip-flop circuit 31 becomes L level. As a result, a signal (H level) corresponding to the incident photon is input from the inverting output terminal of the flip-flop circuit 31 to the AND circuit 362-2.

[0188] Furthermore, when the signal output from the MUX circuit 143 at the timing indicated by arrow W13 is delayed by the delay element 361-2 and supplied to the AND circuit 362-2 at the timing indicated by arrow W14, the output of the AND circuit 362-2 becomes H level. As a result, as indicated by broken line L15, a signal corresponding to the incidence of a photon is supplied to the TDC 24-2, and the TDC 24-2 performs a counting operation.

[0189] In the above-described driving, the latch signal output from the MUX circuit 143 is output from the flip-flop circuit 31 at the same timing. However, the signal output from the flip-flop circuit 31 is not supplied to the TDC 24 at that timing, but remains in a standby state until the signal from the delay element 361 is supplied to the AND circuit 362. In other words, the signal output from the flip-flop circuit 31 is supplied to the TDC 24 at the timing when the signal from the delay element 361 is supplied to the AND circuit 362.

[0190] If the latch signal output from the MUX circuit 143 is directly supplied to the TDC 24 via the flip-flop circuit 31, a difference (skew) in transfer time occurs between the TDC 24-1 and the TDC 24-2 due to the asymmetry of the circuit.

[0191] 10, a delay element 361 and an AND circuit 362 are provided as a configuration for eliminating (suppressing) such a difference in transfer time. That is, a block made up of the delay element 361 and the AND circuit 362 is placed between the flip-flop circuit unit 23 and the TDC 24, and functions as a delay unit that adjusts the supply timing of the signal (output signal) supplied from the flip-flop circuit unit 23 to the TDC 24.

[0192] By providing such a configuration, it is possible to regulate the timing of signal supply to the delay element 361 side, thereby suppressing the occurrence of the above-mentioned transfer time difference. In this example, it can be said that the signal output from the flip-flop circuit 31 is used as a mask signal, and the signal output from the driven pixel (photodiode) is directly allocated to each TDC 24.

[0193] <Fourth embodiment> <Configuration example of photodetector element> In the above, an example has been described in which a signal output from a pixel in response to incident photons is distributed to two TDCs 24, but the signal from a pixel may be distributed in sequence to three or more TDCs.

[0194] For example, when one photodiode (pixel) is connected to three TDCs, the photodetector element 11 can have the configuration shown in Fig. 12. Note that in Fig. 12, parts corresponding to those in Fig. 1 are given the same reference numerals, and their explanation will be omitted as appropriate.

[0195] The photodetector element 11 shown in FIG. 12 includes a photodiode 21, an inverter 22, a flip-flop circuit section 391, a TDC 392-1, a TDC 392-2, and a TDC 392-3.

[0196] In this example, when the photodiode 21 in the pixel detects the incidence of a photon, a signal corresponding to the incidence of the photon is supplied to a flip-flop circuit unit 391 via an inverter 22. The flip-flop circuit unit 391 supplies (outputs) the signal (latch signal) supplied from the inverter 22 as an output signal to one of TDC 392-1, TDC 392-2, and TDC 392-3.

[0197] The TDCs 392-1, 392-2, and 392-3 are counters similar to the TDC 24, and perform counting operations when a signal is supplied from the flip-flop circuit unit 391, and output the resulting count data to the subsequent stage. Note that, hereinafter, when there is no need to particularly distinguish between the TDCs 392-1, 392-2, and 392-3, they will also be simply referred to as TDC 392.

[0198] The flip-flop circuit unit 391 functions as an output destination switching unit that distributes and supplies (outputs) the latch signal supplied from the inverter 22, more specifically, the signal corresponding to the latch signal, in order to the three TDCs 392 connected downstream. In other words, the flip-flop circuit unit 391 switches the output destination of the latch signal so that the latch signal (output signal) is supplied in order from TDC 392-1 to TDC 392-3.

[0199] The flip-flop circuit section 391 includes a flip-flop circuit 401 , a flip-flop circuit 402 , a flip-flop circuit 403 , a flip-flop circuit 404 , an AND circuit 405 , a flip-flop circuit 406 , an AND circuit 407 , a logic circuit 408 , a logic circuit 409 , and a logic circuit 410 .

[0200] In the flip-flop circuit section 391 , the signal (latch signal) output from the inverter 22 is supplied to the clock input terminals of the flip-flop circuits 401 , 402 , 403 , and 404 .

[0201] The output terminal of the flip-flop circuit 404 is connected to the input terminals of the logic circuits 408, 409, and 410, and the inverting output terminal of the flip-flop circuit 404 is connected to the input terminal of the AND circuit 405 and the clock input terminal of the flip-flop circuit 406.

[0202] One input terminal of the AND circuit 405 is connected to the inverting output terminal of the flip-flop circuit 404, and the other input terminal of the AND circuit 405 is connected to the output terminal of the logic circuit 410. The output terminal of the AND circuit 405 is connected to the input terminal of the flip-flop circuit 404.

[0203] The input terminal of the flip-flop circuit 406 is connected to the output terminal of the AND circuit 407, and the output terminal of the flip-flop circuit 406 is connected to the input terminals of the logic circuits 408, 409, and 410. The inverting output terminal of the flip-flop circuit 406 is connected to the input terminal of the AND circuit 407.

[0204] One input terminal of the AND circuit 407 is connected to the inverting output terminal of the flip-flop circuit 406, and the other input terminal of the AND circuit 407 is connected to the output terminal of the logic circuit 410. The output terminal of the AND circuit 407 is connected to the input terminal of the flip-flop circuit 406.

[0205] Logic circuit 408 receives the outputs of flip-flop circuits 406 and 404 as inputs, and supplies an output corresponding to these signals to the input terminal of flip-flop circuit 401. The output terminal of flip-flop circuit 401 is connected to TDC 392-1, and flip-flop circuit 401 supplies a signal corresponding to the output of logic circuit 408 to TDC 392-1.

[0206] The logic circuit 409 receives the outputs of the flip-flop circuits 406 and 404 as inputs, and supplies an output corresponding to these signals to the input terminal of the flip-flop circuit 402. The output terminal of the flip-flop circuit 402 is connected to the TDC 392-2, and the flip-flop circuit 402 supplies a signal corresponding to the output of the logic circuit 409 to the TDC 392-2.

[0207] The logic circuit 410 receives the outputs of the flip-flop circuits 406 and 404 as inputs, and supplies an output corresponding to these signals to the input terminal of the flip-flop circuit 403. The output terminal of the flip-flop circuit 403 is connected to the TDC 392-3, and the flip-flop circuit 403 supplies a signal corresponding to the output of the logic circuit 410 to the TDC 392-3.

[0208] The photodetector element 11 described above has a binary counter circuit configuration in which three TDCs 392 are connected to one photodiode 21 (pixel). By sequentially allocating and supplying a signal corresponding to the incidence of a photon on one photodiode 21 to the three TDCs 392 in this way, it is possible to improve the slew rate of the counter when the three TDCs 392 are considered as one counter.

[0209] Fifth Embodiment Example of the Configuration of the Photodetector Element When one photodiode (pixel) is connected to four TDCs, the photodetector element 11 may have the configuration shown in Fig. 13. In Fig. 13, parts corresponding to those in Fig. 1 are denoted by the same reference numerals, and their description will be omitted as appropriate.

[0210] The photodetector element 11 shown in FIG. 13 includes a photodiode 21, an inverter 22, a flip-flop circuit section 441, a TDC 442-1, a TDC 442-2, a TDC 442-3, and a TDC 442-4.

[0211] In this example, when the photodiode 21 in the pixel detects the incidence of a photon, a signal corresponding to the incidence of the photon is supplied to the flip-flop circuit unit 441 via the inverter 22. The flip-flop circuit unit 441 supplies (outputs) the signal (latch signal) supplied from the inverter 22 as an output signal to one of the TDCs 442-1 to 442-4.

[0212] The TDCs 442-1 to 442-4 are counters similar to the TDC 24, and perform a counting operation when a signal is supplied from the flip-flop circuit unit 441, and output the resulting count data to the subsequent stage. Note that, hereinafter, when there is no need to particularly distinguish between the TDCs 442-1 to 442-4, they will also be simply referred to as TDCs 442.

[0213] The flip-flop circuit unit 441 functions as an output destination switching unit that distributes and supplies the latch signal supplied from the inverter 22, more specifically, the signal corresponding to the latch signal, in order to the four TDCs 442 connected in the subsequent stage. In other words, the flip-flop circuit unit 441 switches the output destination of the latch signal so that the latch signal (output signal) is supplied in order from TDC 442-1 to TDC 442-4.

[0214] The flip-flop circuit portion 441 includes a flip-flop circuit 451 , an inverter 452 , and a flip-flop circuit 453 .

[0215] In the flip-flop circuit section 441 , the signal (latch signal) output from the inverter 22 is supplied to the clock input terminal of the flip-flop circuit 451 and the clock input terminal of the flip-flop circuit 453 .

[0216] An input terminal of the flip-flop circuit 451 is connected to an output terminal of the inverter 452, and an output terminal of the flip-flop circuit 451 is connected to the TDC 442-1 and input terminals of the flip-flop circuit 453. Furthermore, an inverting output terminal of the flip-flop circuit 451 is connected to the TDC 442-2.

[0217] The output terminal of the flip-flop circuit 453 is connected to the input terminal of the inverter 452 and the TDC 442-3, and the inverted output terminal of the flip-flop circuit 453 is connected to the TDC 442-4.

[0218] In the photodetector element 11 described above, four TDCs 442 are connected in parallel to one photodiode 21 (pixel), and the flip-flop circuit unit 441 has a Johnson counter circuit configuration. By sequentially allocating and supplying a signal corresponding to the incidence of a photon on one photodiode 21 to the four TDCs 442 in this manner, the slew rate of the counter when viewed as one counter consisting of four TDCs 442 can be four times that of a counter connected to one pixel.

[0219] In the photodetector element 11 described above, the cycles (timings) of the clock signals when operating the plurality of TDCs, that is, the drive cycles, may be the same or different.

[0220] For example, in the photodetector element 11 having the configuration shown in FIG. 1, if the timing of the clock signals supplied to TDC 24-1 and TDC 24-2 is aligned, that is, if the same clock signal is supplied to TDC 24-1 and TDC 24-2, the operation timing of each part of the photodetector element 11 will be as shown in FIG. 14.

[0221] In Figure 14, the horizontal direction represents time, and the first row from the top represents the latch signal input to the flip-flop circuit section 23, and the second row from the top represents the signal (output signal) output from the output terminal of the flip-flop circuit 31.

[0222] In addition, the third row from the top in the figure shows the clock signals supplied to TDC 24-1 and TDC 24-2, the fourth row from the top in the figure shows the dead time period of TDC 24-1, and the fifth row from the top in the figure shows the transmission state of count data by TDC 24-1. Furthermore, the sixth row from the top in the figure shows the dead time period of TDC 24-2, and the seventh row from the top in the figure shows the transmission state of count data by TDC 24-2.

[0223] In this example, when the first latch signal shown in the top row, i.e., the part with an upward convex portion in the figure, is input to flip-flop circuit 31, TDC 24-1 performs a count operation, and a dead time occurs. Also, while TDC 24-1 is in dead time, the next latch signal is input to flip-flop circuit 31, but the signal corresponding to this latch signal is assigned to TDC 24-2, which performs a count operation. Then, at the rising edge of the clock signal, count data is output from TDC 24-1 and TDC 24-2, enabling the next count operation.

[0224] In contrast to this, for example, in the photodetector element 11 configured as shown in FIG. 1, if the timing of the clock signals supplied to TDC 24-1 and TDC 24-2 are not aligned, that is, if different clock signals are supplied to TDC 24-1 and TDC 24-2, the operation timing of each part of the photodetector element 11 will be as shown in FIG. 15.

[0225] In Figure 15, the horizontal direction represents time, and the first row from the top represents the latch signal input to the flip-flop circuit section 23, and the second row from the top represents the signal (output signal) output from the output terminal of the flip-flop circuit 31.

[0226] In addition, the third row from the top of the figure shows the clock signal supplied to TDC 24-1, the fourth row from the top of the figure shows the dead time period of TDC 24-1, and the fifth row from the top of the figure shows the transmission status of count data by TDC 24-1.

[0227] Furthermore, in the figure, the sixth row from the top shows the clock signal supplied to TDC 24-2, the seventh row from the top shows the dead time period of TDC 24-2, and the eighth row from the top shows the transmission status of count data by TDC 24-2.

[0228] In this example, a count operation is performed by TDC 24-1 when the first latch signal shown in the first row from the top, that is, the part with an upward convexity in the figure, is input to flip-flop circuit 31. Also, while TDC 24-1 is in dead time, the next latch signal is input to flip-flop circuit 31, but the signal corresponding to this latch signal is assigned to TDC 24-2, which then performs a count operation.

[0229] Then, count data is output from the TDC 24-1 at the rising edge of the clock signal supplied to the TDC 24-1, enabling the next count operation.Furthermore, after that, count data is output from the TDC 24-2 at the rising edge of the clock signal supplied to the TDC 24-2, enabling the next count operation.

[0230] In this example, the count data output timing of the TDC 24-1 and the TDC 24-2 is different, but as with the example of Fig. 14, it is possible to shorten the dead time period of the TDC 24 when looking at the entire photodetector element 11. Note that there are no particular restrictions on the drive cycle of the TDC 24, but when considering the processing in the logic circuit downstream of the TDC 24, it is possible to keep the circuit scale smaller in the example of Fig. 14.

[0231] As described above, this technology enables the transfer of photon detection results from a single pixel's photodiode to multiple TDCs, thereby shortening the TDC's dead time. This allows count data to be transferred to the histogram builder without reducing the count rate even when the photodiode's dead time is set short. Furthermore, it is possible to improve sensitivity under high background light conditions without increasing the TDC's drive frequency, which increases power consumption.

[0232] <Application Examples to Electronic Devices> The present technology is applicable to general electronic devices that use a solid-state imaging device in an image capture unit (photoelectric conversion unit), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, copiers that use a solid-state imaging device in an image reading unit, etc. The solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which the imaging unit and a signal processing unit or an optical system are packaged together.

[0233] FIG. 16 is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the present technology is applied.

[0234] The imaging device 601 in FIG. 16 includes an optical unit 611 including a lens group and the like, a solid-state imaging device (imaging device) 612 that employs the configuration of the photodetector element 11, and a DSP (Digital Signal Processor) circuit 613 that is a camera signal processing circuit.

[0235] The imaging device 601 also includes a frame memory 614, a display unit 615, a recording unit 616, an operation unit 617, and a power supply unit 618. The DSP circuit 613, the frame memory 614, the display unit 615, the recording unit 616, the operation unit 617, and the power supply unit 618 are connected to each other via a bus line 619.

[0236] The optical unit 611 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 612. The solid-state imaging device 612 converts the amount of incident light formed on the imaging surface by the optical unit 611 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0237] The display unit 615 is configured with a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the solid-state imaging device 612. The recording unit 616 records the moving images or still images captured by the solid-state imaging device 612 on a recording medium such as a hard disk or semiconductor memory.

[0238] An operation unit 617, under the operation of a user, issues operation commands for various functions of the imaging device 601. A power supply unit 618 appropriately supplies various types of power to the DSP circuit 613, frame memory 614, display unit 615, recording unit 616, and operation unit 617 as operating power sources to these power supply targets.

[0239] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0240] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0241] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0242] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0243] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0244] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0245] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0246] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0247] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0248] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0249] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0250] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0251] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0252] In FIG. 18, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0253] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0254] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0255] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0256] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0257] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0258] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0259] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the above-described configurations. Specifically, for example, the photodetector element 11 according to each of the above-described embodiments can be used as the imaging unit 12031, thereby reducing the dead time of the counter while suppressing an increase in power consumption.

[0260] It should be noted that the present technology is not limited to solid-state imaging devices and can be applied to semiconductor devices in general that include other semiconductor integrated circuits.

[0261] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0262] For example, it is possible to adopt a form in which all or part of the above-described embodiments are combined.

[0263] Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and there may be effects other than those described in this specification.

[0264] Furthermore, the present technology can also be configured as follows.

[0265] (1) A photodetector comprising: a photodiode that performs avalanche amplification in response to incident photons and outputs a signal; and an output destination switching unit that switches an output destination of the signal so that the signal output from the photodiode is output to each of a plurality of counters in sequence. (2) The photodetector according to (1), in which the photodiode is a SPAD. (3) The photodetector according to (1) or (2), in which a plurality of the photodiodes are connected to the output destination switching unit. (4) The photodetector according to (3), further comprising a switch unit that is disposed between the plurality of photodiodes and the output destination switching unit and switches whether the signal is supplied to the counter via the output destination switching unit or whether each of the signals output from the plurality of photodiodes is supplied to each of the plurality of counters without passing through the output destination switching unit. (5) The photodetector according to (4), further comprising a control unit that controls the switching by the switch unit. (6) The photodetector according to (5), in which the control unit controls the amount of recharge current of the photodiode. (7) The photodetector element according to (5) or (6), wherein the control unit controls switching by the switch unit based on count data generated by the counter based on the signal. (8) The photodetector element according to (7), further comprising a histogram that generates a histogram indicating photon detection results in the photodiode based on the count data, and the control unit controls switching by the switch unit based on the histogram. (9) The photodetector element according to (8), wherein the control unit controls the amount of recharge current of the photodiode based on the histogram. (10) The photodetector element according to (5) or (6), further comprising a detector that generates a detection signal indicating that the signal has been supplied to the counter during a dead time period, based on the signal supplied to the counter and a signal that is output from an internal circuit of the counter and indicates whether or not the counter is in a dead time period, and the control unit controls switching by the switch unit based on the detection signal.(11) The photodetector element according to (10), wherein the control unit controls the amount of recharge current of the photodiode based on the detection signal. (12) The photodetector element according to (5) or (6), including: a first pixel array unit provided with a plurality of pixels having the photodiode; and a second pixel array unit provided with a plurality of other pixels having other photodiodes for controlling switching by the switch unit. (13) The photodetector element according to (6), wherein the control unit controls switching by the switch unit and the amount of recharge current of the photodiode for each predetermined period. (14) The photodetector element according to any one of (4) to (13), further including a delay unit disposed between the output destination switching unit and the counter, and adjusting a supply timing of the signal supplied from the output destination switching unit to the counter.

[0266] 11 Photodetection element, 21 Photodiode, 23 Flip-flop circuit section, 24-1, 24-2 TDC, 31 Flip-flop circuit, 71 Pixel array section, 81-1 to 81-3 Pixel, 101 Histogram builder, 143 MUX circuit, 201 Circuit control section, 212 Detection section, 281 Discrimination pixel array section, 361-1, 361-2 Delay element, 362-1, 362-2 AND circuit

Claims

1. A photodetector that performs avalanche amplification in response to the incidence of photons and outputs a signal, and an output destination switching unit that switches the output destination of the signal so that the signal output from the photodetector is sequentially output to a plurality of respective counters.

2. The photodetector according to claim 1, wherein the photodetector is a SPAD.

3. The photodetector according to claim 1, wherein a plurality of the photodetectors are connected to the output destination switching unit.

4. Further provided between the plurality of photodetectors and the output destination switching unit is a switch unit that switches whether the signal is supplied to the counter via the output destination switching unit or each of the signals output from the plurality of photodetectors is supplied to each of the plurality of counters without passing through the output destination switching unit. The photodetector according to claim 3.

5. The photodetector according to claim 4, further comprising a control unit that controls the switching by the switch unit.

6. The photodetector according to claim 5, wherein the control unit controls the recharge current amount of the photodetector.

7. The photodetector according to claim 5, wherein the control unit controls the switching by the switch unit based on the count data generated based on the signal by the counter.

8. Further comprising a histogram builder that generates a histogram indicating the detection result of photons in the photodetector based on the count data, and the control unit controls the switching by the switch unit based on the histogram. The photodetector according to claim 7.

9. The photodetector according to claim 8, wherein the control unit controls the recharge current amount of the photodetector based on the histogram.

10. Further comprising a detection unit that generates a detection signal indicating that the signal has been supplied to the counter during the dead time period based on the signal supplied to the counter and a signal output from the internal circuit of the counter indicating whether it is the dead time period of the counter, and the control unit controls the switching by the switch unit based on the detection signal. The photodetector according to claim 5.

11. The photodetector according to claim 10, wherein the control unit controls the recharge current amount of the photodiode based on the detection signal.

12. The photodetector according to claim 5, further comprising: a first pixel array unit provided with a plurality of pixels each having the photodiode; and a second pixel array unit provided with a plurality of other pixels each having the other photodiode for controlling switching by the switch unit.

13. The photodetector according to claim 6, wherein the control unit controls switching by the switch unit and the recharge current amount of the photodiode at predetermined intervals.

14. The photodetector according to claim 4, further comprising a delay unit disposed between the output destination switching unit and the counter, for adjusting the supply timing of the signal supplied from the output destination switching unit to the counter.

Images