Semiconductor device, method for manufacturing semiconductor device, inverter device, and vehicle

Abstract

This semiconductor device comprises: a heat dissipation member; a base material that includes a heat dissipation layer that faces the heat dissipation member in a first direction; a first conductive layer that is positioned on the opposite side of the base material from the heat dissipation member, and that is joined to the base material; a first semiconductor element that is joined to the first conductive layer; and a joining layer that joins the heat dissipation member and the heat dissipation layer. The joining layer includes a sintered body of metal particles. The joining layer is provided with a void portion penetrating in the first direction.

Description

Semiconductor device, semiconductor device manufacturing method, inverter device, and vehicle

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, an inverter device including the semiconductor device, and a vehicle equipped with the semiconductor device.

[0002] Conventionally, semiconductor devices equipped with semiconductor elements (such as MOSFETs and IGBTs) having a switching function have been widely known and are mainly used for power conversion. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document includes a sealing resin that covers the semiconductor element, a heat dissipation member, and an attachment member. The attachment member is a leaf spring. The sealing resin is attached to the heat dissipation member via the attachment member. The sealing resin is sandwiched between the heat dissipation member and the attachment member.

[0003] In addition to the semiconductor device disclosed in Patent Document 1, there are also cases where a substrate is bonded to a heat dissipation member via a bonding layer. The substrate mounts a semiconductor element and is exposed from the sealing resin. The bonding layer is, for example, a sintered body containing metal particles. In this case, the bonding layer is formed by firing. As a result, shear stress caused by the heat of firing occurs at both the interface between the bonding layer and the heat dissipation member and the interface between the bonding layer and the substrate. If the shear stress becomes excessively concentrated, the substrate may peel off from the heat dissipation member when the bonding layer is cooled to room temperature. When such peeling occurs, a gap is formed between the heat dissipation member and the substrate, increasing thermal resistance. This raises concerns about a decrease in the heat dissipation performance of the semiconductor device.

[0004] International Publication No. 2023 / 047890

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress peeling of a substrate from a heat dissipation member.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a heat dissipation member, a base including a heat dissipation layer facing the heat dissipation member in a first direction, a first conductive layer located on the opposite side of the base from the heat dissipation member and bonded to the base, a first semiconductor element bonded to the first conductive layer, and a bonding layer bonding the heat dissipation member and the heat dissipation layer. The bonding layer includes a sintered body of metal particles. A void portion is provided in the bonding layer that penetrates in the first direction.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: a first step of bonding a first conductive layer to a substrate including a heat dissipation layer so that the first conductive layer is located on the opposite side of the substrate from the heat dissipation layer in a first direction; a second step of conductively bonding a first semiconductor element to the first conductive layer; a third step of arranging a bonding material on one side of either the heat dissipation member or the heat dissipation layer in the first direction; and a fourth step of sintering the bonding material to bond the heat dissipation member and the heat dissipation layer. The bonding material includes metal particles. In the third step, a void portion penetrating the first direction is provided in the bonding material.

[0008] A third aspect of the present disclosure provides an inverter device comprising: a heat dissipation member; a substrate including a heat dissipation layer facing the heat dissipation member in a first direction; first and second conductive layers located on the opposite side of the substrate from the heat dissipation member and bonded to the substrate; a first semiconductor element conductively bonded to the first conductive layer; a second semiconductor element conductively bonded to the second conductive layer; a first signal terminal electrically connected to the first semiconductor element; a second signal terminal electrically connected to the second semiconductor element; a wiring substrate individually connected to the first signal terminal and the second signal terminal; and a bonding layer bonding the heat dissipation member to the heat dissipation layer. The bonding layer includes a sintered body of metal particles. The bonding layer has a void portion penetrating in the first direction.

[0009] A fourth aspect of the present disclosure provides a vehicle including a drive source and a semiconductor device. The semiconductor device is electrically connected to the drive source. The semiconductor device further includes a second conductive layer and a second semiconductor element, in addition to the semiconductor device provided by the first aspect of the present disclosure. The second semiconductor element is electrically connected to the second conductive layer and is electrically connected to the first semiconductor element.

[0010] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view corresponding to FIG. 2, seen through the sealing resin. FIG. 4 is a partially enlarged view of FIG. 3. FIG. 5 is a plan view corresponding to FIG. 2, seen through the first conductive member, and omitting the sealing resin and the second conductive member. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a partially enlarged view of the first semiconductor element and its periphery shown in FIG. 9. FIG. 11 is a partially enlarged view of the second semiconductor element and its periphery shown in FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a bottom view corresponding to FIG. 7 , with the heat dissipation member omitted. FIG. 15 is a bottom view of a semiconductor device according to a first modified example of the first embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 16 is a bottom view of a semiconductor device according to a second modified example of the first embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 17 is a cross-sectional view illustrating a first step in the manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 18 is a cross-sectional view illustrating a second step in the manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 19 is a cross-sectional view illustrating a third step in the manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 20 is a cross-sectional view illustrating a fourth step in the manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 21 is a plan view of an inverter device including the semiconductor device shown in FIG. 1 . FIG. 22 is a partially enlarged view of FIG. 21 . FIG. 23 is a front view of the inverter device shown in FIG. 21 and corresponds to FIG. 22 . FIG. 24 is a partially enlarged cross-sectional view of the wiring board shown in FIG. 22 . FIG. 25 is a circuit block diagram of the inverter device shown in FIG. 21 . Fig. 26 is a partially enlarged view of Fig. 25. Fig. 27 is a circuit block diagram of each of a plurality of drive circuits which are elements of the circuit shown in Fig. 25. Fig. 28 is a schematic diagram of a vehicle equipped with the semiconductor device shown in Fig. 1. Fig. 29 is a bottom view of a semiconductor device according to a second embodiment of the present disclosure, with the heat dissipation member omitted. Fig. 30 is a bottom view of a semiconductor device according to a modified example of the second embodiment of the present disclosure, with the heat dissipation member omitted.31 is a bottom view of a semiconductor device according to a third embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 32 is a bottom view of a semiconductor device according to a modified example of the third embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 33 is a bottom view of a semiconductor device according to a fourth embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 34 is a bottom view of a semiconductor device according to a modified example of the fourth embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 35 is a bottom view of a semiconductor device according to a fifth embodiment of the present disclosure, with the heat dissipation member omitted. FIG. 36 is a cross-sectional view of the semiconductor device shown in FIG. 35 and corresponds to FIG. 9 .

[0012] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0013] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 14. The semiconductor device A10 includes a substrate 11, a first conductive layer 121, a second conductive layer 122, a first power terminal 13, two second power terminals 14, two third power terminals 15, a plurality of first semiconductor elements 21, a plurality of second semiconductor elements 22, a first conductive member 31, a second conductive member 32, a sealing resin 50, a heat dissipation member 71, and a bonding layer 72. The semiconductor device A10 further includes a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, two fifth signal terminals 181, two sixth signal terminals 182, a seventh signal terminal 19, two thermistors 23, a first wiring 61, and a second wiring 62. For ease of understanding, the sealing resin 50 is shown in perspective in Figures 3 and 4. In Fig. 3, the transmitted sealing resin 50 is indicated by an imaginary line (two-dot chain line). In Fig. 5, for ease of understanding, the first conductive member 31 is transmitted, and the second conductive member 32 and sealing resin 50 are not shown. In Fig. 14, for ease of understanding, the heat dissipation member 71 is not shown.

[0014] In the description of the semiconductor device A10, for convenience, for example, the normal direction to a first main surface 121A of a first conductive layer 121 (described later) will be referred to as the "first direction z." Furthermore, for example, the direction perpendicular to the first direction z will be referred to as the "second direction x." Furthermore, for example, the direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y."

[0015] The semiconductor device A10 converts DC power input to the first power terminal 13 and two second power terminals 14 into AC power using a plurality of first semiconductor elements 21 and a plurality of second semiconductor elements 22. The converted AC power is input from each of two third power terminals 15 to a power supply target (for example, a motor 89 described below).

[0016] As shown in FIGS. 9 to 11 , the substrate 11 is located on the opposite side of the first semiconductor elements 21 and the second semiconductor elements 22 in the first direction z, with the first conductive layer 121 and the second conductive layer 122 as references. The substrate 11 supports the first conductive layer 121 and the second conductive layer 122. In the semiconductor device A10, the substrate 11 is formed, for example, by active metal brazing (AMB). As shown in FIGS. 9 to 11 , the substrate 11 includes an insulating layer 111, two support layers 112, and a heat dissipation layer 113. The substrate 11 is covered with a sealing resin 50 except for a portion of the heat dissipation layer 113.

[0017] As shown in FIGS. 9 to 11 , the insulating layer 111 includes a portion interposed between the support layer 112 and the heat dissipation layer 113 in the first direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. For example, the insulating layer 111 is made of ceramics containing aluminum nitride (AlN). The insulating layer 111 may be made of an insulating resin sheet in addition to ceramics. The dimension of the insulating layer 111 in the first direction z is smaller than the dimension of each of the first conductive layer 121 and the second conductive layer 122 in the first direction z.

[0018] 9 to 11 , the two support layers 112 are located between the insulating layer 111 and the first and second conductive layers 121 and 122 in the first direction z. The support layers 112 are spaced apart from each other in the second direction x. The composition of the support layer 112 includes copper (Cu). As shown in FIG. 5 , the support layer 112 is located inward from the periphery of the insulating layer 111 when viewed in the first direction z.

[0019] 9 to 11 , the heat dissipation layer 113 is located on the opposite side of the insulating layer 111 from the two support layers 112 in the first direction z. As shown in FIG. 7 , the heat dissipation layer 113 is exposed from the sealing resin 50. The heat dissipation layer 113 contains copper. The dimension of the heat dissipation layer 113 in the first direction z is larger than the dimension of the insulating layer 111 in the first direction z. When viewed in the first direction z, the heat dissipation layer 113 is located inward from the periphery of the insulating layer 111.

[0020] As shown in FIGS. 9 to 11 , the first conductive layer 121 and the second conductive layer 122 are bonded to the substrate 11. The first conductive layer 121 and the second conductive layer 122 contain copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart from each other in the second direction x. As shown in FIGS. 8 and 9 , the first conductive layer 121 has a first main surface 121A facing the first direction z. The first main surface 121A faces the plurality of first semiconductor elements 21. As shown in FIG. 10 , the first conductive layer 121 is bonded to one of the two support layers 112 via a first bonding layer 129. The first bonding layer 129 is, for example, solder. As shown in FIGS. 8 and 9 , the second conductive layer 122 has a second main surface 122A facing the same side as the first main surface 121A in the first direction z. The second main surface 122A faces the plurality of second semiconductor elements 22. As shown in Fig. 11 , the second conductive layer 122 is bonded to the other of the two support layers 112 via a first bonding layer 129.

[0021] As shown in FIGS. 5 and 9 , the multiple first semiconductor elements 21 are bonded to the first main surface 121A of the first conductive layer 121. The multiple first semiconductor elements 21 are arranged along the third direction y. The multiple second semiconductor elements 22 are bonded to the second main surface 122A of the second conductive layer 122. The multiple second semiconductor elements 22 are arranged along the third direction y. The multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 may be switching elements such as insulated gate bipolar transistors (IGBTs). Furthermore, the multiple first semiconductor elements 21 may include multiple switching elements and multiple freewheeling diodes individually connected in parallel to these switching elements. Similarly, the second semiconductor elements 22 may also include a plurality of switching elements and a plurality of freewheeling diodes individually connected in parallel to the switching elements. The freewheeling diodes may be, for example, Schottky barrier diodes. In the description of the semiconductor device A10, the first semiconductor elements 21 and the second semiconductor elements 22 are n-channel MOSFETs with a vertical structure. The first semiconductor elements 21 and the second semiconductor elements 22 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0022] As shown in FIGS. 5 and 10, each of the plurality of first semiconductor elements 21 has a first electrode 211 , a second electrode 212 , a first gate electrode 213 and a first detection electrode 214 .

[0023] As shown in FIG. 10 , the first electrode 211 faces the first main surface 121A of the first conductive layer 121. A current corresponding to the power before conversion by the first semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the first semiconductor element 21. The first electrode 211 is conductively bonded to the first main surface 121A via a conductive bonding layer 29. As a result, the first electrode 211 of each of the multiple first semiconductor elements 21 is electrically connected to the first conductive layer 121. The conductive bonding layer 29 is a sintered body of metal particles containing silver (Ag) or the like. Alternatively, the conductive bonding layer 29 may be solder. Furthermore, the conductive bonding layer 29 may be a liquid metal.

[0024] 10 , the second electrode 212 is located on the opposite side of the first conductive layer 121 from the side facing the first main surface 121A in the first direction z. Therefore, the first electrode 211 and the second electrode 212 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the first semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the first semiconductor element 21.

[0025] 10 , the first gate electrode 213 is located on the opposite side of the first conductive layer 121 from the side facing the first main surface 121A in the first direction z. Therefore, the first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213. As shown in FIG. 5 , the area of ​​the first gate electrode 213 is smaller than the area of ​​the second electrode 212 when viewed in the first direction z.

[0026] 5 , the first detection electrode 214 is located on the same side as the second electrode 212 and the first gate electrode 213 in the first direction z. The first detection electrode 214 is located adjacent to the first gate electrode 213 in the third direction y. A voltage equivalent to the voltage applied to the second electrode 212 is applied to the first detection electrode 214. When viewed in the first direction z, the area of ​​the first detection electrode 214 is approximately equal to the area of ​​the first gate electrode 213.

[0027] As shown in FIGS. 5 and 11 , each of the plurality of second semiconductor elements 22 has a third electrode 221 , a fourth electrode 222 , a second gate electrode 223 and a second detection electrode 224 .

[0028] 11 , the third electrode 221 faces the second main surface 122A of the second conductive layer 122. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the third electrode 221. In other words, the third electrode 221 corresponds to the drain electrode of the second semiconductor element 22. The third electrode 221 is conductively bonded to the second main surface 122A via the conductive bonding layer 29. As a result, the third electrode 221 of each of the multiple second semiconductor elements 22 is electrically connected to the second conductive layer 122.

[0029] 11 , the fourth electrode 222 is located on the opposite side of the second conductive layer 122 from the side facing the second main surface 122A in the first direction z. Therefore, the third electrode 221 and the fourth electrode 222 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 flows through the fourth electrode 222. In other words, the fourth electrode 222 corresponds to the source electrode of the second semiconductor element 22.

[0030] 11 , the second gate electrode 223 is located on the opposite side of the second conductive layer 122 from the side facing the second main surface 122A in the first direction z. Therefore, the second gate electrode 223 is located on the same side as the fourth electrode 222 in the first direction z. A gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223. As shown in FIG. 5 , the area of ​​the second gate electrode 223 is smaller than the area of ​​the fourth electrode 222 when viewed in the first direction z.

[0031] 5 , the second detection electrode 224 is located on the same side as the fourth electrode 222 and the second gate electrode 223 in the first direction z. The second detection electrode 224 is located on both sides of the second gate electrode 223 in the third direction y. A voltage equivalent to the voltage applied to the fourth electrode 222 is applied to the second detection electrode 224. When viewed in the first direction z, the area of ​​the second detection electrode 224 is approximately equal to the area of ​​the second gate electrode 223.

[0032] As shown in FIGS. 3 and 9 , the first power terminal 13 is located on the opposite side of the second conductive layer 122 from the first conductive layer 121 in the second direction x. The first power terminal 13 is conductively bonded to the first conductive layer 121. This electrically connects the first power terminal 13 to the first electrodes 211 of the first semiconductor elements 21 via the first conductive layer 121. The first power terminal 13 is a P terminal (positive electrode) to which DC power to be converted is input. The first power terminal 13 extends from the first conductive layer 121 in the second direction x. The first power terminal 13 has a covering portion 131 and an exposed portion 132. As shown in FIG. 9 , the covering portion 131 is conductively bonded to the first conductive layer 121 and is covered with sealing resin 50. The exposed portion 132 extends from the covering portion 131 in the second direction x and is exposed to the outside from the sealing resin 50.

[0033] As shown in FIGS. 3 and 8 , each of the two second power terminals 14 is located on the same side as the first power terminal 13 in the second direction x with respect to the first conductive layer 121 and the second conductive layer 122, but is spaced apart from the first conductive layer 121 and the second conductive layer 122. Each of the two second power terminals 14 is electrically connected to the fourth electrodes 222 of the second semiconductor elements 22. The two second power terminals 14 are N terminals (negative electrodes) to which DC power to be converted is input. The second power terminals 14 are spaced apart from each other in the third direction y. The first power terminal 13 is located between the two second power terminals 14 in the third direction y. Each of the two second power terminals 14 has a covering portion 141 and an exposed portion 142. As shown in FIG. 8 , the covering portion 141 is spaced apart from the first conductive layer 121 and is covered with the sealing resin 50. The exposed portion 142 extends from the covered portion 141 in the second direction x and is exposed to the outside from the sealing resin 50 .

[0034] As shown in FIGS. 3 and 8 , each of the two third power terminals 15 is located on the opposite side of the first conductive layer 121 from the second conductive layer 122 in the second direction x. Each of the two third power terminals 15 is conductively bonded to the second conductive layer 122. This electrically connects each of the two third power terminals 15 to the third electrodes 221 of the second semiconductor elements 22 via the second conductive layer 122. AC power converted by the first semiconductor elements 21 and the second semiconductor elements 22 is output from each of the two third power terminals 15. In the semiconductor device A10, the two third power terminals 15 are spaced apart from each other in the third direction y. Each of the two third power terminals 15 includes a covering portion 151 and an exposed portion 152. As shown in FIG. 8 , the covering portion 151 is conductively bonded to the second conductive layer 122 and is covered with a sealing resin 50. The exposed portion 152 extends from the covered portion 151 in the second direction x and is exposed to the outside from the sealing resin 50 .

[0035] 10 , the first wiring 61 is bonded to the first main surface 121A of the first conductive layer 121. The first wiring 61 is located on the opposite side of the plurality of second semiconductor elements 22 with respect to the plurality of first semiconductor elements 21 in the second direction x. The first wiring 61 is electrically connected to the plurality of first semiconductor elements 21 and the first conductive layer 121. As shown in FIGS. 5 and 10 , the first wiring 61 has a first mounting layer 611, a first metal layer 612, two first gate wiring layers 613, a first detection wiring layer 614, a first temperature detection wiring layer 615, and a second detection wiring layer 616.

[0036] 5 , the first mounting layer 611 includes two first gate wiring layers 613, a first detection wiring layer 614, two first temperature detection wiring layers 615, and a second detection wiring layer 616. The first mounting layer 611 is an insulator. The first mounting layer 611 is made of, for example, ceramics. Alternatively, the first mounting layer 611 may be made of an insulating resin sheet.

[0037] 10 , the first metal layer 612 is located on a side facing the first main surface 121A of the first conductive layer 121 in the first direction z, with the first mounting layer 611 as a reference. The first metal layer 612 is bonded to the first mounting layer 611. The first metal layer 612 contains copper. The first metal layer 612 is bonded to the first main surface 121A via a second bonding layer 68. The second bonding layer 68 is, for example, solder.

[0038] 5 and 10 , the two first gate wiring layers 613 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first gate wiring layers 613 are bonded to the first mounting layer 611. Of the two first gate wiring layers 613, one of the first gate wiring layers 613 is conductively bonded to a plurality of first wires 41. The plurality of first wires 41 are individually conductively bonded to the first gate electrodes 213 of the plurality of first semiconductor elements 21. Furthermore, a plurality of sixth wires 46 are conductively bonded to each of the two first gate wiring layers 613. As a result, each of the two first gate wiring layers 613 is electrically connected to the first gate electrodes 213 of the plurality of first semiconductor elements 21.

[0039] 5 and 10 , the first detection wiring layer 614 is located on the opposite side of the first mounting layer 611 from the first metal layer 612. The first detection wiring layer 614 is bonded to the first mounting layer 611. A plurality of second wires 42 are conductively bonded to the first detection wiring layer 614. Furthermore, the plurality of second wires 42 are individually conductively bonded to the first detection electrodes 214 of the plurality of first semiconductor elements 21. As a result, the first detection wiring layer 614 is electrically connected to the first detection electrodes 214 of the plurality of first semiconductor elements 21.

[0040] 5 , the two first temperature detection wiring layers 615 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first temperature detection wiring layers 615 are bonded to the first mounting layer 611. The two first temperature detection wiring layers 615 are adjacent to each other in the third direction y.

[0041] 5 , the second detection wiring layer 616 is located on the opposite side of the first metal layer 612 with respect to the first mounting layer 611. The second detection wiring layer 616 is bonded to the first mounting layer 611. A third wire 43 is conductively bonded to the second detection wiring layer 616. The third wire 43 is further conductively bonded to the first main surface 121A of the first conductive layer 121. This provides electrical continuity between the second detection wiring layer 616 and the first conductive layer 121.

[0042] 11 , the second wiring 62 is bonded to the second main surface 122A of the second conductive layer 122. The second wiring 62 is located on the opposite side of the second semiconductor elements 22 from the first semiconductor elements 21 in the second direction x. The second wiring 62 is electrically connected to the second semiconductor elements 22 and the second conductive layer 122. As shown in FIGS. 5 and 11 , the second wiring 62 includes a second mounting layer 621, a second metal layer 622, two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626.

[0043] 5 , the second mounting layer 621 includes two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626. The second mounting layer 621 is an insulator. The second mounting layer 621 is made of, for example, ceramics. Alternatively, the second mounting layer 621 may be made of an insulating resin sheet.

[0044] 11 , the second metal layer 622 is located on a side facing the second main surface 122A of the second conductive layer 122 with the second mounting layer 621 as a reference in the first direction z. The second metal layer 622 is bonded to the second mounting layer 621. The second metal layer 622 contains copper. The second metal layer 622 is bonded to the second main surface 122A via a second bonding layer 68.

[0045] 5 and 11 , the two second gate wiring layers 623 are located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The two second gate wiring layers 623 are bonded to the second mounting layer 621. A plurality of fourth wires 44 are conductively bonded to one of the two second gate wiring layers 623. The plurality of fourth wires 44 are individually conductively bonded to the second gate electrodes 223 of the second semiconductor elements 22. Furthermore, a plurality of seventh wires 47 are conductively bonded to each of the two second gate wiring layers 623. As a result, each of the two second gate wiring layers 623 is electrically connected to the second gate electrodes 223 of the second semiconductor elements 22.

[0046] 5 and 11 , the third detection wiring layer 624 is located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The third detection wiring layer 624 is bonded to the second mounting layer 621. A plurality of fifth wires 45 are conductively bonded to the third detection wiring layer 624. Furthermore, the plurality of fifth wires 45 are individually conductively bonded to the second detection electrodes 224 of the plurality of second semiconductor elements 22. As a result, the third detection wiring layer 624 is electrically connected to the second detection electrodes 224 of the plurality of second semiconductor elements 22.

[0047] 5 , the two second temperature detection wiring layers 625 are located on the opposite side of the second mounting layer 621 from the second metal layer 622. The two second temperature detection wiring layers 625 are bonded to the second mounting layer 621. The two second temperature detection wiring layers 625 are adjacent to each other in the third direction y.

[0048] 5, the fourth detection wiring layer 626 is located on the opposite side of the second mounting layer 621 from the second metal layer 622. The fourth detection wiring layer 626 is bonded to the second mounting layer 621.

[0049] As shown in FIGS. 10 and 11 , each of the multiple sleeves 63 is conductively bonded to either the first wiring 61 or the second wiring 62 via a third bonding layer 69. The third bonding layer 69 is, for example, solder. The multiple sleeves 63 are made of a conductive material such as metal. Each of the multiple sleeves 63 has a cylindrical shape extending in the first direction z. As shown in FIGS. 2 and 9 , each of the multiple sleeves 63 has an end surface 631 that faces the same side as the first main surface 121A of the first conductive layer 121 in the first direction z. The end surface 631 is exposed to the outside from a top surface 51 of the sealing resin 50, which will be described later.

[0050] 4, one of the two thermistors 23 is conductively joined to two first temperature detection wiring layers 615 of the first wiring 61. As shown in FIG. 4, the other of the two thermistors 23 is conductively joined to two second temperature detection wiring layers 625 of the second wiring 62. The two thermistors 23 are used as temperature detection sensors for the semiconductor device A10.

[0051] As shown in FIG. 1 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are formed as metal pins extending in the first direction z. These terminals protrude from a top surface 51 of a sealing resin 50 (described later). Furthermore, these terminals are individually press-fitted into a plurality of sleeves 63. As a result, each of these terminals is supported by one of the plurality of sleeves 63 and is electrically connected to one of the first wiring 61 and the second wiring 62.

[0052] 5 and 10 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two first gate wiring layers 613 of the first wiring 61. This allows the first signal terminal 161 to be electrically connected to the first gate electrodes 213 of the multiple first semiconductor elements 21 via the two first gate wiring layers 613. A gate voltage for driving the multiple first semiconductor elements 21 is applied to the first signal terminal 161.

[0053] 5 and 11 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two second gate wiring layers 623 of the second wiring 62. This allows the second signal terminal 162 to be electrically connected to the second gate electrodes 223 of the multiple second semiconductor elements 22 via the two second gate wiring layers 623. A gate voltage for driving the multiple second semiconductor elements 22 is applied to the second signal terminal 162.

[0054] As shown in Fig. 2 , the third signal terminal 171 is located adjacent to the first signal terminal 161 in the third direction y. As shown in Fig. 5 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the first detection wiring layer 614 of the first wiring 61. This allows the third signal terminal 171 to be electrically connected to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 via the first detection wiring layer 614. A voltage equivalent to the voltage applied to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 is applied to the third signal terminal 171.

[0055] As shown in Fig. 2 , the fourth signal terminal 172 is located adjacent to the second signal terminal 162 in the third direction y. As shown in Fig. 5 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the third detection wiring layer 624 of the second wiring 62. This allows the fourth signal terminal 172 to be electrically connected to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 via the third detection wiring layer 624. A voltage equivalent to the voltage applied to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 is applied to the fourth signal terminal 172.

[0056] As shown in Fig. 2 , the two fifth signal terminals 181 are located on the opposite side of the first signal terminal 161 from the third signal terminal 171 in the third direction y. The two fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in Fig. 5 , the two fifth signal terminals 181 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two first temperature detection wiring layers 615 of the first wiring 61. As a result, the two fifth signal terminals 181 are electrically connected to the two thermistors 23 that are conductively joined to the two first temperature detection wiring layers 615 of the two thermistors 23.

[0057] As shown in Fig. 2 , the two sixth signal terminals 182 are located on the opposite side of the second signal terminal 162 from the fourth signal terminal 172 in the third direction y. The two sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in Fig. 5 , the two sixth signal terminals 182 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two second temperature detection wiring layers 625 of the second wiring 62. As a result, the two sixth signal terminals 182 are electrically connected to the two thermistors 23 that are conductively joined to the two second temperature detection wiring layers 625 of the two thermistors 23.

[0058] As shown in Fig. 2 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 161 in the third direction y with respect to the third signal terminal 171. As shown in Fig. 5 , the seventh signal terminal 19 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the second detection wiring layer 616 of the first wiring 61. This provides electrical continuity between the seventh signal terminal 19 and the first conductive layer 121 via the second detection wiring layer 616. A voltage equivalent to the DC power input to the first power terminal 13 and the two second power terminals 14 is applied to the seventh signal terminal 19.

[0059] As shown in FIGS. 5 and 10 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the plurality of first semiconductor elements 21 and the second main surface 122A of the second conductive layer 122. As a result, the second electrodes 212 of the plurality of first semiconductor elements 21 are electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in FIG. 5 , the first conductive member 31 has a first main portion 311, a plurality of first bonding portions 312, a plurality of first connecting portions 313, a plurality of second bonding portions 314, and a plurality of second connecting portions 315.

[0060] The first main portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 5 , the first main portion 311 extends in the third direction y. As shown in Fig. 9 , the first main portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0061] 10 , the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first semiconductor elements 21. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first semiconductor elements 21.

[0062] 5 , the plurality of first connecting portions 313 are connected to the first main portion 311 and the plurality of first bonding portions 312. The plurality of first connecting portions 313 are spaced apart from one another in the third direction y. As shown in FIG. 9 , when viewed in the third direction y, the plurality of first connecting portions 313 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they extend from the plurality of first bonding portions 312 toward the first main portion 311.

[0063] 5 and 9 , the second bonding portions 314 are bonded to the second main surface 122A of the second conductive layer 122. The second bonding portions 314 face the second main surface 122A. The second bonding portions 314 extend in the third direction y.

[0064] 5 and 9 , the plurality of second connecting portions 315 are connected to the first main portion 311 and the plurality of second bonding portions 314. When viewed in the third direction y, the plurality of second connecting portions 315 are inclined in a direction away from the second main surface 122A of the second conductive layer 122 as they extend from the plurality of second bonding portions 314 toward the first main portion 311.

[0065] 9 , 10 , and 13 , a conductive bonding layer 29 is located between the second electrode 212 of each of the multiple first semiconductor elements 21 and each of the multiple first bonding portions 312. The conductive bonding layer 29 electrically conductively bonds each of the multiple first bonding portions 312 to the second electrode 212 of each of the multiple first semiconductor elements 21. As shown in FIG. 9 , the conductive bonding layer 29 is located between the second main surface 122A of the second conductive layer 122 and the second bonding portion 314. The conductive bonding layer 29 electrically conductively bonds the second main surface 122A to the second bonding portion 314.

[0066] As shown in FIGS. 4 and 11 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second semiconductor elements 22 and the covering portion 141 of the second power terminal 14. As a result, the second electrodes 212 of the plurality of second semiconductor elements 22 are electrically connected to the second power terminal 14. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIG. 4 , the second conductive member 32 has two second main portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, two fourth joint portions 324, two fourth connecting portions 325, a plurality of intermediate portions 326, and a plurality of cross beam portions 327.

[0067] As shown in Fig. 4, the two second main portions 321 are spaced apart from each other in the third direction y. The two second main portions 321 extend in the second direction x. As shown in Fig. 8, the two second main portions 321 are arranged parallel to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. The two second main portions 321 are spaced apart from the first main surface 121A and the second main surface 122A more than the first main portion 311 of the first conductive member 31.

[0068] 4 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the two second main portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x is smaller than the dimension of each of the two second main portions 321 in the second direction x.

[0069] 11 , the multiple third bonding portions 322 are individually bonded to the second electrodes 212 of the multiple second semiconductor elements 22. Each of the multiple third bonding portions 322 faces the fourth electrode 222 of one of the multiple second semiconductor elements 22.

[0070] 4 and 12 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either one of the two second main portions 321 and the multiple intermediate portions 326. When viewed in the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it moves from either one of the multiple third joint portions 322 toward either one of the two second main portions 321 or the multiple intermediate portions 326.

[0071] 4 and 8 , the two fourth joint portions 324 are joined to the covering portion 141 of the second power terminal 14. The two fourth joint portions 324 face the covering portion 141.

[0072] 4 and 8 , the two fourth connecting portions 325 are connected to the two second main portions 321 and the two fourth joint portions 324. When viewed in the third direction y, the two fourth connecting portions 325 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they move from the two fourth joint portions 324 toward the two second main portions 321.

[0073] As shown in FIGS. 4 and 13 , the multiple cross beam portions 327 are arranged along the third direction y. As viewed in the first direction z, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. Of the multiple cross beam portions 327, the cross beam portion 327 located at the center in the third direction y is connected to the multiple intermediate portions 326 on both sides in the third direction y. Of the multiple cross beam portions 327, the remaining two cross beam portions 327 are connected to one of the two second main portions 321 and one of the multiple intermediate portions 326 on both sides in the third direction y. As viewed in the second direction x, the multiple cross beam portions 327 are convex in the first direction z toward the first main surface 121A of the first conductive layer 121.

[0074] 9 , 11 , and 12 , a conductive bonding layer 29 is located between each of the fourth electrodes 222 of the multiple second semiconductor elements 22 and each of the multiple third bonding portions 322. The conductive bonding layer 29 conductively bonds each of the multiple third bonding portions 322 to each of the multiple second semiconductor elements 22. As shown in FIG. 8 , a conductive bonding layer 29 is located between each of the covering portions 141 of the two second power terminals 14 and the two fourth bonding portions 324. The conductive bonding layer 29 conductively bonds each of the covering portions 141 of the two second power terminals 14 to each of the two fourth bonding portions 324.

[0075] As shown in FIGS. 8 , 9 , 12 , and 13 , the sealing resin 50 covers the first conductive layer 121, the second conductive layer 122, the plurality of first semiconductor elements 21, the plurality of second semiconductor elements 22, the first conductive member 31, and the second conductive member 32. The sealing resin 50 also covers a portion of each of the substrate 11, the first power terminal 13, the third power terminal 15, and the second power terminal 14. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, a black epoxy resin. As shown in FIGS. 2 and 6 to 9 , the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and two recesses 55.

[0076] 8 and 9 , top surface 51 faces the same side as first main surface 121A of first conductive layer 121 in first direction z. As shown in Fig. 8 and 9 , bottom surface 52 faces the opposite side from top surface 51 in first direction z. As shown in Fig. 7 , heat dissipation layer 113 of base material 11 is exposed from bottom surface 52.

[0077] 2 and 6 , the first side surface 53 and the second side surface 54 are spaced apart from each other in the second direction x. The first side surface 53 and the second side surface 54 face opposite each other in the second direction x. The exposed portion 132 of the first power terminal 13 and the exposed portion 142 of each of the two second power terminals 14 are exposed to the outside from the first side surface 53. The exposed portion 152 of each of the two third power terminals 15 are exposed to the outside from the second side surface 54.

[0078] 2 and 7 , the two recesses 55 are recessed from the first side surface 53 in the second direction x. The two recesses 55 extend from the top surface 51 to the bottom surface 52 in the first direction z. The two recesses 55 are located on both sides of the first power terminal 13 in the third direction y.

[0079] The heat dissipation member 71 is used to cool the semiconductor device A10. The heat dissipation member 71 contains metal. For example, the heat dissipation member 71 is made of a material containing aluminum (Al).

[0080] As shown in FIGS. 6 and 7 , the heat dissipation member 71 has a base 711 and a heat dissipation portion 712. The base 711 is flat. The base 711 faces the heat dissipation layer 113 of the substrate 11 in the first direction z. As shown in FIG. 2 , the sealing resin 50 is located inward from the periphery of the base 711 when viewed in the first direction z. The heat dissipation portion 712 is connected to the base 711. The heat dissipation portion 712 is located on the opposite side of the substrate 11 from the base 711 in the first direction z. The heat dissipation portion 712 protrudes from the base 711. In the semiconductor device A10, the heat dissipation portion 712 is rectangular. Alternatively, the heat dissipation portion 712 may be a plurality of fins arranged in a direction perpendicular to the first direction z. As shown in FIG. 6 , the heat dissipation portion 712 is located inward from the periphery of the sealing resin 50 when viewed in the first direction z.

[0081] 8 to 13, the bonding layer 72 bonds the base 711 of the heat dissipation member 71 to the heat dissipation layer 113 of the substrate 11. The bonding layer 72 includes a sintered body of metal particles. The metal particles include silver. Alternatively, the metal particles may include copper.

[0082] As shown in FIGS. 10 , 11 , and 14 , the bonding layer 72 has a void 73 penetrating in the first direction z. The void 73 is exposed to the outside of the semiconductor device A10. As shown in FIG. 14 , as viewed in the first direction z, the heat dissipation layer 113 of the base material 11 has a first edge 113A and a second edge 113B. The first edge 113A extends in the second direction x. The second edge 113B extends in a direction perpendicular to the first direction z and in a direction different from the second direction x. As viewed in the first direction z, the first edge 113A or its extension and the second edge 113B or its extension intersect at a first intersection P1. As viewed in the first direction z, the void 73 includes a portion located between the first intersection P1 and the bonding layer 72.

[0083] As shown in FIG. 14 , the bonding layer 72 includes a first bonding portion 721, a second bonding portion 722, and a third bonding portion 723 that are spaced apart in a direction perpendicular to the first direction z. Thus, the bonding layer 72 includes a plurality of regions that are spaced apart from one another. A gap 73 is provided between two adjacent regions among the plurality of regions that are spaced apart from one another. Alternatively, the bonding layer 72 may be a single region as long as the gap 73 is provided. The first bonding portion 721 and the second bonding portion 722 are spaced apart from one another in the second direction x and adjacent to one another. The third bonding portion 723 is spaced apart from the first bonding portion 721 and the second bonding portion 722 in a direction perpendicular to the first direction z. When viewed in the first direction z, the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 have the same area. When viewed in the first direction z, each of the first joint portion 721, the second joint portion 722, and the third joint portion 723 has a circular shape.

[0084] 14 , the third joint 723 is located adjacent to the first joint 721 and the second joint 722 in a direction perpendicular to the first direction z. When viewed in the first direction z, a virtual line passing through the center C0 of the third joint 723 and extending in the third direction y overlaps with the gap 73 located between the first joint 721 and the second joint 722.

[0085] Next, a semiconductor device A11 according to a first modification of the first embodiment of the present disclosure will be described with reference to Fig. 15. Fig. 15 corresponds to Fig. 14 showing the semiconductor device A10. In the semiconductor device A11, the configuration of the bonding layer 72 is different from that of the semiconductor device A10.

[0086] 15 , the third bonding portion 723 is located adjacent to the first bonding portion 721 in the third direction y. When viewed in the first direction z, an imaginary line passing through the center C0 of the third bonding portion 723 and extending in the third direction y overlaps the first bonding portion 721. In the semiconductor device A11, the multiple regions that make up the bonding layer 72 are arranged in a lattice pattern.

[0087] Next, a semiconductor device A12 according to a second modification of the first embodiment of the present disclosure will be described with reference to Fig. 16. Fig. 16 corresponds to Fig. 14 showing the semiconductor device A10. In the semiconductor device A12, the configuration of the bonding layer 72 is different from that of the semiconductor device A10.

[0088] 16 , as viewed in the first direction z, each of the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 is rectangular. The third bonding portion 723 is located adjacent to the first bonding portion 721 in the third direction y. As viewed in the first direction z, each of the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 has a larger area than each of the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 in the semiconductor device A10.

[0089] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 17 to 20. Figures 17 to 20 correspond to Figure 9 showing the semiconductor device A10.

[0090] First, the first step S1 shown in FIG. 17 is performed. In the first step S1, a first conductive layer 121 and a second conductive layer 122 are bonded to the base material 11, which includes the heat dissipation layer 113, so as to be located on the opposite side of the base material 11 from the heat dissipation layer 113 in the first direction z. The first conductive layer 121 and the second conductive layer 122 are individually bonded to the two support layers 112 of the base material 11 via first bonding layers 129. Furthermore, in the first step S1, the first power terminal 13 is conductively bonded to the first conductive layer 121 by laser welding. At the same time, two third power terminals 15 are conductively bonded to the second conductive layer 122 by laser welding.

[0091] Next, the second step S2 shown in FIG. 18 is performed. In the second step S2, a plurality of first semiconductor elements 21 are conductively bonded to the first conductive layer 121 via the conductive bonding layer 29. At the same time, a plurality of second semiconductor elements 22 are conductively bonded to the second conductive layer 122 via the conductive bonding layer 29. Thereafter, a first conductive member 31 is conductively bonded to the plurality of first semiconductor elements 21 and the second conductive layer 122. Thereafter, two second power terminals 14 are arranged, and the second conductive member 32 is conductively bonded to the plurality of second semiconductor elements 22 and the two second power terminals 14. Thereafter, a first wiring 61 is bonded to the first conductive layer 121. At the same time, a second wiring 62 is bonded to the second conductive layer 122. Thereafter, a sealing resin 50 is formed to cover the first conductive layer 121, the second conductive layer 122, the plurality of first semiconductor elements 21, the plurality of second semiconductor elements 22, the first conductive members 31, and the second conductive members 32. The sealing resin 50 is formed by transfer molding. When forming the sealing resin 50, the heat dissipation layer 113 of the base material 11 and the end faces 631 of each of the plurality of sleeves 63 are exposed from the sealing resin 50.

[0092] Next, a third step S3 shown in FIG. 19 is performed. In the third step S3, a bonding material 79 is disposed on one side in the first direction z of either the base 711 of the heat dissipation member 71 or the heat dissipation layer 113 of the substrate 11. In this step, the bonding material 79 is disposed on one side in the first direction z of the base 711. The bonding material 79 is a paste containing metal particles and a solvent. The metal particles include silver. The bonding material 79 is disposed on the base 711 by a dispenser or screen printing. In the third step S3, a void 73 penetrating in the first direction z is provided in the bonding material 79. In the third step S3, the bonding material 79 is disposed so as to include a first portion 791 and a second portion 792 that are separated from each other in a direction perpendicular to the first direction z. Furthermore, in the third step S3, the void 73 is provided so as to be exposed to the outside in a direction perpendicular to the first direction z. After the bonding material 79 is placed on the base 711, the bonding material 79 is dried to remove the solvent contained in the bonding material 79.

[0093] 20 is performed. In the fourth step S4, the bonding material 79 is baked to bond the heat dissipation member 71 and the heat dissipation layer 113 of the base material 11. The bonding material 79 baked in the fourth step S4 becomes the bonding layer 72 of the semiconductor device A10.

[0094] Finally, the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are each press-fitted individually into the multiple sleeves 63. Through the above steps, the semiconductor device A10 is obtained.

[0095] 21 to 27, an inverter device B including the semiconductor device A10 will be described. The inverter device B includes three semiconductor devices A10, a wiring board 81, and a plurality of support members 82. The inverter device B is used to drive a motor 89, which will be described later.

[0096] First, the configuration of the inverter device B will be described with reference to Figures 21 to 24. As shown in Figure 21, three semiconductor devices A10 are arranged along the third direction y on a base 711 of a heat dissipation member 71. In the inverter device B, the heat dissipation members 71 of the three semiconductor devices A10 are integrated. The heat dissipation layer 113 of each of the three semiconductor devices A10 is bonded to the base 711 via a bonding layer 72.

[0097] The wiring board 81 is individually electrically connected to the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 of each of the three semiconductor devices A10. As shown in Figures 22 and 23 , the wiring board 81 faces the top surface 51 of the sealing resin 50 of each of the three semiconductor devices A10.

[0098] As shown in FIG. 24 , the wiring board 81 has a substrate 811, main wiring 812, rear wiring 813, and internal wiring 814. The substrate 811 has a plurality of through holes 811A penetrating in the first direction z. The main wiring 812 is arranged on the opposite side of the substrate 811 from the sealing resin 50 of each of the three semiconductor devices A10 in the first direction z. The rear wiring 813 is arranged on the opposite side of the substrate 811 from the main wiring 812. The internal wiring 814 is arranged in the plurality of through holes 811A. The internal wiring 814 is connected to the main wiring 812 and the rear wiring 813. The main wiring 812 forms a conductive path between the internal wiring 814 and a control circuit 83 and a plurality of drive circuits 84 provided on the wiring board 81. Details of the control circuit 83 and the plurality of drive circuits 84 will be described later.

[0099] 24 , the first signal terminal 161 of each of the three semiconductor devices A10 has a base 161A and a bulge 161B. One side of the base 161A in the first direction z is press-fitted into one of the multiple sleeves 63 of each of the three semiconductor devices A10. The bulge 161B is provided on the other side of the base 161A in the first direction z. The bulge 161B bulges in a direction perpendicular to the first direction z.

[0100] As shown in FIG. 22 , the first signal terminal 161 of each of the three semiconductor devices A10 is press-fitted into one of the multiple through-holes 811A. As a result, as shown in FIG. 24 , the internal wiring 814 arranged in one of the multiple through-holes 811A is press-contacted with the bulging portion 161B of the first signal terminal 161. This allows the first signal terminal 161 to be electrically connected to the wiring board 81. The second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 of each of the three semiconductor devices A10 also have a configuration similar to the base portion 161A and the bulging portion 161B of the first signal terminal 161. Therefore, these signal terminals are press-fitted into one of the multiple through-holes 811A, allowing them to be electrically connected to the wiring board 81. This configuration allows the inverter device B to be made more compact.

[0101] 23 , the multiple support members 82 are located between the base 711 of the heat dissipation member 71 and the wiring board 81 in the first direction z. The wiring board 81 is supported by the multiple support members 82. The multiple support members 82 are columnar.

[0102] Next, the circuit of the inverter device B will be described with reference to Figures 25 and 26. A control circuit 83, which is electrically connected to the main wiring 812, and a plurality of drive circuits 84 are provided on a wiring board 81. The control circuit 83 is a microcomputer including a CPU (Central Processing Unit) and a memory. The control circuit 83 is electrically connected to the plurality of drive circuits 84 and is connected to the outside. The control circuit 83 generates control signals for driving the plurality of drive circuits 84 based on input signals from the outside. The control signals are generated, for example, based on PWM (Pulse Width Modulation) control. The generated control signals are output individually to the plurality of drive circuits 84.

[0103] Each of the plurality of drive circuits 84 generates a drive signal for driving one of the three semiconductor devices A10 based on a control signal input from the control circuit 83. The generated drive signal is output to either a first signal terminal 161 or a second signal terminal 162 of each of the three semiconductor devices A10.

[0104] As shown in FIG. 25 , the multiple drive circuits 84 include three first drive circuits 84A and three second drive circuits 84B. As shown in FIG. 26 , each of the three first drive circuits 84A drives a plurality of first semiconductor elements 21 of one of the three semiconductor devices A10. Each of the three first drive circuits 84A is individually connected to the first signal terminal 161 and the third signal terminal 171 of one of the three semiconductor devices A10. As shown in FIG. 26 , each of the three second drive circuits 84B drives a plurality of second semiconductor elements 22 of one of the three semiconductor devices A10. Each of the three second drive circuits 84B is individually connected to the second signal terminal 162 and the fourth signal terminal 172 of one of the three semiconductor devices A10.

[0105] 25 , the first power terminal 13 of each of the three semiconductor devices A10 is electrically connected to the positive electrode of a DC power supply 88. The two second power terminals 14 of each of the three semiconductor devices A10 are electrically connected to the negative electrode of the DC power supply 88. This allows DC power to be input to each of the three semiconductor devices A10. Then, the multiple drive circuits 84 drive the multiple first semiconductor elements 21 and multiple second semiconductor elements 22 of each of the three semiconductor devices A10, thereby outputting three-phase AC power corresponding to the U phase, V phase, and W phase, respectively, from the two third power terminals 15 of each of the three semiconductor devices A10.

[0106] 25 , a motor 89 is electrically connected to the two third power terminals 15 of each of the three semiconductor devices A10. The motor 89 is, for example, a three-phase induction motor. Three-phase AC power is input to the motor 89, which is output from the two third power terminals 15 of each of the three semiconductor devices A10. This drives the motor 89.

[0107] 27, each of the plurality of drive circuits 84 will be described. Each of the plurality of drive circuits 84 includes an amplifier circuit 841, a first switch circuit 842, a gate resistor 843, a second switch circuit 844, a current cut-off resistor 845, and an overcurrent detection circuit 846.

[0108] A control signal from the control circuit 83 is input to the amplifier circuit 841. The amplifier circuit 841 amplifies the control signal and generates a drive signal for driving one of the three semiconductor devices A10. The first switch circuit 842 has terminals a, b, and c. Terminals a and b are input sides. Terminal c is output side. In the first switch circuit 842, terminal c is connected to either terminal a or terminal b. Terminal a is connected to the amplifier circuit 841. Terminal b is electrically open. Terminal c is electrically connected to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10 via a gate resistor 843.

[0109] The second switch circuit 844 has terminals d, e, and f. Terminal d is the input side. Terminals e and f are the output side. In the second switch circuit 844, terminal d is connected to either terminal e or terminal f. Terminal d is electrically connected to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10 via a current blocking resistor 845. In each of the multiple drive circuits 84, the gate resistor 843 and the current blocking resistor 845 are connected in parallel to each other with respect to the first signal terminal 161 or the second signal terminal 162 of one of the three semiconductor devices A10. Terminal e is electrically open. Terminal f is grounded. The resistance value r2 of the current blocking resistor 845 is greater than the resistance value r1 of the gate resistor 843.

[0110] The overcurrent detection circuit 846 controls the first switch circuit 842 and the second switch circuit 844. The overcurrent detection circuit 846 includes a current detection resistor 846A and a comparison circuit 846B. One end of the current detection resistor 846A is electrically connected to the third signal terminal 171 or the fourth signal terminal 172 of one of the three semiconductor devices A10. The other end of the current detection resistor 846A is grounded. The voltage across the terminals of the current detection resistor 846A (voltage drop amount) corresponds to the drain-source voltage of each of the multiple first semiconductor elements 21 of one of the three semiconductor devices A10, or the drain-source voltage of each of the multiple second semiconductor elements 22 of one of the three semiconductor devices A10. The voltage across the terminals of the current detection resistor 846A is applied to the comparison circuit 846B. The comparison circuit 846B compares the voltage across the current detection resistor 846A with a reference voltage V to determine whether the first semiconductor elements 21 or the second semiconductor elements 22 of any of the three semiconductor devices A10 are in an overcurrent state. The comparison circuit 846B outputs a determination signal representing the result of the determination. Specifically, when the voltage across the current detection resistor 846A is greater than the reference voltage V, it determines that an overcurrent state exists.

[0111] When there is no overcurrent state (normal state), the terminal d of the second switch circuit 844 is connected to the terminal e. This sets the impedance of the terminal d of the second switch circuit 844 to a sufficiently high state. At the same time, the terminal c of the first switch circuit 842 is connected to the terminal a. This causes the drive signal generated by the amplifier circuit 841 to be output to the first signal terminal 161 or the second signal terminal 162 of any of the three semiconductor devices A10 via the gate resistor 843.

[0112] On the other hand, in an overcurrent state, the terminal c of the first switch circuit 842 is connected to the terminal b. This causes the impedance of the terminal c of the first switch circuit 842 to be sufficiently high. At the same time, the terminal d of the second switch circuit 844 is connected to the terminal f. This causes the terminal d to be grounded.

[0113] Therefore, in an overcurrent state, the first signal terminal 161 or the second signal terminal 162 of any of the three semiconductor devices A10 is grounded via the current-blocking resistor 845. This reduces the gate-source voltage of each of the multiple first semiconductor elements 21 of any of the three semiconductor devices A10, or the gate-source voltage of each of the multiple second semiconductor elements 22 of any of the three semiconductor devices A10. Furthermore, the drain-source short-circuit current (hereinafter referred to as "short-circuit current") of each of the multiple first semiconductor elements 21 of any of the three semiconductor devices A10, or the short-circuit current of each of the multiple second semiconductor elements 22 of any of the three semiconductor devices A10, is blocked. This allows the multiple drive circuits 84 to protect the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 from overcurrent. The blocking speed of the short-circuit current varies depending on the resistance value r2 of the current-blocking resistor 845. The larger the resistance value r2, the slower the blocking speed of the short-circuit current.

[0114] Here, if the short-circuit current exceeds the short-circuit resistance of each of the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22, the first semiconductor element 21 or the second semiconductor element 22 may be destroyed before the overcurrent protection by the plurality of drive circuits 84 is completed. Therefore, for example, a measure may be taken to provide an internal resistance between the second electrode 212 and the first detection electrode 214 inside each of the plurality of first semiconductor elements 21. This allows the internal resistance to reduce the gate-source voltage when a short-circuit current flows, thereby more reliably preventing the first semiconductor element 21 or the second semiconductor element 22 from being destroyed.

[0115] Next, a vehicle C equipped with the semiconductor device A10 will be described with reference to Fig. 28. The vehicle C is, for example, an electric vehicle (EV).

[0116] As shown in Fig. 28, vehicle C includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0117] The drive system 93 drives the vehicle C. The drive system 93 includes an inverter 931 and a drive source 932. The semiconductor device A10 constitutes part of the inverter 931. Alternatively, the inverter device B described above may be used as the configuration of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. Alternatively, unlike the power system shown in FIG. 28 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931, including the semiconductor device A10, is electrically connected to the drive source 932. The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of vehicle C. This drives vehicle C. To drive vehicle C, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, semiconductor device A10 in inverter 931 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotational speed of the AC motor.

[0118] Next, the effects of the semiconductor device A10 will be described.

[0119] The semiconductor device A10 includes a heat dissipation member 71, a base material 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding layer 72. The base material 11 faces the heat dissipation member 71 in the first direction z. The bonding layer 72 bonds the heat dissipation member 71 to the heat dissipation layer 113. The bonding layer 72 includes a sintered body of metal particles. The bonding layer 72 has a void 73 penetrating it in the first direction z. During the fourth step S4 of the manufacturing process of the semiconductor device A10, when the bonding layer 72 is formed by firing the bonding material 79, shear stress due to the heat of firing is generated at both the interface between the bonding layer 72 and the heat dissipation member 71 and the interface between the bonding layer 72 and the heat dissipation layer 113. Therefore, by adopting this configuration, the void 73 interrupts the flow of shear stress in any direction perpendicular to the first direction z. As a result, even if peeling of the base material 11 from the heat dissipation member 71 occurs, the progress of the peeling is restricted by the gap 73. Therefore, according to this configuration, in the semiconductor device A10, peeling of the base material 11 from the heat dissipation member 71 can be suppressed.

[0120] The void portion 73 is exposed to the outside of the semiconductor device A10. By adopting this configuration, the degree of drying of the bonding material 79 becomes more uniform in the third step S3 of the manufacturing process of the semiconductor device A10, and therefore the solvent contained in the bonding material 79 can be effectively removed.

[0121] As viewed in the first direction z, the heat dissipation layer 113 of the substrate 11 has a first edge 113A and a second edge 113B. As viewed in the first direction z, the first edge 113A or its extension intersects with the second edge 113B or its extension at a first intersection P1. As viewed in the first direction z, the void 73 is located between the first intersection P1 and the bonding layer 72. As a result, as viewed in the first direction z, the void 73 is located at the corner of the heat dissipation layer 113. Here, shear stress caused by the heat of firing the bonding material 79 tends to concentrate in the corner of the heat dissipation layer 113. Therefore, by adopting this configuration, peeling of the substrate 11 from the heat dissipation member 71 can be effectively suppressed.

[0122] The bonding layer 72 includes a first bonding portion 721 and a second bonding portion 722 that are spaced apart from each other in the second direction x. The bonding layer 72 also includes a third bonding portion 723 that is spaced apart from the first bonding portion 721 and the second bonding portion 722 in a direction perpendicular to the first direction z. This configuration allows the distribution of shear stress caused by the heat of firing the bonding material 79 to be further dispersed.

[0123] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Fig. 29. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, the heat dissipation member 71 is not shown in Fig. 29. Fig. 29 corresponds to Fig. 14, which shows the semiconductor device A10.

[0124] In the semiconductor device A20, the configuration of the bonding layer 72 is different from that of the semiconductor device A10.

[0125] 29 , the second bonding portion 722 of the bonding layer 72 surrounds the first bonding portion 721 of the bonding layer 72. The third bonding portion 723 of the bonding layer 72 surrounds the second bonding portion 722. The dimension d1 of the first bonding portion 721 in the second direction x is greater than the dimension d2 of the second bonding portion 722 in the second direction x and the dimension d3 of the third bonding portion 723 in the second direction x. When viewed in the first direction z, the first bonding portion 721 has a circular shape. When viewed in the first direction z, each of the second bonding portion 722 and the third bonding portion 723 has an annular shape.

[0126] Next, a semiconductor device A21 according to a modification of the second embodiment of the present disclosure will be described with reference to Fig. 30. Fig. 30 corresponds to Fig. 29 showing the semiconductor device A20. In the semiconductor device A21, the configuration of the bonding layer 72 is different from that of the semiconductor device A20.

[0127] 30 , when viewed in the first direction z, the first bonding portion 721 of the bonding layer 72 has a rectangular shape. When viewed in the first direction z, the second bonding portion 722 and the third bonding portion 723 of the bonding layer 72 each have a frame shape.

[0128] Next, the effects of the semiconductor device A20 will be described.

[0129] The semiconductor device A20 includes a heat dissipation member 71, a substrate 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding layer 72. The substrate 11 faces the heat dissipation member 71 in the first direction z. The bonding layer 72 bonds the heat dissipation member 71 and the heat dissipation layer 113. The bonding layer 72 includes a sintered body of metal particles. The bonding layer 72 has a void 73 penetrating in the first direction z. Therefore, with this configuration, the semiconductor device A20 can also suppress peeling of the substrate 11 from the heat dissipation member 71. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0130] In the semiconductor device A20, the second bonding portion 722 of the bonding layer 72 surrounds the first bonding portion 721 of the bonding layer 72. This results in a configuration in which the void portion 73 surrounds the first bonding portion 721. With this configuration, the direction of the flow of shear stress caused by the heat generated by firing the bonding material 79, which is divided by the void portion 73, is radial in a direction perpendicular to the first direction z. This makes it possible to more effectively suppress peeling of the base material 11 from the heat dissipation member 71.

[0131] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIG. 31. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, the heat dissipation member 71 is not shown in FIG. 31. FIG. 31 corresponds to FIG. 14, which shows the semiconductor device A10.

[0132] In the semiconductor device A30, the configuration of the bonding layer 72 is different from that of the semiconductor device A10.

[0133] 31 , the positional relationship between the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 of the bonding layer 72 in the semiconductor device A30 corresponds to the positional relationship in the semiconductor device A10. As viewed in the first direction z, the first bonding portion 721 is located closer to the first intersection P1 than the second bonding portion 722. As viewed in the first direction z, the area of ​​the first bonding portion 721 is larger than the area of ​​the second bonding portion 722.

[0134] Next, a semiconductor device A31 according to a modification of the third embodiment of the present disclosure will be described with reference to Fig. 32. Fig. 32 corresponds to Fig. 31 showing the semiconductor device A30. In the semiconductor device A31, the configuration of the bonding layer 72 is different from that of the semiconductor device A30.

[0135] 32 , the positional relationship between the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 of the bonding layer 72 in the semiconductor device A31 corresponds to the positional relationship in the semiconductor device A11 described above. As viewed in the first direction z, the first bonding portion 721 is located closer to the first intersection P1 than the second bonding portion 722. As viewed in the first direction z, the area of ​​the first bonding portion 721 is larger than the area of ​​the second bonding portion 722.

[0136] Next, the effects of the semiconductor device A30 will be described.

[0137] The semiconductor device A30 includes a heat dissipation member 71, a base material 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding layer 72. The base material 11 faces the heat dissipation member 71 in the first direction z. The bonding layer 72 bonds the heat dissipation member 71 and the heat dissipation layer 113. The bonding layer 72 includes a sintered body of metal particles. The bonding layer 72 has a void 73 penetrating in the first direction z. Therefore, with this configuration, the semiconductor device A30 can also suppress peeling of the base material 11 from the heat dissipation member 71. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0138] In the semiconductor device A30, the first bonding portion 721 of the bonding layer 72 is located closer to the first intersection P1 than the second bonding portion 722 of the bonding layer 72 as viewed in the first direction z. The area of ​​the first bonding portion 721 is larger than the area of ​​the second bonding portion 722 as viewed in the first direction z. This configuration results in the first bonding portion 721, which has a relatively large area as viewed in the first direction z, being located near the corners of the heat dissipation layer 113 of the substrate 11, where shear stress caused by firing of the bonding material 79 is likely to concentrate. This reduces the concentration of shear stress at the interfaces between the first bonding portion 721 and the heat dissipation member 71 and the heat dissipation layer 113. This therefore more effectively suppresses peeling of the substrate 11 from the heat dissipation member 71.

[0139] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to FIG. 33. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, the heat dissipation member 71 is not shown in FIG. 33. FIG. 33 corresponds to FIG. 14, which shows the semiconductor device A10.

[0140] In the semiconductor device A40, the configuration of the bonding layer 72 is different from that of the semiconductor device A10.

[0141] 33 , the configurations of the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 of the bonding layer 72 in the semiconductor device A40 correspond to those of the semiconductor device A10. The bonding layer 72 includes two connecting portions 724. The two connecting portions 724 are spaced apart from each other in the second direction x. Each of the two connecting portions 724 has a strip shape extending in the third direction y. Each of the two connecting portions 724 is connected to the first bonding portion 721 and the second bonding portion 722 of the bonding layer 72. The dimension d4 in the second direction x of each of the two connecting portions 724 is larger than the dimension in the second direction x of each of the first bonding portion 721 and the second bonding portion 722. When viewed in the first direction z, the multiple first semiconductor elements 21 overlap one of the two connecting portions 724. When viewed in the first direction z, the multiple second semiconductor elements 22 overlap the other of the two connecting portions 724 .

[0142] Next, a semiconductor device A41 according to a modification of the fourth embodiment of the present disclosure will be described with reference to Fig. 34. Fig. 34 corresponds to Fig. 33 showing the semiconductor device A40. In the semiconductor device A41, the configuration of the bonding layer 72 is different from that of the semiconductor device A40.

[0143] 34 , the configurations of the first bonding portion 721, the second bonding portion 722, and the third bonding portion 723 of the bonding layer 72 in the semiconductor device A41 correspond to those in the semiconductor device A20. The bonding layer 72 includes two connecting portions 724. The configurations of the two connecting portions 724 are the same as those in the semiconductor device A40.

[0144] Next, the effects of the semiconductor device A40 will be described.

[0145] The semiconductor device A40 includes a heat dissipation member 71, a base material 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding layer 72. The base material 11 faces the heat dissipation member 71 in the first direction z. The bonding layer 72 bonds the heat dissipation member 71 and the heat dissipation layer 113. The bonding layer 72 includes a sintered body of metal particles. The bonding layer 72 has a void 73 that penetrates in the first direction z. Therefore, with this configuration, the semiconductor device A40 can also suppress peeling of the base material 11 from the heat dissipation member 71. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0146] In the semiconductor device A40, the bonding layer 72 includes a connecting portion 724 that connects to the first bonding portion 721 and the second bonding portion 722. The dimension d4 of the connecting portion 724 in the second direction x is larger than the dimensions of each of the first bonding portion 721 and the second bonding portion 722 in the second direction x. This configuration further increases the area of ​​the bonding layer 72 as viewed in the first direction z. This improves the bonding strength between the heat dissipation member 71 and the heat dissipation layer 113 of the base material 11.

[0147] In the above case, when viewed in the first direction z, the first semiconductor element 21 overlaps the connecting portion 724. By adopting this configuration, when the semiconductor device A40 is in use, heat generated from the first semiconductor element 21 can be smoothly conducted from the heat dissipation layer 113 of the base material 11 to the heat dissipation member 71 via the connecting portion 724.

[0148] Fifth Embodiment: A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 35 and 36. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, the heat dissipation member 71 is not shown in FIG. 35. FIG. 35 corresponds to FIG. 14, which shows the semiconductor device A10. FIG. 36 corresponds to FIG. 9, which shows the semiconductor device A10.

[0149] In the semiconductor device A50, the configuration of the heat dissipation layer 113 of the base material 11 is different from that of the semiconductor device A10.

[0150] 35 and 36 , the heat dissipation layer 113 of the substrate 11 has a first surface 113C and a second surface 113D that face the base 711 of the heat dissipation member 71. The first surface 113C and the second surface 113D are spaced apart from each other in the second direction x. A first bonding portion 721 of the bonding layer 72 bonds the first surface 113C. A second bonding portion 722 of the bonding layer 72 bonds the second surface 113D.

[0151] 35 and 36 , the heat dissipation layer 113 of the base material 11 has a groove 113E recessed in the first direction z. The groove 113E extends in the third direction y. The first surface 113C and the second surface 113D of the heat dissipation layer 113 are located on opposite sides of the groove 113E. As viewed in the first direction z, the multiple first semiconductor elements 21 overlap the first surface 113C. As viewed in the first direction z, the multiple second semiconductor elements 22 overlap the second surface 113D.

[0152] Next, the effects of the semiconductor device A50 will be described.

[0153] The semiconductor device A50 includes a heat dissipation member 71, a base material 11 including a heat dissipation layer 113, a first conductive layer 121, a first semiconductor element 21, and a bonding layer 72. The base material 11 faces the heat dissipation member 71 in the first direction z. The bonding layer 72 bonds the heat dissipation member 71 and the heat dissipation layer 113. The bonding layer 72 includes a sintered body of metal particles. The bonding layer 72 has a void 73 penetrating in the first direction z. Therefore, with this configuration, the semiconductor device A50 can also suppress peeling of the base material 11 from the heat dissipation member 71. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A50 achieves the same effects as the semiconductor device A10.

[0154] In the semiconductor device A50, the heat dissipation layer 113 of the substrate 11 is provided with a groove 113E recessed in the first direction z. With this configuration, the flow of shear stress caused by the heat of firing the bonding material 79 in any direction perpendicular to the first direction z is interrupted not only by the void 73 but also by the groove 113E. As a result, even if peeling of the substrate 11 from the heat dissipation member 71 occurs, the void 73 and the groove 113E restrict the progress of the peeling. Therefore, peeling of the substrate 11 from the heat dissipation member 71 can be more effectively suppressed.

[0155] The heat dissipation layer 113 of the base material 11 has a first surface 113C and a second surface 113D that face the heat dissipation member 71. The first surface 113C and the second surface 113D are located on opposite sides of the groove 113E. When viewed in the first direction z, the first semiconductor element 21 overlaps the first surface 113C. When viewed in the first direction z, the second semiconductor element 22 overlaps the second surface 113D. With this configuration, when the semiconductor device A50 is in use, heat generated from each of the first semiconductor element 21 and the second semiconductor element 22 can be conducted to the heat dissipation member 71 without being hindered by the groove 113E provided in the heat dissipation layer 113.

[0156] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0157] The present disclosure includes embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: a heat dissipation member; a base including a heat dissipation layer facing the heat dissipation member in a first direction; a first conductive layer located on the opposite side of the base from the heat dissipation member and bonded to the base; a first semiconductor element bonded to the first conductive layer; and a bonding layer bonding the heat dissipation member and the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles, and a void portion penetrating the bonding layer in the first direction. Appendix 2. The semiconductor device according to Appendix 1, wherein the bonding layer includes a first bonding portion and a second bonding portion spaced apart from each other in a second direction orthogonal to the first direction. Appendix 3. The semiconductor device according to Appendix 2, wherein the void portion is exposed to the outside. Appendix 4. Supplementary Note 3: The semiconductor device according to Supplementary Note 3, wherein, as viewed in the first direction, the heat dissipation layer has a first edge and a second edge, the first edge extends in the second direction, the second edge extends in a direction perpendicular to the first direction and different from the second direction, the first edge or an extension thereof and the second edge or an extension thereof intersect at a first intersection as viewed in the first direction, and the gap includes a portion located between the first intersection and the bonding layer as viewed in the first direction. Supplementary Note 5: The semiconductor device according to Supplementary Note 4, wherein, as viewed in the first direction, the first bonding portion is located closer to the first intersection than the second bonding portion, and an area of ​​the first bonding portion is larger than an area of ​​the second bonding portion as viewed in the first direction. Supplementary Note 6: The semiconductor device according to Supplementary Note 3, wherein the first bonding portion and the second bonding portion are adjacent to each other, and the bonding layer includes a third bonding portion separated from the first bonding portion and the second bonding portion in the direction perpendicular to the first direction. Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein the third bonded portion is located adjacent to the first bonded portion and the second bonded portion in a direction perpendicular to the first direction, and an imaginary line that passes through a center of the third bonded portion and extends in a third direction perpendicular to each of the first direction and the second direction overlaps with the gap portion located between the first bonded portion and the second bonded portion as viewed in the first direction.Appendix 8. The semiconductor device according to Appendix 6, wherein the third bonding portion is located adjacent to the first bonding portion in a third direction orthogonal to each of the first direction and the second direction, and an imaginary line passing through the center of the third bonding portion and extending in the third direction overlaps the first bonding portion as viewed in the first direction. Appendix 9. The semiconductor device according to Appendix 6, wherein the first bonding portion, the second bonding portion, and the third bonding portion each have the same area as each other as viewed in the first direction. Appendix 10. The semiconductor device according to Appendix 3, wherein the second bonding portion surrounds the first bonding portion. Appendix 11. The semiconductor device according to Appendix 10, wherein the dimension of the first bonding portion in the second direction is larger than the dimension of the second bonding portion in the second direction. Appendix 12. The semiconductor device according to Appendix 3, wherein the bonding layer includes a connecting portion connected to the first bonding portion and the second bonding portion, and the dimension of the connecting portion in the second direction is larger than the dimension of each of the first bonding portion and the second bonding portion in the second direction. Appendix 13. The semiconductor device according to Appendix 12, wherein the first semiconductor element overlaps the connecting portion when viewed in the first direction. Appendix 14. The semiconductor device according to any one of Appendixes 3 to 13, wherein the base includes an insulating layer located on the opposite side of the heat dissipation layer from the heat dissipation member, and the first conductive layer is bonded to the insulating layer. Appendix 15. The semiconductor device according to Appendix 14, further comprising: a second conductive layer located on the same side of the base as the first conductive layer and bonded to the insulating layer; and a second semiconductor element conductively bonded to the second conductive layer, wherein the first semiconductor element is conductively bonded to the first conductive layer, and the second semiconductor element is electrically connected to the first semiconductor element. Appendix 16. The semiconductor device according to Appendix 15, wherein the metal particles include silver. Appendix 17. The semiconductor device according to Appendix 15, wherein the conductive bonding of the first semiconductor element to the first conductive layer and the conductive bonding of the second semiconductor element to the second conductive layer are achieved by liquid metal.Appendix 18. A method for manufacturing a semiconductor device, comprising: a first step of bonding a first conductive layer to a base material including a heat dissipation layer so that the first conductive layer is located on an opposite side of the base material from the heat dissipation layer in a first direction; a second step of conductively bonding a first semiconductor element to the first conductive layer; a third step of arranging a bonding material on one side of either the heat dissipation member or the heat dissipation layer in the first direction; and a fourth step of firing the bonding material to bond the heat dissipation member and the heat dissipation layer, wherein the bonding material contains metal particles, and in the third step, a void portion penetrating in the first direction is provided in the bonding material. Appendix 19. The method for manufacturing a semiconductor device according to Appendix 18, wherein in the third step, the bonding material is arranged to include a first portion and a second portion separated from each other in a direction perpendicular to the first direction, and in the third step, the void portion is provided so as to be exposed to the outside in the direction perpendicular to the first direction. Appendix 20. the first semiconductor element is conductively bonded to the first conductive layer by liquid metal. Appendix 21. An inverter device comprising: a heat dissipation member; a base including a heat dissipation layer facing the heat dissipation member in a first direction; first and second conductive layers located on the opposite side of the base from the heat dissipation member and bonded to the base; a first semiconductor element conductively bonded to the first conductive layer; a second semiconductor element conductively bonded to the second conductive layer; a first signal terminal electrically connected to the first semiconductor element; a second signal terminal electrically connected to the second semiconductor element; a wiring board individually connected to the first signal terminal and the second signal terminal; and a bonding layer bonding the heat dissipation member to the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles, and the bonding layer is provided with a void portion penetrating in the first direction. The inverter device according to claim 21, wherein the first semiconductor element is electrically connected to the first conductive layer and the second semiconductor element is electrically connected to the second conductive layer by liquid metal. 23. A vehicle comprising: a drive source; and the semiconductor device according to any one of claims 15 to 17, wherein the semiconductor device is electrically connected to the drive source.Appendix 24. The semiconductor device according to Appendix 6, wherein the first bonding portion, the second bonding portion, and the third bonding portion are each circular when viewed in the first direction. Appendix 25. The semiconductor device according to Appendix 6, wherein the first bonding portion, the second bonding portion, and the third bonding portion are each rectangular when viewed in the first direction. Appendix 26. The semiconductor device according to Appendix 11, wherein the bonding layer includes a third bonding layer surrounding the second bonding portion, and wherein a dimension of the first bonding portion in the second direction is larger than a dimension of the third bonding portion in the second direction. Appendix 27. The semiconductor device according to Appendix 26, wherein the first bonding portion is circular when viewed in the first direction, and wherein the second bonding portion and the third bonding portion are each annular when viewed in the first direction. Appendix 28. The semiconductor device according to Supplementary Note 26 or 27, wherein the bonding layer includes a connecting portion connecting to the first bonding portion, the second bonding portion, and the third bonding portion, and wherein a dimension of the connecting portion in the second direction is larger than a dimension of each of the second bonding portion and the third bonding portion in the second direction. Supplementary Note 29. The semiconductor device according to any of Supplementary Notes 15 to 17, wherein the heat dissipation layer has a first surface and a second surface facing the heat dissipation member, the first surface and the second surface being spaced apart from each other in the second direction, the first bonding portion bonding the first surfaces, and the second bonding portion bonding the second surfaces. Supplementary Note 30. The semiconductor device according to Supplementary Note 29, wherein, when viewed in the first direction, the first semiconductor element overlaps the first surface, and the second semiconductor element overlaps the second surface. Supplementary Note 31. The semiconductor device according to claim 30, wherein the heat dissipation layer is provided with a groove recessed in the first direction, and the first surface and the second surface are located on opposite sides of the groove. Attachment 32. The semiconductor device according to any of attachments 15 to 17, wherein the metal particles include copper. Attachment 33. The semiconductor device according to any of attachments 15 to 17, further comprising: a first terminal electrically connected to the first conductive layer; and a second terminal electrically connected to the second conductive layer.Appendix 34. The semiconductor device according to Appendix 33, further comprising a sealing resin covering the first semiconductor element and the second semiconductor element, wherein the heat dissipation layer, the first terminal, and the second terminal are exposed from the sealing resin. Appendix 35. The method for manufacturing a semiconductor device according to Appendix 19 or 20, wherein the metal particles include silver. Appendix 36. A vehicle comprising: a drive source; and the inverter device according to Appendix 21 or 22, wherein the inverter device is electrically connected to the drive source.

[0158] A10 to A50: Semiconductor device B: Inverter device C: Vehicle S1 to S4: First to fourth steps 11: Base material 111: Insulating layer 112: Support layer 113: Heat dissipation layer 113A, 113B: First edge, second edge 113C, 113D: First surface, second surface 113E: Groove portion 121: First conductive layer 121A: First main surface 122: Second conductive layer 122A: Second main surface 129: First bonding layer 13: First power terminal 131: Covered portion 132: Exposed portion 14: Second power terminal 141: Covered portion 142: Exposed portion 15: Third power terminal 151: Covered portion 152: Exposed portion 161: First signal terminal 161A: Base portion 161B: Bulging portion 162: Second signal terminal 171: Third signal terminal 172: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 19: Seventh signal terminal 21: First semiconductor element 211: First electrode 212: Second electrode 213: First gate electrode 214: First detection electrode 22: Second semiconductor element 221: Third electrode 222: Fourth electrode 223: Second gate electrode 224: Second detection electrode 23: Thermistor 29: Conductive bonding layer 31: First conductive member 311: First main portion 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 32: Second conductive member 321: Second main portion 322: Third bonding portion 323: Third connecting portion 324: Fourth bonding portion 325: Fourth connecting portion 326: Middle portion 327: Horizontal beam portion 41 to 47: First wire to seventh wire 50: Sealing resin 51: Top surface 52: Bottom surface 53, 54: First side surface, second side surface 55: Recess 61: First wiring 611: First mounting layer 612: First metal layer 613: First gate wiring layer 614: First detection wiring layer 615: First temperature detection wiring layer 616: Second detection wiring layer 62: Second wiring 621: Second mounting layer 622: Second metal layer 623: Second gate wiring layer 624: Third detection wiring layer 625: Second temperature detection wiring layer 626: Fourth detection wiring layer 63: Sleeve 631: End surface 68, 69: Second bonding layerThird bonding layer 71: Heat dissipation member 711: Base 712: Heat dissipation portion 72: Bonding layer 721 to 723: First bonding portion to third bonding portion 724: Connection portion 73: Gap portion 79: Bonding material 791, 792: First portion, second portion 81: Wiring board 811: Board 811A: Through hole 812: Main portion wiring 813: Back portion wiring 814: Internal wiring 82: Support member 83: Control circuit 84: Drive circuit 841: Amplification circuit 842: First switch circuit 843: Gate resistor 844: Second switch circuit 845: Current interruption resistor 846: Overcurrent detection circuit 846A: Current detection resistor 846B: Comparison circuit 91: On-board charger 92: Storage battery 93: Drive system 931: Inverter 932: Drive source z: first direction x: second direction y: third direction,

Claims

1. A semiconductor device comprising: a heat dissipation member; a substrate including a heat dissipation layer facing the heat dissipation member in a first direction; a first conductive layer located on the opposite side of the substrate from the heat dissipation member and bonded to the substrate; a first semiconductor element bonded to the first conductive layer; and a bonding layer bonding the heat dissipation member and the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles, and the bonding layer has a void portion that penetrates in the first direction.

2. The semiconductor device according to claim 1, wherein said bonding layer includes a first bonding portion and a second bonding portion spaced apart from each other in a second direction perpendicular to said first direction.

3. The semiconductor device according to claim 2, wherein the void portion is exposed to the outside.

4. The semiconductor device described in claim 3, wherein, when viewed in the first direction, the heat dissipation layer has a first edge and a second edge, the first edge extends in the second direction, the second edge extends in a direction perpendicular to the first direction and different from the second direction, when viewed in the first direction, the first edge or an extension thereof and the second edge or an extension thereof intersect at a first intersection, and when viewed in the first direction, the void portion includes a portion located between the first intersection and the bonding layer.

5. The semiconductor device described in claim 4, wherein, when viewed in the first direction, the first joint is located closer to the first intersection than the second joint, and, when viewed in the first direction, the area of ​​the first joint is larger than the area of ​​the second joint.

6. The semiconductor device according to claim 3, wherein the first bonding portion and the second bonding portion are adjacent to each other, and the bonding layer includes a third bonding portion spaced apart from the first bonding portion and the second bonding portion in a direction perpendicular to the first direction.

7. The semiconductor device described in claim 6, wherein the third joint is located adjacent to the first joint and the second joint in a direction perpendicular to the first direction, and when viewed in the first direction, an imaginary line passing through a center of the third joint and extending in a third direction perpendicular to each of the first direction and the second direction overlaps with the gap located between the first joint and the second joint.

8. The semiconductor device described in claim 6, wherein the third joint is located adjacent to the first joint in a third direction perpendicular to each of the first direction and the second direction, and when viewed in the first direction, a virtual line passing through a center of the third joint and extending in the third direction overlaps with the first joint.

9. The semiconductor device according to claim 6, wherein the areas of the first bonding portion, the second bonding portion and the third bonding portion are equal to each other when viewed in the first direction.

10. The semiconductor device according to claim 3, wherein the second joint portion surrounds the first joint portion.

11. The semiconductor device according to claim 10, wherein the dimension of the first joint portion in the second direction is larger than the dimension of the second joint portion in the second direction.

12. The semiconductor device described in claim 3, wherein the bonding layer includes a connecting portion connected to the first bonding portion and the second bonding portion, and the dimension of the connecting portion in the second direction is larger than the dimensions of each of the first bonding portion and the second bonding portion in the second direction.

13. The semiconductor device according to claim 12, wherein the first semiconductor element overlaps the connecting portion when viewed in the first direction.

14. A semiconductor device according to any one of claims 3 to 13, wherein the base material includes an insulating layer located on the opposite side of the heat dissipation member relative to the heat dissipation layer, and the first conductive layer is bonded to the insulating layer.

15. The semiconductor device described in claim 14, further comprising: a second conductive layer located on the same side of the substrate as the first conductive layer and bonded to the insulating layer; and a second semiconductor element conductively bonded to the second conductive layer, wherein the first semiconductor element is conductively bonded to the first conductive layer, and the second semiconductor element is electrically connected to the first semiconductor element.

16. The semiconductor device according to claim 15, wherein the metal particles include silver.

17. A method for manufacturing a semiconductor device, comprising: a first step of joining a first conductive layer to a substrate including a heat dissipation layer so that the first conductive layer is located on the opposite side of the heat dissipation layer in a first direction; a second step of conductively joining a first semiconductor element to the first conductive layer; a third step of arranging a bonding material on one side in the first direction of either the heat dissipation member or the heat dissipation layer; and a fourth step of bonding the heat dissipation member and the heat dissipation layer by firing the bonding material, wherein the bonding material contains metal particles, and in the third step, a void portion penetrating in the first direction is provided in the bonding material.

18. A method for manufacturing a semiconductor device as described in claim 17, wherein in the third step, the bonding material is arranged to include a first portion and a second portion spaced apart from each other in a direction perpendicular to the first direction, and in the third step, the void portion is provided so as to be exposed to the outside in a direction perpendicular to the first direction.

19. An inverter device comprising: a heat dissipation member; a substrate including a heat dissipation layer facing the heat dissipation member in a first direction; first and second conductive layers located on the opposite side of the substrate to the heat dissipation member and joined to the substrate; a first semiconductor element conductively joined to the first conductive layer; a second semiconductor element conductively joined to the second conductive layer; a first signal terminal electrically connected to the first semiconductor element; a second signal terminal electrically connected to the second semiconductor element; a wiring board individually connected to the first signal terminal and the second signal terminal; and a bonding layer bonding the heat dissipation member and the heat dissipation layer, wherein the bonding layer includes a sintered body of metal particles, and the bonding layer is provided with a void portion penetrating in the first direction.

20. A vehicle comprising: a driving source; and the semiconductor device according to claim 15, wherein the semiconductor device is electrically connected to the driving source.

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