Dual buffer circuit, gamma voltage generation circuit including same, and data drive circuit

Abstract

The present invention relates to a dual buffer circuit capable of eliminating an offset voltage, a gamma voltage generation circuit including same, and a data drive circuit. The dual buffer circuit according to an embodiment may include a first buffer circuit and a second buffer circuit which are connected in parallel between an input terminal and an output terminal, and each of the first buffer circuit and the second buffer circuit may include an operational amplifier, a chopping switching unit, and a switch unit. The first buffer circuit and the second buffer circuit can perform an operation in at least one of a chopping mode or an auto-zero mode. When the first buffer circuit and the second buffer circuit operate in the auto-zero mode, the first buffer circuit and the second buffer circuit can alternately implement a sampling period for sampling an offset in the auto-zero mode and a holding period for compensating for the offset.

Description

Dual buffer circuit and gamma voltage generation circuit and data driving circuit having the same

[0001] The present invention relates to a dual buffer circuit and a gamma voltage generation circuit and a data driving circuit having the same.

[0002] A gamma voltage generation circuit built into a data driving circuit in a display device can receive a plurality of reference gamma voltages from a reference gamma voltage generation circuit and generate a subdivided gamma voltage by subdividing the plurality of reference gamma voltages through a resistor string.

[0003] The gamma voltage generation circuit includes multiple buffer circuits that each buffer and output multiple reference gamma voltages. The buffer circuits utilize operational amplifiers, and the operational amplifiers may include offset voltages due to design and process variations.

[0004] Since the input and output voltage difference occurs due to the offset voltage in the buffer circuit, a method to remove the offset voltage is required.

[0005] In order to achieve low power consumption in data drive circuits and display devices, buffer circuits require a method to reduce power consumption.

[0006] The present invention provides a dual buffer circuit capable of removing an offset voltage, a gamma voltage generation circuit having the same, and a data driving circuit.

[0007] The present invention provides a dual buffer circuit capable of reducing power consumption, and a gamma voltage generation circuit and a data driving circuit having the same.

[0008] According to one embodiment of the present invention, a dual buffer circuit includes a first buffer circuit and a second buffer circuit connected in parallel between an input terminal and an output terminal, and each of the first buffer circuit and the second buffer circuit may include an operational amplifier including first and second input terminals and an output node, a chopping switching unit connected to the operational amplifier to control a chopping mode operation, and a switching unit connected to the operational amplifier to control an auto-zero mode operation. The first buffer circuit and the second buffer circuit may perform an operation in at least one mode among the chopping mode and the auto-zero mode. When the first buffer circuit and the second buffer circuit also operate in the auto-zero mode, the first buffer circuit and the second buffer circuit may alternately perform a sampling period for sampling an offset and a holding period for compensating for the offset in the auto-zero mode.

[0009] In a dual buffer circuit according to one embodiment of the present invention, one of the first buffer circuit and the second buffer circuit may operate in a chopping mode, and the other may be turned off.

[0010] In a dual buffer circuit according to one embodiment of the present invention, the first buffer circuit and the second buffer circuit can perform the chopping mode and the auto-zero mode simultaneously.

[0011] A dual buffer circuit according to one embodiment of the present invention can stably output an output voltage corresponding to an input voltage by effectively removing offset voltage and noise components by simultaneously performing a dual auto-zero mode and a chopping mode.

[0012] A gamma voltage generation circuit and a data driving circuit having a dual buffer circuit according to one embodiment of the present invention can improve reliability by utilizing a reference gamma voltage from which an offset voltage and noise component are removed through the dual buffer circuit according to one embodiment.

[0013] A dual buffer circuit and a gamma voltage generation circuit and a data driving circuit having the same according to one embodiment of the present invention can reduce power consumption by having the dual buffer circuit operate in either a dual auto-zero mode or a chopping mode depending on a specific mode.

[0014] FIG. 1 is an exemplary diagram showing the configuration of a dual buffer circuit according to one embodiment of the present invention.

[0015] FIG. 2 is an exemplary diagram showing a switch control unit connected to a dual buffer circuit according to one embodiment of the present invention.

[0016] FIG. 3 is a table illustrating switch operation states for each operation mode of a dual buffer circuit according to one embodiment of the present invention.

[0017] FIG. 4 is an exemplary diagram showing a driving waveform of a dual buffer circuit according to one embodiment illustrated in FIG. 1 that simultaneously performs dual auto-zero mode and chopping mode.

[0018] FIG. 5 is an exemplary diagram showing a driving waveform of a first horizontal period in which a dual buffer circuit according to one embodiment illustrated in FIG. 1 operates in dual auto-zero mode and chopping mode.

[0019] FIG. 6 is an exemplary diagram showing a driving waveform of a second horizontal period in which a dual buffer circuit according to one embodiment illustrated in FIG. 1 operates in dual auto-zero mode and chopping mode.

[0020] FIG. 7 is an exemplary diagram showing a state in which a dual buffer circuit according to one embodiment illustrated in FIG. 1 operates in chopping mode.

[0021] FIG. 8 is an example diagram showing a chopping mode driving waveform of a dual buffer circuit according to one embodiment illustrated in FIG. 7.

[0022] FIG. 9a and FIG. 9b are exemplary diagrams showing a state in which a dual buffer circuit according to one embodiment illustrated in FIG. 1 operates in double auto-zero mode.

[0023] FIG. 10 is an example diagram showing a dual auto-zero mode driving waveform of a dual buffer circuit according to one embodiment illustrated in FIGS. 9a and 9b.

[0024] Fig. 11 is an exemplary diagram showing the internal configuration of a first buffer circuit according to one embodiment of the present invention.

[0025] Fig. 12 is an exemplary diagram showing the configuration of a gamma voltage generation circuit according to one embodiment of the present invention.

[0026] Fig. 13 is an exemplary diagram showing the configuration of a data driving circuit according to one embodiment of the present invention.

[0027] Figure 14 is an exemplary diagram showing the configuration of a display device according to one embodiment of the present invention.

[0028] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0029] Throughout the specification, identical reference numerals designate identical components. Furthermore, in describing the present invention, detailed descriptions of related known technologies are omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0030] In this specification, when the terms "includes," "has," and "consists of," are used, other parts may be added, unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0031] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description of the error range.

[0032] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on," "above," "below," "next to," or "adjacent to," there may be one or more other parts located between the two parts, unless, for example, "directly," "directly," or "nearby" is used.

[0033] When describing a temporal relationship, for example, when the temporal continuity is described as 'after', 'following', 'next to', 'before', etc., it can also include cases where it is not continuous, as long as 'right away' or 'directly' is not used.

[0034] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0035] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0036] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0037] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. The scale of the components illustrated in the drawings is different from the actual scale for convenience of explanation, and is therefore not limited to the scale illustrated in the drawings.

[0038] FIG. 1 is an exemplary diagram showing the configuration of a dual buffer circuit according to one embodiment of the present invention, FIG. 2 is an exemplary diagram showing a switch control unit connected to a dual buffer circuit according to one embodiment of the present invention, and FIG. 3 is a table showing the switch operation states of a dual buffer circuit according to one embodiment of the present invention by operation mode.

[0039] Referring to FIG. 1, a dual buffer circuit (10) according to one embodiment may include first and second buffer circuits (20-1, 20-2) that share an input terminal (12) and an output terminal (14).

[0040] The first buffer circuit (20-1) may include a first operational amplifier (AMP1), eleventh to fourteenth switches (SW11, SW12, SW13, SW14), a second capacitor (Cs1), and eleventh and twelfth chopping switch units (CP11, CP12).

[0041] A capacitor (Cs1) is connected to the second input terminal (inverting input terminal) (-) of the first operational amplifier (AMP1) so as to sample and store the offset voltage of the first operational amplifier (AMP1).

[0042] The 11th switch (SW11) can selectively connect the input terminal (12) of the dual buffer circuit (10) and the capacitor (Cs1) in response to the 11th clock signal (CLK11).

[0043] The 12th switch (SW12) can selectively connect the output terminal and the second input terminal (-) of the operational amplifier (AMP1) in response to the 12th clock signal (CLK12).

[0044] The 13th switch (SW13) can selectively connect the output terminal (14) of the dual buffer circuit (10) and the capacitor (Cs1) in response to the 13th clock signal (CLK13).

[0045] The 14th switch (SW14) can selectively connect the output terminal of the operational amplifier (AMP1) and the output terminal (14) of the dual buffer circuit (10) in response to the 14th clock signal (CLK14).

[0046] The 11th and 12th chopping switch sections (CP11, CP12) can be connected to the input terminal and the amplification terminal of the operational amplifier (AMP1), respectively. The chopping switch sections (CP11, CP12) can periodically switch the current path of the operational amplifier (AMP1) between the chop state A and the chop state B in response to the first chopping clock (CH_CLK1). The operational amplifier (AMP1) can eliminate the offset voltage of the operational amplifier (AMP1) in an average manner since the polarities of the offset voltage are opposite in the sequentially operating chop state A (first chop state) and the chop state B (second chop state), and the polarities of the noise component are also opposite so that the noise component of the operational amplifier (AMP1) can also be eliminated in an average manner.

[0047] The second buffer circuit (20-2) may have the same structure as the first buffer circuit (20-1) and may include a second operational amplifier (AMP2), 21st and 22nd chopping switch units (CP21, CP22), 21st to 24th switches (SW21, SW22, SW23, SW24), and a second capacitor (Cs2).

[0048] The 21st to 24th switches (SW21, SW22, SW23, SW24) can be controlled by the 21st to 24th clock signals (CLK21, CLK22, CLK23, CLK24), respectively. The 21st and 22nd chopping switch units (CP21, CP22) can be controlled by the second chopping clock (CH_CLK2).

[0049] The first and second buffer circuits (20-1, 20-2) can perform double auto-zero mode operation and chopping mode operation simultaneously to remove offset voltage, or can perform either double auto-zero mode operation or chopping mode operation. A detailed description thereof will be provided later.

[0050] In the dual buffer circuit (10), the first buffer circuit (20-1) and the second buffer circuit (20-2) alternately perform the sampling period of the sampling mode performing offset sampling in the dual auto-zero mode and the holding period of the holding mode performing offset cancelling, thereby maintaining the output voltage (Vout) in a constant holding state. A detailed description thereof will be given later.

[0051] Referring to FIG. 2, the switch control unit (30) can receive an auto-zero enable signal (AZ_EN), a chopping enable signal (CP_EN), first and second chopping clock signals (CP_CLK1, CP_CLK2), and first and second auto-zero clock signals (AZ_CLK1, AZ_CLK2). The switch control unit (30) can generate the first and second chopping clock signals (CP_CLK1, CP_CLK2) and the eleventh to fourteenth, twenty-first to twenty-fourth clock signals (CLK11 to CLK14, CLK21 to CLK24) and output them to the dual buffer circuit (10).

[0052] Referring to FIGS. 2 and 3, the switch control unit (30) can output the first and second chopping clock signals (CP_CLK1, CP_CLK2) when the chopping enable signal (CP_EN) is in an enabled state (ON). When the chopping enable signal (CP_EN) is in a disabled state (OFF), the switch control unit (30) can output only the first chopping clock signal (CP_CLK1) and deactivate the second chopping clock signal (CP_CLK1) with a low voltage.

[0053] The switch control unit (30) can generate and output the 11th to 14th clock signals (CLK11 to CLK14) using the first auto-zero clock signal (AZ_CLK1) and generate and output the 21st to 24th clock signals (CLK21 to CLK24) using the second auto-zero clock signal (AZ_CLK2) when the chopping enable signal (CP_EN) is in an enabled state (ON) or a disabled state (OFF) and the auto-zero enable signal (AZ_EN) is in an enabled state (ON).

[0054] In the sampling period of the first buffer circuit (20-1), the eleventh and twelfth switches (SW11, SW12) may be turned on in response to the eleventh and twelfth clock signals (CLK11, CLK12), and the thirteenth and fourteenth switches (SW13, 14) may be turned off in response to the thirteenth and fourteenth clock signals (CLK13, CLK14). In the holding period of the first buffer circuit (20-1), the thirteenth and fourteenth switches (SW13, SW14) may be turned on in response to the thirteenth and fourteenth clock signals (CLK13, CLK14), and the eleventh and twelfth switches (SW11, SW12) may be turned off in response to the eleventh and twelfth clock signals (CLK11, CLK12).

[0055] In the sampling period of the second buffer circuit (20-2), the twenty-first and twenty-second switches (SW21, SW22) may be turned on in response to the twenty-first and twenty-second clock signals (CLK21, CLK22), and the twenty-third and twenty-fourth switches (SW23, SW24) may be turned off in response to the twenty-third and twenty-fourth clock signals (CLK23, CLK24). In the holding period of the first buffer circuit (20-1), the twenty-third and twenty-fourth switches (SW23, SW24) may be turned on in response to the twenty-third and twenty-fourth clock signals (CLK23, CLK24), and the twenty-first and twenty-second switches (SW21, SW22) may be turned off in response to the twenty-first and twenty-second clock signals (CLK21, CLK22).

[0056] When the chopping enable signal (CP_EN) is in an enabled state (ON) and the auto-zero enable signal (AZ_EN) is in a disabled state (OFF), the switch control unit (30) can turn on the 12th to 14th switches (SW12, SW13, SW14) in response to the 12th to 14th clock signals (CLK12, CLK13, CLK14), turn off the 11th switch (SW11) in response to the 11th clock signal (CLK11), and turn off the 21st to 24th switches (SW21, SW22, SW23, SW24) of the second buffer circuit (20-2).

[0057] FIG. 4 is an exemplary diagram showing a driving waveform of a dual buffer circuit according to an embodiment illustrated in FIG. 1 simultaneously performing a dual auto-zero mode and a chopping mode, FIG. 5 is an exemplary diagram showing a driving waveform of a first horizontal period in which a dual buffer circuit according to an embodiment illustrated in FIG. 1 operates in a dual auto-zero mode and a chopping mode, and FIG. 6 is an exemplary diagram showing a driving waveform of a second horizontal period in which a dual buffer circuit according to an embodiment illustrated in FIG. 1 operates in a dual auto-zero mode and a chopping mode.

[0058] Referring to FIGS. 2 and 4, the switch control unit (30) can receive chopping clock signals (CP_CLK1, CP_CLK2) and auto-zero clock signals (AZ_CLK1, AZ_CLK2) generated based on the timing of the horizontal synchronization signal (HSYNC) of the display device. Each of the horizontal periods (H1, H2, H3, H4) of the horizontal synchronization signal (HSYNC) can include an active period (ACT), and a first blank period (P1) and a second blank period (P2) before and after the active period (ACT).

[0059] Each of the first and second chopping clock signals (CP_CLK1, CP_CLK2) can have a 4H cycle including a high voltage (VH) of 2H and a low voltage (VL) of 2H. The first chopping clock signal (CP_CLK1) and the second chopping clock signal (CP_CLK2) can have different phases. Each of the low voltage (VL) period and the high voltage (VH) period of the first chopping clock signal (CP_CLK1) can overlap with the low and high voltage (VL, VH) periods of the second chopping clock signal (CP_CLK2).

[0060] Each of the first and second auto-zero clock signals (AZ_CLK1, AZ_CLK2) can have a 2H cycle including a high voltage (VH) of 1H period and a low voltage (VL) of 1H period. The first auto-zero clock signal (AZ_CLK1) and the second auto-zero clock signal (AZ_CLK2) can have different phases. The high voltage (VH) periods of the auto-zero clock signals (AZ_CLK1, AZ_CLK2) can be non-overlapping. The low voltage (VL) periods of the auto-zero clock signals (AZ_CLK1, AZ_CLK2) can partially overlap in the second blank period (P2) of each horizontal period.

[0061] In the dual buffer circuit (10), the first buffer circuit (20-1) and the second buffer circuit (20-2) can alternately perform a sampling period for performing offset sampling in dual auto-zero mode and a holding period for performing offset cancelling in units of 1H.

[0062] Each of the first and second chopped state (A, B) periods during which the first operational amplifier (AMP1) of the first buffer circuit (20-1) operates in chopping mode may include a sampling period and a holding period of the auto-zero mode of the first buffer circuit (20-1). Each of the first and second chopped state (A, B) periods during which the second operational amplifier (AMP2) of the second buffer circuit (20-2) operates in chopping mode may include a sampling period and a holding period of the auto-zero mode of the second buffer circuit (20-2).

[0063] In the dual buffer circuit (10), the chopping switch section (CP11 / CP12, CP21 / CP22) of the operational amplifier (AMP1, AMP2) can switch between chop state A and chop state B every 2H period in response to the chopping clock signal (CP_CLK1, CP_CLK2).

[0064] The chopping switch section (CP11, CP12) of the first operational amplifier (AMP1) can be switched to a first chop state (A) during a horizontal period (H1, H2) in which the first chopping clock signal (CP_CLK1) is a high voltage (VH) to provide a first type of current path, and can be switched to a second chop state (B) during a horizontal period (H3, H4) in which the first chopping clock signal (CP_CLK1) is a low voltage (VL) to provide a second type of current path.

[0065] For example, at the input terminal of the first operational amplifier (AMP1), the 11th chopping switch unit (CP11) can connect the input line connected to the input terminal (12) to the first input terminal (+) of the operational amplifier (AMP1) in the first chop state (A), and can connect the feedback line connected to the feedback switch (SW12, SW13) to the second input terminal (-). In the second chop state (B), the chopping switch unit (CP11) can connect the input line connected to the input terminal (12) to the second input terminal (-) of the operational amplifier (AMP1), and can connect the feedback line connected to the feedback switch (SW12, SW13) to the first input terminal (+), opposite to the first chop state (A).

[0066] In the amplification stage of the first operational amplifier (AMP1), the 12th chopping switch unit (CP12) can also switch the current path between the first chop state (A) and the second chop state in response to the first chopping clock signal (CP_CLK1).

[0067] The eleventh and twelfth clock signals (CLK11, CLK12) can have an ON voltage (ON) in the sampling period of the first buffer circuit (20-1), and the thirteenth and fourteenth clock signals (CLK13, CLK14) can have an ON voltage (ON) in the holding period of the first buffer circuit (20-1). The twenty-first and twenty-second clock signals (CLK21, CLK22) can have an ON voltage (ON) in the sampling period of the second buffer circuit (20-2), and the twenty-third and twenty-fourth clock signals (CLK23, CLK24) can have an ON voltage (ON) in the holding period of the second buffer circuit (20-2).

[0068] The sampling period of the first buffer circuit (20-1) in which the 11th and 12th clock signals (CLK11 to CLK12) are in an on voltage (VON) state may not overlap with the holding period of the first buffer circuit (20-1) in which the 13th and 14th clock signals (CLK13 to CLK12) are in an on voltage (VON) state. The off voltage (VOFF) period of the 11th and 12th clock signals (CLK11 to CLK12) may partially overlap with the off voltage (VOFF) period of the 13th and 14th clock signals (CLK13 to CLK12) in the second blank period (P2) of each horizontal period.

[0069] The sampling period of the second buffer circuit (20-2) in which the 21st and 22nd clock signals (CLK21 to CLK22) are in an on voltage (VON) state may not overlap with the holding period of the second buffer circuit (20-2) in which the 23rd and 24th clock signals (CLK23 to CLK22) are in an on voltage (VON) state. The off voltage (VOFF) period of the 21st and 22nd clock signals (CLK21 to CLK22) may partially overlap with the off voltage (VOFF) period of the 23rd and 24th clock signals (CLK23 to CLK24) in the second blank period (P2) of each horizontal period.

[0070] The sampling period of the first buffer circuit (20-1) in which the 11th and 12th clock signals (CLK11 to CLK12) are in an on voltage (VON) state may overlap with the holding period of the second buffer circuit (20-2) in which the 21st and 22nd clock signals (CLK21 to CLK22) are in an on voltage (VON) state. The holding period of the second buffer circuit (20-2) may be longer than the sampling period of the first buffer circuit (20-1).

[0071] The holding period of the first buffer circuit (20-1) in which the 13th and 14th clock signals (CLK13 to CLK12) are in an on voltage (VON) state may overlap with the sampling period of the second buffer circuit (20-2) in which the 21st and 22nd clock signals (CLK21 to CLK22) are in an on voltage (VON) state. The holding period of the first buffer circuit (20-1) may be longer than the sampling period of the second buffer circuit (20-2).

[0072] The transition timing (rising / falling timing) of the high voltage (VH) and the low voltage (VL) of the first chopping clock signal (CP_CLK1) may overlap with the second period (P2) of the blank period of the even horizontal period (H2, H4). The transition timing (rising / falling timing) of the high voltage (VH) and the low voltage (VL) of the second chopping clock signal (CP_CLK2) may overlap with the second period (P2) of the blank period of the odd horizontal period (H1, H3). The transition timing of the chopping clock signals (CP_CLK1, CP_CLK2) may overlap with the period in which the auto-zero clock signals (AZ_CLK1, AZ_CLK2), i.e., the clock signals (CLK11 to CLK14, CLK21 to CLK24) are all at the low voltage (VL).

[0073] Referring to FIGS. 4 and 5, in the first horizontal period (H1), the first buffer circuit (20-1) can simultaneously perform the first chop state (A) operation of the chopping mode and the sampling mode operation of the auto-zero mode. The second buffer circuit (20-2) can simultaneously perform the first chop state (A) operation of the chopping mode and the holding mode operation of the auto-zero mode.

[0074] The first buffer circuit (20-1) can operate in the first chop state (A) of the chopping mode. At the same time, the first buffer circuit (20-1) can turn on the eleventh and twelfth switches (SW11, SW12) in response to the eleventh and twelfth clock signals (CLK11, CLK12) in the sampling period of the auto-zero mode, and turn off the thirteenth and fourteenth switches (SW13, 14) in response to the thirteenth and fourteenth clock signals (CLK13, CLK14). Accordingly, the first capacitor (Cs1) of the first buffer circuit (20-1) can sample and store the offset voltage of the first operational amplifier (AMP1), which is the difference between the input voltage (Vin) supplied from the input terminal (12) through the 11th switch (SW11) and the output voltage (Vout) fed back through the 12th switch (SW12).

[0075] The second buffer circuit (20-2) can operate in the first chop state (A) of the chopping mode. The second buffer circuit (20-2) can operate in the holding mode of the auto-zero mode by turning on the 23rd and 24th switches (SW23, SW24) in response to the 23rd and 24th clock signals (CLK23, CLK24) in the holding period, and turning off the 21st and 22nd switches (SW21, SW22) in response to the 21st and 22nd clock signals (CLK21, CLK22). Accordingly, the offset voltage, which is the difference between the input voltage (Vin) and the output voltage (Vout) of the second buffer circuit (20-2), is compensated (offset) by the offset voltage stored in the capacitor (Cs2), thereby outputting the output voltage (Vout) from which the offset voltage of the second operational amplifier (AMP2) is removed.

[0076] Referring to FIGS. 4 and 6, in the second horizontal period (H2), the first buffer circuit (20-1) can simultaneously perform the first chop state (A) operation of the chopping mode and the holding mode operation of the auto-zero mode. The second buffer circuit (20-2) can simultaneously perform the second chop state (B) operation of the chopping mode and the sampling mode operation of the auto-zero mode.

[0077] The first buffer circuit (20-1) can operate in the first chop state (A) of the chopping mode. In the holding period of the auto-zero mode, the first buffer circuit (20-1) can turn off the eleventh and twelfth switches (SW11, SW12) in response to the eleventh and twelfth clock signals (CLK11, CLK12), and turn on the thirteenth and fourteenth switches (SW13, 14) in response to the thirteenth and fourteenth clock signals (CLK13, CLK14). Accordingly, the offset voltage, which is the difference between the input voltage (Vin) and the output voltage (Vout) of the first buffer circuit (20-1), is compensated (offset) by the offset voltage stored in the capacitor (Cs1), thereby outputting the output voltage (Vout) from which the offset voltage of the first operational amplifier (AMP1) is removed.

[0078] The second buffer circuit (20-2) can operate in the second chop state (B) of the chopping mode. The second buffer circuit (20-2) can operate in the sampling mode of the auto-zero mode by turning on the 21st and 22nd switches (SW21, SW22) in response to the 21st and 22nd clock signals (CLK21, CLK22) in the sampling period, and turning off the 23rd and 24th switches (SW23, SW24) in response to the 23rd and 24th clock signals (CLK23, CLK24). Accordingly, the second capacitor (Cs2) of the second buffer circuit (20-2) can sample and store the offset voltage of the second operational amplifier (AMP2), which is the difference between the input voltage (Vin) and the output voltage (Vout).

[0079] FIG. 7 is an exemplary diagram showing a state in which a dual buffer circuit according to an embodiment illustrated in FIG. 1 operates in chopping mode, and FIG. 8 is an exemplary diagram showing a chopping mode driving waveform of a dual buffer circuit according to an embodiment illustrated in FIG. 7.

[0080] Referring to FIGS. 7 and 8, when the dual buffer circuit (10) operates only in chopping mode, only the first buffer circuit (20-1) may operate in chopping mode and the second buffer circuit (20-2) may be turned off.

[0081] The first buffer circuit (20-1) can operate in chopping mode by periodically switching between the first chop state (A) and the second chop state (B) every 2H in response to the first chopping clock (CP_CLK1) through the chopping switch unit (CP11, CP12).

[0082] In response to the 12th to 14th clock signals (CLK12, CLK13, CLK14), the 12th to 14th switches (SW12, SW13, SW14) of the first buffer circuit (20-1) can be turned on to operate in buffer mode, and in response to the 11th clock signal (CLK11), the 11th switch (SW11) can be turned off.

[0083] The auto-zero clock (AZ_CLK1, AZ_CLK2), the second chopping clock (CP_CLK2), and the 21st to 24th clock signals (CLK211 to CLK24) are deactivated, so that the second buffer circuit (20-2) can be turned off. Accordingly, the power consumption of the dual buffer circuit (10) can be reduced.

[0084] FIG. 9a and FIG. 9b are exemplary diagrams showing a state in which a dual buffer circuit according to an embodiment illustrated in FIG. 1 operates in a dual auto-zero mode, and FIG. 10 is an exemplary diagram showing a dual auto-zero mode driving waveform of a dual buffer circuit according to an embodiment illustrated in FIG. 9a and FIG. 9b.

[0085] Referring to FIGS. 9a, 9b and 10, both the first and second chopping clocks (CP_CLK1, CP_CLK2) are deactivated to a low voltage (VL), so that the chopping switch units (CP11, CP12, CP21, CP22) of the first and second buffer circuits (20-1, 20-1) can maintain the current path only in the first chop state (A).

[0086] Referring to FIG. 9a and FIG. 10, in the first horizontal period (H1), the first buffer circuit (20-1) can operate in a sampling mode of the auto-zero mode, and the second buffer circuit (20-2) can operate in a holding mode of the auto-zero mode.

[0087] Referring to FIG. 9b and FIG. 10, in the second horizontal period (H2), the first buffer circuit (20-1) can operate in the holding mode of the auto-zero mode, and the second buffer circuit (20-2) can operate in the sampling mode of the auto-zero mode.

[0088] Fig. 11 is an exemplary diagram showing the internal configuration of a first operational amplifier according to one embodiment of the present invention.

[0089] Referring to FIG. 11, a first operational amplifier (AMP1) according to one embodiment may include an input terminal (22), an amplification terminal (24), and an output terminal (20).

[0090] The first input terminal (VINP) may correspond to the non-inverting input terminal (+) of the operational amplifier (AMP1) illustrated in Fig. 1, and the second input terminal (VINN) may correspond to the inverting input terminal (-) of the operational amplifier (AMP1).

[0091] The input terminal (22) may include PMOS transistors (PM1, PM2) connected to the first and second input terminals (VINP, VINN), NMOS transistors (NM1, NM2) connected to the first and second input terminals (VINP, VINN), a PMOS transistor (PM3) to which a bias signal (VB1) is applied, and an NMOS transistor (NM3) to which a bias signal (VB2) is applied. The PMOS transistor (PM3) may be connected between a first power supply voltage (VDD) and the PMOS transistors (PM1, PM2) to supply a bias current. The PMOS transistor (NM3) may be connected in series between the first power supply voltage (VDD) and the NMOS transistors (NM1, NM2) to supply a bias current.

[0092] A chopping switch unit (CP11) connected between the first and second input terminals (VINP, VINN) and the input terminal (22) and controlled by a chopping clock (CP_CLK1) can be connected.

[0093] PMOS transistors (PM1, PM2) can generate a current corresponding to the voltage difference between the first and second input voltages (VINP, VINN) and supply the current to the amplifier stage. NMOS transistors (NM1, NM2) can generate a current corresponding to the voltage difference between the first and second input voltages (VINP, VINN) and supply the current to the amplifier stage.

[0094] The amplifier stage (24) may include a first current mirror composed of PMOS transistors (PM4, PM5), a first cascode circuit composed of PMOS transistors (PM6, PM7), a second current mirror composed of NMOS transistors (NM4, NM5), a second cascode circuit composed of NMOS transistors (NM6, NM7), a third bias circuit composed of PMOS and NMOS transistors (PM8, NM8), and a fourth bias circuit composed of PMOS and NMOS transistors (PM9, NM9). The amplifier stage (24) may include a chopping switch unit (CP12-1) connected between the first current mirror and the first cascode circuit and controlled by a chopping clock (CP_CLK1), and a chopping switch unit (CP12-2) connected between the second current mirror and the second cascode circuit and controlled by the chopping clock (CP_CLK1).

[0095] The PMOS transistors (PM4, PM5) of the first current mirror are connected to the NMOS transistors (NM1, NM2) of the input terminal (22), and can be connected between the supply line of the first power voltage (VDD) and the first cascode circuit. The first cascode circuit can be connected to the output terminal (26). The chopping switch unit (CP12-1) is connected between the first current mirror and the first cascode circuit, and can switch the current path in response to the chopping clock (CP_CLK1).

[0096] The NMOS transistors (NM4, NM5) of the second current mirror are connected to the PMOS transistors (PM1, PM2) of the input terminal (22), and can be connected between the second cascode circuit and the supply line of the second power voltage (VSS). The first cascode circuit can be connected to the output terminal (26). The chopping switch unit (CP12-2) is connected between the second current mirror and the second cascode circuit, and can switch the current path in response to the chopping clock (CP_CLK1).

[0097] The PMOS transistor (PM8) and the NMOS transistor (NM8) of the third bias circuit are connected between the PMOS transistor (PM6) of the first cascode circuit and the NMOS transistor (NM6) of the second cascode circuit, and can be controlled by the fifth and sixth bias voltages (VB5, VB6), respectively, to provide a bias current flowing from the first cascode circuit to the second cascode circuit.

[0098] The PMOS transistor (PM9) and the NMOS transistor (NM9) of the fourth bias circuit are connected between the PMOS transistor (PM7) of the first cascode circuit and the NMOS transistor (NM7) of the second cascode circuit, and can be controlled by the seventh and eighth bias voltages (VB7, VB8), respectively, to provide a bias current flowing from the first cascode circuit to the second cascode circuit.

[0099] The output stage (26) may include a pull-up PMOS transistor (PM10) and a pull-down NMOS transistor (NM10) connected to the amplifier stage (24). The pull-up PMOS transistor (PM10) is controlled by a first control voltage of the amplifier stage (24) and is connected between a first power supply voltage (VDD) supply line and an output terminal (Vout). The pull-down NMOS transistor (NM10) is controlled by a second control voltage of the amplifier stage (24) and is connected between the output terminal (Vout) and a second power supply voltage (VSS) supply line.

[0100] FIG. 12 is an exemplary diagram showing the configuration of a gamma voltage generation circuit according to one embodiment of the present invention, FIG. 13 is an exemplary diagram showing the configuration of a data driving circuit according to one embodiment of the present invention, and FIG. 14 is an exemplary diagram showing the configuration of a display device according to one embodiment of the present invention.

[0101] Referring to FIG. 12, a gamma voltage generation circuit (360) according to one embodiment may include a gamma buffer unit (362) and a resistor string (364), and may further include a switch control unit (30) according to one embodiment illustrated in FIG. 2.

[0102] The gamma buffer unit (362) may include a plurality of gamma buffer circuits (BGF to BF10) that respectively buffer and output a plurality of reference gamma voltages (GMA1 to GMA10). Each of the plurality of gamma buffer circuits (BGF to BF10) may utilize a dual buffer circuit (10) according to an embodiment. Each of the gamma buffer circuits (BGF to BF10) may simultaneously or selectively perform a dual auto-zero mode and a chopping mode using the dual buffer circuit (10) according to an embodiment, thereby removing offset voltage and noise components, thereby stably outputting output reference gamma voltages (GMA1 to GMA10) corresponding to each input reference gamma voltage (GMA1 to GMA10).

[0103] The resistor string (364) can divide a plurality of reference gamma voltages (GMA1 to GMA10) supplied from the gamma buffer unit (362) through resistors (R) to generate and output a plurality of gamma voltages (GMA1, GMA11, GMA12, ... GMA2, GMA21, GAM22, ... GMA10) corresponding to the grayscale voltages.

[0104] The dual buffer circuit (10) applied to each of the gamma buffer circuits (BGF to BF10) can perform double auto-zero mode operation and chopping mode operation simultaneously or selectively in response to a chopping enable signal (CP_EN) and an auto-zero enable signal (AZ_EN).

[0105] For example, in one embodiment, when the data driving circuit and the display device are in normal operation, the chopping enable signal (CP_EN) and the auto-zero enable signal (AZ_EN) are enabled (ON), so that the dual buffer circuit (10) of each of the gamma buffer circuits (BGF to BF10) can simultaneously perform the double auto-zero mode operation and the chopping mode operation as described above. Accordingly, the reference gamma voltage with the offset voltage and noise components removed can be used, thereby improving reliability.

[0106] In one embodiment, when the screen of the display device is off or during a period prior to normal operation, only the chopping enable signal (CP_EN) is enabled (ON), so that only one of the first and second buffer circuits (20-1, 20-2) of the dual buffer circuit (10) of each of the gamma buffer circuits (BGF to BF10) can operate in chopping mode, thereby reducing power consumption.

[0107] In one embodiment, when the display device is driven at a low frequency of about 1 Hz, only the auto-zero enable signal (AZ_EN) is enabled (ON), so that the first and second buffer circuits (20-1, 20-2) of the dual buffer circuit (10) can operate only in double auto-zero mode, thereby reducing power consumption.

[0108] Referring to FIG. 13, a data driving circuit (300) according to one embodiment may include a digital circuit unit (310) including a control unit (320), a shift register unit (330), and a latch unit (340), a gamma voltage generation circuit (360), a digital-to-analog converter (DAC) unit (370), and an output buffer unit (380). The data driving circuit (300) may be expressed as a source driving circuit.

[0109] The control unit (320) can receive image data (VD) and a data control signal (DCS), control the shift register (330), the latch unit (340), and the gamma voltage generation circuit (360), and supply the image data (VD) to the latch unit (340). The control unit (320) can supply an auto-zero enable signal (AZ_EN), a chopping enable signal (CP_EN), first and second chopping clock signals (CP_CLK1, CP_CLK2), and first and second auto-zero clock signals (AZ_CLK1, AZ_CLK2) to the switch control unit (30) of the gamma voltage generation circuit (360) described in FIG. 2.

[0110] The shift register unit (330) can sequentially output multiple sampling signals to the latch unit (340) while sequentially shifting the source start pulse supplied from the control unit (320) according to the source clock signal.

[0111] The latch unit (340) responds to a sampling signal of multiple channels sequentially input from the shift register unit (330), latches image data (VD) by channel in subpixel units, and can output the latched image data to the DAC unit (370).

[0112] The gamma voltage generation circuit (360) can generate multiple gamma voltages (GMAs) in which multiple reference gamma voltages (GMA1 to GMA10) are subdivided, as shown in FIG. 12, and output them to the DAC unit (370).

[0113] The DAC unit (370) can convert digital image data supplied from the latch unit (340) into an analog data signal using multiple gamma voltages (GMAs) and output it to the output buffer unit (380).

[0114] The output buffer unit (380) can buffer the data signal supplied from the DAC unit (370) by channel and output it to each of the multiple data lines (DL1 to DLm).

[0115] Fig. 14 is a block diagram schematically showing the configuration of a display device according to one embodiment.

[0116] A display device according to one embodiment may be any one of various display devices including a liquid crystal display device, an electroluminescent display device, a micro LED (Light Emitting Diode) display device, etc. The electroluminescent display device may be an organic light emitting diode (OLED) display device, a quantum-dot light emitting diode (QD) display device, or an inorganic light emitting diode (ILED) display device.

[0117] Referring to FIG. 14, the display device may include a display panel (100), a gate driving circuit (200), a data driving circuit (300), a timing control unit (400), etc. The gate driving circuit (200) and the data driving circuit (300) may be defined as a panel driver. The gate driving circuit (200), the data driving circuit (300), and the timing control unit (400) may be expressed as a display driving circuit.

[0118] The display panel (100) displays an image through a display area in which subpixels are arranged in a matrix form. Each subpixel is one of a red subpixel that emits red light, a green subpixel that emits green light, a blue subpixel that emits blue light, and a white subpixel that emits white light, and is independently driven by at least one thin film transistor (TFT). A unit pixel may be composed of a combination of two, three, or four subpixels of different colors. The subpixels of the display panel (100) may be connected to a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm).

[0119] The display panel (100) may further include a touch sensor screen that entirely overlaps the display area to sense a user's touch, and the touch sensor screen may be built into the panel (100) or placed on the display area of ​​the panel (100).

[0120] The timing control unit (400) can receive image data and synchronization signals from a host system (not shown). For example, the host system may be any one of a computer, a TV system, a set-top box, a tablet, a mobile phone, or a portable terminal system. The synchronization signal may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0121] The timing control unit (400) can generate a plurality of data control signals (DCS) using the supplied synchronization signals and timing setting information (start timing, pulse width, etc.) stored in the internal register and supply them to the data driving circuit (300), and can generate a plurality of gate control signals (GCS) and supply them to the gate driving circuit (200).

[0122] The timing control unit (400) can perform various image processing, such as brightness correction for reducing power consumption or image quality correction, on the supplied image data, and supply the image-processed data (VD) to the data driving circuit (300).

[0123] The gate driving circuit (200) is controlled according to a plurality of gate control signals (GCS) supplied from the timing control unit (400), and can individually drive the gate lines (GL1 to GLn) of the display panel (100). The gate driving circuit (200) can supply a scan signal of a gate-on voltage to each gate line (GL) during a driving period of the gate line, and can supply a gate-off voltage to the gate line during a non-driving period of the gate line.

[0124] The gate driving circuit (200) may be formed on a TFT substrate together with the TFT of each subpixel of the display panel (100) and built into the bezel area of ​​the display panel (100).

[0125] The data driving circuit (300) is controlled according to a data control signal (DCS) supplied from the timing control unit (400), and converts digital image data (VD) supplied from the timing control unit (400) into an analog data signal, and can supply the data signal to each of the data lines (DL1 to DLm) of the display panel (100). The data driving circuit (300) can convert digital image data into an analog data signal using gamma voltages generated from a built-in gamma voltage generation circuit (360).

[0126] As described above, the dual buffer circuit according to one embodiment of the present invention can stably output an output voltage corresponding to an input voltage by effectively removing offset voltage and noise components by simultaneously performing a dual auto-zero mode and a chopping mode.

[0127] A gamma voltage generation circuit and a data driving circuit having a dual buffer circuit according to one embodiment of the present invention can improve reliability by utilizing a reference gamma voltage from which an offset voltage and noise component are removed through the dual buffer circuit according to one embodiment.

[0128] A dual buffer circuit and a gamma voltage generation circuit and a data driving circuit having the same according to one embodiment of the present invention can reduce power consumption by having the dual buffer circuit operate in either a dual auto-zero mode or a chopping mode depending on a specific mode.

[0129] Those skilled in the art will appreciate that the present invention described above can be implemented in other specific forms without changing the technical idea or essential features thereof.

[0130] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

Claims

1. Includes a first buffer circuit and a second buffer circuit connected in parallel between the input terminal and the output terminal, Each of the above first buffer circuit and second buffer circuit An operational amplifier including first and second input terminals and an output node; A chopping switching unit connected to the above operational amplifier to control chopping mode operation; and A switch section connected to the above operational amplifier for controlling auto-zero mode operation is included, The above first buffer circuit and the above second buffer circuit Performing an operation of at least one of the above chopping mode and the above auto-zero mode, When the first buffer circuit and the second buffer circuit operate in the auto-zero mode, The first buffer circuit and the second buffer circuit are a dual buffer circuit that alternately performs a sampling period for sampling an offset in the auto-zero mode and a holding period for compensating for the offset.

2. In claim 1, The first buffer circuit and the second buffer circuit are a dual buffer circuit that performs the chopping mode operation and the auto-zero mode operation simultaneously.

3. In claim 1, A dual buffer circuit wherein one of the first buffer circuit and the second buffer circuit operates in the chopping mode and the other is turned off.

4. In claim 1, The chopping mode of each of the first and second buffer circuits is In the above chopping mode, a first chopping period providing a path of a first chop state and a second chopping period providing a path of a second chop state are included, A dual buffer circuit wherein each of the first chopping period and the second chopping period of the first buffer circuit overlaps with a portion of the first chopping period and a portion of the second chopping period of the second buffer circuit.

5. In claim 4, Each of the first and second chopping periods of the first buffer circuit is A dual buffer circuit overlapping the sampling period and holding period of the auto-zero mode of the first buffer circuit.

6. In claim 1, In claim 4, Each of the first and second chopping periods of the second buffer circuit is A dual buffer circuit overlapping the sampling period and holding period of the auto-zero mode of the second buffer circuit.

7. In claim 1, Each of the above first buffer circuit and second buffer circuit The chopping switch section connected to the input terminal and amplifier terminal of the above operational amplifier, respectively; A capacitor connected to the second input terminal of the above operational amplifier; A first switch connected between the input terminal and the capacitor; A second switch connected between the output node of the above operational amplifier and the second input terminal; a third switch connected between the capacitor and the output terminal; and A dual buffer circuit including a fourth switch connected between the output node of the above operational amplifier and the output terminal.

8. In claim 7, The chopping switch section of the first buffer circuit provides different current paths in the first chopping period and the second chopping period in response to the first chopping clock, Each of the first and second chopping periods of the first buffer circuit is A dual buffer circuit including a sampling period of the auto-zero mode in which the first and second switches of the first buffer circuit are turned on, and a holding period of the auto-zero mode in which the third and fourth switches of the first buffer circuit are turned on.

9. In claim 8, The chopping switch section of the second buffer circuit provides different current paths in the first chopping period and the second chopping period in response to the second chopping clock, Each of the first and second chopping periods of the second buffer circuit is A dual buffer circuit including a sampling period of the auto-zero mode in which the first and second switches of the second buffer circuit are turned on, and a holding period of the auto-zero mode in which the third and fourth switches of the second buffer circuit are turned on.

10. In claim 8, When the above first buffer circuit operates only in the chopping mode, A dual buffer circuit in which the first switch of the first buffer circuit is turned off and the second to fourth switches of the first buffer circuit are turned on.

11. In claim 9, When the first and second buffer circuits operate only in the auto-zero mode, The first sampling period during which the first and second switches of the first buffer circuit are turned on overlaps the second holding period during which the third and fourth switches of the second buffer circuit are turned on, A dual buffer circuit in which a first holding period in which the third and fourth switches of the first buffer circuit are turned on overlaps a second sampling period in which the first and second switches of the second buffer circuit are turned on.

12. In claim 9, The first timing at which the voltage level of the first chopping clock switches and the second timing at which the voltage level of the second chopping clock switches have a difference of the first horizontal period, A dual buffer circuit in which the first and second timings overlap with the blank period of the horizontal synchronization signal.

13. In claim 19, A dual buffer circuit in which the third timing at which the voltage levels of the first and second clocks, which respectively control the first and second switches of each of the first and second buffer circuits, are switched, and the fourth timing at which the voltage levels of the third and fourth clocks, which respectively control the third and fourth switches of each of the first and second buffer circuits, are switched do not overlap.

14. In claim 9, Receiving a chopping enable signal and an auto-zero enable signal, first and second auto-zero clocks, and the first and second chopping clocks; Selectively outputting the first and second chopping clock signals according to the chopping enable signal, A dual buffer circuit further comprising a switch control unit which generates and outputs eleventh to fourteenth clocks for controlling the first to fourth switches of the first buffer circuit, respectively, using the first auto-zero clock, in response to the auto-zero enable signal, and which generates and outputs twenty-first to twenty-fourth clocks for controlling the first to fourth switches of the second buffer circuit, respectively, using the second auto-zero clock.

15. A gamma buffer section including a plurality of gamma buffers that respectively buffer and output a plurality of reference gamma voltages; and It includes a resistor string that divides the plurality of reference gamma voltages output from the gamma buffer section and outputs a plurality of gamma voltages, A gamma voltage generation circuit, wherein each of the plurality of gamma buffers comprises a dual buffer circuit as described in any one of claims 1 to 14.

16. A gamma voltage generation circuit that divides multiple reference gamma voltages to output multiple gamma voltages; and It includes a digital-to-analog converter unit that converts digital data into an analog data signal and outputs it using the above multiple gamma voltages, A gamma buffer unit including a plurality of gamma buffers for respectively buffering and outputting the plurality of reference gamma voltages; and It includes a resistor string that divides the plurality of reference gamma voltages output from the gamma buffer section and outputs the plurality of gamma voltages, A data driving circuit wherein each of the plurality of gamma buffers comprises a dual buffer circuit as described in any one of claims 1 to 14.

Images