Systems and methods for row or column redundancy in in-memory computing arrays

Abstract

An in-memory computing architecture can include a compute-in-memory (CIM) array of computing cells, the CIM array comprising a plurality of rows and a plurality of columns, each computing cell including a memory cell, computing logic, and a capacitor for storing a result of computation. An in-memory computing architecture can include a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein a set of ADC channels of the plurality of ADC channels are defined as redundant ADC channels that are normally disabled. An in-memory computing architecture can include a selection circuit configured to, responsive to receiving an indication that one of the ADC channels has a defect, disabling a defective ADC channel and enabling one of normally disabled redundant ADC channels.

Description

SYSTEMS AND METHODS FOR ROW OR COLUMN REDUNDANCY IN IN-MEMORY COMPUTING ARRAYSCROSS REFERENCE TO RELATED APPLICATIONSThis Application claims priority to and the benefit of United States Provisional Patent Application Number 63 / 606,013, filed December 4, 2023.TECHNICAL FIELD

[0001] This disclosure relates to in-memory computing arrays, and in particular to row or column redundancy in in-memory computing arrays.DESCRIPTION OF THE RELATED TECHNOLOGY

[0002] Using in-memory computing for neural network acceleration is an emerging and innovative approach that leverages the unique properties of memory devices to enhance the speed and efficiency of neural network computations. Traditional neural network training and inference processes involve moving data back and forth between memory (RAM) and processing units (CPUs or GPUs), which can be a significant bottleneck in terms of speed and energy consumption. In-memory computing seeks to overcome these limitations by processing data directly within the memory itself.SUMMARY

[0003] In some aspects, the techniques described herein relate to an in-memory computing architecture, including: a compute-in-memory (CIM) array of computing cells, the CIM array including a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation; a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled; and a selection circuit configured to, responsive to an indication that one of the ADC channels of the plurality of ADC channels has a defect, disable a defective ADC channel and enable one of normally disabled redundant ADC channels.

[0004] In some aspects, the techniques described herein relate to an in-memorycomputing architecture, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured, responsive to the indication that one of the ADC channels has a defect, to direct bit-line signals for the defective ADC channel to an enabled redundant ADC channel, the at least one output selection circuit configured, responsive to receiving the indication that one of the ADC channels has a defect, deselect a digital output of the defective ADC channel and select a digital output of the enabled redundant ADC channel.

[0005] In some aspects, the techniques described herein relate to an in-memory computing architecture, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication that one of the ADC channels has a defect, shifts bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifts bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

[0006] In some aspects, the techniques described herein relate to an in-memory computing architecture, further including: a bit-line circuit configured to hold bit-lines associated with the defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

[0007] In some aspects, the techniques described herein relate to an in-memory computing architecture, the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicating that the defective ADC channel cannot be replaced.

[0008] In some aspects, the techniques described herein relate to an in-memory computing architecture, further including a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

[0009] In some aspects, the techniques described herein relate to an in-memory computing architecture, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

[0010] In some aspects, the techniques described herein relate to an in-memory computing architecture, wherein the defect detection module is configured to test theplurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

[0011] In some aspects, the techniques described herein relate to an in-memory computing architecture, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

[0012] In some aspects, the techniques described herein relate to an in-memory computing architecture, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.

[0013] In some aspects, the techniques described herein relate to a method for mitigating defects in a compute in-memory (CIM) array, the CIM array including: a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation, a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled, and a selection circuit configured to select and deselect the plurality of ADC channels, the method including: responsive to an indication that one of the ADC channels has a defect, disabling a defective ADC channel; and enabling one of normally disabled redundant ADC channels.

[0014] In some aspects, the techniques described herein relate to a method, including: responsive to the indication that one of the ADC channels has a defect, directing bit-line signals for a defective ADC channel to an enabled redundant ADC channel, and responsive to the indication that one of the ADC channels has a defect, deselecting a digital output of the defective ADC channel and selecting a digital output of the enabled redundant ADC channel.

[0015] In some aspects, the techniques described herein relate to a method, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder or ADC channels, the method including: responsive to the indication that one of the ADC channels has a defect, shifting bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifting bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

[0016] In some aspects, the techniques described herein relate to a method further including: holding bit-line signals associated with the defective ADC channel to a high- impedance state; and holding one or more column lines associated with the defective ADC channel in a discharged state.

[0017] In some aspects, the techniques described herein relate to a method, including: responsive to another indication that another one of the ADC channels has a defect, determining that none of the redundant ADC channels are available, and based on the determination, indicating that the defective ADC channel cannot be replaced.

[0018] In some aspects, the techniques described herein relate to a method, including: testing the plurality of ADC channels for defects, and responsive to detecting a defect, indicating an identity of a defective ADC channel.

[0019] In some aspects, the techniques described herein relate to a method, including: testing the plurality of ADC channels for defects at power up.

[0020] In some aspects, the techniques described herein relate to a method, including: testing the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

[0021] In some aspects, the techniques described herein relate to a method, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the method including: responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disabling the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

[0022] In some aspects, the techniques described herein relate to a method, including: disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells, and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computingcells to be directed to analog voltage driver circuits and word line driver circuits of the enabled redundant row of computing cells.

[0023] In some aspects, the techniques described herein relate to an in-memory computing (IMC) device, including: a compute-in-memory (CIM) array of computing cells, the CIM array including a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation; a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels comprises one or more redundant ADC channels normally disabled; and a selection circuit configured to, responsive to an indication from one of the ADC channels of the plurality of ADC channels, disable an ADC channel and enable one of normally disabled redundant ADC channels.

[0024] In some aspects, the techniques described herein relate to an IMC device, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured to, responsive to the indication, direct bit-line signals for the ADC channel subject to the indication to an enabled redundant ADC channel.

[0025] In some aspects, the techniques described herein relate to an IMC device, wherein the at least one output selection circuit, responsive to receiving the indication, is configured to deselect a digital output of the ADC channel subject to the indication and select a digital output of the enabled redundant ADC channel.

[0026] In some aspects, the techniques described herein relate to an IMC device, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication, is configured to shift bit-line signals for the ADC channel subject to the indication to an adjacent ADC channel, and to shift bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

[0027] In some aspects, the techniques described herein relate to an IMC device, further including: a bit-line circuit configured to hold bit-lines associated with a defective ADCchannel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

[0028] In some aspects, the techniques described herein relate to an IMC device, wherein the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicate that the defective ADC channel cannot be replaced.

[0029] In some aspects, the techniques described herein relate to an IMC device, further including a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

[0030] In some aspects, the techniques described herein relate to an IMC device, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

[0031] In some aspects, the techniques described herein relate to an IMC device, wherein the defect detection module is configured to test the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

[0032] In some aspects, the techniques described herein relate to an IMC device, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enable one of normally disabled redundant row of computing cells.

[0033] In some aspects, the techniques described herein relate to an IMC device, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to now be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1 depicts a block diagram of an example in-memory computing architecture.

[0035] FIG. 2 shows a block diagram of a compute in-memory array.

[0036] FIG. 3 shows an example circuit diagram of the computing cells discussed above in relation to FIG. 2.

[0037] FIG. 4A shows an example arrangement of compute in-memory array.

[0038] FIG. 4B depicts one approach to addressing defects in an ADC channel shown in FIG. 4A.

[0039] FIG. 5 shows another example CIM array employing another ADC channel replacement approach.

[0040] FIG. 6 shows another example CIM array employing an approach for replacing a defective row of computing cells.

[0041] FIG. 7 shows a block diagram of an example system for addressing defects in CIM arrays.

[0042] FIG. 8 shows a flow diagram of an example process for addressing defects in ADC channels in CIM arrays.

[0043] FIG. 9 shows a flow diagram of an example process for addressing defects in rows of computing cells in CIM arrays.

[0044] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0045] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0046] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual aspects described and illustrated herein has discrete components and features which can be readily separated from or combined with the features of any of the other several aspects without departing from the scope or spirit of the present disclosure.

[0047] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its stepsbe performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0048] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and / or materials in connection with which the publications are cited. All such publications and patents are herein incorporated by references as if each individual publication or patent were specifically and individually indicated to be incorporated by reference. Such incorporation by reference is expressly limited to the methods and / or materials described in the cited publications and patents and does not extend to any lexicographical definitions from the cited publications and patents. Any lexicographical definition in the publications and patents cited that is not also expressly repeated in the instant specification should not be treated as such and should not be read as defining any terms appearing in the accompanying claims. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided herein can be different from the actual publication dates, which can require independent confirmation.

[0049] While aspects of the present disclosure can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only and one of skill in the art will understand that each aspect of the present disclosure can be described and claimed in any statutory class.

[0050] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed compositions and methods belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0052] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0053] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub-ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0054] As used herein, the terms “about,” “approximate,” “at or about,” and“substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0055] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms can be defined elsewhere in the present disclosure.

[0056] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0057] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a proton beam degrader,” “a degrader foil,” or “a conduit,” includes, but is not limited to, two or more such proton beam degraders, degrader foils, or conduits, and the like.

[0058] The terms “configured for” or “configured to,” as used herein with respect to a specified operation or function, refer to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and / or arranged to perform the specified operation or function.

[0059] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0060] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0061] Unless otherwise specified, temperatures referred to herein are based on atmospheric pressure (i.e., one atmosphere).

[0062] In-memory Computing Architecture

[0063] FIG. 1 depicts a block diagram of an example in-memory computing architecture 100. The in-memory computing architecture 100 can be adapted, for example, to a scalable neural network accelerator architecture based on in-memory computing (IMC). However, the in-memory computing architecture 100 is not limited to neural network applications, and can be employed in numerous applications where high data throughput with low power consumption is desired. The in-memory computing architecture 100 includes a plurality of Compute In-Memory unit (CIMU) tiles 102. The plurality of CIMU tiles 102 are arranged in an array within the architecture. The plurality of CIMU tiles 102 can be individually enabled / disabled based on the computations to be carried out by the in-memory computing architecture 100. In examples where the in-memory computing architecture 100 can be used to implement neural networks, the neural networks can be mapped to one or more CIMU tiles of the plurality of CIMU tiles 102. The remainder of the CIMU tiles of the plurality of CIMU tiles 102 can be disabled to reduce power consumption.

[0064] The in-memory computing architecture 100 can include, in part, activation buffers 104, segmented weight buffers 106, and one or more phase-locked loops (PLLs) 108. The activation buffers 104 can provide signals representative of activations from previous stages of computation, for instance previous layers in a neural network. The segmented weight buffers 106 can provide data required for computation together with the activations / data from previous stages, for instance these weight buffers could store the weights of neural network layers. The one or more PLLs 108 can provide reference clock signals to various portions of the in-memory computing architecture 100. The in-memory computing architecture 100 can also include off-chip control elements 110 or interfaces for communication with off-chip processors or software to send and receive control or data signals. The off-chip interface 110 can, by itself or in concert with other elements, provide circuits and protocols for high-speed interfaces for wired or wireless connections involving data, control signals, or both, to other processors or other arrays of CIMU tiles, for example, enabling the in-memory computing architecture 100 to scale upward asdesired.

[0065] Each of the plurality of CIMU tiles 102 can include a plurality of CIMUs 112, an on-chip network 114, and a weight network 116. While FIG. 1 shows each of the plurality of CIMU tiles 102 including four CIMUs 112, this is only an example, and the CIMU tiles 102 can include fewer or more CIMUs 112. One or more of the CIMUs 112 can include a compute in-memory (CIM) array 118, compute dataflow buffers 120, programmable digital single instruction multiple data (SIMD) 122, and a programming and control module 124. The CIM array 118 can be an array of computing cells, discussed further below. The CIM array 118 can carry out computations based on data stored in the computing cells and data provided by the activation buffers 104. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. The CIM array 118 can carry out matrix operations between multi -bit operands, which is particularly useful in neural network computations where activations are multiplied with weights. In some such applications, the weights can be stored in the memory cells of the CIM array 118 and activations can be provided as input vectors. Each computing cell in the CIM array 118 can perform the multiplication operation between a 1 -bit weight and a portion of the input activation, which can be represented in digital or analog signal form. Some example computing cells can generate a result that is in the form of an electrical signal. For example, the computing cell can output an analog voltage that is representative of the computation result. In some other examples, the computing cell can output an electrical current that is representative of the computation result. The electrical signals of various computing cells can be accumulated and processed to generate the overall matrix multiplication result. For example, electrical signals representative of computation from all computing cells in a single column of the CIM array 118 can be accumulated to represent a portion of the computation. Accumulated electrical signals from multiple columns of computing cells of the CIM array 118 can be combined and processed to generate an overall matrix multiplication result. For instances where the electrical signal generated by the computing cells is an electrical current, the currents from various computing cells within a column can be summed to generate a representative accumulated electrical current. In instances where the electrical signal generated by the computing cell is an analog voltage, the analog voltage generated by each computing cell can be stored in capacitors within the computing cell and then accumulated as a voltagethat is representative of a portion of the overall matrix multiplication result. The accumulated result, whether an electrical current or an analog voltage, can be converted into digital form using analog to digital converters (ADCs) and further processed, stored, or passed on to other CIM arrays 118 for further computations.

[0066] The programmable digital SIMD 122 can have an instruction set for flexible element-wise operation and the compute dataflow buffers 120 can support wide range of neural network dataflows. Each CIMUs 112 can provide a high-level of configurability and can be abstracted into a software library of instructions for interfacing with a compiler (for allocating / mapping an application, neural network and the like to the architecture), and where instructions can thus also be added prospectively. That is, the library can include single / fused instructions such as element mult / add, h(») activation, (N-step convolutional stride + matrix-vector-multiplication (MVM) + batch norm. +h(») activation + max. pool), (dense + MVM) and the like. In various examples, h(») can indicate an activation function, including without limitation the rectified linear unit ReLU(x) function, the sigmoid function (o(x)), and other such functions. Max pooling, a downsampling technique for reducing spatial dimensions to maintain computational efficiency while retaining other important features of the CIMU array or the network, can also be a subject of the computation. The N-step convolutional stride can refer to the number of pixels or other information bits that a kernel or convolutional filter moves or glides across the input image during convolution to effect operations like feature detection, pattern recognition, blurring, image sharpening, image recognition, and the like.

[0067] The on-chip network 114 (OCN) can include routing channels within Network In / Out Blocks, and a Switch Block, which provides flexibility via a disjoint architecture as shown, for example, by the disjoint buffer switch 133 in the enlarged view of OCN 114. This flexibility, among other benefits, enables modules that are independent of one another to work in parallel. The OCN 114 works with configurable CIMU input / output ports to optimize data structuring to / from an in-memory computing engine, to maximize data locality across MVM dimensionalities and tensor depth / pixel indices. The OCN 114 routing channels can include bidirectional wire pairs as shown by the exemplary duodirectional pipelined routing structure 131 in the expanded view if the OCN 114, so as to ease repeater / pipeline-FF insertion, while providing sufficient density.

[0068] The in-memory computing architecture 100 can be used to implement a neural network (NN) accelerator, wherein a plurality of compute in memory units (CIMUs 112)are arrayed and interconnected using a very flexible on-chip network (OCN 114) wherein the outputs of one CIMU can be connected to or flow to the inputs of another CIMU or to multiple other CIMUs, the outputs of many CIMUs can be connected to the inputs of one CIMU, the outputs of one CIMU can be connected to the inputs of another CIMU and so on. The OCN 114 can be implemented as a single on-chip network, as a plurality of on-chip network portions, or as a combination of on-chip and off-chip network portions.

[0069] The CIMUs 112 can be surrounded by an on-chip network 114 for moving activations between CIMUs 112 (activation network) as well as moving weights from embedded L2 memory to CIMUs 112 (weight-loading interface). This has similarities with architectures used for coarse-grained reconfigurable arrays (CGRAs), but with cores providing high-efficiency MVM and element-wise computations targeted for neural network acceleration. Various options exist for implementing the on-chip network. The approach in FIG. 1 enables routing segments along a CIMU 112 to take outputs from that CIMU 112 and / or to provide inputs to that CIMU 112. In this manner data originating from any CIMU 112 can be routed to any CIMU 112, and any number of CIMUs 112.

[0070] Each CIMU 112 is associated with an input buffer (not shown) for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMU to generate thereby computed data comprising an output vector.

[0071] Each CIMU 112 is associated with a shortcut buffer (not shown), for receiving computational data from the on-chip network 114, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU 112 or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs 112 is maintained. At least some of the input buffers can be configured to impart a temporal delay to computational data received from the on-chip network 114 or from a shortcut buffer. The dataflow map can support pixel-level pipelining to provide pipeline latency matching.

[0072] The temporal delay imparted by a shortcut or input buffers comprises at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU 112, a control signal received from a dataflow controller, a control signal received from another CIMU 112, and a control signal generated by the CIMU 112 in response to the occurrence of anevent within the CIMU. In some aspects, at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs 112 in the array of CIMUs 112 can be configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching. The array of CIMUs 112 can also include parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers.

[0073] A least a subset of the CIMUs 112 can be associated with on-chip network 114 portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC. The application mapped onto the IMC comprises a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs 112 executing at a next layer, said parallel output computed data forming respective NN feature-map pixels.

[0074] The input buffer can be configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step, such as discussed above. The NN can comprise a convolution neural network (CNN), and the input buffer can be used to buffer a number of rows of an input feature map corresponding to a size or height of the CNN kernel.

[0075] The CIM array 118 in each CIMU 112 can perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BPB S) computing process in which single bit computations are performed using an iterative barrel shifting with column weighting process, followed by a results accumulation process.

[0076] FIG. 2 shows additional details of a portion of the in-memory computing architecture 100 shown in FIG. 1, and in particular, details of an example compute inmemory (CIM) array 200 and associated components. The CIM array 200 can be used, for example, to implement, in part, the CIM array 118 discussed above in relation to the in-memory computing architecture 100 shown in FIG. 1. In one example implementation the CIM array 200 can include a fully row / column-parallel (1152 row X 256 column) array of computing cells 202 of an in-memory-computing (IMC) macro enabling N-bit (5-bit) input processing. The number of rows (1152), the number or columns (256), and the number of bits (5-bit) of input shown in FIG. 2 are only examples, and any or all of these can be varied based on desired implementations. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR,etc.) or multiplication operations carried out between inputs. In some examples, the operands of the computation can be 1-bit each. In some other examples, one of the operands can be an analog signal (voltage or current) while the other operand can be a 1- bit operand stored in the memory cell.

[0077] The in-memory computing architecture 100, in some examples, can be utilized for matrix vector multiplication (MVM) operations, which dominate compute-intensive and data-intensive Al workloads, in a manner that reduces compute energy and data movement by orders of magnitude. This is achieved through efficient analog compute in the computing cells 202, and by thus accessing a compute result (e.g., inner product), rather than individual bits, from memory. But, doing so fundamentally instates an energy / throughput-vs.-SNR tradeoff, where going to analog introduces compute noise and accessing a compute result increases dynamic range (i.e., reducing SNR for given readout architecture). The computing cells 202, which store computational results in the form of a voltage in capacitors within the computing cells 202, can employ metal-fringing capacitors, which can achieve very low noise from analog nonidealities, and thus have the potential for extremely high dynamic range.

[0078] FIG. 2 shows a block diagram of the CIM array 200 including a 1152 (row) X 256 (col.) array of 10T (“ten transistor”) SRAM computing cells 202, which in this example are multiplying bit-cells (M-BCs) (such as, for example, a 10T M-BC 202, although the number of transistors of SRAM interface 204 and M-BCs 202 is implementationdependent and the circuit can use different numbers of transistors or other circuit elements without departing from the principles of the disclosure); peripheral circuits for standard writing / reading thereto (e.g., a bit line (BL) decoder 204 and 256 BL drivers 206-1 through 206-256 (collectively referred to as BL drivers 206), a word line (WL) or address decoder 208 and 1152 WL drivers 210-1 through 210-1152 (collectively referred to as WL drivers 210), and control block 212 for controlling the BL decoder 204 such as SRAM interface and the WL decoder 208); peripheral circuitry for providing 5-bit input-vector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 214-1 through 214- 1152 (collectively referred to as DRD DACs 214), and a corresponding controller 216); peripheral circuitry for digitizing the compute result from each column (e.g., 256 8-bit SAR ADCs 218-1 through 218-256 (collectively referred to as SAR ADCs 218), and column reset mechanisms 220-1 through 220-256 (collectively referred to as column reset mechanisms 220) (e.g., CMOS switches configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation, andallow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation).

[0079] In addition, the lower right portion of FIG. 2 depicts an example enlarged view of a representative one of the 256 8-bit ADCs, which includes various switch mechanisms ADCRST, ADCSMP and voltage designations VADCRST and VCMPR, the latter voltage designation connected in this example to a positive terminal of the comparator CMPR and the former voltage designation selectively applied via the ADCRST and ADCSMP switch to reset the comparator. The negative terminal of comparator CMPR receives a CL value when the circuit is activated. An output of comparator CMPR is coupled to SAR logic for outputting an 8-bit digital result. It will be appreciated, however, that the implementation details of the above circuits are representative in nature and that variations to the circuits are possible without departing from the scope or spirit of the present disclosure.

[0080] While writing / reading is typically performed row-by-row, MVM operations are typically performed by applying input-vector elements corresponding to neural -network input activations to all rows at once. That is, each DRD DAC 214j, in response to a respective 5-bit input-vector element Xj[4:0], generates a respective differential output signal (lAj / IAbj) which is subjected to a 1-bit multiplication with the stored weights (Aij / Abij) at each computing cells 202j in the corresponding row of computing cells 202, and accumulation through charge-redistribution across computing cells 202 capacitors on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective SAR ADCs 218 of each column.

[0081] FIG. 3 shows an example circuit diagram of the computing cells 202 discussed above in relation to FIG. 2. The computing cells 202 can include a highly dense structure for achieving weight storage and multiplication, thereby minimizing data-broad-cast distance and control signals within the context of i-row, j -column arrays implemented using such computing cells, such as the 1152 (row) X 256 (col.) CIM array 200 of 10T SRAM multiplying bit cells (M-BCs).

[0082] The exemplary computing cells 202 includes a six-transistor bit cell portion 222, a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 224, a first bit line (BLj) 227, a second bit line (BLbj) 228, and a compute line (CL) 230.

[0083] The six-transistor bit cell portion 222 is depicted as being located in a middle portion of the computing cells 202, and includes six transistors 226a-226f in this example. The 6-transistor bit cell portion 222 can be used for storage, and to read and write data.In one example, the 6-transistor bit cell portion 222 stores the filter weight. In some examples, data is written to the computing cells 202 through the word line (WL) 224, the first bit line (BL) 227, and the second bit line (BLb) 228.

[0084] The computing cells 202 can include a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW 1 is depicted as being controlled by a first stored signal Aij such that, when closed, the first switch SW1 couples one of the received differential output signals provided by the DRD DACs 214, illustratively IA, to a first terminal of the capacitor C. The second switch SW2 is depicted as being controlled by a second stored signal Abij such that, when closed, the second switch SW2 couples the other one of the received differential output signals (IA or lAb) of the corresponding DRD DACs 214, illustratively lAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to a compute line (CL) 230 via an output port 232 that provides a result of the computation of the computation cell 202. It is noted that in various other examples, the input signals provided to the first and second switches SW 1 and SW2 can comprise a fixed voltage (e.g., Vaa), ground, or some other voltage level.

[0085] The computing cells 202, including the first SW1 and second SW2 switches, can implement computation on the data stored in the six-transistor bit cell portion 222. The result of a computation is sampled as charge on the capacitor C. According to various implementations, the capacitor C can be is positioned above the computing cell 202 and utilize no additional area on the circuit. In some implementations, a logic value of either Vdd or ground is stored on the capacitor C. In other implementations, the voltage stored on the capacitor C can comprise a positive or negative voltage in accordance with the operation of the first and the second switches SW 1 and SW2, and the output voltage level generated by the corresponding DRD DACs 214 as shown in FIG. 2.

[0086] Thus, with continued reference to FIG. 3, the value that is stored on the capacitor C is highly stable, since the capacitor C value is either driven up to the supply voltage or down to ground. In some examples, the capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, the capacitor C can be about 0.1 femto-Farhads (fF) to about 10 fF or can be about 1.2 fF. MOM capacitors have very good matching temperature and process characteristics, and thus have highly linear and stable compute operations. Note that other types of logic functions can be implemented using the computing cells 202 by changing the way the transistors 226a-226f and / or the first and the second switches SW 1 and SW2 are connected and / or operated during the reset and evaluation phases of operation. The six-transistor bit cell portion 222 can be implementedusing different numbers of transistors and can have different architectures. In some examples, the six-transistor bit cell portion 222 can be a SRAM, DRAM, MRAM, or an RRAM.

[0087] Row-Column Redundancy In In-Memory Computing Arrays

[0088] The in-memory computing architecture 100 discussed in relation to FIGS. 1-3, when implemented on an integrated circuit, can suffer from defects arising from fabrication, packaging, or during operation. In some instances, these defects can affect critical operations of the in-memory computing architecture 100, thereby rendering the entire integrated circuit unusable. For example, if any of the computing cells 202 within the CIM array 200 suffer from a stuck-at fault, the computational results produced by the CIM array 200 can be fatally compromised.

[0089] One approach to mitigating the presence of defects in the in-memory computing architecture 100 can include building redundancy within the components. In particular, in one aspect, the architecture can include components that remain redundant but can be employed to replace defective components. As discussed herein, the in-memory computing architecture 100 can include redundant channels with respect to the row dimension or the column dimension within the CIM array 200. These redundant channels can normally remain disabled when no defect is detected. However, once a defect is detected, selection circuitry within the in-memory computing architecture 100 can redirect signals such that one of the redundant channels can operate in place of the defective channel.

[0090] FIG. 4A shows an example arrangement of compute in-memory (CIM) array 400. In particular, FIG. 4 A shows a plurality of analog-to-digital channels 401-1 - 401-65 (collectively referred to as “a plurality of ADC channels 401”). Each ADC channel of the plurality of ADC channels 401 can include an ADC and one or more columns of computing cells. For example, in FIG. 4A, a first ADC channel 401-1 includes four columns of computing cells labeled 404-1 - 404-4 and one ADC 402-1. It should be noted that each ADC channel can include only one column of computing cells, or include a plurality of columns of computing cells, an example of which is shown in FIG. 4A. Each column of computing cell can include computing cells of an in-memory computing (IMC) array. For example, the columns of computing cells 404-1 - 404-4 can include columns of computing cells 202 in the CIM array 200. Referring to FIG. 2, the CIM array 200 includes 256 columns of computing cells 202. Each column of computing cells 202 is coupled in this example implementation with one ADC. Digitized outputs of ADCsassociated with multiple columns can then be processed (e.g., weight adjusted) to arrive at the final result. In such instances, an ADC channel can then include one ADC and one column of computing cells 202. However, in some other examples, such as that shown in FIG. 4A, one ADC can receive results from multiple columns, and the ADC can simultaneously process the analog signals received from multiple columns to generate the final result. The output of each ADC can be a multi-bit digital value that corresponds to the analog signals received from the output ports of the one or more columns of computing cells. For example, the ADC 402-1 in the first ADC channel 401-lin FIG. 4A generates a first 8-bit digital value 416-1 that corresponds to the analog signals from the output ports of computing cells in columns 404-1 - 404-4. Similarly, the ADC 402-64 of the ADC channel 401-64 generates an 8-bit digital value 416-2 that corresponds to the analog signals from the output ports of computing cells in columns 404-253 - 404-256.

[0091] A set of ADC channels of the plurality of ADC channels can be defined as redundant ADC channels. For example, referring to FIG. 4A, the ADC channel 401-65 can be designated as a redundant ADC channel, which structurally is similar to the other ADC channels of the plurality of ADC channels 401. For example, the redundant ADC channel 401-65 is coupled with four columns 404-257 - 404-260 of computing cells and generates an 8-bit digital value 416-65 that corresponds to the analog signals from the output ports of computing cells in the columns 404-257 - 404-260. While FIG. 4A shows only one redundant ADC channel, it should be noted that the set of ADC channels that are defined or designated as redundant ADC channels can include one or more ADC channels.

[0092] The CIM array 400 can include a selection circuit 410. When no defects have been indicated, the ADC channels defined or designated as redundant ADC channels can be normally disabled, which can mean at least that an output of the normally disabled ADC channel is not considered. For example, the selection circuit 410 can select which ones of the ADC outputs from the plurality of ADC channels 401 are selected to form the Y1-Y64 ADC outputs. For the ADC channels that are defined or designated as redundant, the selection circuit 410 can not consider or can deselect the output of the ADC 402-65 of the ADC channel 401-65 from contributing to the 64 ADC outputs Y1-Y64. Instead, the ADC outputs Y1-Y64 are selected from the plurality of ADC channels 401 that are not defined or designated as redundant ADC channels. In FIG. 4 A, the plurality of ADC channels 401 that are not currently indicated as defective and are not the ones designated or defined as redundant ADC channels are the ADC channels 401-1 - 401-64, the outputsof which the selection circuit 410 selects as the Y1-Y64 ADC outputs.

[0093] Responsive to an indication that one of the ADC channels has a defect, the selection circuit 410 can be configured to disable a defective ADC channel and enable one of the normally disabled redundant ADC channels. FIG. 4B depicts one approach to addressing defects in an ADC channel shown in FIG. 4A. For example, in response to an indication of a defect within an ADC channel of the plurality of ADC channels 401, the selection circuit 410 can disable the defective ADC channel and enable one of the normally disabled redundant ADC channels. As shown in FIG. 4B, the ADC channel 401-64 is indicated as being defective. The defect could be in any portion of the ADC channel for the entire ADC channel to be defective. Thus, if any one of the computing cells 202 in the four columns of computing cells of the ADC channel 401-64 were defective, the entire ADC channel 401-64 can be regarded as being defective. The selection circuit 410 can disable the defective ADC channel 401-64 by at least not considering its ADC output or deselecting its output from contributing to the 64 ADC outputs Y1-Y64. In some examples, disabling an ADC channel can also include powering down the ADC channel, pulling the output of the ADC channel to ground, redirecting inputs normally directed to the ADC channel to another ADC channel, or any action that could generally render the ADC channel non-operational. With reference to FIG. 4B, the selection circuit 410 deselects the output of the defective ADC channel 401-64 from contributing to the 64 ADC outputs Y1-Y64.

[0094] The selection circuit 410 also can enable one of the normally disabled redundant ADC channels by selecting its output to contribute to the 64 ADC outputs Y1-Y64. Enabling an ADC channel can also include powering up the ADC channel, providing input signals to the ADC channel that were previously provided to the defective ADC channel, enabling the ADC channel outputs, or any action that generally renders the ADC channel operational.

[0095] The selection circuit 410 can include at least one input selection circuit 411 and at least one output selection circuit 412. The selection circuit 410 is configured to interchange signals between an ADC channel 401 and redundant ADC channel 401-65 at bit-line interfaces via at least on input selection circuit 411 and ADC output interfaces via at least one output selection circuit 412. Responsive to an indication that one of the ADC channels 401 has a defect, the at least one input selection circuit 411 directs bit-line signals for the defective ADC channel 401 to an enabled redundant ADC channel 401, and the at least one output selection circuit 412 deselects a digital output of the defectiveADC channel 401-64 and selects a digital output of the enabled redundant ADC channel 401-65.

[0096] In the example shown in FIG. 4B, a defect is detected at the ADC channel 401-64 (corresponding to ADC 402-64) within a column 404-255 of computing cells. The plurality of ADC channels 401 are connected to selection circuit 410. Selection circuit 410 enables redundant ADC channel 401-65 (corresponding to ADC 402-65) and interchanges signals between ADC channel 401-64 and redundant ADC channel 401-65 to maintain 64 ADC outputs as indicated in FIG. 4B. One example of bit-line inputs can be the BLi / BLbi pairs shown in the BL driver 206-1 in FIG. 2, where the BLi / BLbi bit- line inputs are coupled with the computing cells 202 of the leftmost column of the CIM array 200.

[0097] With continued reference to FIG. 4B, the at least one input selection circuit 411 can selectively allow bit-line signals directed to a defective ADC channel to be redirected to an enabled redundant ADC channel. In one example, the at least one input selection circuit 411 can include a plurality of demultiplexers corresponding to the plurality of ADC channels, each of which receives as an input the bit-line signals for the respective column. One output of the demultiplexer can be coupled with the respective ADC channel, while one or more other outputs can be coupled with one or more redundant ADC channels. During operation when the ADC channel is not defective, the demultiplexer can be controlled to direct the bit-line pair signals to the non-defective ADC channel. However, upon an indication that the ADC channel is defective, the demultiplexer can be controlled to redirect the bit-line pair signals to a selected and enabled redundant ADC channel. In this manner, the bit-line signals directed to any ADC channel can be redirected to any redundant ADC channel. Similarly, the at least one output selection circuit 412 can include a plurality of multiplexers corresponding to the plurality of outputs Y1-Y64, where for each multiplexer, the inputs are coupled with the respective ADC channel as well as redundant ADC channels. During operation where no defect is indicated, the multiplexer can be controlled to select the output from the respective ADC channel. However, if a defect is indicated, the multiplexer can deselect the output from the defective ADC channel and instead select the output from an enabled redundant ADC channel to be provided to the corresponding digital output from Y1-Y64. In some other examples, switching networks can be employed for one or both of the at least one input selection circuit 411 or the output selection circuit 412 to allow the signal redirection from any of the ADC channels to the redundant ADC channels.

[0098] FIG. 5 shows another example CIM array 500 employing another ADC channel replacement approach. The CIM array 500 can include a plurality of ADC channels, in particular ADC channels 501-1 - 501-10 (collectively referred to as “a plurality of ADC channels 501”). The plurality of ADC channels 501 includes a set of redundant channels. In the example shown in FIG. 5, the plurality of ADC channels 501 have two ADC channels 501-9 - 501-10 as redundant ADC channels. The plurality of ADC channels 501 can be similar to the plurality of ADC channels 401 discussed in relation to the compute in-memory array 400 shown in FIG. 4A and FIG. 4B, and can include among other common components, the ADCs and the one or more columns of computing cells in each ADC channel.

[0099] The plurality of ADC channels 501 are arranged in series such that the redundant ADC channels 501-9 - 501-10 located at one end of the remainder of the plurality of ADC channels 501. In the example of FIG. 5, the redundant ADC channels 501-9 - 501-10 are located at the right end of the remainder of the plurality of ADC channels 501. In an alternate example, the redundant ADC channels 501-9 - 501-10 can be located at the left end of the remainder of the plurality of ADC channels 501. The CIM array 500 shown in FIG. 5 includes only eight active ADC channels. This, of course, is only an example with reduced number of ADC channels shown merely for simplifying illustration of the concepts.

[0100] FIG. 5 depicts a selection circuit 510 that includes input multiplexers 511-1 — 511- 9 (collectively referred to as “at least one input selection circuit 511”) and output multiplexers 512-1 - 512-8 (collectively referred to as “at least one output selection circuit 512”). The CIM array 500 receives bit-line input signals BL 1 / B Lb 1 to BL8 / BLb8, corresponding to the eight active ADC channels. The BL / BLb bit-line signals can represent the plurality of bit-line signal pairs provided to the one or more columns in each of the ADC channels. The BLl / BLbl bit-line signals are directly provided to the first ADC channel 501-1 and as inputs to the next two adjacent input multiplexers. For example, the BLl / BLbl bit-line signals are also provided as inputs to the input multiplexer 511-1 and 511-2. The bit-line input signals BL2 / BLb2 are provided as input to the input multiplexer 511-1 and additionally to two adjacent input multiplexers 511-2 and 511-3. Similarly, the bit-line input signals BL3 / BLb3 are provided as input to the input multiplexer 511-2 and additionally to two adjacent input multiplexers 511-3 and 511-4, and so on such that the last bit-line pair BL8 / BLb8, is provided as an input to the multiplexer 511-7 and additionally to two input multiplexers 511-8 and 511-9. The outputof the multiplexers 511-1 to 511-9 are provided as inputs to the ADC channels 501-2 to 501-9, respectively. The at least one output selection circuit 512 includes eight output multiplexers 512-1 - 512-8 respectively corresponding to the eight multi -bit outputs Yl- Y8. Each output multiplexer in this example can receive, as inputs, outputs of three ADC channels. For example, the output multiplexer 512-1 receives as inputs, outputs of the ADC channel 501-1, the ADC channel 501-2, and the ADC channel 501-3. Similarly, the output multiplexer 512-8 receives as inputs, outputs of the ADC channel 501-8, the ADC channel 501-9, and the ADC channel 501-10.

[0101] When no defects are indicated in the CIM array 500, the redundant ADC channels 501-9 and 501-10 remain disabled. The at least one input selection circuit 511 is configured such that the input multiplexer 511-1 allows the BL2 / BLb2 bit-line signals to pass through to the ADC channel 501-2, the input multiplexer 511-2 allows the BL3 / BLb3 bit-line signals to pass through to the ADC channel 501-3, and so on until the input multiplexer 511-7 allows the BL8 / BLb8 bit-line signals to the ADC channel 501-8. The input multiplexers 511-8 and 511-9 outputs are disabled or placed in a high-impedance state, thereby providing no signals to the normally disabled redundant ADC channels 501- 9 and 501-10. The at least one output selection circuit 512 is configured such that the digital output of the ADC channel 501-1 is provided at the Y1 output, the digital output of the ADC channel 501-2 is provided to the Y2 output, and so on until the digital output of the ADC channel 501-8 is provided to the Y8 output.

[0102] The selection circuit 510, responsive to an indication that one of the ADC channels 501 has a defect, can shift bit-line signals for the defective ADC channel 501 to an adjacent ADC channel 501, and shift bit-line signals for the adjacent ADC channel to the next adjacent ADC channel and so on until bit-line signals of a last of the enabled ADC channel 501 are shifted to an adjacent enabled redundant ADC channel 501.

[0103] For example, if a defect is indicated in ADC channel 501-6, the selection circuit 510 will shift bit-line signals BL6 / BLb6 for ADC channel 501-6 to ADC channel 510-7, bit-line signals BL7 / BLb7 for ADC channel 501-7 to ADC channel 510-8, and bit-line signals BL8 / BLb8 for ADC channel 501-8 to redundant ADC channel 510-9. In particular, the output of input multiplexer 511-5, which provides inputs to the defective ADC channel 501-6, is disabled or placed into a high-impedance state. Further, the next adjacent input multiplexer 511-6 is configured to select the BL6 / BLb6 bit-line signals (instead of the BL7 / BLb7, as previously selected) to be provided to the ADC channel 501-7, which is the next non-defective ADC channel adjacent to the defective ADCchannel 501-6. Similarly, the input multiplexer 511-7 is configured to select the BL7 / BLb7 bit-line signals for the ADC channel 501-8, and the input multiplexer 511-8 is configured to select the BL8 / BLb8 bit-line signals for the ADC channel 501-9. In addition, the previously disabled redundant ADC channel 501-9 is enabled.

[0104] With regard to the output signals, the at least one output selection circuit 512 can shift receiving digital outputs from the next adjacent ADC channels. For example, the output multiplexer 512-6 is configured to deselect the output from the defective ADC channel 501-6 and instead select the digital output of the next adjacent ADC channel 501- 7 as the output Y6. Similarly, the output multiplexer 512-7 is configured to deselect digital output from the ADC channel 501-7 (which is now output as Y6), and instead select the digital output of the ADC channel 501-8 as the output Y7. In addition, the output multiplexer 512-8 is configured to deselect the digital output from the ADC channel 501-8 (which is now output as Y7), and instead select the digital output of the now enabled redundant ADC channel 501-9 as the output Y8. In this manner, the inputs and the outputs for all ADC channels that were previously enabled and positioned after the defective ADC channels are shifted by one ADC channel such that the signals associated with the last of the enabled ADC channels are shifted to the adjacent enabled redundant ADC channel.

[0105] If there is an indication that another one of the ADC channels 501 has a defect, the selection circuit 510 determines if an additional redundant ADC channel 501 is available. If an additional redundant ADC channel 501 is available, the selection circuit 510 shifts bit-line signals for the defective ADC channel 501 to an adjacent ADC channel 501, and shifts bit-line signals for the adjacent ADC channel to the next adjacent ADC channel and so on until bit-line signals of a last of the enabled ADC channels 401 are shifted to an adjacent enabled redundant ADC channel 501. If none of the additional redundant ADC channels 501 are available, the selection circuit 510 indicates that the defective ADC channel 501 cannot be replaced.

[0106] FIG. 6 shows another example CIM array 600 employing an approach for replacing a defective row of computing cells. FIG. 6 depicts a plurality of rows of computing cells 602. The plurality of rows of computing cells 602 includes a set of redundant rows of computing cells that are normally disabled. In the example shown in FIG. 6, the plurality of rows of computing cells 602 are depicted as rows of computing cells 602-1 - 602-10 with rows of computing cells 602-9 - 602-10 being redundant rows of computing cells. FIG. 6 depicts row selection circuit 604 that includes at least oneinput selection circuit 605 (shown in this example as input multiplexers 605-1 - 605-9). Based on an indication that a row of computing cells 602 of the plurality of rows of computing cells 602 has a defect, the row selection circuit 604 disables the defective row of computing cells 602 and enables one of normally disabled redundant row of computing cells 602 (here, one of computing cells 602-9 or 602-10). In an example, disabling a defective row of computing cells 602 includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells 602 and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cells 602 to analog voltage driver circuits and write enable driver circuits of the redundant row of computing cells 602.

[0107] In the approach shown in FIG. 6, based on an indication that one of the rows of computing cells 602 has a defect, the selection circuit 604 shifts word-line (one of WL0[0] - WL0[7]) and lA / IAb (one of IA / IAb[0] - IA / IAb[7]) signals for the defective row of computing cells 602 to an adjacent row of computing cells 602, and shifts word-line and lA / IAb signals for the adjacent row of computing cells 602 to the next adjacent row of computing cells 602 and so on until word-line and lA / IAb signals of a last of the enabled rows of computing cells 602 are shifted to an adjacent enabled redundant row of computing cells 602.

[0108] For example, if a defect is indicated in row of computing cells 602-6, the selection circuit 604 will shift word-line and lA / IAb signals for row of computing cells 602-6 to row of computing cells 602-7, word-line and lA / IAb signals for row of computing cells 602-7 to row of computing cells 602-8, and word-line and lA / IAb signals for row of computing cells 602-8 to redundant row of computing cells 602-9. The arrangement of the multiplexers 605-1 - 605-9 can be similar to the arrangement discussed above in relation to the at least one input selection circuit 511 shown in FIG. 5.

[0109] If there is another indication that one of the rows of computing cells 602 has a defect, the selection circuit 604 determines if an additional redundant row of computing cells 602 is available. If an additional redundant row of computing cells 602 is available, the selection circuit 604 shifts word-line and lA / IAb signals for the defective row of computing cells 602 to an adjacent row of computing cells 602, and shifts word-line and lA / IAb signals for the adjacent row of computing cells 602 to the next adjacent row of computing cells 602 and so on until word-line and lA / IAb signals of a last of the enabled rows of computing cells 602 are shifted to an adjacent enabled redundant row of computing cells 602. If no additional redundant rows of computing cells 602 areavailable, the selection circuit 604 indicates that the defective row of computing cells 602 cannot be replaced.

[0110] In some examples, the selection circuit 604 can be similar to the selection circuit 410 discussed above in relation to compute in-memory array 400 shown in FIG. 4A- and FIG. 4B. That is, the selection circuit 604 can have the capability of redirecting the wordline signals and the lA / IAb signals from a defective row of computing cells 602 directly to a redundant row of computing cells 602. In this case, the selection circuit 604, can include demultiplexers that can selectively direct the word-line signals and the lA / IAb signals to an appropriate redundant row of computing cells 602. However, additional or different circuit components can also be possible for performing one or more of the abovedescribed functions without departing from the principles of the disclosure.[OHl] In additional examples, the example architecture described herein includes a bit- line circuit to hold bit-lines associated with a defective ADC channel 401 to a high impedance state; and a column line circuit to hold one or more column lines associated with the defective ADC channel 401 in a discharged state. The example architecture described herein also includes a defect detection module to test the plurality of ADC channels 401 for defects, and upon detecting a defect, indicating an identity of the defected ADC channel 401. The defect detection module is configured to test the plurality of ADC channels 401 for defects at power up, after a threshold number of read or write operations to the CIM array, or a combination thereof.

[0112] FIG. 7 shows a block diagram of an example system 700 including the selection circuit 702, the CIM array 704, a defect indication register 706, and a defect detection module 714. The selection circuit 702 can include a controller 708, an input selection circuit 710 and an output selection circuit 712. In some examples, the controller 708 can be the SRAM control block 212 discussed in relation to FIG. 2. In some other examples, the controller 708 can be a separate standalone controller. In yet other examples, the SRAM control block 212 and a separate controller 708 can work in combination. The controller 708 (and / or the SRAM control block 212) can be a microcontroller, a microprocessor, an application specific integrated circuit, a field programmable gate array, etc., and can send control signals to the input selection circuit 710 and the output selection circuit 712 to redirect the input signals and the output data appropriately. The controller 708 can read the defect indication register 706 to determine whether any of the ADC channels or rows of computing cells in the CIM array 704 are defective. The defect indication register 706 can be a location in memory that can be written into by the defectdetection module 714. In some examples, the defect indication register 706 can include one bit associated with each ADC channel or a row of computing cell in the CIM array 704, and the defect detection module 714 can write into the appropriate bit location to indicate that the corresponding ADC channel or a corresponding row of computing cells is defective. In some instances, the defect indication register 706 can be written into and read by software that carries out defect detection. The controller 708 can then repeatedly read the defect indication register 706 to receive an indication of any defects, and in response, controller 708 can control the input selection circuit 710 and the output selection circuit 712 to redirect signals to redundant ADC channels or redundant rows of computing cells. The controller 708 can also write to the register to indicate that one or more of the redundant ADC channels or redundant computing rows have been used, or indicate that no redundant ADC channels or redundant rows of computing cells are available for use and that any defective ADC channels or defective rows of computing cells cannot be replaced.

[0113] The input selection circuit 710 can be similar to the at least one input selection circuit 411 discussed in relation to the compute in-memory array 400 shown in FIG. 4A and FIG. 4B, or the at least one input selection circuit 511 discussed above in relation to the CIM array 500 shown in FIG. 5, or the selection circuit 604 discussed above in relation to the CIM array 600 shown in FIG. 6. The output selection circuit 712 can be similar to the at least one output selection circuit 412 discussed above in relation to the compute inmemory array 400 shown in FIG. 4A and FIG. 4B, or the at least one output selection circuit 512 discussed above in relation to the CIM array 500 shown in FIG. 5. The controller 708 can send signals to one or more demultiplexer or multiplexers or other circuitry to control the functionality of these selection circuits. The controller 708 can also send control signals to bit-line circuitry and column line circuitry to control the appropriate states of the defective ADC channels.

[0114] In some examples, the defect detection module 714 can be a built-in-self-test (BIST) module that can carry out testing of the CIM arrays and detect defects. In some other examples, the defect detection can be carried out in software external to the chip on which he CIM array is built, and the defect detection module 714 can be an interface module to the external software to read and write to the defect indication register 706. In some examples, the defect detection module 714 and / or the software carrying out defect detection can test the plurality of ADC channels for defects at power up. In some examples, the defect detection module 714 and / or the software carrying out defectdetection can test the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array. In some such examples, the CIM array can increment a counter stored in the defect indication register 706, or some other memory location accessible by the defect detection module 714 and / or the software carrying out the testing. The defect detection module 714 and / or the software can monitor the counter, and after the counter reaches a threshold value, testing of the plurality of ADC channels can be carried out. The CIM array 704 can include any one of the CIM arrays discussed herein. In some examples, the selection circuit 702 can directly receive indications of defects in one or more ADC channels or rows of computing cells as signals from the defect detection module 714 or from CIM arrays.

[0115] FIG. 8 shows a flow diagram of an example process 800 for replacing defective ADC channels. The process 800 can be executed by the selection circuits discussed herein and for example by the controller 708 of the selection circuit 702 shown in FIG. 7. The process 800 includes responsive to an indication that one of the ADC channels has a defect, disabling a defective ADC channel (802) and responsive to an indication that one of the ADC channels has a defect, enabling one of normally disabled redundant ADC channel (804). As discussed above in relation to the CIM array 400 and CIM array 500 shown in FIGS. 4A-5, the CIM array can include a plurality of ADC channels. Each ADC channel including an ADC and one or more columns of computing cells, where each ADC receives analog signals from the output ports of the one or more columns of computing cells and generates a corresponding digital output, and where a set of ADC channels of the plurality of ADC channels are defined as redundant ADC channels that are normally disabled. Responsive to an indication that one of the ADC channels is defective, such as for example, reading the status of the ADC channels in the defect indication register 706, the selection circuit can disable the defective ADC channel and enable one of the normally disabled redundant defective ADC channels. In this manner, the defective ADC channel operations can be carried out by the now enabled redundant ADC channel.

[0116] FIG. 9 shows a flow diagram of an example process 900 for replacing defective rows of computing cells. The process 900 can be executed by the selection circuits discussed herein and for example by the controller 708 of the selection circuit 702 shown in FIG. 7. The process 900 includes responsive to an indication that one of the plurality of rows of computing cells has a defect, disabling the defective row of computing cells (902) and responsive to the indication that one of the plurality of rows of computing cells has a defect, enabling one of normally disabled redundant row of computing cells (904).As discussed herein in relation to FIG. 6, the CIM array 600 can include a plurality of rows of computing cells 602-1 - 602-10, which include a set of redundant rows of computing cells 602-1 - 602-10 that are normally disabled. Responsive to the indication that one of the plurality of rows of computing cells is defective, such as for example, reading the status of the rows of computing cells in the defect indication register 706, the selection circuit can disable the defective row of computing cells and enable one of normally disabled redundant row of computing cells. In this manner, the operations of the defective row of computing cells can be carried out by the now enabled redundant row of computing cells.ASPECTS OF THE DISCLOSURE

[0117] The present disclosure will be better understood upon reading the following numbered aspects, which should not be confused with the claims. Each of the numbered aspects described below can, in some instances, be combined with aspects described elsewhere in the disclosure. The following listing of example aspects is supported by the disclosure provided herein.

[0118] Aspect 1. An in-memory computing architecture, including: a compute-inmemory (CIM) array of computing cells, the CIM array including a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation; a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled; and a selection circuit configured to, responsive to an indication that one of the ADC channels of the plurality of ADC channels has a defect, disable a defective ADC channel and enable one of normally disabled redundant ADC channels.

[0119] Aspect 2. The in-memory computing architecture of any one of Aspects 1- 11, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured, responsive to the indication that one of the ADC channels has a defect, to direct bit-line signals for the defective ADC channel to an enabled redundant ADC channel, the at least one output selection circuit configured, responsive to receiving the indication that one of the ADCchannels has a defect, to deselect a digital output of the defective ADC channel and select a digital output of the enabled redundant ADC channel.

[0120] Aspect 3. The in-memory computing architecture of any one of Aspects 1- 11, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication that one of the ADC channels has a defect, shifts bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifts bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

[0121] Aspect 4. The in-memory computing architecture of any one of Aspects 1- 11, further including: a bit-line circuit configured to hold bit-lines associated with the defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

[0122] Aspect 5. The in-memory computing architecture of any one of Aspects 1- 11, further including: a bit-line circuit configured to hold bit-lines associated with the defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

[0123] Aspect 6. The in-memory computing architecture of any one of Aspects 1- 11, the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicate that the defective ADC channel cannot be replaced.

[0124] Aspect 7. The in-memory computing architecture of any one of Aspects 1- 11, further including a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

[0125] Aspect 8. The in-memory computing architecture of any one of Aspects 1- 11, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

[0126] Aspect 9. The in-memory computing architecture of any one of Aspects 1- 11, wherein the defect detection module is configured to test the plurality of ADCchannels for defects after a threshold number of read or write operations to the CIM array.

[0127] Aspect 10. The in-memory computing architecture of any one of Aspects 1- 11, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

[0128] Aspect 11. The in-memory computing architecture of any one of Aspects 1- 10, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.

[0129] Aspect 12. A method for mitigating defects in a compute in-memory (CIM) array, the CIM array including: a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation, a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled, and a selection circuit configured to select and deselect the plurality of ADC channels, the method including: responsive to an indication that one of the ADC channels has a defect, disabling a defective ADC channel; and enabling one of normally disabled redundant ADC channels.

[0130] Aspect 13. The method of any one of Aspects 12-22 including: responsive to the indication that one of the ADC channels has a defect, directing bit-line signals for a defective ADC channel to an enabled redundant ADC channel, and responsive to the indication that one of the ADC channels has a defect, deselecting a digital output of the defective ADC channel and selecting a digital output of the enabled redundant ADC channel.

[0131] Aspect 14. The method of any one of Aspects 12-22 wherein the plurality ofADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder or ADC channels, the method including: responsive to the indication that one of the ADC channels has a defect, shifting bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifting bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

[0132] Aspect 15. The method of any one of Aspects 12-22 further including: holding bit-line signals associated with the defective ADC channel to a high-impedance state; and holding one or more column lines associated with the defective ADC channel in a discharged state.

[0133] Aspect 16. The method of any one of Aspects 12-22 further including: holding bit-line signals associated with the defective ADC channel to a high-impedance state; and holding one or more column lines associated with the defective ADC channel in a discharged state.

[0134] Aspect 17. The method of any one of Aspects 12-22 including: responsive to another indication that another one of the ADC channels has a defect, determining that none of the redundant ADC channels are available, and based on the determination, indicating that the defective ADC channel cannot be replaced.

[0135] Aspect 18. The method of any one of Aspects 12-22 including: testing the plurality of ADC channels for defects, and responsive to detecting a defect, indicating an identity of a defective ADC channel.

[0136] Aspect 19. The method of any one of Aspects 12-22 including: testing the plurality of ADC channels for defects at power up.

[0137] Aspect 20. The method of any one of Aspects 12-22 including: testing the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

[0138] Aspect 21. The method of any one of Aspects 12-22 wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the method including: responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disabling the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

[0139] Aspect 22. The method of any one of Aspects 12-21, including: disablinganalog voltage driver circuits and word line driver circuits associated with the defective row of computing cells, and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cells to be directed to analog voltage driver circuits and word line driver circuits of the enabled redundant row of computing cells.

[0140] Aspect 23. An in-memory computing (IMC) device, including: a compute-inmemory (CIM) array of computing cells, the CIM array including a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation^ plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels comprise one or more redundant ADC channels normally disabled; and a selection circuit configured to, responsive to an indication from one of the ADC channels of the plurality of ADC channels, disable an ADC channel and enable one of normally disabled redundant ADC channels.

[0141] Aspect 24. The IMC device of any one of Aspects 23-33, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured to, responsive to the indication, direct bit-line signals for the ADC channel subject to the indication to an enabled redundant ADC channel.

[0142] Aspect 25. The IMC device of any one of Aspects 23-33, wherein the at least one output selection circuit, responsive to receiving the indication, is configured to deselect a digital output of the ADC channel subject to the indication and select a digital output of the enabled redundant ADC channel.

[0143] Aspect 26. The IMC device of any one of Aspects 23-33, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication, is configured to shift bit-line signals for the ADC channel subject to the indication to an adjacent ADC channel, and to shift bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundantADC channel.

[0144] Aspect 27. The IMC device of any one of Aspects 23-33, further including: a bit-line circuit configured to hold bit-lines associated with a defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

[0145] Aspect 28. The IMC device of any one of Aspects 23-33, the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicate that the defective ADC channel cannot be replaced.

[0146] Aspect 29. The IMC device of any one of Aspects 23-33, further including a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

[0147] Aspect 30. The IMC device of any one of Aspects 23-33, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

[0148] Aspect 31. The IMC device of any one of Aspects 23-33, wherein the defect detection module is configured to test the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

[0149] Aspect 32. The IMC device of any one of Aspects 23-33, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enable one of normally disabled redundant row of computing cells.

[0150] Aspect 33. The IMC device of any one of Aspects 23-32, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to now be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.

[0151] The examples disclosed herein are illustrative and not limiting in nature. Details disclosed with respect to the methods described herein included in one example or aspect can be applied to other examples and aspects. Any aspect of the present disclosure thathas been described herein can be disclaimed, i.e., exclude from the claimed subject matter whether by proviso or otherwise.

[0152] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. An in-memory computing architecture, comprising: a compute-in-memory (CIM) array of computing cells, the CIM array comprising a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation; a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled; and a selection circuit configured to, responsive to an indication that one of the ADC channels of the plurality of ADC channels has a defect, disable a defective ADC channel and enable one of normally disabled redundant ADC channels.

2. The in-memory computing architecture of claim 1, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured, responsive to the indication that one of the ADC channels has a defect, to direct bit-line signals for the defective ADC channel to an enabled redundant ADC channel, the at least one output selection circuit configured, responsive to receiving the indication that one of the ADC channels has a defect, to deselect a digital output of the defective ADC channel and select a digital output of the enabled redundant ADC channel.

3. The in-memory computing architecture of claim 1, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication that one of the ADC channels has a defect, shifts bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifts bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-linesignals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

4. The in-memory computing architecture of claim 2, further comprising: a bit-line circuit configured to hold bit-lines associated with the defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

5. The in-memory computing architecture of claim 3, further comprising: a bit-line circuit configured to hold bit-lines associated with the defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

6. The in-memory computing architecture of claim 1, the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicate that the defective ADC channel cannot be replaced.

7. The in-memory computing architecture of claim 1, further comprising a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

8. The in-memory computing architecture of claim 7, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

9. The in-memory computing architecture of claim 7, wherein the defect detection module is configured to test the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

10. The in-memory computing architecture of claim 1, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row ofcomputing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

11. The in-memory computing architecture of claim 10, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.

12. A method for mitigating defects in a compute in-memory (CIM) array, the CIM array comprising: a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation, a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels includes redundant ADC channels that are normally disabled, and a selection circuit configured to select and deselect the plurality of ADC channels, the method comprising: responsive to an indication that one of the ADC channels has a defect, disabling a defective ADC channel; and enabling one of normally disabled redundant ADC channels.

13. The method of claim 12, comprising: responsive to the indication that one of the ADC channels has a defect, directing bit-line signals for a defective ADC channel to an enabled redundant ADC channel, and responsive to the indication that one of the ADC channels has a defect, deselecting a digital output of the defective ADC channel and selecting a digital output of the enabled redundant ADC channel.

14. The method of claim 12, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder or ADC channels, the method comprising: responsive to the indication that one of the ADC channels has a defect, shifting bit-line signals for the defective ADC channel to an adjacent ADC channel, and shifting bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

15. The method of claim 13, further comprising: holding bit-line signals associated with the defective ADC channel to a high- impedance state; and holding one or more column lines associated with the defective ADC channel in a discharged state.

16. The method of claim 14, further comprising: holding bit-line signals associated with the defective ADC channel to a high- impedance state; and holding one or more column lines associated with the defective ADC channel in a discharged state.

17. The method of claim 12, comprising: responsive to another indication that another one of the ADC channels has a defect, determining that none of the redundant ADC channels are available, and based on the determination, indicating that the defective ADC channel cannot be replaced.

18. The method of claim 12, comprising: testing the plurality of ADC channels for defects, and responsive to detecting a defect, indicating an identity of a defective ADC channel.

19. The method of claim 18, comprising: testing the plurality of ADC channels for defects at power up.

20. The method of claim 18, comprising: testing the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

21. The method of claim 12, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the method comprising: responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disabling the defective row of computing cells and enabling one of normally disabled redundant row of computing cells.

22. The method of claim 21, comprising: disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells, and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cells to be directed to analog voltage driver circuits and word line driver circuits of the enabled redundant row of computing cells.

23. An in-memory computing (IMC) device, comprising: a compute-in-memory (CIM) array of computing cells, the CIM array comprising a plurality of rows and a plurality of columns, each computing cell including a memory cell and an output port for providing an analog signal representing a result of computation; a plurality of analog to digital converter (ADC) channels, each ADC channel including an ADC and one or more columns of computing cells from the plurality of columns of computing cells, wherein each ADC receives analog signals from the output ports of computing cells of the one or more columns of computing cells and generates a corresponding digital output, wherein a set of ADC channels of the plurality of ADC channels comprise one or more redundant ADC channels normally disabled; and a selection circuit configured to, responsive to an indication from one of the ADC channels of the plurality of ADC channels, disable an ADC channel and enable one of normally disabled redundant ADC channels.

24. The IMC device of claim 23, wherein the selection circuit includes at least one input selection circuit and at least one output selection circuit, the at least one input selection circuit configured to, responsive to the indication, direct bit-line signals for the ADC channel subject to the indication to an enabled redundant ADC channel.

25. The IMC device of claim 24, wherein the at least one output selection circuit, responsive to receiving the indication, is configured to deselect a digital output of the ADC channel subject to the indication and select a digital output of the enabled redundant ADC channel.

26. The IMC device of claim 23, wherein the plurality of ADC channels are arranged in series such that the redundant ADC channels are positioned at one end of a remainder of ADC channels, wherein the selection circuit, responsive to the indication, is configured to shift bit-line signals for the ADC channel subject to the indication to an adjacent ADC channel, and to shift bit-line signals for the adjacent ADC channel to a next adjacent ADC channel one or more times until bit-line signals of a last of the enabled ADC channel are shifted to an adjacent enabled redundant ADC channel.

27. The IMC device of claim 24, further comprising: a bit-line circuit configured to hold bit-lines associated with a defective ADC channel to a high-impedance state; and a column line circuit configured to hold one or more column lines associated with the defective ADC channel in a discharged state.

28. The IMC device of claim 23, the selection circuit configured to, responsive to another indication that another one of the ADC channels has a defect, determine that none of the redundant ADC channels are available, and based on the determination, indicate that the defective ADC channel cannot be replaced.

29. The IMC device of claim 23, further comprising a defect detection module configured to test the plurality of ADC channels for defects, and upon detecting a defect, indicate an identity of a defective ADC channel.

30. The IMC device of claim 29, wherein the defect detection module is configured to test the plurality of ADC channels for defects at power up.

31. The IMC device of claim 29, wherein the defect detection module is configured to test the plurality of ADC channels for defects after a threshold number of read or write operations to the CIM array.

32. The IMC device of claim 23, wherein the plurality of rows of computing cells includes a set of redundant rows of computing cells that are normally disabled, the selection circuit is configured to, responsive to an indication that a row of computing cells of the plurality of rows of computing cells has a defect, disable the defective row of computing cells and enable one of normally disabled redundant row of computing cells.

33. The IMC device of claim 32, wherein disabling the defective row of computing cells includes disabling analog voltage driver circuits and word line driver circuits associated with the defective row of computing cells and switching signals previously directed to the analog voltage driver circuits and the word line driver circuits of the disabled row of computing cell to now be directed to analog voltage driver circuits and word line driver circuits of the redundant row of computing cells.

Images