Array substrate and display apparatus

Abstract

An array substrate and a display apparatus. The array substrate comprises a substrate (20); the substrate (20) comprises a display area (AA) and a non-display area (BB) surrounding the display area (AA); the display area (AA) comprises at least one first transistor (21); the first transistor (21) comprises a first active portion (17), a first conductive portion (16) and a second conductive portion (18); the non-display area (BB) comprises at least one second transistor (22); the second transistor (22) comprises a second active portion (25), a third conductive portion (26) and a fourth conductive portion (24); the first active portion (17) and the second active portion (25) are both located at a semiconductor layer; the first conductive portion (16) and the third conductive portion (26) are located at different conductive layers; within the plane perpendicular to the array substrate, the second conductive portion (18) and the fourth conductive portion (24) are respectively located on two opposite sides of the semiconductor layer; and the second conductive portion (18) is in a floating state.

Description

Array substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are a common type of display. LCDs use two polarized materials with a liquid crystal solution (liquid crystal) between them. Applying a voltage across the two polarized materials causes the liquid crystal to deflect. The degree of deflection can be controlled by controlling the applied voltage. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate and a display device.

[0006] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, the substrate including a display area and a non-display area surrounding the display area; the display area includes at least one first transistor, the first transistor including a first active portion, a first conductive portion, and a second conductive portion; the non-display area includes at least one second transistor, the second transistor including a second active portion, a third conductive portion, and a fourth conductive portion; the first active portion and the second active portion are both located in a semiconductor layer, and the first conductive portion and the third conductive portion are located in different conductive layers;

[0007] In a plane perpendicular to the array substrate, the second conductive portion and the fourth conductive portion are respectively located on two opposite sides of the semiconductor layer; and the second conductive portion is in a floating state.

[0008] In an exemplary embodiment, the non-display area includes a gate driving circuit, the gate driving circuit is configured to be electrically connected to the gate line of the display area, and the gate driving circuit includes the at least one second transistor.

[0009] In an exemplary embodiment, the non-display area includes at least one of an electrostatic discharge circuit, a test circuit, and a demultiplexer circuit; and the electrostatic discharge circuit, the test circuit, and the demultiplexer circuit all include the at least one second transistor.

[0010] In an exemplary embodiment, the first conductive portion is a gate of the first transistor, the second conductive portion and the first conductive portion are located on opposite sides of the first active portion, and an orthographic projection of the second conductive portion on a plane where the substrate is located at least partially overlaps with an orthographic projection of the first active portion on the plane where the substrate is located;

[0011] The third conductive portion is a gate of the second transistor, the fourth conductive portion and the third conductive portion are respectively located on opposite sides of the second active portion, and an orthographic projection of the fourth conductive portion on the plane where the substrate is located at least partially overlaps with an orthographic projection of the second active portion on the plane where the substrate is located;

[0012] The voltages applied by the second conductive part and the fourth conductive part are the same or different.

[0013] In an exemplary embodiment, the fourth conductive portion is electrically connected to the first conductive portion, and the fourth conductive portion and the first conductive portion apply the same voltage.

[0014] In an exemplary embodiment, the voltage of the second conductive part is lower than the voltage of the first conductive part.

[0015] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, the substrate including a display area and a non-display area surrounding the display area; the display area includes at least one first transistor, the first transistor including a first conductive portion, a first active portion, a second conductive portion, and a fifth conductive portion; the second conductive portion and the fifth conductive portion are disposed in the same layer; the second conductive portion is located on a side of the first conductive portion away from the substrate; and the second conductive portion is in a floating state.

[0016] In an exemplary embodiment, an absolute value of a difference between a voltage applied by the second conductive part and a voltage applied by the fifth conductive part is greater than an absolute value of a difference between a voltage applied by the second conductive part and a voltage applied by the first conductive part.

[0017] In an exemplary embodiment, the display area further includes at least one data line, and the at least one data line is disposed in the same layer as the second conductive portion.

[0018] In an exemplary embodiment, the at least one data line is electrically connected to the at least one first transistor via the fifth conductive portion; and the orthographic projection of the at least one data line on the plane where the substrate is located includes the orthographic projection of the fifth conductive portion on the plane where the substrate is located.

[0019] In an exemplary embodiment, the display area further includes a gate insulating layer, and the gate insulating layer is located on a side of the first active portion away from the substrate; the gate insulating layer includes at least one first opening, and the fifth conductive portion is located within the at least one first opening.

[0020] In an exemplary embodiment, an orthographic projection of the at least one data line on the plane where the substrate is located at least partially overlaps with an orthographic projection of the at least one first opening on the plane where the substrate is located.

[0021] In an exemplary embodiment, the orthographic projection of the at least one data line on the plane where the substrate is located includes the orthographic projection of the at least one first opening on the plane where the substrate is located.

[0022] In an exemplary embodiment, the at least one first opening exposes a portion of the surface of the first active portion away from the substrate, and the fifth conductive portion contacts a portion of the surface of the first active portion away from the substrate.

[0023] In an exemplary embodiment, the display area further includes at least one common electrode and at least one pixel electrode, and the at least one common electrode and the at least one pixel electrode are both located on a side of the gate insulating layer away from the substrate, and an orthographic projection of the at least one common electrode on a plane where the substrate is located at least partially overlaps with an orthographic projection of the at least one pixel electrode on the plane where the substrate is located;

[0024] The gate insulating layer further includes at least one second opening, and the at least one pixel electrode is electrically connected to the at least one first transistor via the at least one second opening.

[0025] In an exemplary embodiment, the display area further includes at least one gate line, and the at least one gate line is provided in the same layer as the first conductive portion; the first active portion includes a first segment, a second segment, and a third segment that are connected to each other; a first end of the first segment is connected to a first end of the second segment, and a second end of the first segment extends along a second direction; a second end of the second segment extends along the first direction, and a first end of the third segment is connected to a second end of the second segment, and a second end of the third segment extends along the second direction; the first direction intersects the second direction;

[0026] The orthographic projection of the at least one first opening on the plane where the substrate is located is located within the orthographic projection of the first segment on the plane where the substrate is located, the orthographic projection of the at least one second opening on the plane where the substrate is located is located within the orthographic projection of the third segment on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on the same side of the gate line.

[0027] In an exemplary embodiment, the display area further includes at least one gate line, and the at least one gate line is provided in the same layer as the first conductive portion; the first active portion includes a first segment and a second segment connected to each other; the first segment extends along a first direction, a first end of the second segment is connected to one end of the first segment, and a second end of the second segment extends along a second direction; the first direction intersects the second direction;

[0028] Wherein, the orthographic projection of the at least one first opening on the plane where the substrate is located is located within the orthographic projection of the first segment on the plane where the substrate is located, the orthographic projection of the at least one second opening on the plane where the substrate is located is located within the orthographic projection of the second segment on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on both sides of the gate line.

[0029] In an exemplary embodiment, the display area further includes at least one gate line, and the at least one gate line is provided in the same layer as the first conductive portion; the first active portion includes a first segment and a second segment connected to each other; the first segment extends along a first direction, a first end of the second segment is connected to one end of the first segment, and a second end of the second segment extends along a third direction, the first direction is perpendicular to the second direction, and the third direction is different from both the first direction and the second direction;

[0030] Wherein, the orthographic projection of the at least one first opening on the plane where the substrate is located is located within the orthographic projection of the first segment on the plane where the substrate is located, the orthographic projection of the at least one second opening on the plane where the substrate is located is located within the orthographic projection of the second segment on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on both sides of the gate line.

[0031] In an exemplary embodiment, the display area further includes at least one gate line, and the at least one gate line is provided in the same layer as the first conductive portion; the first active portion includes a first segment, a second segment, and a third segment that are connected to each other; a first end of the first segment is connected to a first end of the second segment, a second end of the first segment extends in a direction opposite to the first direction, and a second end of the second segment extends in a third direction, the first direction is perpendicular to the second direction, and the third direction is different from both the first direction and the second direction; a first end of the third segment is connected to a second end of the second segment, and a second end of the third segment extends in the second direction;

[0032] In which, the orthographic projection of the at least one first opening on the plane where the substrate is located is located within the orthographic projection of the first segment on the plane where the substrate is located; the orthographic projection of the at least one second opening on the plane where the substrate is located is located within the orthographic projection of the third segment on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on both sides of the gate line.

[0033] On the other hand, an embodiment of the present disclosure provides a display device, which includes the array substrate, opposing substrate and liquid crystal layer described in any of the above embodiments; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0034] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0035] Summary of the Figures

[0036] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0037] FIG1A is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0038] FIG1B is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0039] FIG2 is a schematic partial top view of a display area of ​​an array substrate according to an embodiment of the present disclosure;

[0040] FIG2A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to an embodiment of the present disclosure;

[0041] FIG3A is a schematic diagram of a partial top view of a display area of ​​an array substrate according to an embodiment of the present disclosure; ...

[0042] FIG3B is a second schematic partial top view of the display area of ​​the array substrate according to an embodiment of the present disclosure;

[0043] FIG3C is a third schematic top view of a portion of the display area of ​​the array substrate according to an embodiment of the present disclosure;

[0044] FIG3D is a fourth schematic top view of a portion of the display area of ​​the array substrate according to an embodiment of the present disclosure;

[0045] FIG4 is a schematic partial top view of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0046] 4A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0047] FIG5A is a schematic diagram of a partial top view of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0048] FIG5B is a second schematic partial top view of the display area of ​​the array substrate according to another embodiment of the present disclosure;

[0049] FIG5C is a third schematic top view of a portion of the display area of ​​an array substrate according to another embodiment of the present disclosure;

[0050] FIG5D is a fourth schematic top view of a portion of the display area of ​​the array substrate according to another embodiment of the present disclosure;

[0051] FIG6 is a schematic partial top view of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0052] 6A is a schematic partial cross-sectional view of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0053] FIG7A is a first schematic partial top view of a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0054] FIG7B is a second schematic partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure;

[0055] FIG7C is a third schematic top view of a portion of the display area of ​​an array substrate according to another embodiment of the present disclosure;

[0056] FIG7D is a fourth schematic top view of a portion of the display area of ​​the array substrate according to another embodiment of the present disclosure;

[0057] FIG8 is a schematic partial top view of a display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0058] 8A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0059] FIG9A is a schematic diagram of a partial top view of a display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0060] FIG9B is a second schematic partial top view of the display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0061] FIG9C is a third schematic top view of a portion of the display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0062] FIG9D is a fourth schematic top view of a portion of the display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0063] FIG10 is a schematic partial top view of a display area of ​​an array substrate according to an exemplary embodiment of the present disclosure;

[0064] FIG10A is a schematic partial cross-sectional view of a display area of ​​an array substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG11 is a partial top view of a display area of ​​an array substrate according to another exemplary embodiment of the present disclosure;

[0066] FIG11A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to another exemplary embodiment of the present disclosure;

[0067] FIG12 is a partial top view of a display area of ​​an array substrate according to another exemplary embodiment of the present disclosure;

[0068] FIG12A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to another exemplary embodiment of the present disclosure;

[0069] FIG13 is a partial schematic top view of a display area of ​​an array substrate according to yet another exemplary embodiment of the present disclosure;

[0070] FIG13A is a partial cross-sectional schematic diagram of a display area of ​​an array substrate according to yet another exemplary embodiment of the present disclosure;

[0071] FIG14 is a schematic top view of a portion of a non-display area of ​​an array substrate according to an embodiment of the present disclosure;

[0072] FIG14A is a partial cross-sectional schematic diagram of a non-display area of ​​an array substrate according to an embodiment of the present disclosure;

[0073] FIG15 is a partial cross-sectional schematic diagram of a non-display area of ​​an array substrate according to another embodiment of the present disclosure;

[0074] 16A to 16H are schematic diagrams showing a process for preparing a display area of ​​an array substrate according to an embodiment of the present disclosure;

[0075] 17A to 17C are schematic diagrams showing a process for preparing a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0076] 18A to 18C are schematic diagrams showing a process for preparing a display area of ​​an array substrate according to another embodiment of the present disclosure;

[0077] 19A to 19C are schematic diagrams showing a process for preparing a display area of ​​an array substrate according to yet another embodiment of the present disclosure;

[0078] FIG20 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure;

[0079] FIG21 is a characteristic test simulation curve diagram of the first transistor.

[0080] Reference numerals:

[0081] AA-display area, BB-non-display area, B1-first frame area, B2-second frame area;

[0082] 10-pixel electrode, 21-first transistor, 22-second transistor, DL-data line, GL-gate line, 20-substrate, 11-first insulating layer, 12-second insulating layer, 12-1-second insulating layer initial pattern, 13-third insulating layer, 14-fourth insulating layer, 15-fifth insulating layer, 16-first conductive portion, 17-first active portion, 17-1-first region, 17-2-second region, 17-3-first channel region, 171-first segment, 172-second segment, 173-third section, 18-second conductive portion, 19-fifth conductive portion, 23-pixel connecting electrode, 24-fourth conductive portion, 25-second active portion, 25-1-second channel region, 25-2-third region, 25-3-fourth region, 26-third conductive portion, 27-first connecting electrode, 28-second connecting electrode, 29-second gate, 30-common electrode, 301-hollow area, 1-opposing substrate, 2-liquid crystal layer, 3-black matrix, 4-color filter layer, 5-array substrate.

[0083] Details

[0084] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0085] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0086] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0087] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0088] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0089] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0090] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0091] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be interchanged.

[0092] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0093] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0094] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0095] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0096] An embodiment of the present disclosure provides an array substrate. The array substrate includes a substrate, the substrate including a display area and a non-display area surrounding the display area; the display area includes at least one first transistor, the first transistor including a first active portion, a first conductive portion, and a second conductive portion; the non-display area includes at least one second transistor, the second transistor including a second active portion, a third conductive portion, and a fourth conductive portion; the first active portion and the second active portion are both located in a semiconductor layer, and the first conductive portion and the third conductive portion are located in different conductive layers;

[0097] In a plane perpendicular to the array substrate, the second conductive portion and the fourth conductive portion are respectively located on two opposite sides of the semiconductor layer; and the second conductive portion is in a floating state.

[0098] The array substrate provided in the embodiment of the present disclosure optimizes the positional relationship of the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion relative to the semiconductor layer by setting the structure of the first transistor and the second transistor, which is beneficial for adjusting the first transistor to a positive threshold voltage and is beneficial for improving the sand phenomenon in the display area.

[0099] Figure 1A is a schematic front view of an array substrate according to one embodiment of the present disclosure. As shown in Figure 1A , the array substrate may include a display area AA and a non-display area BB located around the display area AA. The non-display area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0100] In one exemplary embodiment, as shown in FIG1A , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0101] In an exemplary embodiment, as shown in FIG1A , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area obscured by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area surrounds the opening area and does not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0102] In an exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. As shown in FIG1A , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG1A ), and the pixel electrode 10 and the common electrode of the sub-pixel may overlap in their orthographic projections on the substrate. The common electrode of the plurality of sub-pixels in the display area AA may be an integral structure. For example, the common electrode may be located on a side of the pixel electrode 10 close to the substrate. The sub-pixel may also include a first transistor 21. The first transistor 21 may be adjacent to the intersection of the data line DL and the gate line GL. The first transistor 21 may include a first gate, a first electrode, and a second electrode. The first gate electrode can be electrically connected to the gate line GL, the first electrode of the first transistor 21 can be electrically connected to the data line DL, and the second electrode can be electrically connected to the pixel electrode 10 of a sub-pixel. The first transistor 21 can be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0103] In an exemplary embodiment, the second border area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a second transistor. The second transistor may include a second gate, a third electrode, and a fourth electrode. In the present disclosure, the third electrode may be a drain electrode and the fourth electrode may be a source electrode, or the third electrode may be a source electrode and the fourth electrode may be a drain electrode.

[0104] In an exemplary embodiment, the non-display area BB may further include at least one of an electrostatic discharge circuit, a test circuit, and a demultiplexer circuit. The electrostatic discharge circuit, the test circuit, and the demultiplexer circuit may each include at least one second transistor. The demultiplexer is a device that recovers the composite signal from the multiplexed signal and restores these signals to their respective independent channels. The electrostatic discharge circuit may be configured to prevent electrostatic damage to the array substrate by eliminating static electricity.

[0105] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the pixel electrode and common electrode are both located on one side of the array substrate. In the TN and VA modes, the pixel electrode and common electrode are respectively arranged on opposite sides of the liquid crystal layer, with the pixel electrode located on one side of the array substrate and the common electrode on the opposite substrate.

[0106] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0107] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0108] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0109] The structure of the array substrate is described below by taking the ADS mode array substrate structure as an example.

[0110] Figure 1B is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure. As shown in Figure 1B , the array substrate may include a substrate 20, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 20. The array substrate may further include a first insulating layer 11 positioned between the first conductive layer and the semiconductor layer, a second insulating layer 12 positioned between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 positioned between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 positioned between the third conductive layer and the fourth conductive layer.

[0111] As shown in FIG1B , the first conductive layer may include a first conductive portion 16 and a gate line GL of a first transistor 21. The first conductive portion 16 is also the first gate of the first transistor. The semiconductor layer may include a first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, and a second conductive portion 18. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19.

[0112] As shown in FIG1B , the first conductive layer may further include a fourth conductive portion 24 of the second transistor 22. The semiconductor layer may further include a second active portion 25 of the second transistor 22. The second conductive layer may further include a third conductive portion 26 of the second transistor 22. The third conductive portion 26 may be a second gate of the second transistor. The fourth conductive portion 24 may be a light shielding layer of the second transistor.

[0113] Figure 2 is a partial top view of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of the display area of ​​the array substrate according to an embodiment of the present disclosure. Figure 2A is a cross-sectional view taken along the line AA in Figure 2. As shown in Figures 2 and 2A, the display area of ​​the array substrate may include a substrate 20 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 20. The display area of ​​the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. In the embodiment of the present disclosure, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, the third insulating layer may also be referred to as a first passivation (PVX1) layer, the fourth insulating layer may also be referred to as an organic insulating layer, and the fifth insulating layer may also be referred to as a second passivation (PVX2) layer.

[0114] The first conductive layer may include a first conductive portion 16 and a gate line GL of the first transistor 21. The first conductive portion 16 is also the first gate of the first transistor. The semiconductor layer may include a first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, and a second conductive portion 18. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19. The fifth conductive portion 19 and the data line DL may be an integrated structure connected to each other. The third conductive layer may include a common electrode 30. The fourth conductive layer may include a pixel electrode 10. The pixel electrode 10 is electrically connected to the second electrode of the first transistor 21. The common electrode 30 has a hollow region 301. The pixel electrode 10 can be electrically connected to the second electrode of the first transistor 21 via the hollow region 301. In the disclosed embodiment, by arranging the data line DL on the side of the first transistor away from the substrate 20, the size of the first opening K1 provided in the second insulating layer 12 can be reduced. The data line DL is electrically connected to the first electrode of the first transistor 21 via the first opening K1. The fifth conductive portion 19 is located within the first opening K1, which can increase the area of ​​the opening region of the array substrate and improve the aperture ratio of the array substrate. Furthermore, arranging the data line DL on the side of the first transistor away from the substrate 20 can avoid damage to the first transistor caused by etching operations such as etching the first opening K1, thereby reducing the thickness of the first active portion of the first transistor and improving transistor performance.

[0115] As shown in Figure 2, the data line DL and the second conductive part 18 can be set to the same layer structure, which can simplify the preparation process of the array substrate, reduce the number of masks used, and reduce the production cost of the display substrate. The second conductive part 18 can act as a light-shielding layer and improve the performance of the first transistor. The second conductive part 18 is in a floating state, and the first conductive part 16 is closer to the substrate than the second conductive part 18, which is beneficial for adjusting the first transistor to a positive threshold voltage and improving the sand phenomenon in the display area. In the embodiment of the present disclosure, the floating state means that the second conductive part 18 is not electrically connected to other components, or the second conductive part 18 is electrically connected to other components and the applied voltage is zero.

[0116] In an exemplary embodiment, the voltage of the second conductive portion 18 is lower than the voltage of the first conductive portion 16 .

[0117] In an exemplary embodiment, the absolute value of the difference between the voltage applied by the second conductive part 18 and the voltage applied by the fifth conductive part 19 is greater than the absolute value of the difference between the voltage applied by the second conductive part 18 and the voltage applied by the first conductive part 16 .

[0118] In an exemplary embodiment, the line width of the data line DL may be greater than or equal to 0.4 micrometers and less than or equal to 5.0 micrometers. For example, the line width of the data line DL may be 2.5 micrometers.

[0119] In an exemplary embodiment, the substrate 20 may provide support for film layers other than the substrate 20 in the array substrate. For example, the substrate 20 may be a transparent substrate. For example, the substrate 20 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the disclosed embodiments are not limited thereto.

[0120] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0121] In one exemplary embodiment, the fourth conductive layer may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0122] In an exemplary embodiment, as shown in FIG2A , the orthographic projection of the first insulating layer 11 on the array substrate may include the orthographic projection of the first conductive layer on the array substrate. The first insulating layer 11 can prevent water and oxygen from corroding the gate line and the first conductive portion 16 , thereby improving the reliability of the array substrate.

[0123] In an exemplary embodiment, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x) or silicon oxide (SiO x The first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 can be a single layer or multiple layers or a composite layer.

[0124] In one exemplary embodiment, the fourth insulating layer 14 can be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The fourth insulating layer 14 can be a single layer, multiple layers, or a composite layer. In the disclosed embodiment, providing an organic insulating layer can reduce crosstalk from the first conductive portion to the common electrode.

[0125] In an exemplary embodiment, as shown in FIG2A , the orthographic projection of the first active portion 17 on the array substrate may at least partially overlap with the orthographic projection of the first conductive portion 16 on the array substrate. The first active portion 17 may include a first channel region 17-3, a first region 17-1 and a second region 17-2 located on opposite sides of the first channel region 17-3. For example, during the preparation of the array substrate, a portion of the first active portion 17 may be subjected to a conductorization treatment so that portions of the first active portion 17 form the first region 17-1 and the second region 17-2, respectively. The first region 17-1 of the first active portion 17 may be used as the first electrode of the first transistor, and the second region 17-2 of the first active portion 17 may be used as the second electrode of the first transistor. The embodiments of the present disclosure do not limit the conductorization process of the semiconductor layer.

[0126] In an exemplary embodiment, the first active portion 17 may include two or more sub-active layers. For example, the first active portion 17 may include two sub-active layers, or the first active portion 17 may include three sub-active layers.

[0127] In an exemplary embodiment, the material of the first active portion 17 may include a metal oxide semiconductor material. The materials of the multiple sub-active layers may be the same or different. The metal oxide semiconductor material may include one or more metal oxide materials such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium gallium zinc Y oxide (IGZYO, where Y represents doped tin). However, the present disclosure is not limited to metal oxide semiconductor materials. The material of the first active portion 17 may be low temperature polysilicon (LTPS) or the like.

[0128] In an exemplary embodiment, as shown in FIG2A , the fifth conductive portion 19 can be electrically connected to the data line DL and the first region 17-1 via the first opening K1 located in the second insulating layer 12. The pixel electrode 10 can be electrically connected to the second region 17-2 via the second opening K2 located in the second insulating layer 12. The orthographic projection of the fifth conductive portion 19 on the array substrate can be located within the orthographic projection of the first opening K1 on the array substrate. For example, the orthographic projection of the fifth conductive portion 19 on the array substrate coincides with the orthographic projection of the first opening K1 on the array substrate. The fifth conductive portion 19 and the data line DL can be an integrated structure connected to each other. The orthographic projection of the data line DL on the array substrate can include the orthographic projection of the fifth conductive portion 19 on the array substrate, which can reduce the area occupied by the fifth conductive portion 19 in the opening region of the array substrate and improve the aperture ratio of the array substrate.

[0129] In an exemplary embodiment, the aperture of the first opening K1 ranges from 1.0 μm to 6.0 μm.

[0130] In an exemplary embodiment, the diameter of the second opening K2 ranges from 1.0 μm to 15.0 μm.

[0131] In an exemplary embodiment, at least a portion of the orthographic projection of the first opening K1 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate. For example, a portion of the orthographic projection of the first opening K1 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate, or the entire orthographic projection of the first opening K1 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate.

[0132] In an exemplary embodiment, at least a portion of the orthographic projection of the second opening K2 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate. For example, a portion of the orthographic projection of the second opening K2 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate, or the entire orthographic projection of the second opening K2 on the array substrate is located within the orthographic projection of the first active portion 17 on the array substrate.

[0133] In an exemplary embodiment, as shown in FIG2 , the gate line GL may be in the form of a line extending along a first direction X, and the data line DL may be in the form of a line extending along a second direction Y. In the embodiment of the present disclosure, the line width direction of the data line DL is parallel to the first direction X. The orthographic projection of the data line DL on the array substrate may include the orthographic projection of the first opening K1 on the array substrate.

[0134] As shown in FIG2 , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 that are connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend along the second direction Y. The second end of the second segment 172 may extend along the first direction X. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend along the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173. The orthographic projection of the first opening K1 on the array substrate may be located in the first segment 171, and the orthographic projection of the second opening K2 on the array substrate may be located in the third segment 173. The first opening K1 and the second opening K2 are located on the same side of the gate line GL extending direction.

[0135] In an exemplary embodiment, as shown in FIG. 2 , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the second segment 172 on the array substrate.

[0136] In some exemplary embodiments, the first opening K1 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0137] Figure 3A is a schematic diagram of a partial top view of the display area of ​​an array substrate according to one embodiment of the present disclosure. Figure 3A shows a schematic diagram of a partial top view of the display area of ​​the array substrate after a second conductive layer is formed. As shown in Figure 3A , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0138] As shown in FIG3A , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. The first end of the second segment 172 is connected to one end of the first segment 171, and the second end of the second segment 172 extends along a second direction Y. The first region and the first channel region of the first active portion 17 may both be located in the first segment 171, and the second region of the first active portion 17 may be located in the second segment 172. The orthographic projection of the first opening K1 on the array substrate may be located in the first segment 171, and the orthographic projection of the second opening K2 on the array substrate may be located in the second segment 172. The first opening K1 and the second opening K2 are located on either side of the gate line GL in the extending direction.

[0139] As shown in FIG. 3A , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the first segment 171 on the array substrate.

[0140] Figure 3B is a second schematic top view of a partial view of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 3B shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 3B , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0141] As shown in FIG3B , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. The first end of the second segment 172 is connected to one end of the first segment 171. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y, which may be referred to as a third direction. For example, the third direction may be a diagonal direction between the first direction X and the second direction Y. The second end of the second segment 172 may extend in a diagonal direction between the first direction X and the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, and the second region of the first active portion 17 may be located in the second segment 172. A portion of the first channel region of the first active portion 17 may be located in the first segment 171, while the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172. The orthographic projection of the first opening K1 on the array substrate may be located in the first section 171 , the orthographic projection of the second opening K2 on the array substrate may be located in the second section 172 , and the first opening K1 and the second opening K2 are located on both sides of the gate line GL extending direction.

[0142] As shown in FIG3B , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0143] Figure 3C is a third schematic top view of a partial view of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 3C shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 3C , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0144] As shown in FIG3C , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 that are connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a third direction that is different from the first direction X and the second direction Y. For example, the third direction may be a diagonal direction between the first direction X and the second direction Y. The second end of the second segment 172 may extend in a diagonal direction between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the second direction Y. The first area of ​​the first active portion 17 may be located in the first section 171, part of the first channel region of the first active portion 17 may be located in the first section 171, the remaining part of the first channel region of the first active portion 17 may be located in the second section 172, and the second area of ​​the first active portion 17 may be located in the third section 173. The orthographic projection of the first opening K1 on the array substrate may be located in the first section 171, and the orthographic projection of the second opening K2 on the array substrate may be located in the third section 173. The first opening K1 and the second opening K2 are located on either side of the gate line GL in the extending direction.

[0145] As shown in FIG3C , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0146] Figure 3D is a fourth schematic top view of a portion of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 3D shows a schematic top view of a portion of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 3D , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0147] As shown in FIG3D , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a third direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the first direction X. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173. The orthographic projection of the first opening K1 on the array substrate may be located in the first section 171 , the orthographic projection of the second opening K2 on the array substrate may be located in the third section 173 , and the first opening K1 and the second opening K2 are located on both sides of the gate line GL extending direction.

[0148] As shown in FIG3D , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0149] The array substrate provided in the embodiment of the present disclosure can adapt to different structural layouts of display devices through various deformations of the shape of the first active portion, thereby improving the design flexibility of the array substrate and enhancing the versatility of the array substrate.

[0150] Figure 4 is a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 4A is a partial cross-sectional view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 4A is a cross-sectional view of the area marked BB in Figure 4 . As shown in Figures 4 and 4A, the display area of ​​the array substrate may include a substrate 20 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 20. The display area of ​​the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer.

[0151] The first conductive layer may include a first conductive portion 16 and a gate line GL of the first transistor 21. The first conductive portion 16 may be the first gate of the first transistor. The semiconductor layer may include a first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, and a second conductive portion 18. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19. The fifth conductive portion 19 and the data line DL may be an integrally connected structure. The third conductive layer may include a common electrode 30. The fourth conductive layer may include a pixel electrode 10. The pixel electrode 10 is electrically connected to the second electrode of the first transistor 21. The common electrode 30 has a hollow region 301. The pixel electrode 10 may be electrically connected to the second electrode of the first transistor 21 via the hollow region 301. In the embodiment of the present disclosure, by positioning the data line DL on the side of the first transistor away from the substrate 20, the size of the opening provided in the second insulating layer 12 can be reduced. The data line DL is electrically connected to the first electrode of the first transistor 21 via the opening. The fifth conductive portion 19 is located within the opening, which increases the area of ​​the opening region of the array substrate and improves the aperture ratio of the array substrate. Furthermore, disposing the data line DL on the side of the first transistor away from the substrate 20 can avoid damage to the first transistor caused by etching operations during etching of the first opening K1, reduce the thickness of the first active portion of the first transistor, and improve transistor performance.

[0152] In an exemplary embodiment, as shown in FIG4A , the fifth conductive portion 19 can be electrically connected to the data line DL and the first region 17-1 via the first opening K1 located in the second insulating layer 12. The pixel electrode 10 can be electrically connected to the second region 17-2 via the second opening K2 located in the second insulating layer 12. The orthographic projection of the fifth conductive portion 19 on the array substrate is located within the orthographic projection of the first opening K1 on the array substrate, and the orthographic projection of the fifth conductive portion 19 on the array substrate is smaller than the orthographic projection of the first opening K1 on the array substrate. The fifth conductive portion 19 and the data line DL can be an integrated structure connected to each other, and the orthographic projection of the data line DL on the array substrate can include the orthographic projection of the fifth conductive portion 19 on the array substrate, which can reduce the area occupied by the fifth conductive portion 19 in the opening region of the array substrate and improve the aperture ratio of the array substrate.

[0153] In an exemplary embodiment, as shown in FIG4A , the orthographic projection of the data line DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate, and the dimension of the partial overlap along the line width direction of the data line DL is less than or equal to 1.5 microns.

[0154] 4 , the gate line GL may be a line extending along a first direction X, and the data line DL may be a line extending along a second direction Y. The orthographic projection of the data line DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0155] As shown in FIG4 , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 that are connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend along the second direction Y. The second end of the second segment 172 may extend along the first direction X, the first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend along the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0156] As shown in FIG. 4 , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the second segment 172 on the array substrate.

[0157] In some exemplary embodiments, the first opening K1 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0158] Figure 5A is a schematic diagram of a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 5A shows a schematic diagram of a partial top view of the display area of ​​the array substrate after a second conductive layer is formed. As shown in Figure 5A , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps the orthographic projection of the first opening K1 on the array substrate.

[0159] As shown in FIG5A , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. A first end of the second segment 172 is connected to one end of the first segment 171 , and a second end of the second segment 172 extends along a second direction Y. The first region and the first channel region of the first active portion 17 may both be located in the first segment 171 , and the second region of the first active portion 17 may be located in the second segment 172 .

[0160] As shown in FIG. 5A , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the first segment 171 on the array substrate.

[0161] Figure 5B is a second schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 5B shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 5B , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0162] As shown in FIG5B , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. The first end of the second segment 172 is connected to one end of the first segment 171. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, and the second region of the first active portion 17 may be located in the second segment 172. A portion of the first channel region of the first active portion 17 may be located in the first segment 171, and the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172.

[0163] As shown in FIG. 5B , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0164] Figure 5C is a third schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 5C shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 5C , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0165] As shown in FIG5C , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0166] As shown in FIG. 5C , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0167] Figure 5D is a fourth schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 5D shows a schematic top view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 5D , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0168] As shown in FIG5D , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the first direction X. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0169] As shown in FIG. 5D , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0170] Figure 6 is a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 6A is a partial cross-sectional view of the display area of ​​the array substrate according to another embodiment of the present disclosure. Figure 6A is a cross-sectional view taken at position CC in Figure 6 . As shown in Figures 6 and 6A, the display area of ​​the array substrate may include a substrate 20 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 20. The display area of ​​the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer.

[0171] The first conductive layer may include a first conductive portion 16 and a gate line GL of a first transistor 21. The first conductive portion 16 may be a first gate of the first transistor. The semiconductor layer may include a first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, a second conductive portion 18, and a pixel connection electrode 23. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19. The fifth conductive portion 19 and the data line DL may be an integrated structure connected to each other. The third conductive layer may include a common electrode 30. The fourth conductive layer may include a pixel electrode 10. The pixel electrode 10 is electrically connected to the second electrode of the first transistor 21 via the pixel connection electrode 23. The common electrode 30 has a hollow region 301. The pixel electrode 10 may be electrically connected to the second electrode of the first transistor 21 via the hollow region 301. In the embodiment of the present disclosure, by arranging the data line DL on the side of the first transistor away from the substrate 20, the size of the opening provided in the second insulating layer 12 can be reduced. The data line DL is electrically connected to the first electrode of the first transistor 21 via the opening. The fifth conductive portion 19 is located within the opening, which can increase the area of ​​the opening region of the array substrate and improve the aperture ratio of the array substrate.

[0172] In an exemplary embodiment, as shown in FIG6A , the fifth conductive portion 19 can be electrically connected to the data line DL and the first region 17-1 via the first opening K1 located in the second insulating layer 12. The orthographic projection of the fifth conductive portion 19 on the array substrate can be located within the orthographic projection of the first opening K1 on the array substrate. For example, the orthographic projection of the fifth conductive portion 19 on the array substrate coincides with the orthographic projection of the first opening K1 on the array substrate. The fifth conductive portion 19 and the data line DL can be an interconnected integral structure. The orthographic projection of the data line DL on the array substrate can include the orthographic projection of the fifth conductive portion 19 on the array substrate. This can reduce the area occupied by the fifth conductive portion 19 in the opening region of the array substrate and improve the aperture ratio of the array substrate.

[0173] In an exemplary embodiment, as shown in FIG6A , the pixel connection electrode 23 can be electrically connected to the pixel electrode 10 and the second region 17-2 via the second opening K2 located in the second insulating layer 12. The orthographic projection of the pixel connection electrode 23 on the array substrate can be located within the orthographic projection of the second opening K2 on the array substrate. For example, the orthographic projection of the pixel connection electrode 23 on the array substrate coincides with the orthographic projection of the second opening K2 on the array substrate. Providing the pixel connection electrode 23 can reduce the size of the pixel electrode 10 along the thickness direction of the array substrate and improve the reliability of the pixel electrode electrical connection.

[0174] 6 , the gate line GL may be a line extending along a first direction X, and the data line DL may be a line extending along a second direction Y. The orthographic projection of the data line DL on the array substrate may include the orthographic projection of the first opening K1 on the array substrate.

[0175] In one exemplary embodiment, as shown in FIG6 , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 that are connected. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend along the second direction Y. The second end of the second segment 172 may extend along the first direction X, and the first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend along the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0176] As shown in FIG. 6 , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the second segment 172 on the array substrate.

[0177] As shown in Figure 6, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0178] In some exemplary embodiments, the first opening K1 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0179] In some exemplary embodiments, the second opening K2 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0180] Figure 7A is a schematic diagram of a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 7A shows a schematic diagram of a partial top view of the display area of ​​the array substrate after a second conductive layer is formed. As shown in Figure 7A , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0181] As shown in FIG7A , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. A first end of the second segment 172 is connected to one end of the first segment 171 , and a second end of the second segment 172 extends along a second direction Y. The first region and the first channel region of the first active portion 17 may both be located in the first segment 171 , and the second region of the first active portion 17 may be located in the second segment 172 .

[0182] As shown in FIG. 7A , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the first segment 171 on the array substrate.

[0183] As shown in Figure 7A, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the second section 172 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0184] Figure 7B is a second schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 7B shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 7B , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0185] As shown in FIG7B , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. The first end of the second segment 172 is connected to one end of the first segment 171. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, and the second region of the first active portion 17 may be located in the second segment 172. A portion of the first channel region of the first active portion 17 may be located in the first segment 171, and the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172.

[0186] As shown in FIG. 7B , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0187] As shown in Figure 7B, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the second section 172 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0188] Figure 7C is a third schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 7C shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 7C , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0189] As shown in FIG7C , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0190] As shown in FIG. 7C , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0191] As shown in Figure 7C, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0192] Figure 7D is a fourth schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 7D shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 7D , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate can include the orthographic projection of the first opening K1 on the array substrate.

[0193] As shown in FIG7D , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the first direction X. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0194] As shown in FIG. 7D , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projections of the first segment 171 and the second segment 172 on the array substrate.

[0195] As shown in Figure 7D, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0196] Figure 8 is a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 8A is a partial cross-sectional view of the display area of ​​the array substrate according to another embodiment of the present disclosure. Figure 8A is a cross-sectional view taken at DD in Figure 8 . As shown in Figures 8 and 8A, the display area of ​​the array substrate may include a substrate 20, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 20. The display area of ​​the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer.

[0197] The first conductive layer may include the first conductive portion 16 of the first transistor 21 and the gate line GL. The semiconductor layer may include the first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, a second conductive portion 18, and a pixel connection electrode 23. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19. The fifth conductive portion 19 and the data line DL may be an integrally connected structure. The third conductive layer may include a common electrode 30. The fourth conductive layer may include a pixel electrode 10. The pixel electrode 10 is electrically connected to the second electrode of the first transistor 21 via the pixel connection electrode 23. The common electrode 30 has a hollow region 301. The pixel electrode 10 may be electrically connected to the second electrode of the first transistor 21 via the hollow region 301. In the embodiment of the present disclosure, by positioning the data line DL on the side of the first transistor away from the substrate 20, the size of the opening provided in the second insulating layer 12 can be reduced. The data line DL is electrically connected to the first electrode of the first transistor 21 via the opening. The fifth conductive portion 19 may be located within the opening, thereby increasing the area of ​​the opening region of the array substrate and improving the aperture ratio of the array substrate.

[0198] In one exemplary embodiment, as shown in FIG8A , the fifth conductive portion 19 can be electrically connected to the data line DL and the first region 17-1 via the first opening K1 located in the second insulating layer 12. The pixel electrode 10 can be electrically connected to the second region 17-2 via the pixel connection electrode 23. At least a portion of the pixel connection electrode 23 can be located within the second opening K2 located in the second insulating layer 12. The orthographic projection of the fifth conductive portion 19 on the array substrate is located within the orthographic projection of the first opening K1 on the array substrate, and the orthographic projection of the fifth conductive portion 19 on the array substrate is smaller than the orthographic projection of the first opening K1 on the array substrate. The fifth conductive portion 19 and the data line DL can be an integral structure connected to each other. The orthographic projection of the data line DL on the array substrate can include the orthographic projection of the fifth conductive portion 19 on the array substrate. This can reduce the area occupied by the fifth conductive portion 19 in the opening region of the array substrate and improve the aperture ratio of the array substrate.

[0199] In an exemplary embodiment, as shown in FIG8 , the gate line GL may be a line extending along a first direction X, and the data line DL may be a line extending along a second direction Y. The orthographic projection of the data line DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0200] As shown in FIG8 , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 that are connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend along the second direction Y. The second end of the second segment 172 may extend along the first direction X, the first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend along the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0201] As shown in FIG. 8 , the orthographic projection of the second conductive portion 18 on the array substrate may be rectangular, and the orthographic projection of the second conductive portion 18 on the array substrate may at least partially overlap with the orthographic projection of the second segment 172 on the array substrate.

[0202] As shown in Figure 8, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate includes the orthographic projection of the second opening K2 on the array substrate.

[0203] In some exemplary embodiments, the first opening K1 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0204] In some exemplary embodiments, the second opening K2 may be a circular hole, a rectangular hole, an elliptical hole, a hexagonal hole, or the like.

[0205] Figure 9A is a schematic diagram of a partial top view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 9A shows a schematic diagram of a partial top view of the display area of ​​the array substrate after a second conductive layer is formed. As shown in Figure 9A , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps the orthographic projection of the first opening K1 on the array substrate.

[0206] As shown in FIG9A , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. A first end of the second segment 172 is connected to one end of the first segment 171 , and a second end of the second segment 172 extends along a second direction Y. The first region and the first channel region of the first active portion 17 may both be located in the first segment 171 , and the second region of the first active portion 17 may be located in the second segment 172 .

[0207] As shown in Figure 9A, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the second section 172 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate includes the orthographic projection of the second opening K2 on the array substrate.

[0208] Figure 9B is a second schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 9B shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 9B , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0209] As shown in FIG9B , the first active portion 17 may include a first segment 171 and a second segment 172 connected to each other. The first segment 171 extends along a first direction X. The first end of the second segment 172 is connected to one end of the first segment 171. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, and the second region of the first active portion 17 may be located in the second segment 172. A portion of the first channel region of the first active portion 17 may be located in the first segment 171, and the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172.

[0210] As shown in Figure 9B, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the second section 172 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate includes the orthographic projection of the second opening K2 on the array substrate.

[0211] Figure 9C is a third schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 9C shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 9C , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps with the orthographic projection of the first opening K1 on the array substrate.

[0212] As shown in FIG9C , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the second direction Y. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0213] As shown in Figure 9C, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate can include the orthographic projection of the second opening K2 on the array substrate.

[0214] Figure 9D is a fourth schematic top view of a partial view of the display area of ​​an array substrate according to another embodiment of the present disclosure. Figure 9D shows a schematic top view of a partial view of the display area of ​​the array substrate after the second conductive layer is formed. As shown in Figure 9D , the gate lines GL can be linear extending along a first direction X, and the data lines DL can be linear extending along a second direction Y. The orthographic projection of the data lines DL on the array substrate partially overlaps the orthographic projection of the first opening K1 on the array substrate.

[0215] As shown in FIG9D , the first active portion 17 may include a first segment 171, a second segment 172, and a third segment 173 connected to each other. The first end of the first segment 171 may be connected to the first end of the second segment 172, and the second end of the first segment 171 may extend in a direction opposite to the first direction X. The second end of the second segment 172 may extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second segment 172 may extend diagonally between the first direction X and the second direction Y. The first end of the third segment 173 may be connected to the second end of the second segment 172, and the second end of the third segment 173 may extend in the first direction X. The first region of the first active portion 17 may be located in the first segment 171, a portion of the first channel region of the first active portion 17 may be located in the first segment 171, the remaining portion of the first channel region of the first active portion 17 may be located in the second segment 172, and the second region of the first active portion 17 may be located in the third segment 173.

[0216] As shown in Figure 9D, the orthographic projection of the pixel connecting electrode 23 on the array substrate can be rectangular, at least part of the orthographic projection of the pixel connecting electrode 23 on the array substrate can be located within the orthographic projection of the third section 173 on the array substrate, and the orthographic projection of the pixel connecting electrode 23 on the array substrate includes the orthographic projection of the second opening K2 on the array substrate.

[0217] Figure 10 is a partial top view schematic diagram of the display area of ​​the array substrate of an exemplary embodiment of the present disclosure, Figure 10A is a partial cross-sectional schematic diagram of the display area of ​​the array substrate of an exemplary embodiment of the present disclosure, and Figure 10A is a cross-sectional schematic diagram at the mark EE in Figure 10. As shown in Figures 10 and 10A, the orthographic projection of the second conductive portion 18 on the array substrate is located within the orthographic projection of the second insulating layer 12 on the array substrate. In the process of preparing the second conductive layer pattern, the second insulating layer 12 can be etched a second time to improve the uniformity of the etching. Due to the secondary etching of the second insulating layer 12, the first active portion 17 will be partially thinned. In Figure 10, the two rectangular dotted boxes indicate the area where the first active portion 17 is partially thinned.

[0218] Figure 11 is a partial top view schematic diagram of the display area of ​​the array substrate of another exemplary embodiment of the present disclosure, and Figure 11A is a partial cross-sectional schematic diagram of the display area of ​​the array substrate of another exemplary embodiment of the present disclosure. Figure 11A is a cross-sectional schematic diagram at the position marked FF in Figure 11. As shown in Figures 11 and 11A, the orthographic projection of the second conductive portion 18 on the array substrate is located within the orthographic projection of the second insulating layer 12 on the array substrate, and the orthographic projection of the data line DL on the array substrate includes other parts of the orthographic projection of the second insulating layer 12 on the array substrate. In the process of preparing the second conductive layer pattern, the second insulating layer 12 can be etched a second time to improve the uniformity of the etching. Due to the secondary etching of the second insulating layer 12, a part of the first active portion 17 will be thinned. In Figure 11, the two rectangular dotted boxes indicate the area where the first active portion 17 is partially thinned.

[0219] Figure 12 is a partial top view of the display area of ​​an array substrate according to another exemplary embodiment of the present disclosure, and Figure 12A is a partial cross-sectional view of the display area of ​​the array substrate according to another exemplary embodiment of the present disclosure. Figure 12A is a cross-sectional view at the point marked GG in Figure 12 . As shown in Figures 12 and 12A, the display area of ​​the array substrate may include a substrate 20, and a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer disposed on one side of the substrate 20. The display area of ​​the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, and a third insulating layer 13 located between the second conductive layer and the third conductive layer. The first conductive layer may include a first conductive portion 16 of a first transistor 21 and a gate line GL. The semiconductor layer may include a first active portion 17 of the first transistor 21. The second conductive layer may include a data line DL, a fifth conductive portion 19, and a second conductive portion 18. The data line DL is electrically connected to the first electrode of the first transistor 21 via the fifth conductive portion 19. The fifth conductive portion 19 and the data line DL may be an integrally connected structure. The third conductive layer may include a common electrode 30. The pixel electrode 10 and the first active portion 17 can be an integrated structure connected to each other, which can reduce the number of film layers of the array substrate, simplify the preparation process of the array substrate, and avoid damage to the active layer caused by etching holes in the insulating layer.

[0220] Figure 13 is a partial top view schematic diagram of the display area of ​​the array substrate of another exemplary embodiment of the present disclosure, and Figure 13A is a partial cross-sectional schematic diagram of the display area of ​​the array substrate of another exemplary embodiment of the present disclosure. Figure 13A is a cross-sectional schematic diagram at the mark HH in Figure 13. As shown in Figures 13 and 13A, the orthographic projection of the second conductive portion 18 on the array substrate is located within the orthographic projection of the second insulating layer 12 on the array substrate, and the orthographic projection of the data line DL on the array substrate includes other parts of the orthographic projection of the second insulating layer 12 on the array substrate. In the process of preparing the second conductive layer pattern, the second insulating layer 12 can be etched a second time to improve the uniformity of the etching. Due to the secondary etching of the second insulating layer 12, the first active portion 17 will be partially thinned. In Figure 13, the two rectangular dotted boxes indicate the area where the first active portion 17 is partially thinned.

[0221] Figure 14 is a partial top view of a non-display region of an array substrate according to an embodiment of the present disclosure. Figure 14A is a partial cross-sectional view of the non-display region of the array substrate according to an embodiment of the present disclosure. Figure 14A is a cross-sectional view taken at JJ in Figure 14 . As shown in Figures 14 and 14A, the non-display region of the array substrate may include a substrate 20, and a first conductive layer, a semiconductor layer, and a second conductive layer disposed on one side of the substrate 20. The non-display region of the array substrate may further include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, and a third insulating layer 13, a fourth insulating layer 14, and a fifth insulating layer 15 located, in that order, on the side of the second conductive layer away from the substrate 20. The first conductive layer may include a fourth conductive portion 24 of a second transistor 22. The semiconductor layer may include a second active portion 25 of the second transistor 22. The second conductive layer may include a third conductive portion 26 of the second transistor 22. The orthographic projections of the fourth conductive portion 24, the second active portion 25, and the third conductive portion 26 on the array substrate may at least partially overlap. The third conductive portion 26 may be a second gate of the second transistor, and the fourth conductive portion 24 may be a light shielding layer of the second transistor.

[0222] In one exemplary embodiment, as shown in FIG14A , the second active portion 25 may include a second channel region 25-1, a third region 25-2, and a fourth region 25-3 located on opposite sides of the second channel region 25-1. For example, during the process of preparing the array substrate, a portion of the second active portion 25 may be subjected to a conductorization process so that portions of the second active portion 25 form the third region 25-2 and the fourth region 25-3, respectively. The third region 25-2 of the second active portion 25 may serve as the first electrode of the second transistor, and the fourth region 25-3 of the second active portion 25 may serve as the second electrode of the second transistor 22. The presently disclosed embodiments do not limit the conductorization process for the semiconductor layer.

[0223] In an exemplary embodiment, as shown in FIG14A , the second conductive layer may further include a first connecting electrode 27 and a second connecting electrode 28. For example, the second transistor 22 may be electrically connected to the data line via the first connecting electrode 27. The first connecting electrode 27 may be electrically connected to the third region 25-2 of the second active portion 25 via the third opening K3 located in the second insulating layer 12. The orthographic projection of the first connecting electrode 27 on the array substrate may at least partially overlap with the orthographic projection of the third opening K3 on the array substrate. The second connecting electrode 28 may be electrically connected to the fourth region 25-3 of the second active portion 25 via the fourth opening K4 located in the second insulating layer 12. The orthographic projection of the second connecting electrode 28 on the array substrate may at least partially overlap with the orthographic projection of the fourth opening K4 on the array substrate.

[0224] In an exemplary embodiment, the voltages applied by the second conductive part and the fourth conductive part are the same or different.

[0225] Figure 15 is a partial cross-sectional schematic diagram of a non-display area of ​​an array substrate according to another embodiment of the present disclosure. As shown in Figure 15 , the non-display area of ​​the array substrate may include a substrate 20, a semiconductor layer disposed on one side of the substrate 20, and a second conductive layer. The non-display area of ​​the array substrate may further include a first insulating layer 11 located between the substrate 20 and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, and a third insulating layer 13, a fourth insulating layer 14, and a fifth insulating layer 15 located, in that order, on the side of the second conductive layer away from the substrate 20. The semiconductor layer may include a second active portion 25 of a second transistor 22. The second active portion 25 may include a second channel region 25-1, a third region 25-2, and a fourth region 25-3 located on opposite sides of the second channel region 25-1. The second conductive layer may include a second gate 29, a first connecting electrode 27, and a second connecting electrode 28 of the second transistor 22. For example, the second transistor 22 may be electrically connected to a data line via the first connecting electrode 27. The first connection electrode 27 may be electrically connected to the third region 25-2 of the second active portion 25 via the third opening K3 in the second insulating layer 12. The second connection electrode 28 may be electrically connected to the fourth region 25-3 of the second active portion 25 via the fourth opening K4 in the second insulating layer 12.

[0226] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spray coating, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material formed on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer structure" referred to in this disclosure means that A and B are formed through the same patterning process.

[0227] Figures 16A to 16H are schematic diagrams of a process for preparing a display area of ​​an array substrate according to an embodiment of the present disclosure. The process for preparing the array substrate may include the following steps:

[0228] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include depositing a first conductive film on one side of the substrate 20 and patterning the first conductive film through a patterning process to form a first conductive layer pattern located on one side of the substrate 20. The first conductive layer may include a gate line GL and a first conductive portion 16 of the first transistor, as shown in FIG16A .

[0229] In some exemplary embodiments, the first conductive layer may have a thickness ranging from 1,000 angstroms to 10,000 angstroms.

[0230] (12) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the semiconductor film through a patterning process to form a first insulating layer 11 located on a side of the first conductive layer away from the substrate 20, and a semiconductor layer pattern located on a side of the first insulating layer 11 away from the substrate 20. The semiconductor layer may include a first active portion 17 of a first transistor, as shown in FIG16B .

[0231] In some exemplary embodiments, the thickness of the first insulating layer 11 may be in a range of 100 nanometers to 700 nanometers.

[0232] In some exemplary embodiments, the semiconductor layer may have a thickness ranging from 10 nanometers to 80 nanometers.

[0233] (13) Forming a second insulating layer pattern. Forming the second insulating layer pattern may include: depositing a second insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second insulating film through a patterning process to form a second insulating layer 12 located on the side of the semiconductor layer away from the substrate 20, as shown in FIG16C . The second insulating layer 12 is provided with at least one first opening K1 and at least one second opening K2. The at least one first opening K1 and the at least one second opening K2 both penetrate the second insulating layer 12 and expose a portion of the surface of the first active portion 17. The first opening K1 is configured so that the fifth conductive portion formed subsequently is located within the opening, and the second opening K2 is configured so that at least a portion of the pixel connection electrode formed subsequently is located within the opening.

[0234] In some exemplary embodiments, the second insulating layer may have a thickness ranging from 600 angstroms to 2000 angstroms.

[0235] (14) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on a side of the second insulating layer 12 away from the substrate 20. The second conductive layer may include a data line DL, a fifth conductive portion 19, a second conductive portion 18, and a pixel connection electrode 23, as shown in FIG16D .

[0236] Forming the second conductive layer pattern may further include performing a conductorization process on a portion of the first active portion 17. The conductorization process may be performed on a portion of the first active portion 17 so that portions of the first active portion 17 form a first region 17-1 and a second region 17-2, respectively. The first region 17-1 of the first active portion 17 may serve as a first electrode of a first transistor, and the second region 17-2 of the first active portion 17 may serve as a second electrode of the first transistor. The presently disclosed embodiment does not limit the conductorization process for the semiconductor layer. The first active portion 17 may further include a first channel region 17-3 located between the first region 17-1 and the second region 17-2.

[0237] As shown in Figure 16D, the data line DL and the fifth conductive portion 19 can be an interconnected integral structure. The fifth conductive portion 19 is located within the first opening K1 and is electrically connected to the first region 17-1 of the first active portion 17. The orthographic projection of the data line DL on the array substrate can include the orthographic projection of the fifth conductive portion 19 on the array substrate, which can reduce the size of the first opening K1 and increase the aperture ratio of the array substrate.

[0238] As shown in FIG16D , at least a portion of the pixel connection electrode 23 is located within the second opening K2 and is electrically connected to the second region 17 - 2 of the first active portion 17 . The pixel connection electrode 23 is configured to be electrically connected to a subsequently formed pixel electrode.

[0239] In some exemplary embodiments, the second conductive layer may have a thickness ranging from 200 nanometers to 1200 nanometers.

[0240] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: sequentially depositing a third insulating film and a fourth insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the fourth insulating film through a patterning process to form a third insulating layer 13 and a fourth insulating layer 14 located on a side of the second conductive layer away from the substrate 20, as shown in FIG16E .

[0241] As shown in FIG16E , the fourth insulating layer 14 includes at least one fifth opening K5. The fifth opening K5 penetrates the fourth insulating layer and exposes a portion of the surface of the third insulating layer away from the substrate 20. The orthographic projection of the fifth opening K5 on the array substrate at least partially overlaps with the orthographic projection of the pixel connection electrode 23 on the array substrate. The fifth opening K5 is configured to electrically connect a subsequently formed pixel electrode to the pixel connection electrode 23 via the opening, thereby electrically connecting the pixel electrode to the second region 17-2 of the first active portion 17.

[0242] As shown in FIG. 16E , the orthographic projection of the fifth opening K5 on the array substrate may include the orthographic projection of the pixel connection electrode 23 on the array substrate, which can improve the reliability of the electrical connection between the subsequently formed pixel electrode and the pixel connection electrode 23 .

[0243] In some exemplary embodiments, the third insulating layer 13 may have a thickness ranging from 200 nanometers to 400 nanometers.

[0244] In some exemplary embodiments, the fourth insulating layer 14 may have a thickness ranging from 2.0 micrometers to 3.0 micrometers.

[0245] (16) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include depositing a third conductive film on one side of the substrate 20 and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the fourth insulating layer 14 away from the substrate 20. The third conductive layer may include a common electrode 30, as shown in FIG16F.

[0246] In some exemplary embodiments, the third conductive layer may have a thickness ranging from 400 angstroms to 1000 angstroms.

[0247] (17) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the fifth insulating film through a patterning process to form a fifth insulating layer 15 located on a side of the third conductive layer away from the substrate 20, as shown in FIG16G .

[0248] As shown in FIG16G , the fifth insulating layer 15 may include at least one sixth opening K6. The fifth insulating layer 15 and the third insulating layer 13 located within the sixth opening K6 are etched away, exposing a portion of the surface of the pixel connection electrode 23 on the side away from the substrate 20. The orthographic projection of the sixth opening K6 on the array substrate includes the orthographic projection of the fifth opening K5 on the array substrate, which can reduce the difficulty of etching the sixth opening K6 and shorten the time for preparing the sixth opening K6.

[0249] The sixth opening K6 is configured to allow a subsequently formed pixel electrode to be electrically connected to the pixel connection electrode 23 via the opening.

[0250] In some exemplary embodiments, the fifth insulating layer 15 may have a thickness ranging from 1000 angstroms to 3000 angstroms.

[0251] (18) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on a side of the fifth insulating layer 15 away from the substrate 20. The fourth conductive layer may include a pixel electrode 10, as shown in FIG16H. The pixel electrode 10 is electrically connected to the pixel connection electrode 23 via the sixth opening K6.

[0252] In some exemplary embodiments, the fourth conductive layer may have a thickness ranging from 40 nanometers to 135 nanometers.

[0253] Figures 17A to 17C are schematic diagrams of a process for preparing a display area of ​​an array substrate according to another embodiment of the present disclosure. The process for preparing the array substrate may include the following steps:

[0254] (21) A first conductive layer pattern, a semiconductor layer pattern, a second insulating layer pattern, and a second conductive layer pattern are sequentially formed, and reference can be made to the description of the above embodiment.

[0255] (22) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: sequentially depositing a third insulating film, a fourth insulating film, and a third conductive film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to sequentially form a third insulating layer 13, a fourth insulating layer 14, and a third conductive layer pattern located on a side of the second conductive layer away from the substrate 20. The third conductive layer may include a common electrode 30, as shown in FIG17A.

[0256] (23) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the fifth insulating film through a patterning process to form a fifth insulating layer 15 located on a side of the third conductive layer away from the substrate 20, as shown in FIG17B .

[0257] As shown in FIG17B , the fifth insulating layer 15 may include at least one seventh opening K7. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 located within the seventh opening K7 are all etched away, exposing a portion of the surface of the pixel connection electrode 23 on a side away from the substrate 20. The seventh opening K7 is configured to electrically connect a subsequently formed pixel electrode to the pixel connection electrode 23 via the opening.

[0258] (24) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the side of the pattern substrate 20 formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on the side of the fifth insulating layer 15 away from the substrate 20. The fourth conductive layer may include a pixel electrode 10, as shown in FIG17C. The pixel electrode 10 is electrically connected to the pixel connection electrode 23 via the seventh opening K7.

[0259] Figures 18A to 18C are schematic diagrams of a manufacturing process of a display area of ​​an array substrate according to another embodiment of the present disclosure. The manufacturing process of the array substrate may include the following steps:

[0260] (31) The first conductive layer pattern and the semiconductor layer pattern are formed in sequence. Please refer to the above embodiment and will not elaborate on them.

[0261] (32) Forming a second insulating layer initial pattern. Forming the second insulating layer initial pattern 12-1 may include: depositing a second insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second insulating film through a patterning process to form a second insulating layer initial pattern 12-1 located on the side of the semiconductor layer away from the substrate 20, as shown in FIG18A. The second insulating layer initial pattern 12-1 is provided with at least one first opening K1 and at least one second opening K2. The at least one first opening K1 and the at least one second opening K2 both penetrate the second insulating film and expose a portion of the surface of the first active portion 17. The first opening K1 is configured so that the fifth conductive portion formed subsequently is located within the opening, and the second opening K2 is configured so that at least a portion of the pixel connection electrode formed subsequently is located within the opening.

[0262] (33) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on a side of the initial pattern of the second insulating layer away from the substrate 20. The second conductive layer may include a data line DL, a fifth conductive portion 19, a second conductive portion 18, and a pixel connection electrode 23, as shown in FIG18B.

[0263] Forming the second conductive layer pattern may further include performing a conductor process on a portion of the first active portion 17. The conductor process may be performed on a portion of the first active portion 17 so that the first active portion 17 forms a first region 17-1 and a second region 17-2, respectively. The first region 17-1 of the first active portion 17 may serve as a first electrode of a first transistor, and the second region 17-2 of the first active portion 17 may serve as a second electrode of the first transistor.

[0264] Forming the second conductive layer pattern may further include patterning the second insulating layer preliminary pattern to form a second insulating layer 12, as shown in FIG. 18B .

[0265] (34) A third insulating layer 13, a fourth insulating layer 14, a third conductive layer, a fifth insulating layer 15 and a fourth conductive layer are formed in sequence, as shown in FIG18C. Please refer to the aforementioned embodiment and will not elaborate further.

[0266] 19A to 19C are schematic diagrams illustrating a process for preparing a display area of ​​an array substrate according to another embodiment of the present disclosure. The process for preparing the array substrate may include the following steps:

[0267] (41) The first conductive layer pattern and the semiconductor layer pattern are formed in sequence. Please refer to the above embodiment and will not elaborate on it again.

[0268] (42) Forming a second insulating layer initial pattern. Forming the second insulating layer initial pattern 12-1 may include: depositing a second insulating film on one side of the substrate 20 on which the aforementioned pattern is formed, and patterning the second insulating film through a patterning process to form a second insulating layer initial pattern 12-1 located on the side of the semiconductor layer away from the substrate 20, as shown in FIG19A . The second insulating layer initial pattern 12-1 is provided with at least one first opening K1 and at least one second opening K2. The at least one first opening K1 and the at least one second opening K2 both penetrate the second insulating film and expose a portion of the surface of the first active portion 17. The first opening K1 is configured so that the fifth conductive portion formed subsequently is located within the opening.

[0269] (43) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate 20 having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on a side of the second insulating layer initial pattern away from the substrate 20. The second conductive layer may include a data line DL, a fifth conductive portion 19, and a second conductive portion 18, as shown in FIG19B .

[0270] Forming the second conductive layer pattern may further include performing a conductor process on a portion of the first active portion 17. The conductor process may be performed on a portion of the first active portion 17 so that the first active portion 17 forms a first region 17-1 and a second region 17-2, respectively. The first region 17-1 of the first active portion 17 may serve as a first electrode of a first transistor, and the second region 17-2 of the first active portion 17 may serve as a second electrode of the first transistor.

[0271] Forming the second conductive layer pattern may further include patterning the second insulating layer preliminary pattern to form a second insulating layer 12, as shown in FIG. 19B .

[0272] As shown in FIG19B , the pixel electrode 10 and the first active portion 17 can be an integrated structure connected to each other, which can simplify the film structure of the array substrate. There is no need to set up openings for achieving electrical connection of the pixel electrode, and damage to the first active portion caused by the etching operation can be avoided.

[0273] (44) A third insulating layer 13 and a third conductive layer are formed in sequence, as shown in FIG19C . Please refer to the aforementioned embodiment and will not elaborate further.

[0274] Figure 20 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in Figure 20 , another embodiment of the present disclosure provides a display device. For example, a display device capable of implementing an Advanced Super Dimension Switch (ADS) mode may include an array substrate 5 , which may be any of the array substrates provided in the aforementioned embodiments.

[0275] The display device may further include an opposing substrate 1 and a liquid crystal layer 2 disposed between an array substrate 5 and the opposing substrate 1. The pixel electrodes and common electrodes included in the array substrate 5 may be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. As shown in FIG20 , the liquid crystal molecules in the liquid crystal layer 2 may be horizontally aligned on the array substrate 5. In the embodiment of the present disclosure, the horizontal direction is parallel to the plane on which the array substrate 5 is located.

[0276] In an exemplary embodiment, as shown in Figure 20 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0277] Figure 21 is a graph showing a characteristic test simulation of a first transistor. As shown in Figure 21, curve ① represents a case where the first gate of the first transistor is further away from the substrate than the data line, while curve ② represents a case where the first transistor employs the first transistor structure provided by any of the aforementioned embodiments of the present disclosure. As can be seen from Figure 21, employing the first transistor structure provided by an embodiment of the present disclosure facilitates adjusting the transistor to a positive threshold voltage and helps alleviate the sand phenomenon in the display area.

[0278] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0279] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate includes a substrate, the substrate includes a display area and a non-display area surrounding the display area; the display area includes at least one first transistor, the first transistor includes a first active portion, a first conductive portion, and a second conductive portion; the non-display area includes at least one second transistor, the second transistor includes a second active portion, a third conductive portion, and a fourth conductive portion; the first active portion and the second active portion are both located in a semiconductor layer, and the first conductive portion and the third conductive portion are located in different conductive layers; In a plane perpendicular to the array substrate, the second conductive portion and the fourth conductive portion are respectively located on opposite sides of the semiconductor layer; the second conductive portion is in a floating state.

2. The array substrate according to claim 1, wherein, The non-display area includes a gate driving circuit configured to be electrically connected to the gate lines of the display area, and the gate driving circuit includes the at least one second transistor.

3. The array substrate according to claim 1, wherein, The non-display area includes at least one of an electrostatic discharge circuit, a test circuit, and a demultiplexer circuit; the electrostatic discharge circuit, the test circuit, and the demultiplexer circuit all include the at least one second transistor.

4. The array substrate according to claim 1, wherein, The first conductive portion is the gate of the first transistor, the second conductive portion and the first conductive portion are respectively located on opposite sides of the first active portion, and at least a part of the orthographic projection of the second conductive portion on the plane of the substrate overlaps with at least a part of the orthographic projection of the first active portion on the plane of the substrate; The third conductive portion is the gate of the second transistor, the fourth conductive portion and the third conductive portion are respectively located on opposite sides of the second active portion, and at least a part of the orthographic projection of the fourth conductive portion on the plane of the substrate overlaps with at least a part of the orthographic projection of the second active portion on the plane of the substrate; Wherein, the voltages applied to the second conductive portion and the fourth conductive portion are the same or different.

5. The array substrate according to claim 4, wherein, The fourth conductive portion is electrically connected to the first conductive portion, and the voltages applied to the fourth conductive portion and the first conductive portion are the same.

6. The array substrate according to claim 4, wherein, The voltage of the second conductive portion is lower than the voltage of the first conductive portion.

7. An array substrate includes a substrate, the substrate includes a display area and a non-display area surrounding the display area; the display area includes at least one first transistor, the first transistor includes a first conductive portion, a first active portion, a second conductive portion, and a fifth conductive portion; the second conductive portion and the fifth conductive portion are provided in the same layer; the second conductive portion is located on a side of the first conductive portion away from the substrate; the second conductive portion is in a floating state.

8. The array substrate according to claim 7, wherein, The absolute value of the difference between the voltage value applied to the second conductive portion and the voltage value applied to the fifth conductive portion is greater than the absolute value of the difference between the voltage value applied to the second conductive portion and the voltage value applied to the first conductive portion.

9. The array substrate according to claim 7, wherein, The display area further includes at least one data line, and the at least one data line is disposed on the same layer as the second conductive portion.

10. The array substrate according to claim 9, wherein, The at least one data line is electrically connected to the at least one first transistor via the fifth conductive portion; the orthographic projection of the at least one data line on the plane of the substrate includes the orthographic projection of the fifth conductive portion on the plane of the substrate.

11. The array substrate according to claim 10, wherein, The display area further includes a gate insulating layer, and the gate insulating layer is located on a side of the first active portion away from the substrate; the gate insulating layer includes at least one first opening, and the fifth conductive portion is located within the at least one first opening.

12. The array substrate according to claim 11, wherein, At least a part of the orthographic projection of the at least one data line on the plane of the substrate overlaps with at least a part of the orthographic projection of the at least one first opening on the plane of the substrate.

13. The array substrate according to claim 12, wherein, The orthographic projection of the at least one data line on the plane of the substrate includes the orthographic projection of the at least one first opening on the plane of the substrate.

14. The array substrate according to claim 11, wherein, The at least one first opening exposes a part of the surface of the first active portion on the side away from the substrate, and the fifth conductive portion is in contact with the part of the surface of the first active portion on the side away from the substrate.

15. The array substrate according to any one of claims 11 to 14, wherein, The display region further includes at least one common electrode and at least one pixel electrode, and both the at least one common electrode and the at least one pixel electrode are located on a side of the gate insulating layer away from the substrate. At least a part of a positive projection of the at least one common electrode on a plane where the substrate is located overlaps with a positive projection of the at least one pixel electrode on the plane where the substrate is located; The gate insulating layer further includes at least one second opening, and the at least one pixel electrode is electrically connected to the at least one first transistor via the at least one second opening.

16. The array substrate according to claim 15, wherein, The display region further includes at least one gate line, and the at least one gate line is provided on the same layer as the first conductive portion; the first active portion includes a first section, a second section, and a third section connected to each other; a first end of the first section is connected to a first end of the second section, and a second end of the first section extends along a second direction; a second end of the second section extends along a first direction, and a first end of the third section is connected to the second end of the second section, and a second end of the third section extends along the second direction; the first direction intersects with the second direction; Wherein, a positive projection of the at least one first opening on a plane where the substrate is located is located within a positive projection of the first section on the plane where the substrate is located, a positive projection of the at least one second opening on a plane where the substrate is located is located within a positive projection of the third section on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on the same side of the gate line.

17. The array substrate according to claim 15, wherein, The display region further includes at least one gate line, and the at least one gate line is provided on the same layer as the first conductive portion; the first active portion includes a first section and a second section connected to each other; the first section extends along a first direction, a first end of the second section is connected to one end of the first section, and a second end of the second section extends along a second direction; the first direction intersects with the second direction; Wherein, a positive projection of the at least one first opening on a plane where the substrate is located is located within a positive projection of the first section on the plane where the substrate is located, a positive projection of the at least one second opening on a plane where the substrate is located is located within a positive projection of the second section on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on two sides of the gate line.

18. The array substrate according to claim 15, wherein, The display region further includes at least one gate line, and the at least one gate line is provided on the same layer as the first conductive portion; the first active portion includes a first section and a second section connected to each other; the first section extends along a first direction, a first end of the second section is connected to one end of the first section, and a second end of the second section extends along a third direction, the first direction is perpendicular to the second direction, and the third direction is different from both the first direction and the second direction; Among them, the orthographic projection of the at least one first opening on the plane where the substrate is located is within the orthographic projection of the first section on the plane where the substrate is located, the orthographic projection of the at least one second opening on the plane where the substrate is located is within the orthographic projection of the second section on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on both sides of the gate line.

19. The array substrate according to claim 15, wherein, The display area further includes at least one gate line, and the at least one gate line is disposed on the same layer as the first conductive portion; the first active portion includes a first section, a second section, and a third section connected to each other; a first end of the first section is connected to a first end of the second section, a second end of the first section extends in a direction opposite to a first direction, a second end of the second section extends in a third direction, the first direction is perpendicular to a second direction, and the third direction is different from both the first direction and the second direction; a first end of the third section is connected to a second end of the second section, and a second end of the third section extends in the second direction; Among them, the orthographic projection of the at least one first opening on the plane where the substrate is located is within the orthographic projection of the first section on the plane where the substrate is located; the orthographic projection of the at least one second opening on the plane where the substrate is located is within the orthographic projection of the third section on the plane where the substrate is located, and the at least one first opening and the at least one second opening are located on both sides of the gate line.

20. A display device, comprising the array substrate according to any one of claims 1 to 19, a counter substrate, and a liquid crystal layer; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

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