Display panel and display apparatus

Abstract

The present application discloses a display panel and a display apparatus. According to the display panel, an optical sensor multiplexes a first gate driving signal and a second gate driving signal provided for a pixel circuit by a gate driving circuit to work, and even when the optical sensor is added, a corresponding driving circuit does not need to be additionally provided for the optical sensor, thereby reducing power consumption, and also reducing the space occupied by a frame.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Light sensors can add more functions to display panels due to their applications in remote light interaction, gesture sensing, ambient light sensing, and personal identification.

[0003] However, adding a light sensor also requires additionally providing a corresponding driving circuit in the display panel, which not only increases the power consumption of the display panel, but also increases the space occupied by the frame of the display panel. SUMMARY OF THE INVENTION

[0004] The present application provides a display panel and a display device to alleviate the technical problems of increased power consumption and increased frame space occupied by adding light sensors.

[0005] In a first aspect, the present application provides a display panel, which includes a first gate drive line for transmitting a first gate drive signal, a second gate drive line for transmitting a second gate drive signal, a gate drive circuit, a pixel circuit, and a light sensor, wherein the gate drive circuit is electrically connected to the first gate drive line and the second gate drive line, and the gate drive circuit provides a first gate drive signal and a second gate drive signal; a pixel circuit is electrically connected to a first gate drive line and a second gate drive line; a light sensor is electrically connected to a first gate drive line and a second gate drive line, and the light sensor is reset and controlled to read out according to the first gate drive signal and the second gate drive signal, respectively.

[0006] In a second aspect, the present application provides a display device, which includes the display panel of at least one of the above-mentioned embodiments, wherein the display panel further includes a display area, and the pixel circuits and the light sensors are arrayed in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG1 is a schematic diagram of a first structure of a display panel provided in an embodiment of the present application.

[0008] FIG2 is a schematic diagram of a second structure of a display panel provided in an embodiment of the present application.

[0009] FIG3 is a schematic structural diagram of the display panel shown in FIG2 .

[0010] FIG4 is a first circuit schematic diagram of the optical sensor provided in an embodiment of the present application.

[0011] FIG5 is a second circuit schematic diagram of the optical sensor provided in an embodiment of the present application.

[0012] FIG6 is a timing diagram of a light sensor in the related art.

[0013] FIG7 is a timing diagram of the optical sensor provided in an embodiment of the present application.

[0014] FIG8 is a schematic diagram showing a timing comparison before and after the improvement of FIG7 .

[0015] FIG9 is a circuit schematic diagram of a pixel circuit provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0016] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0017] This embodiment provides a display panel, please refer to Figures 1 to 8. As shown in Figure 1, the display panel includes a gate drive circuit 100 and a light sensor 11. The gate drive circuit 100 provides a first gate drive signal Nscan and a second gate drive signal Pscan for display; the light sensor 11 is electrically connected to the gate drive circuit 100, and the light sensor 11 is reset and controlled to read out according to the first gate drive signal Nscan and the second gate drive signal Pscan, respectively.

[0018] It can be understood that the display panel provided in this embodiment operates by multiplexing the first gate drive signal Nscan and the second gate drive signal Pscan provided by the gate drive circuit 100 to the pixel circuit 12 through the light sensor 11. Even when the light sensor 11 is added, there is no need to set up a corresponding drive circuit for the light sensor 11. This not only reduces power consumption, but also reduces the space occupied by the border.

[0019] It should be noted that the display panel may further include a pixel circuit 12 located in the display area AA. The pixel circuit 12 is electrically connected to the gate driving circuit 100 . The pixel circuit 12 performs display according to the first gate driving signal Nscan and the second gate driving signal Pscan.

[0020] Among them, a pixel circuit includes at least one N-channel transistor and at least one P-channel transistor, the gate of an N-channel transistor is connected to the first gate drive line GL1 to receive the first gate drive signal Nscan, and the gate of a P-channel transistor is connected to the second gate drive line GL2 to receive the second gate drive signal Pscan.

[0021] Among them, the above-mentioned gate drive circuit 100 can be located in the non-display area NA (border area) on one side of the display area AA. In some embodiments, the pixel circuit 12 can be distributed in an array in the display area AA. The light sensor 11 can be located in the display area AA or in the non-display area NA. In the case where the light sensor 11 is located in the display area AA, the light sensor 11 can be integrated into the array substrate of the display panel, which improves the integration of the display panel. In some embodiments, the light sensor 11 can also be distributed in an array in the display area AA, and a light sensor 11 is integrated into at least one pixel circuit 12. For example, one light sensor 11 is integrated into every N pixel circuits 12, and N can be a positive integer, such as 1, 2, 3, 4, 5... etc.

[0022] The gate drive circuit 100 may include multiple cascaded shift registers, each of which may provide a corresponding first gate drive signal Nscan and a second gate drive signal Pscan via a first gate drive line GL1 and a second gate drive line GL2, respectively. It is understood that, compared to the display panel shown in FIG2 , the display panel shown in FIG1 may reduce the space occupied by the frame due to the lack of a gate drive circuit 100.

[0023] In the case of row-by-row scanning, the light sensors 11 and pixel circuits 12 in the same row are electrically connected to a first gate drive line GL1 and a second gate drive line GL2, so that the interval time of each reset of the light sensor 11 and the interval time of each acquisition can be kept consistent.

[0024] In one embodiment, as shown in FIG2 , the display panel includes two identical gate driver circuits 100, one located in the non-display area NA on opposite sides of the display area AA. Each of the first gate driver line GL1 and the second gate driver line GL2 is electrically connected to the two gate driver circuits 100 at both ends, thereby providing a first gate driver signal Nscan to the first gate driver line GL1 and a second gate driver signal Pscan to the second gate driver line GL2. This reduces transmission delays in the first gate driver signal Nscan and the second gate driver signal Pscan, thereby increasing the charging time of the pixel circuit 12 and improving the accuracy of the reset and output timings of the photosensor 11.

[0025] In one embodiment, as shown in FIG3 , each gate driver circuit 100 in FIG2 includes a first gate driver circuit 110 and a second gate driver circuit 120. The first gate driver circuit 110 includes a plurality of cascaded first shift registers 111, and the second gate driver circuit 120 includes a plurality of cascaded second shift registers 121. Each first gate driver line GL1 is electrically connected to two first shift registers 111, a row of pixel circuits 12, and a row of light sensors 11. Each second gate driver line GL2 is electrically connected to two second shift registers 121, a row of pixel circuits 12, and a row of light sensors 11.

[0026] The first gate driving signal Nscan serves as a reset control signal RST of the light sensor 11 , and the second gate driving signal Pscan serves as a selection control signal SEL of the light sensor 11 .

[0027] In one embodiment, as shown in Figure 4, the photosensor 11 includes a photosensitive device PD, a first capacitor Cst, a first reset transistor T11, an amplifier transistor T9, and a selection transistor T10. One end of the photosensitive device PD is electrically connected to the positive terminal of the first power supply SVDD; one end of the first capacitor Cst is electrically connected to one end of the photosensitive device PD, and the other end of the first capacitor Cst is electrically connected to the other end of the photosensitive device PD; a first electrode of the first reset transistor T11 is electrically connected to the other end of the photosensitive device PD, a second electrode of the first reset transistor T11 is electrically connected to the negative terminal of the first power supply SVSS, and a gate of the first reset transistor T11 is connected to a reset control signal RST; a first electrode of the amplifier transistor T9 is electrically connected to the second electrode of the first reset transistor T11, and a gate of the amplifier transistor T9 is electrically connected to the first electrode of the first reset transistor T11; a first electrode of the selection transistor T10 is electrically connected to the second electrode of the amplifier transistor T9, and a gate of the selection transistor T10 is connected to the selection control signal SEL, and the second electrode of the selection transistor T10 outputs a readout signal Readout.

[0028] It should be noted that the reset control signal RST is the first gate driving signal Nscan, and the selection control signal SEL is the second gate driving signal Pscan.

[0029] The first electrode may be a source electrode or a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, if the first electrode is a source electrode, the second electrode may be a drain electrode; or if the first electrode is a drain electrode, the second electrode may be a source electrode.

[0030] The photosensitive device PD may be a photodiode (photodiode) or a phototransistor.

[0031] In some embodiments, the amplifier transistor T9 and the select transistor T10 can both be P-channel amorphous silicon thin-film transistors. It is understood that the light sensor 11 based on amorphous silicon (a-Si) thin-film transistors (TFTs) can have advantages such as mature technology, high uniformity over large areas, low cost, high responsiveness, high signal-to-noise ratio, and small size. The first reset transistor T11 can be an N-channel oxide thin-film transistor, which can better prevent leakage of the photocurrent generated by the photosensitive device PD.

[0032] In other embodiments, the amplifying transistor T9 and the selecting transistor T10 may both be oxide thin film transistors, and the first reset transistor T11 may also be an amorphous silicon thin film transistor.

[0033] In some embodiments, as shown in FIG4 , the light sensor 11 further includes a voltage divider transistor T0 , wherein a first electrode of the voltage divider transistor T0 is electrically connected to a second electrode of the selection transistor T10 , a second electrode of the voltage divider transistor T0 is electrically connected to a second power supply positive terminal SVDD2 , and a gate of the voltage divider transistor T0 is connected to a voltage divider control signal Vb.

[0034] It should be noted that the voltage divider transistor T0 is used to adjust the voltage range and / or current range of the readout signal Readout to match the recognition range of the readout circuit or readout chip that receives the readout signal.

[0035] The voltage divider transistor T0 can be integrated into a corresponding chip to reduce the occupied space in the chip. The voltage divider transistor T0 can be an N-channel or P-channel thin film transistor, for example, an amorphous silicon or oxide thin film transistor.

[0036] In one embodiment, as shown in FIG5 , the light sensor 11 includes a photosensitive device PD, a first capacitor Cst, a first reset transistor T11, a second capacitor C1, a second reset transistor T12, an amplifying transistor T9, and a selecting transistor T10. One end of the photosensitive device PD is electrically connected to the positive terminal SVDD of the first power supply; one end of the first capacitor Cst is electrically connected to one end of the photosensitive device PD, and the other end of the first capacitor Cst is electrically connected to the other end of the photosensitive device PD; a first electrode of the first reset transistor T11 is electrically connected to the other end of the photosensitive device PD, a second electrode of the first reset transistor T11 is electrically connected to the negative terminal SVSS of the first power supply, and a gate of the first reset transistor T11 is connected to a reset control signal RS T; one end of the second capacitor C1 is electrically connected to the first electrode of the first reset transistor T11; the first electrode of the first reset transistor T11 is electrically connected to the other end of the second capacitor C1, the second electrode of the first reset transistor T11 is electrically connected to the second negative power supply terminal VSS2, and the gate of the first reset transistor T11 is electrically connected to the gate of the first reset transistor T11; the first electrode of the amplifying transistor T9 is electrically connected to the voltage terminal Vm, and the gate of the amplifying transistor T9 is electrically connected to the other end of the second capacitor C1; the first electrode of the selecting transistor T10 is electrically connected to the second electrode of the amplifying transistor T9, the gate of the selecting transistor T10 is connected to the selecting control signal SEL, and the second electrode of the selecting transistor T10 outputs the readout signal Readout.

[0037] It should be noted that, in this embodiment, the communication type of the first reset transistor T11 is the same as the channel type of the second reset transistor T12 .

[0038] The first capacitor Cst is used to store the photocurrent generated by the photosensitive device PD and shift the potential of the node GA1 from the potential of the first power supply negative terminal SVSS to the potential of the first power supply positive terminal SVDD. The second capacitor C1 not only performs a blocking function but also utilizes its own bootstrap effect to transfer the photocurrent generated by the photosensitive device PD from node GA1 to node GA2.

[0039] To match the voltage range or current range of the readout signal Readout, the potential of the second negative power supply terminal VSS2 is higher than the potential of the first negative power supply terminal SVSS. For example, the potential of the first negative power supply terminal SVSS can be -3V, and the potential of the second negative power supply terminal VSS2 can be 1V. This is due to the layout space and the voltage difference required by the optical sensor 11. An excessively large voltage difference can increase leakage current. Consequently, the voltage range of node GA1 is approximately -1V to -3V (excluding the -3V range), which reduces the conversion efficiency of the amplifier transistor T9. The voltage range or current range of the readout signal Readout is at the edge of what the readout circuit or chip can measure, which can easily lead to the readout circuit or chip failing to detect it.

[0040] Figure 6 is a timing diagram of a related art photosensor 11. When a positive pulse of the reset control signal RST arrives, the first reset transistor T11, or the first reset transistor T11 and the second reset transistor T12, turn on to reset the potential at the other end of the photosensitive device PD. After the exposure time has elapsed, a negative pulse of the selection control signal SEL and the voltage divider control signal Vb arrives, turning on the selection transistor T10 and the voltage divider transistor T0. The amplifier transistor T9 amplifies the photogenerated current of the photosensitive device PD and outputs it as a readout signal, Readout.

[0041] The exposure time is the interval between the falling edge of the reset control signal RST and the rising edge of the selection control signal SEL.

[0042] FIG7 is a timing diagram of the light sensor 11 provided in an embodiment of the present application. The display panel further includes a driver chip and a touch module. The touch module is connected to the light sensor 11 and the driver chip. The driver chip is connected to the gate drive circuit 100. The touch module outputs a corresponding detection signal based on the readout signal Readout output by the detected light sensor 11. The driver chip controls the first gate drive signal Nscan and the second gate drive signal Pscan output by the gate drive circuit 100 based on the detection signal to reduce the refresh frequency of the display so that the light sensor 11 outputs the readout signal Readout after the exposure time. The driver chip increases the drive voltage and / or light-emitting current of the pixel circuit 12 based on the detection signal to increase the display brightness.

[0043] It should be noted that when a touch action is detected, the display panel increases the display brightness. Since higher brightness means greater light intensity, this can enable a faster response time for the light sensor 11. In addition, due to the reduction in refresh frequency, the positive pulse of the first gate drive signal Nscan / reset control signal RST no longer appears in at least one subsequent frame, and the light sensor 11 will not be reset again, thereby achieving a longer exposure time.

[0044] Specifically, when a touch action (such as a fingerprint) is detected, fingerprint recognition is performed through the optical sensor 11 , which can reduce power consumption compared to performing fingerprint recognition through the optical sensor 11 when no fingerprint is detected.

[0045] The refresh rate and exposure time change in a positive direction. For example, when the refresh rate is less than 24Hz, the exposure time can be greater than 30ms. Therefore, it can be seen that the exposure time can be increased or decreased by changing the refresh rate.

[0046] After the exposure time is complete, the negative pulse of the second gate drive signal Pscan / selection control signal SEL turns on the selection control transistor, and the photosensor 11 outputs the readout signal Readout. In FIG4 , under the control of the negative pulse of the voltage divider control signal Vb, the voltage divider transistor T0 turns on and outputs the readout signal Readout.

[0047] EM is a light-emitting control signal of the pixel circuit 12 . When EM is at a high potential, the pixel circuit 12 does not emit light; when EM is at a low potential, the pixel circuit 12 emits light.

[0048] Figure 8 is a schematic diagram comparing the timings before and after the improvement in Figure 7. Before the improvement, the second gate drive signal Pscan / selection control signal SEL had two negative pulses in each frame. After the improvement, the second gate drive signal Pscan / selection control signal SEL only had two negative pulses in the first frame (the write frame) after the refresh frequency is reduced, and only one negative pulse in frames 2 through 5.

[0049] It can be seen from this that the first gate drive signal Nscan has a positive pulse, the first reset transistor T11 is an N-channel transistor, and the gate of the first reset transistor T11 is connected to the first gate drive signal Nscan to reset the light sensor 11; the second gate drive signal Pscan has a negative pulse, the selection transistor T10 is a P-channel transistor, and the gate of the selection transistor T10 is connected to the second gate drive signal Pscan to control the output of the readout signal Readout.

[0050] In one embodiment, the pixel circuit 12 may include at least one of a write transistor T2P, a drive transistor T1P, a first light-emitting control transistor T5P, a second light-emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a compensation transistor T3P, a light-emitting device D1, and a storage capacitor Cst.

[0051] The first power line is electrically connected to the first electrode of the first emission control transistor T5P and one end of the storage capacitor Cst. The second electrode of the first emission control transistor T5P is electrically connected to the first electrode of the drive transistor T1P and the first electrode of the write transistor T2P. The second electrode of the drive transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second emission control transistor T6P. The second electrode of the second emission control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1. The cathode of the light-emitting device D1 is electrically connected to the second power line. The emission control line is electrically connected to the gates of the first emission control transistor T5P and the second emission control transistor T6P. The second electrode of the write transistor T2P is electrically connected to the data line, and the gate of the write transistor T2P is electrically connected to the first scan line. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is electrically connected to the second scan line. The second electrode of the compensation transistor T3P is electrically connected to the gate of the drive transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the third scan line. The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst and the first electrode of the first initialization transistor T4P. The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the fourth scan line.

[0052] The first electrode may be a source electrode or a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is a source electrode, the second electrode is a drain electrode; or when the first electrode is a drain electrode, the second electrode is a source electrode.

[0053] The first power line is used to transmit a positive power signal VDD, and the second power line is used to transmit a negative power signal VSS. The potential of the positive power signal VDD is higher than that of the negative power signal VSS. The data line is used to transmit a data signal Data. The light control line is used to transmit a light control signal EM. The first initialization line is used to transmit a first initialization signal Vi1. The second initialization line is used to transmit a second initialization signal Vi2. The first scan line is used to transmit a second gate drive signal Pscan. The second scan line is used to transmit a scan signal Pscan2. The third scan line is used to transmit a first gate drive signal Nscan. The fourth scan line is used to transmit a scan signal Nscan [nX], where X is an integer greater than or equal to 1.

[0054] The write transistor T2P is a P-channel thin film transistor, specifically a polysilicon thin film transistor, such as a low-temperature polysilicon thin film transistor. The first initialization transistor T4P or the compensation transistor T3P is an N-channel thin film transistor, specifically an oxide thin film transistor, such as an indium gallium zinc oxide thin film transistor. At least one of the drive transistor T1P, the first emission control transistor T5P, the second emission control transistor T6P, and the second initialization transistor T7P can be a P-channel thin film transistor or an N-channel thin film transistor.

[0055] In one embodiment, this embodiment provides a display device, which includes the display panel according to at least one of the above embodiments.

[0056] It can be understood that since the display device provided in this embodiment includes the display panel of at least one of the above-mentioned embodiments, it can also work by multiplexing the first gate drive signal Nscan and the second gate drive signal Pscan for display provided by the gate drive circuit 100 through the light sensor 11. Even when the light sensor 11 is added, there is no need to set up a corresponding drive circuit for the light sensor 11, which not only reduces power consumption, but also reduces the space occupied by the frame.

[0057] Among them, the display panel can be an organic light emitting diode display panel, a mini light emitting diode display panel, a micro light emitting diode display panel, a quantum dot light emitting diode display panel, etc.

[0058] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. A display panel, wherein, The display panel includes: A first gate driving line for transmitting a first gate driving signal; A second gate driving line for transmitting a second gate driving signal; A gate driving circuit, the gate driving circuit being electrically connected to the first gate driving line and the second gate driving line, and the gate driving circuit providing the first gate driving signal and the second gate driving signal; A pixel circuit, one pixel circuit being electrically connected to one first gate driving line and one second gate driving line; A photosensor, one photosensor being electrically connected to one first gate driving line and one second gate driving line, and the photosensor performing reset and control readout according to the first gate driving signal and the second gate driving signal respectively.

2. The display panel according to claim 1, wherein, The photosensor includes: A photosensitive device, one end of the photosensitive device being electrically connected to the positive terminal of the first power supply; A first capacitor, one end of the first capacitor being electrically connected to one end of the photosensitive device, and the other end of the first capacitor being electrically connected to the other end of the photosensitive device; A first reset transistor, a first pole of the first reset transistor being electrically connected to the other end of the photosensitive device, a second pole of the first reset transistor being electrically connected to the negative terminal of the first power supply, and a gate of the first reset transistor being connected to the first gate driving signal; An amplifying transistor, a first pole of the amplifying transistor being electrically connected to the second pole of the first reset transistor, and a gate of the amplifying transistor being electrically connected to the first pole of the first reset transistor; A selection transistor, a first pole of the selection transistor being electrically connected to the second pole of the amplifying transistor, a gate of the selection transistor being connected to the second gate driving signal, and a second pole of the selection transistor outputting a readout signal.

3. The display panel according to claim 2, wherein, The photosensor further includes a voltage dividing transistor, a first pole of the voltage dividing transistor being electrically connected to the second pole of the selection transistor, a second pole of the voltage dividing transistor being electrically connected to the positive terminal of the second power supply, and a gate of the voltage dividing transistor being connected to a voltage dividing control signal.

4. The display panel according to claim 1, wherein, The photosensor includes: A photosensitive device, one end of the photosensitive device being electrically connected to the positive terminal of the first power supply; A first capacitor, one end of the first capacitor being electrically connected to one end of the photosensitive device, and the other end of the first capacitor being electrically connected to the other end of the photosensitive device; A first reset transistor, a first pole of the first reset transistor being electrically connected to the other end of the photosensitive device, a second pole of the first reset transistor being electrically connected to the negative terminal of the first power supply, and a gate of the first reset transistor being connected to the first gate driving signal; A second capacitor, one end of the second capacitor being electrically connected to the first pole of the first reset transistor; A second reset transistor, a first pole of the first reset transistor being electrically connected to the other end of the second capacitor, a second pole of the first reset transistor being electrically connected to the negative terminal of the second power supply, and a gate of the first reset transistor being electrically connected to the gate of the first reset transistor; An amplifying transistor, a first pole of the amplifying transistor being electrically connected to a voltage terminal, and a gate of the amplifying transistor being electrically connected to the other end of the second capacitor; A selection transistor, a first pole of the selection transistor is electrically connected to a second pole of the amplifying transistor, a gate of the selection transistor receives the second gate driving signal, and a second pole of the selection transistor outputs a readout signal.

5. The display panel according to claim 4, wherein, The conduction type of the first reset transistor is the same as that of the second reset transistor.

6. The display panel according to claim 5, wherein, The potential of the negative terminal of the second power supply is higher than that of the negative terminal of the first power supply.

7. The display panel according to claim 2, wherein, The first gate driving signal controls the first reset transistor to reset the photosensor; the second gate driving signal controls the selection transistor to control the output of the readout signal.

8. The display panel according to claim 7, wherein, The first gate driving signal has a positive pulse, the first reset transistor is an N-channel transistor, and a gate of the first reset transistor receives the first gate driving signal; The second gate driving signal has a negative pulse, the selection transistor is a P-channel transistor, and a gate of the selection transistor receives the second gate driving signal.

9. The display panel according to claim 8, wherein, One pixel circuit includes at least one N-channel transistor and at least one P-channel transistor. A gate of one N-channel transistor is connected to the first gate driving line to receive the first gate driving signal, and a gate of one P-channel transistor is connected to the second gate driving line to receive the second gate driving signal.

10. The display panel according to claim 1, wherein, The display panel further includes a driving chip and a touch control module. The touch control module is connected to the photosensor and the driving chip. The driving chip is connected to the gate driving circuit. The touch control module outputs a corresponding detection signal according to the detected readout signal output by the photosensor. The driving chip controls the first gate driving signal and the second gate driving signal output by the gate driving circuit to reduce the refresh frequency of the display according to the detection signal, so that the photosensor outputs a readout signal after experiencing an exposure time.

11. The display panel according to claim 10, wherein, The refresh frequency changes positively with the exposure time.

12. The display panel according to claim 10, wherein,The driving chip increases the driving voltage and / or the light emitting current of the pixel circuit according to the detection signal to increase the display brightness.

13. A display device, wherein, The display device includes the display panel as described in claim 1. The display panel further includes a display area, and the pixel circuit and the photosensor are both distributed in an array in the display area.

14. The display device according to claim 13, wherein, The photosensor includes: A photosensitive device, one end of the photosensitive device is electrically connected to the positive terminal of the first power supply; A first capacitor, one end of the first capacitor is electrically connected to one end of the photosensitive device, and the other end of the first capacitor is electrically connected to the other end of the photosensitive device; A first reset transistor, a first pole of the first reset transistor is electrically connected to the other end of the photosensitive device, a second pole of the first reset transistor is electrically connected to the negative terminal of the first power supply, and a gate of the first reset transistor receives the first gate driving signal; An amplifying transistor, a first pole of the amplifying transistor is electrically connected to the second pole of the first reset transistor, and a gate of the amplifying transistor is electrically connected to the first pole of the first reset transistor; A selection transistor, a first pole of the selection transistor is electrically connected to a second pole of the amplification transistor, a gate of the selection transistor receives the second gate driving signal, and a second pole of the selection transistor outputs a readout signal.

15. The display device according to claim 14, wherein, The optical sensor further includes a voltage-dividing transistor, a first pole of the voltage-dividing transistor is electrically connected to a second pole of the selection transistor, a second pole of the voltage-dividing transistor is electrically connected to a positive terminal of a second power supply, and a gate of the voltage-dividing transistor receives a voltage-dividing control signal.

16. The display device according to claim 13, wherein, The optical sensor includes: A photosensitive device, one end of the photosensitive device is electrically connected to a positive terminal of a first power supply; A first capacitor, one end of the first capacitor is electrically connected to one end of the photosensitive device, and the other end of the first capacitor is electrically connected to the other end of the photosensitive device; A first reset transistor, a first pole of the first reset transistor is electrically connected to the other end of the photosensitive device, a second pole of the first reset transistor is electrically connected to a negative terminal of the first power supply, and a gate of the first reset transistor receives the first gate driving signal; A second capacitor, one end of the second capacitor is electrically connected to the first pole of the first reset transistor; A second reset transistor, a first pole of the first reset transistor is electrically connected to the other end of the second capacitor, a second pole of the first reset transistor is electrically connected to a negative terminal of a second power supply, and a gate of the first reset transistor is electrically connected to the gate of the first reset transistor; An amplification transistor, a first pole of the amplification transistor is electrically connected to a voltage terminal, and a gate of the amplification transistor is electrically connected to the other end of the second capacitor; A selection transistor, a first pole of the selection transistor is electrically connected to a second pole of the amplification transistor, a gate of the selection transistor receives the second gate driving signal, and a second pole of the selection transistor outputs a readout signal.

17. The display device according to claim 16, wherein, The conduction type of the first reset transistor is the same as the channel type of the second reset transistor.

18. The display device according to claim 17, wherein, The potential of the negative terminal of the second power supply is higher than the potential of the negative terminal of the first power supply.

19. The display device according to claim 14, wherein, The first gate driving signal controls the first reset transistor to reset the optical sensor; the second gate driving signal controls the selection transistor to control the output of the readout signal.

20. The display device according to claim 19, wherein, The first gate driving signal has a positive pulse, the first reset transistor is an N-channel transistor, and the gate of the first reset transistor receives the first gate driving signal; The second gate driving signal has a negative pulse, the selection transistor is a P-channel transistor, and the gate of the selection transistor receives the second gate driving signal.

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