Semiconductor integrated circuit device

Abstract

A standard cell according to the present invention comprises: an active region (2P1); an active region (2N1) which is formed above the active region (2P1) and overlaps, in plan view, with the active region (2P1); and power supply lines (11, 12) which are formed in a back wiring layer. The surface of a nanosheet (21, 22) on a first side, which is one side in a second direction, is exposed from a gate line (31). The power supply line (11) is disposed in the edge portion of the standard cell on the first side. The power supply line (12) is disposed in the edge portion of the standard cell on a second side, which is the other side in the second direction.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Patent Document 1 discloses a standard cell using a complementary FET (CFET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device. In Patent Document 1, wiring is provided on the back surface directly below the transistor, and the source and drain of the transistor are connected to this wiring.

[0005] Patent Document 2 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a fork-shaped gate electrode, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 2 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0006] US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0246644

[0007] However, with regard to standard cells using CFETs, no specific study has yet been made on the layout structure of standard cells using fork-sheet transistors instead of nanosheet transistors as transistors.

[0008] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, with respect to standard cells using CFETs.

[0009] In an aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second transistor of a second conductivity type different from the first conductivity type, the channel comprising a second nanosheet extending in the first direction; a first gate wiring extending in the first direction and surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a second power supply wiring formed on the back side of the first transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage, wherein the first and second nanosheets have a first side surface, which is one side in the second direction, exposed from the first gate wiring, and the first power supply wiring is arranged at an end of the first standard cell on the first side, and the second power supply wiring is arranged at an end of the second side, which is the other side in the second direction, of the first standard cell.

[0010] According to the present disclosure, the first power supply wiring is arranged on a first side, which is one side of the first standard cell in the second direction, in a plan view. The second power supply wiring is arranged on a second side, which is the other side of the first standard cell in the second direction, in a plan view. By arranging the first standard cell in a circuit block, the first standard cell can share the first power supply wiring with standard cells arranged on the first side of the first standard cell, and can share the second power supply wiring with standard cells arranged on the second side of the first standard cell. Therefore, the power supply wiring that supplies the power supply voltage can be strengthened, thereby suppressing a drop in the power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0011] According to the present disclosure, in a layout of a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, for standard cells using CFETs, it is possible to suppress a drop in power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0012] 1. A plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment. 2. A plan view showing an example of the layout structure of an inverter cell according to an embodiment. 3. A cross-sectional view of the inverter cell of FIG. 2. 4. A circuit diagram of the inverter cell of FIG. 2. 5. Another configuration example of a semiconductor integrated circuit device according to an embodiment. 6. A plan view showing an example of the layout structure of an inverter cell according to a modified example of an embodiment. 7. A plan view showing an example of the layout structure of a two-input NAND cell according to an embodiment. 8. A plan view showing an example of the layout structure of a two-input NOR cell according to an embodiment. 9. A circuit diagram of the standard cell of FIGS. 7 and 8.

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include fork sheet transistors with fork-shaped gate electrodes, which are nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0014] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0015] 1A and 1B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment. Specifically, FIG. 1A shows the lower part of a cell, i.e., the part including a fork sheet transistor formed on the side closer to the substrate, and FIG. 1B shows the upper part of a cell, i.e., the part including a fork sheet transistor formed on the side farther from the substrate.

[0016] 1 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a backside metal 0 (BM0) wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0017] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0018] 1 and other plan views, the dotted lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0019] In the layout of FIG. 1, a plurality of cells aligned in the X direction constitute a cell column CR (CR1 to CR3). A plurality of cell columns CR (three columns in FIG. 1) are aligned in the Y direction. The plurality of cells includes cells with logic functions such as inverters, NAND gates, and NOR gates. The plurality of cells includes, for example, inverter cells C1 and C4, two-input NAND cells C2 and C5, and two-input NOR cells C3 and C6, which will be described later.

[0020] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0021] Cell rows CR1 and CR2 adjacent in the Y direction are continuous in the X direction at the cell boundary, and share a power supply wiring 11 that supplies a power supply voltage VDD. Cell rows CR2 and CR3 adjacent in the Y direction are continuous in the X direction at the cell boundary, and share a power supply wiring 12 that supplies a power supply voltage VSS. That is, in the block layout of FIG. 1 , cell rows CR adjacent in the Y direction share a power supply wiring formed at the cell boundary. By sharing a power supply wiring between cell rows CR adjacent in the Y direction, the power supply wiring is strengthened, which can suppress a drop in power supply voltage and suppress the occurrence of electromigration due to current concentration.

[0022] An active region 2P that forms the channel, source, and drain of a P-type transistor is formed at the bottom of each cell. An active region 2N that forms the channel, source, and drain of an N-type transistor is formed at the top of each cell. In a cell row CR, the active regions 2P are arranged side by side in the X direction, and the active regions 2N are arranged side by side in the X direction.

[0023] As will be described in more detail later, in the standard cells arranged in cell row CR1, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR2, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR3, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction not exposed from the gate wiring, and their lower surface in the Y direction exposed from the gate wiring. That is, in the block layout of FIG. 1, in cells adjacent in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring facing each other in the Y direction, and their surfaces not exposed from the gate wiring facing each other in the Y direction. Specifically, the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR1 and the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR2 have surfaces that face each other in the Y direction exposed from the gate wiring. The nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR2 and the nanosheets of the active regions 2P (2N) of the standard cells arranged in cell row CR3 have surfaces that face each other in the Y direction not exposed from the gate wiring. This allows the distance d1 between the active regions 2P (2N) of the standard cells arranged in cell row CR1 and the active regions 2P (2N) of the standard cells arranged in cell row CR2 to be reduced, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced. In other words, the distance d1 between the active area 2P (2N) of the standard cell arranged in cell row CR1 and the active area 2P (2N) of the standard cell arranged in cell row CR2 is smaller than the distance d2 between the active area 2P (2N) of the standard cell arranged in cell row CR2 and the active area 2P (2N) of the standard cell arranged in cell row CR3.

[0024] Furthermore, the standard cells arranged in cell row CR1 have the lower ends of their active regions 2P (2N) arranged at the same position in the Y direction. The standard cells arranged in cell row CR2 have the upper ends of their active regions 2P (2N) arranged at the same position in the Y direction. The standard cells arranged in cell row CR3 have the lower ends of their active regions 2P (2N) arranged at the same position in the Y direction. That is, in cell row CR1, the lower ends of the active regions 2P (2N) in the Y direction are aligned. In cell row CR2, the upper ends of the active regions 2P (2N) in the Y direction are aligned. In cell row CR3, the lower ends of the active regions 2P (2N) in the Y direction are aligned. Furthermore, in the standard cells arranged in cell row CR1, the nanosheets included in the active regions 2P (2N) have the lower surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR2, the nanosheets included in the active region 2P (2N) have their upper surface in the Y direction exposed from the gate wiring. In the standard cells arranged in cell row CR3, the nanosheets included in the active region 2P (2N) have their lower surface in the Y direction exposed from the gate wiring. That is, in the standard cells arranged in cell row CR1, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. In the standard cells arranged in cell row CR2, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. In the standard cells arranged in cell row CR3, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing a structure made of an insulator between them. 1, in a cell row in which standard cells are arranged in the X direction, the position of the surface of the nanosheet exposed from the gate wiring can be aligned in the Y direction, thereby making it possible to make the shape of the structure, i.e., the size and layout area in the Y direction, constant, which facilitates the manufacture of semiconductor integrated circuit devices.

[0025] (Configuration of Inverter Cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C4 according to the embodiment, Fig. 3 is a cross-sectional view showing an example of the layout structure of the inverter cell according to the embodiment, and Fig. 4 is a circuit diagram configured in the inverter cell according to the embodiment. Specifically, Fig. 2(a) shows the lower part of inverter cell C1, Fig. 2(b) shows the upper part of inverter cell C1, Fig. 2(c) shows the lower part of inverter cell C4, Fig. 2(d) shows the upper part of inverter cell C4, Fig. 3(a) is a cross-section taken along X1-X1' in Figs. 2(a) and 2(b), Fig. 3(b) is a cross-section taken along Y1-Y1' in Figs. 2(a) and 2(b), Fig. 3(c) is a cross-section taken along Y2-Y2' in Figs. 2(a) and 2(b), and Fig. 3(d) is a cross-section taken along Y3-Y3' in Figs. 2(a) and 2(b).

[0026] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0027] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit having an input A and an output Y is configured.

[0028] 2A, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of a semiconductor chip on which transistors are formed. Power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. Power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. Power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0029] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0030] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0031] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0032] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has, as a channel, a nanosheet 22 having a structure of three overlapping sheets in a plan view and extending in the X direction.

[0033] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0034] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0035] 3(d), the gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so that part of the outer peripheries of the nanosheets 21 and 22 are exposed. Specifically, the right-hand side surfaces of the nanosheets 21 and 22 in the drawing are not covered by the gate wiring 31. That is, the right-hand side surfaces of the nanosheets 21 and 22 in the drawing are exposed from the gate wiring 31. Therefore, in FIG. 2, the lower surfaces of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper surfaces of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0036] 2, dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0037] 2A, a local interconnect (LI) 41 extending in the Y direction is formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that will become the drain of the transistor P1.

[0038] As shown in FIG. 2B , local wirings 42 and 43 extending in the Y direction are formed above the cell. The local wiring 42 is connected to a portion of the active region 2N1 that will become the source of the transistor N1. The local wiring 42 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in a region where the power supply wiring 12 and the local wiring 42 overlap in a planar view. That is, the power supply wiring 12 is connected to a portion of the active region 2N1 that will become the source of the transistor N1 via the via 62 and the local wiring 42. The local wiring 43 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0039] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, wires 51 and 52 extending in the X direction are formed. The wire 51 corresponds to the input A, and the wire 52 corresponds to the output Y.

[0040] The wiring 51 is disposed near the center of the cell in the Y direction. The wiring 51 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 51 and the active region 2N1 overlap in a plan view.

[0041] The wiring 52 is disposed on the upper side in the Y direction in the drawing. The wiring 52 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 41, 42.

[0042] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0043] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0044] In the inverter cell C1 shown in FIG. 2, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row CR is arranged in a flipped orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d3 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P1 and 2N1 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0045] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d3 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P1 (2N1) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P1 (2N1) is positioned closer to the lower end of the cell frame in the Y direction, based on the center of the cell frame in the Y direction. That is, in a planar view, the center of the active region 2P1 (2N1) in the Y direction is lower than the center of the cell frame in the Y direction.

[0046] Furthermore, power supply wiring 11 is formed at the bottom end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below inverter cell C1 in the Y direction in the drawing. Power supply wiring 12 is formed at the top end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above inverter cell C1 in the Y direction in the drawing. Thus, by placing inverter cell C1 in the circuit block of Figure 1, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and preventing electromigration due to current concentration.

[0047] Furthermore, the via 61 connecting the power supply wiring 11 and the portion of the active region 2P1 that serves as the source of the transistor P1 is formed in the area where the power supply wiring 11 and the active region 2P1 overlap in a planar view. In planar view, the via 61 is disposed toward the upper side of the area where the power supply wiring 11 and the active region 2P1 overlap in a planar view. In other words, in planar view, the distance d5 in the Y direction from the center of the via 61 to the upper end of the power supply wiring 11 is smaller than the distance d6 in the Y direction from the center of the via 61 to the lower end of the active region 2P1. As a result, since the via 61 is disposed toward the center of the active region 2P1 in the Y direction, the difference in resistance between the via 61 to the upper end of the nanosheet 21 of the transistor P1 in the active region 2P1 and the via 61 to the lower end of the nanosheet 21 of the transistor P1 in the active region 2P1 is reduced. Therefore, the current flowing through the transistor P1 is equalized in the Y direction (up and down in the drawing), which increases the speed of the semiconductor integrated circuit device.

[0048] Furthermore, the power supply wiring 12 is connected to the portion of the active region 2N1 that serves as the source of the transistor N1 via the via 62 and the local wiring 42. The via 62 connects the power supply wiring 12 formed in the BM0 wiring layer to the local wiring 42 formed above the cell, and therefore has a long length in the Z direction. As described above, the distance d3 from the bottom edge of the active region 2P1 (2N1) in the Y direction to the bottom edge of the cell frame in the Y direction is smaller than the distance d4 from the top edge of the active region 2P1 (2N1) in the Y direction to the top edge of the cell frame in the Y direction. This allows for a larger area from the top edge of the active region 2P1 (2N1) in the Y direction to the top edge of the cell frame in the Y direction, making it easier to form the via 62 in that area. This facilitates the manufacture of semiconductor integrated circuit devices, and improves yield and reliability.

[0049] Furthermore, the via 62 is formed in a region where the power supply wiring 12 and the local wiring 42 overlap in a planar view. In a planar view, the via 62 is disposed toward the lower side of the region where the power supply wiring 12 and the local wiring 42 overlap in a planar view. In other words, in a planar view, a distance d7 in the Y direction from the center of the via 62 to the bottom end of the power supply wiring 12 is smaller than a distance d8 in the Y direction from the center of the via 62 to the top end of the local wiring 42 in the planar view. This positions the via 62 closer to the active region 2N1, thereby reducing the resistance from the power supply wiring 12 to the portion of the active region 2N1 that serves as the source of the transistor N1, thereby increasing the speed of the semiconductor integrated circuit device.

[0050] Furthermore, via 63 connecting wiring 51 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N1 and gate wiring 31. This makes it possible to reduce the distance from wiring 51 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance value from wiring 51 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0051] Furthermore, the wiring 52 is arranged higher in the Y direction than the wiring 51 in the drawing (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N1 is arranged closer to the cell frame). The via 64 connecting the wiring 52 and the local wiring 43 and the via 65 connecting the local wirings 43 and 41 are formed higher in the Y direction than the wiring 51 in the drawing in a plan view. This reduces the distance from the wiring 52 to the portion of the active region 2P1 that serves as the drain of the transistor P1 and the portion of the active region 2N1 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 52 to the portion of the active region 2P1 (2N1) that serves as the drain of the transistor P1 (N1), and thereby increasing the speed of the semiconductor integrated circuit device.

[0052] (Configuration of Inverter Cell C4) The inverter cell C4 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y.

[0053] As shown in Figures 2(c) and (d), compared to the inverter cell C1 shown in Figures 2(a) and (b), the inverter cell C4 has active regions 2P4 and 2N4, each having a different width in the Y direction, arranged in place of the active regions 2P1 and 2N1.

[0054] Specifically, the active regions 2P4 and 2N4 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C4.

[0055] As shown in FIG. 2, the bottom edge of the active region 2P4 (2N4) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1 (2N1). That is, the bottom edge of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P4 (2N4) of the inverter cell C4 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C4 have their lower surfaces in the Y direction exposed from the gate wiring 31. That is, the nanosheet surfaces exposed from the gate wiring of the inverter cells C1 and C4 are aligned in the Y direction. This allows the shape of the insulating structure between the opposing nanosheets exposed from the gate wiring, i.e., their size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0056] In this embodiment, two inverter cells with different active region widths are arranged in a circuit block. However, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each inverter cell can be aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0057] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0058] Fig. 5(a) shows another example of the configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0059] 5B shows a cross section of inverter cell C1 of FIG. 2 taken along line Y1-Y1' in this configuration example. As shown in FIG. 5B, a power supply wiring 11 for supplying a power supply voltage VDD and a power supply wiring 12 for supplying a power supply voltage VSS are formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region 2P1 of chip A via via 61. Power supply wiring 12 is connected to active region 2N1 of chip A via via 62 and local wiring 42.

[0060] This configuration example also provides the same effects as the inverter cell described above.

[0061] (Modification) Fig. 6 is a plan view showing an example of the layout structure of an inverter cell according to a modification of the embodiment. Fig. 6 shows the lower part of the cell. Compared to Fig. 2(a), Fig. 6 has vias 61a and 62a arranged instead of vias 61 and 62.

[0062] 6, the vias 61a and 62a have a rectangular cross section in a plan view. Specifically, the vias 61a and 62a each have a length d9 in the Y direction that is longer than a length d10 in the X direction.

[0063] Furthermore, in plan view, the via 61a has a length d9 in the Y direction that is approximately the same as the length from the upper end of the power supply wiring 11 in the Y direction to the lower end of the active region 2P1 in the Y direction. In plan view, the via 62a has a length d9 in the Y direction that is approximately the same as the length from the upper end of the local wiring 42 in the Y direction to the lower end of the power supply wiring 12 in the Y direction.

[0064] According to the configuration of Figure 6, the resistance value of via 61a connecting power supply wiring 11 and the portion that serves as the source of transistor P1 in active region 2P1, and via 62a connecting power supply wiring 12 and the portion that serves as the source of transistor N1 in active region 2N1 can be reduced, thereby suppressing a drop in power supply voltage and preventing the occurrence of electromigration.

[0065] Furthermore, the via 62a has a long length in the Z direction because it connects the power supply wiring 12 formed in the BM0 wiring layer with the local wiring 42 formed above the cell. Therefore, by reducing the resistance value of the via 62a, it is possible to more effectively suppress a drop in the power supply voltage.

[0066] 6, vias 61a and 62a are arranged instead of the vias 61 and 62 in FIG. 2, but this is not limiting. Only one of the vias 61 and 62 in FIG. 2 may be changed to the vias 61a and 62a. In this case, changing the via 62 in FIG. 2 to the via 62a can more effectively suppress a drop in the power supply voltage.

[0067] 7(a) shows the lower part of a two-input NAND cell C2, FIG. 7(b) shows the upper part of a two-input NAND cell C2, FIG. 7(c) shows the lower part of a two-input NAND cell C5, FIG. 7(d) shows the upper part of a two-input NAND cell C5, FIG. 8(a) shows the lower part of a two-input NOR cell C3, FIG. 8(b) shows the upper part of a two-input NOR cell C3, FIG. 8(c) shows the lower part of a two-input NOR cell C6, FIG. 8(d) shows the upper part of a two-input NOR cell C6, FIG. 9(a) is a circuit diagram of a two-input NAND cell, and FIG. 9(b) is a circuit diagram of a two-input NOR cell.

[0068] The layout structures of FIGS. 7 and 8 can be easily inferred from the above description of the inverter cells and the circuit diagram of FIG. 9, and therefore will not be described further.

[0069] 7A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. Power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies power supply voltage VDD. Power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies power supply voltage VSS.

[0070] An active region 2P2 is formed in the P-type transistor region at the bottom of the cell. Transistors P11 and P12 are configured in the active region 2P2. The transistors P11 and P12 have nanosheets 23 and 24 extending in the X direction, respectively. In the active region 2P2, the portions that become the sources of the transistors P11 and P12 are connected to the power supply wiring 11 via vias 66 and 67, respectively. The vias 66 and 67 are formed in a region where the power supply wiring 11 and the active region 2P2 overlap in a planar view.

[0071] 7B, an active region 2N2 is formed in the N-type transistor region in the upper part of the cell. The active region 2N2 overlaps with the active region 2P2 in plan view.

[0072] The active region 2N2 includes transistors N11 and N12. The transistors N11 and N12 have nanosheets 25 and 26, respectively, that extend in the X direction.

[0073] Gate wirings 34 and 35 are formed extending in the Y direction. The nanosheets 23 and 25 overlap the gate wiring 34 in a planar view. The nanosheets 24 and 26 overlap the gate wiring 35 in a planar view. The gate wiring 34 corresponds to the gates of the transistors P11 and N11. The gate wiring 35 corresponds to the gates of the transistors P12 and N12.

[0074] The gate wiring 34 covers the outer peripheries of the nanosheets 23 and 25 in the Y and Z directions so that part of the outer peripheries of the nanosheets 23 and 25 are exposed. The gate wiring 35 covers the outer peripheries of the nanosheets 24 and 26 in the Y and Z directions so that part of the outer peripheries of the nanosheets 24 and 26 are exposed. Specifically, the lower surfaces of the nanosheets 23 and 25 in the Y direction are exposed from the gate wiring 34, and the upper surfaces of the nanosheets 24 and 26 in the Y direction are covered by the gate wiring 34. The lower surfaces of the nanosheets 24 and 26 in the Y direction are exposed from the gate wiring 35, and the upper surfaces of the nanosheets 24 and 26 in the Y direction are covered by the gate wiring 35.

[0075] 7B, a local wiring 44 extending in the Y direction is formed above the cell. The local wiring 44 is connected to a portion of the active region 2N2 that will become the source of the transistor N11. The local wiring 44 is connected to the power supply wiring 12 via a via 68. The via 68 is formed in a region where the power supply wiring 12 and the local wiring 44 overlap in a planar view. In other words, the power supply wiring 12 is connected to a portion of the active region 2N2 that will become the source of the transistor N11 via the via 68 and the local wiring 44.

[0076] In the M0 wiring layer, wires 51 to 53 extending in the X direction are formed. The wire 51 corresponds to the input A, the wire 52 corresponds to the output Y, and the wire 53 corresponds to the input B.

[0077] The wiring 51 is disposed near the center of the cell in the Y direction in the drawing. The wiring 51 is connected to the gate wiring 34 through a via 69. The via 69 is formed in a region where the wiring 51 and the active region 2N2 overlap in a plan view.

[0078] The wiring 52 is arranged at the top of the cell in the Y direction in the drawing. The wiring 52 is connected to the drains of the transistors P11 and P12 in the active region 2P2 and the drain of the transistor N12 in the active region 2N2 via vias 70 and 71 and local wiring.

[0079] The wiring 53 is disposed near the center of the cell in the Y direction in the drawing. The wiring 53 is connected to the gate wiring 35 through a via 72. The via 72 is formed in a region where the wiring 53 and the active region 2N2 overlap in a plan view.

[0080] As described above, the two-input NAND cell C2 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and realizes a NAND circuit with inputs A and B and an output Y.

[0081] As shown in FIGS. 7A and 7B, the active regions 2P2 and 2N2 in the two-input NAND cell C2 have a width of w1 in the Y direction in plan view.

[0082] In the two-input NAND cell C2 shown in FIG. 7, the nanosheets 23 and 25 have their lower surfaces in the Y direction exposed from the gate wiring 34. The nanosheets 24 and 26 have their lower surfaces in the Y direction exposed from the gate wiring 35. Furthermore, every other cell row CR is arranged inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d3 from the lower end of the active region 2P2 (2N2) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P2 and 2N2 (nanosheets 23-26) can be arranged close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0083] Furthermore, the upper surfaces of the nanosheets 23 and 25 in the Y direction are not exposed from the gate wiring 34. The upper surfaces of the nanosheets 24 and 26 in the Y direction are not exposed from the gate wiring 35. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d3 from the lower end of the active region 2P2 (2N2) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P2 (2N2) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P2 (2N2) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P2 (2N2) in the Y direction is located below the center of the cell frame in the Y direction.

[0084] Furthermore, power supply wiring 11 is formed at the bottom end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below two-input NAND cell C2 in the Y direction in the drawing. Power supply wiring 12 is formed at the top end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above two-input NAND cell C2 in the Y direction in the drawing. Thus, by placing two-input NAND cell C2 in the circuit block of Figure 1, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and preventing electromigration due to current concentration.

[0085] Furthermore, the via 66 (67) connecting the power supply wiring 11 and the portion of the active region 2P2 that serves as the source of the transistor P11 (P12) is formed in the region where the power supply wiring 11 and the active region 2P2 overlap in a planar view. In a planar view, the via 66 (67) is disposed toward the upper side of the region where the power supply wiring 11 and the active region 2P2 overlap in a planar view. In other words, in a planar view, the distance d5 in the Y direction from the center of the via 66 (67) to the upper end of the power supply wiring 11 is smaller than the distance d6 in the Y direction from the center of the via 66 (67) to the lower end of the active region 2P2. As a result, the via 66 (67) is positioned closer to the center of the active region 2P2 in the Y direction of the drawing, thereby reducing the difference in resistance between the resistance from the via 66 (67) to the upper end of the nanosheets 23, 24 of the transistor P11 (P12) in the active region 2P2 in the drawing and the resistance from the via 66 (67) to the lower end of the nanosheets 23, 24 of the transistor P11 (P12) in the active region 2P2 in the drawing. Therefore, the current flowing through the transistor P11 (P12) is equalized in the vertical direction of the drawing in the Y direction, thereby increasing the speed of the semiconductor integrated circuit device.

[0086] Furthermore, the power supply wiring 12 is connected to the portion of the active region 2N2 that serves as the source of the transistor N11 via the via 68 and the local wiring 44. The via 68 connects the power supply wiring 12 formed in the BM0 wiring layer to the local wiring 44 formed above the cell, and therefore has a long length in the Z direction. As described above, the distance d3 from the bottom edge of the active region 2P2 (2N2) in the Y direction to the bottom edge of the cell frame in the Y direction is smaller than the distance d4 from the top edge of the active region 2P2 (2N2) in the Y direction to the top edge of the cell frame in the Y direction. This allows for a larger area from the top edge of the active region 2P2 (2N2) in the Y direction to the top edge of the cell frame in the Y direction, making it easier to form the via 68 in that area. This facilitates the manufacture of semiconductor integrated circuit devices, and improves yield and reliability.

[0087] Furthermore, the via 68 is formed in a region where the power supply wiring 12 and the local wiring 44 overlap in a planar view. In a planar view, the via 68 is disposed toward the lower side of the region where the power supply wiring 12 and the local wiring 44 overlap in a planar view. In other words, in a planar view, a distance d7 in the Y direction from the center of the via 68 to the bottom end of the power supply wiring 12 is smaller than a distance d8 in the Y direction from the center of the via 68 to the top end of the local wiring 44. This positions the via 68 closer to the active region 2N2, thereby reducing the resistance from the power supply wiring 12 to the portion of the active region 2N2 that serves as the source of the transistor N11, thereby increasing the speed of the semiconductor integrated circuit device.

[0088] Furthermore, vias 69 (72) connecting wiring 51 (53) and gate wiring 34 (35) are formed in a region that overlaps with active region 2N2 and gate wiring 34 (35) in plan view. This reduces the distance from wiring 51 (53) corresponding to input A (input B) to the portion of gate wiring 34 (35) that overlaps with nanosheets 23, 25 (24, 26) in plan view and covers nanosheets 23, 25 (24, 26), thereby reducing the resistance from wiring 51 (53) and increasing the speed of the semiconductor integrated circuit device.

[0089] Furthermore, the wiring 52 is arranged higher in the Y direction than the wirings 51 and 53 in the drawing (the side where the nanosheets 25 and 26 are not exposed from the gate wirings 34 and 35, respectively, and opposite the side where the active region 2N2 is arranged closer to the cell frame). The via 70 connects the wiring 52 to a local wiring connected to a portion of the active region 2P2 that will become the drain of the transistors P11 and P12. The via 71 connects the wiring 52 to a local wiring connected to a portion of the active region 2N2 that will become the drain of the transistor N12. The vias 70 and 71 are formed higher in the Y direction than the wirings 51 and 53 in a plan view. This reduces the distance from wiring 52 to the portion that becomes the drain of transistors P11 and P12 in active region 2P2 and the portion that becomes the drain of transistor N12 in active region 2N2, thereby reducing the resistance value from wiring 52 to the portion that becomes the drain of transistors P11 and P12 (N12) in active region 2P2 (2N2), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0090] (Configuration of Two-Input NAND Cell C5) The two-input NAND cell C5 has a configuration similar to that of the two-input NAND cell C2. Specifically, the two-input NAND cell C5 has P-type transistors P11 and P12 and N-type transistors N11 and N12, and implements a NAND circuit with inputs A and B and an output Y.

[0091] As shown in Figures 7(c) and (d), compared to the two-input NAND cell C2 shown in Figures 7(a) and (b), the two-input NAND cell C5 has active regions 2P5 and 2N5 with different widths in the Y direction arranged therein instead of the active regions 2P2 and 2N2.

[0092] Specifically, the active regions 2P5 and 2N5 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the two-input NAND cell C2 is greater than the drive capability of the two-input NAND cell C5.

[0093] As shown in FIG. 7, the bottom edge of the active region 2P5 (2N5) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P2 (2N2) in the Y direction. That is, the bottom edge of the active region 2P2 (2N2) of the two-input NAND cell C2 in the Y direction and the bottom edge of the active region 2P5 (2N5) of the two-input NAND cell C5 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 23 (25) of the two-input NAND cells C2 and C5 have their lower surfaces exposed from the gate wiring 34. The nanosheets 24 (26) of the two-input NAND cells C2 and C5 have their lower surfaces exposed from the gate wiring 35 in the Y direction. That is, the nanosheet surfaces exposed from the gate wiring of the two-input NAND cells C2 and C5 are aligned in the Y direction. This allows the shape of the insulating structure, which is exposed from the gate wiring and provided between the opposing nanosheets, i.e., the size and placement area in the Y direction, to be constant, thereby facilitating the manufacture of semiconductor integrated circuit devices.

[0094] In this embodiment, two two-input NAND cells with different active area widths are arranged in a circuit block. However, three or more two-input NAND cells with different active area widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each two-input NAND cell is simply aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0095] 8A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. Power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies power supply voltage VDD. Power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies power supply voltage VSS.

[0096] An active region 2P3 is formed in the P-type transistor region at the bottom of the two-input NOR cell C3. Transistors P21 and P22 are configured in the active region 2P3. The transistors P21 and P22 have nanosheets 27 and 28 extending in the X direction, respectively. In the active region 2P3, the portions that serve as the sources of the transistors P21 and P22 are connected to the power supply wiring 11 via vias 73. The vias 73 are formed in a region where the power supply wiring 11 and the active region 2P3 overlap in a planar view.

[0097] 8B, an active region 2N3 is formed in the N-type transistor region in the upper part of the cell. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0098] The active region 2N3 includes transistors N21 and N22. The transistors N21 and N22 have nanosheets 29 and 30, respectively, that extend in the X direction.

[0099] Gate wirings 36 and 37 are formed extending in the Y direction. The nanosheets 27 and 29 overlap the gate wiring 36 in a planar view. The nanosheets 28 and 30 overlap the gate wiring 37 in a planar view. The gate wiring 36 corresponds to the gates of the transistors P21 and N21. The gate wiring 37 corresponds to the gates of the transistors P22 and N22.

[0100] The gate wiring 36 covers the outer peripheries of the nanosheets 27, 29 in the Y and Z directions so that part of the outer peripheries of the nanosheets 27, 29 are exposed. The gate wiring 37 covers the outer peripheries of the nanosheets 28, 30 in the Y and Z directions so that part of the outer peripheries of the nanosheets 28, 30 are exposed. Specifically, the lower surfaces of the nanosheets 27, 29 in the Y direction are exposed from the gate wiring 36, and the upper surfaces of the nanosheets 27, 29 in the Y direction are covered by the gate wiring 36. The lower surfaces of the nanosheets 27, 29 in the Y direction are exposed from the gate wiring 37, and the upper surfaces of the nanosheets 27, 29 in the Y direction are covered by the gate wiring 37.

[0101] 8B, a local wiring 45 extending in the Y direction is formed above the cell. The local wiring 45 is connected to the portions of the active region 2N3 that serve as the sources of the transistors N21 and N22. The local wiring 45 is connected to the power supply wiring 12 via a via 74. The via 74 is formed in a region where the power supply wiring 12 and the local wiring 45 overlap in a planar view. In other words, the power supply wiring 12 is connected to the portions of the active region 2N3 that serve as the sources of the transistors N21 and N22 via the via 74 and the local wiring 45.

[0102] In the M0 wiring layer, wires 51 to 53 extending in the X direction are formed. The wire 51 corresponds to the input A, the wire 52 corresponds to the output Y, and the wire 53 corresponds to the input B.

[0103] The wiring 51 is disposed near the center of the cell in the Y direction in the drawing. The wiring 51 is connected to the gate wiring 36 through a via 75. The via 75 is formed in a region where the wiring 51 and the active region 2N3 overlap in a plan view.

[0104] The wiring 52 is arranged at the top of the cell in the Y direction in the drawing. The wiring 52 is connected to the portion that will become the drain of the transistor P22 in the active region 2P3 and the portions that will become the drains of the transistors N21 and N22 in the active region 2N3 through vias 76 to 78 and local wiring.

[0105] The wiring 53 is disposed near the center of the cell in the Y direction in the drawing. The wiring 53 is connected to the gate wiring 37 through a via 79. The via 79 is formed in a region where the wiring 53 and the active region 2N3 overlap in a plan view.

[0106] As described above, the two-input NOR cell C3 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and an output Y.

[0107] As shown in FIGS. 8A and 8B, the active regions 2P3 and 2N3 of the two-input NOR cell C3 have a width of w1 in the Y direction in plan view.

[0108] In the two-input NOR cell C3 shown in FIG. 8, the nanosheets 27 and 29 have their lower Y-direction surfaces exposed from the gate wiring 36. The nanosheets 28 and 30 have their lower Y-direction surfaces exposed from the gate wiring 37. Furthermore, every other cell row CR is inverted in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their exposed surfaces (lower surfaces) from the gate wiring facing each other in the Y direction. This reduces the distance d3 from the lower Y-direction edge of the active region 2P3 (2N3) to the lower Y-direction edge of the cell frame. In other words, the active regions 2P3 and 2N3 (nanosheets 27-30) can be positioned close to the lower Y-direction edge of the cell frame. This allows for a smaller area for the semiconductor integrated circuit device.

[0109] Furthermore, the upper surfaces of the nanosheets 27 and 29 in the Y direction are not exposed from the gate wiring 36. The upper surfaces of the nanosheets 28 and 30 in the Y direction are not exposed from the gate wiring 37. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction face each other in the Y direction with the surfaces exposed from the gate wiring (the lower surfaces) facing each other, and the surfaces not exposed from the gate wiring (the upper surfaces) facing each other. Therefore, the distance d3 from the lower end of the active region 2P3 (2N3) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d4 from the upper end of the active region 2P3 (2N3) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P3 (2N3) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P3 (2N3) in the Y direction is located below the center of the cell frame in the Y direction.

[0110] Furthermore, power supply wiring 11 is formed at the bottom end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below two-input NOR cell C3 in the Y direction in the drawing. Power supply wiring 12 is formed at the top end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above two-input NOR cell C3 in the Y direction in the drawing. Thus, by placing two-input NOR cell C3 in the circuit block of Figure 1, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and preventing electromigration due to current concentration.

[0111] Furthermore, the via 73 connecting the power supply wiring 11 and the portion of the active region 2P3 that serves as the source of the transistor P21 is formed in the region where the power supply wiring 11 and the active region 2P3 overlap in a planar view. In planar view, the via 73 is disposed toward the upper side of the region where the power supply wiring 11 and the active region 2P3 overlap in a planar view. In other words, in planar view, the distance d5 in the Y direction from the center of the via 73 to the upper end of the power supply wiring 11 is smaller than the distance d6 in the Y direction from the center of the via 73 to the lower end of the active region 2P3. As a result, since the via 73 is disposed toward the center of the active region 2P3 in the Y direction, the difference in resistance between the via 73 to the upper end of the nanosheet 27 of the transistor P21 in the active region 2P3 and the lower end of the nanosheet 27 of the transistor P21 in the active region 2P3 is reduced. Therefore, the current flowing through the transistor P21 is equalized in the Y direction (up and down in the drawing), which increases the speed of the semiconductor integrated circuit device.

[0112] Furthermore, the power supply wiring 12 is connected to the source portions of the transistors N21 and N22 in the active region 2N3 via the via 74 and the local wiring 45. The via 74 connects the power supply wiring 12 formed in the BM0 wiring layer to the local wiring 45 formed above the cell, and therefore has a long length in the Z direction. As described above, the distance d3 from the bottom edge of the active region 2P3 (2N3) in the Y direction to the bottom edge of the cell frame in the Y direction is smaller than the distance d4 from the top edge of the active region 2P3 (2N3) in the Y direction to the top edge of the cell frame in the Y direction. This allows for a larger area from the top edge of the active region 2P3 (2N3) in the Y direction to the top edge of the cell frame in the Y direction, making it easier to form the via 74 in that area. This facilitates the manufacture of semiconductor integrated circuit devices, and improves yield and reliability.

[0113] Furthermore, the via 74 is formed in a region where the power supply wiring 12 and the local wiring 45 overlap in a planar view. In a planar view, the via 74 is disposed toward the lower side of the region where the power supply wiring 12 and the local wiring 45 overlap in a planar view. In other words, in a planar view, a distance d7 in the Y direction from the center of the via 74 to the bottom end of the power supply wiring 12 is smaller than a distance d8 in the Y direction from the center of the via 74 to the top end of the local wiring 45 in the planar view. This positions the via 74 closer to the active region 2N3, thereby reducing the resistance from the power supply wiring 12 to the portions of the active region 2N3 that serve as the sources of the transistors N21 and N22, thereby increasing the speed of the semiconductor integrated circuit device.

[0114] Furthermore, via 75 (79) connecting wiring 51 (53) and gate wiring 36 (37) is formed in a region that overlaps with active region 2N3 and gate wiring 36 (37) in plan view. This reduces the distance from wiring 51 (53) corresponding to input A (input B) to the portion of gate wiring 36 (37) that overlaps with nanosheets 27, 29 (28, 30) in plan view and covers nanosheets 27, 29 (28, 30), thereby reducing the resistance from wiring 51 (53) and enabling the speed of the semiconductor integrated circuit device to be increased.

[0115] Furthermore, the wiring 52 is arranged higher in the Y direction than the wirings 51 and 53 in the drawing (the side where the nanosheets 29 and 30 are not exposed from the gate wirings 36 and 37, respectively, and opposite the side where the active region 2N3 is arranged closer to the cell frame). The via 76 connects the wiring 52 to a local wiring connected to a portion of the active region 2N3 that will become the drain of the transistor N21. The via 77 connects the wiring 52 to a local wiring connected to a portion of the active region 2N3 that will become the drain of the transistor N22. The via 78 connects the local wiring connected to a portion of the active region 2N3 that will become the drain of the transistor N22 and a local wiring connected to a portion of the active region 2P3 that will become the drain of the transistor P22. The vias 76 to 78 are formed higher in the Y direction than the wirings 51 and 53 in a plan view. This reduces the distance from wiring 52 to the portion that becomes the drain of transistor P22 in active region 2P3 and the portion that becomes the drain of transistors N21 and N22 in active region 2N3, thereby reducing the resistance value from wiring 52 to the portion that becomes the drain of transistor P22 (N21, N22) in active region 2P3 (2N3), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0116] (Configuration of 2-input NOR cell C6) The 2-input NOR cell C6 has almost the same configuration as the 2-input NOR cell C3. Specifically, the 2-input NOR cell C6 has P-type transistors P21 and P22 and N-type transistors N21 and N22, and realizes a NOR circuit with inputs A and B and output Y.

[0117] As shown in Figures 8(c) and (d), compared to the two-input NOR cell C3 shown in Figures 8(a) and (b), the two-input NOR cell C6 has active regions 2P6 and 2N6, which have different widths in the Y direction, arranged in place of the active regions 2P3 and 2N3.

[0118] Specifically, the active regions 2P6 and 2N6 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the two-input NOR cell C3 is greater than the drive capability of the two-input NOR cell C6.

[0119] As shown in FIG. 8 , the bottom edge of the active region 2P6 (2N6) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P3 (2N3). That is, the bottom edge of the active region 2P3 (2N3) of the two-input NOR cell C3 in the Y direction and the bottom edge of the active region 2P6 (2N6) of the two-input NOR cell C6 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 27 (29) of the two-input NOR cells C3 and C6 have their lower surfaces exposed from the gate wiring 36. The nanosheets 28 (30) of the two-input NOR cells C3 and C6 have their lower surfaces exposed from the gate wiring 37. That is, the nanosheets of the two-input NOR cells C3 and C6 have their surfaces exposed from the gate wiring aligned in the Y direction. This allows the shape of the insulating structure, which is exposed from the gate wiring and provided between the opposing nanosheets, i.e., the size and area of ​​placement in the Y direction, to be constant, thereby facilitating the manufacture of semiconductor integrated circuit devices.

[0120] In this embodiment, two two-input NOR cells with different active area widths are arranged in a circuit block. However, three or more two-input NOR cells with different active area widths may be arranged in a circuit block. In this case, the position of the surface of the nanosheet exposed from the gate wiring in each two-input NOR cell is simply aligned in the Y direction. This allows the shape of the insulating structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and layout area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0121] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0122] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0123] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0124] In addition, in the above-described embodiments and modifications, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0125] In the two-input NAND cells C2 and C5, the vias 66 and 67 (68) may be replaced by a via whose length in the Y direction is greater than its length in the X direction, such as the via 61a (62a) shown in Fig. 6. Similarly, in the two-input NOR cells C3 and C6, the via 73 (74) may be replaced by a via whose length in the Y direction is greater than its length in the X direction, such as the via 61a (62a) shown in Fig. 6.

[0126] Regarding standard cells using CFETs, in the layout of a semiconductor integrated circuit device including standard cells using fork-sheet transistors as transistors, it is possible to suppress a drop in power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0127] 11, 12 Power supply wiring 21-30 Nanosheet 31, 34-37 Gate wiring 41-45 Local wiring 51-53 Wiring 61-78, 61a, 62a Via 2P, 2P1-2P6, 2N, 2N1-2N6 Active area P1, P11, P12, P21, P22, N1, N11, N12, N21, N22 Transistor C1, C4 Inverter cell C2, C5 2-input NAND cell C3, C6 2-input NOR cell

Claims

1. A semiconductor integrated circuit device including a plurality of standard cells including a first standard cell, wherein the first standard cell comprises: a first active region forming a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region forming a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being a second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; and a second power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage, a semiconductor integrated circuit device, wherein the first and second nanosheets have a first side surface, which is one side in the second direction, exposed from the first gate wiring, the first power supply wiring is disposed at an end of the first standard cell on the first side, and the second power supply wiring is disposed at an end of the second side, which is the other side in the second direction, of the first standard cell.

2. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells includes a second standard cell arranged adjacent to the first side of the first standard cell, and the first power supply wiring is shared by the first and second standard cells.

3. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells includes a third standard cell arranged adjacent to the second side of the first standard cell, and the second power supply wiring is shared by the first and third standard cells.

4. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell is formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, and further comprising a first via connecting the source of the first transistor in the first active region to the first power supply wiring.

5. A semiconductor integrated circuit device according to claim 4, wherein, in a plan view, the distance from the center of the first via in the second direction to the end of the first power supply voltage on the second side is smaller than the distance from the center of the first via in the second direction to the end of the first active region on the first side.

6. A semiconductor integrated circuit device according to claim 4, wherein the length of said first via in said second direction is longer than the length of said first via in said first direction.

7. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell further comprises: a first wiring connected to a region in the second active region that serves as the source of the second transistor; and a second via formed in a region where the first wiring and the second power supply wiring overlap in a planar view, the second via connecting the first wiring and the second power supply wiring.

8. A semiconductor integrated circuit device according to claim 7, wherein, in a plan view, the distance from the center of the second via in the second direction to the end of the second power supply wiring on the first side is smaller than the distance from the center of the second via in the second direction to the end of the first wiring on the second side.

9. A semiconductor integrated circuit device according to claim 7, wherein the second via has a length in the second direction longer than its length in the first direction.

10. A semiconductor integrated circuit device according to claim 1, wherein the distance from the first side end of the first active region to the first side end of the first standard cell is smaller than the distance from the second side end of the first active region to the second side end of the first standard cell.

11. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells include a second standard cell arranged adjacent to the first side of the first standard cell, and a third standard cell arranged adjacent to the second side of the first standard cell, wherein the second standard cell comprises: a third active region constituting a channel, source and drain of a third transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel, and a third gate wiring extending in the second direction and surrounding the periphery of the third nanosheet in the second direction and the depth direction, wherein the third standard cell comprises: a fourth active region constituting a channel, source and drain of a fourth transistor of the first conductivity type, the fourth active region including a fourth nanosheet extending in the first direction as the channel, and a fourth gate wiring extending in the second direction and surrounding the periphery of the fourth nanosheet in the second direction and the depth direction, wherein the second side surface of the third nanosheet is exposed from the third gate wiring, a semiconductor integrated circuit device, wherein the fourth nanosheet has a second side surface exposed from the fourth gate wiring, and a distance between the first active region and the third active region in the second direction is smaller than a distance between the first active region and the fourth active region in the second direction.

12. A semiconductor integrated circuit device according to claim 1, wherein the first active region constitutes a channel, source and drain of a fifth transistor of the first conductivity type, and includes a fifth nanosheet extending in the first direction as the channel; the second active region constitutes a channel, source and drain of a sixth transistor of the second conductivity type, and includes a sixth nanosheet extending in the first direction as the channel; the first standard cell is provided with a second gate wiring extending in the second direction and surrounding the outer periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring.

13. A semiconductor integrated circuit device according to claim 1, wherein the plurality of standard cells include a fourth standard cell arranged alongside the first standard cell in the first direction, the fourth standard cell comprising: a seventh active region constituting a channel, source and drain of a seventh transistor of the first conductivity type and including a seventh nanosheet extending in the first direction as the channel; an eighth active region formed above the seventh active region in the depth direction and overlapping with the seventh active region in a plan view, constituting a channel, source and drain of an eighth transistor of the second conductivity type and including an eighth nanosheet extending in the first direction as the channel; and a fifth gate wiring extending in the second direction and surrounding the outer periphery of the seventh and eighth nanosheets in the second direction and the depth direction, wherein the seventh and eighth nanosheets have a first side surface which is one side in the second direction exposed from the fifth gate wiring, and in a plan view, the width of the seventh nanosheet in the second direction is smaller than the width of the first nanosheet in the second direction, A semiconductor integrated circuit device, wherein, in a planar view, the end portion on the first side of the first nanosheet and the end portion on the first side of the seventh nanosheet are arranged at the same position in the second direction.

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