Three-dimensional flash memory with silicon-based channel structure

Abstract

Disclosed is a three-dimensional flash memory with a silicon-based channel structure. The three-dimensional flash memory according to an embodiment may have a structure of a composite vertical channel pattern including a first vertical channel pattern formed of a polycrystalline material, a second vertical channel pattern formed of a single crystal material, and an ion barrier film interposed between the first vertical channel pattern and the second vertical channel pattern.

Description

3D flash memory with silicon-based channel structure

[0001] The embodiments below describe a technology for a three-dimensional flash memory with a silicon-based channel structure.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is necessary to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a memory cell string has been proposed.

[0004] In such 3D flash memory, there is a problem that the mobility of the vertical channel pattern decreases as the vertical direction is increased. To solve this problem, a single crystallization process, such as a metal-induced crystallization (MILC) process that converts the polycrystalline silicon material constituting the vertical channel pattern into a single crystal silicon material, has been applied.

[0005] However, the metal-induced crystallization process generates metal ions, which cause the metal ions to penetrate into the data storage pattern included in the 3D flash memory, thereby lowering memory performance.

[0006] Therefore, there is a need to propose a technology to prevent or solve the problem of metal ions generated in the metal-induced crystallization process penetrating into the data storage pattern and degrading memory performance.

[0007]

[0008] One embodiment proposes a three-dimensional flash memory having a structure in which an ion barrier film is interposed between a first vertical channel pattern formed of a polycrystalline material and a second vertical channel pattern formed of a single crystal material to block ions generated in a single crystallization process from moving to a data storage pattern in order to ensure memory performance, and a method for manufacturing the same.

[0009] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0010] According to one embodiment, a three-dimensional flash memory may include word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed to contact an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines, wherein the composite vertical channel pattern includes a first vertical channel pattern formed of a polycrystalline material, a second vertical channel pattern formed of a single-crystalline material, and an ion barrier film interposed between the first vertical channel pattern and the second vertical channel pattern.

[0011] According to one aspect, the ion barrier film may be characterized by blocking ions generated in a single crystallization process for forming the second vertical channel pattern from moving to the data storage pattern.

[0012] According to another aspect, the ion barrier film may be characterized by blocking metal ions generated in a metal-induced crystallization (MILC) process that converts the polycrystalline material into the single-crystal material from moving to the data storage pattern.

[0013] According to another aspect, the ion barrier film is TiO x , GaO x , Al2O3, SiO2 or SiN x It may be characterized by being formed of an insulating material based on the substrate, or being formed by doping Ga, Ti, Sn, Zn or In into the insulating material, or being formed by stacking the insulating material in multiple layers to form a multilayer structure.

[0014] According to another aspect, the ion barrier film may be formed to a thickness that satisfies a condition capable of blocking ions generated in a single crystallization process for forming the second vertical channel pattern from moving to the data storage pattern.

[0015] According to another aspect, the ion barrier film may be characterized by being formed with a thickness of between 1 nm and 3 nm.

[0016] According to one embodiment, a method for manufacturing a three-dimensional flash memory, comprising: word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed to contact an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines; may include a step of forming the composite vertical channel pattern with a first vertical channel pattern formed of a polycrystalline material, a second vertical channel pattern formed of a single-crystalline material, and an ion barrier film interposed between the first vertical channel pattern and the second vertical channel pattern.

[0017] According to one aspect, the step of forming the composite vertical channel pattern includes: forming the first vertical channel pattern with the polycrystalline material on the inner wall of the data storage pattern; forming the ion barrier film on the inner wall of the first vertical channel pattern; and forming the second vertical channel pattern with the single crystal material on the inner wall of the ion barrier film, wherein the step of forming the ion barrier film may be characterized as a step of forming the ion barrier film that blocks ions generated in a single crystallization process of forming the second vertical channel pattern from moving to the data storage pattern.

[0018] According to another aspect, the step of forming the second vertical channel pattern may include the step of depositing the polycrystalline material on the inner wall of the ion barrier film; and the step of performing a metal-induced crystallization (MILC) process to convert the polycrystalline material into the single-crystal material.

[0019] According to another aspect, the step of forming the ion barrier film may be characterized as a step of forming the ion barrier film that blocks metal ions generated in the metal-induced crystallization process for converting the polycrystalline material into the single-crystal material from moving to the data storage pattern.

[0020] One embodiment proposes a three-dimensional flash memory having a structure in which an ion barrier film is interposed between a first vertical channel pattern formed of a polycrystalline material and a second vertical channel pattern formed of a single-crystalline material to block ions generated in a single-crystallization process for forming a second vertical channel pattern from moving to a data storage pattern, and a method for manufacturing the same, thereby achieving a technical effect of ensuring memory performance.

[0021] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0022] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0023] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0024] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0025] FIG. 4 is a cross-sectional view illustrating an ion barrier film of a composite vertical channel pattern in a three-dimensional flash memory according to one embodiment.

[0026] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0027] FIGS. 6A to 6D are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain a method for manufacturing the three-dimensional flash memory illustrated in FIG. 5.

[0028] FIG. 7 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0030] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents of this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used in this specification do not exclude the presence or addition of one or more other components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0031] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0032] Hereinafter, with reference to the drawings, a three-dimensional flash memory having a structure in which an ion barrier film is interposed between a first vertical channel pattern formed of a polycrystalline material and a second vertical channel pattern formed of a single crystal material to block ions generated in a single crystallization process from moving to a data storage pattern in order to ensure memory performance, and a manufacturing method thereof will be described in detail.

[0033]

[0034] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0035] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0036] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0037] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be two-dimensionally arranged while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically identically voltage-applied, but the present invention is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

[0038] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0039] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0040] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

[0041] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0042] The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

[0043] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction (D1), are spaced apart from each other in a second direction (D2) and can be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from common source lines (CSL) can be electrically isolated from each other. In addition, erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and / or the common source lines (CSL) during an erase operation of the memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0044] The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

[0045]

[0046] FIG. 2 is a plan view illustrating a structure of a three-dimensional flash memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 4 is a cross-sectional view illustrating an ion barrier film of a complex vertical channel pattern in a three-dimensional flash memory according to one embodiment.

[0047] Referring to the drawings, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0048] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0049] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0050] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0051] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0052] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0053] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0054] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0055] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0056] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0057] The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 2, twelve vertical channel structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical channel structures (VS) forming the array is not limited or restricted thereto.

[0058] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0059] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on a horizontal plane and to be misaligned with each other. For example, the vertical channel structures (VS) included in a first column may be arranged in the first and third rows, and the vertical channel structures (VS) included in a second column may be arranged in the second and fourth rows, such that the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0060] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0061] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a composite vertical channel pattern (CVCP), a vertical filling pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the composite vertical channel pattern (CVCP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical filling pattern (VFP) may have a shape that fills an inner space of the composite vertical channel pattern (CVCP). However, without being limited thereto, the composite vertical channel pattern (CVCP) may also have a pipe shape or a macaroni shape with a closed bottom.

[0062] The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the composite vertical channel pattern (CVCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with regions corresponding to the second gate electrodes (EL2) of the composite vertical channel pattern (CVCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0063] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0064] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the composite vertical channel pattern (CVCP).

[0065] A composite vertical channel pattern (CVCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The composite vertical channel pattern (CVCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the composite vertical channel pattern (CVCP) may be composed of a plurality of vertical channel patterns (VCP1, VCP2) and an ion barrier film (IB) interposed between the vertical channel patterns (VCP1, VCP2).

[0066] Hereinafter, the composite vertical channel pattern (CVCP) is described as including two vertical channel patterns (VCP1, VCP2), but is not limited thereto and may include three or more vertical channel patterns. In this case, two ion transport barrier films may be respectively arranged in two spaces between the three or more vertical channel patterns.

[0067] Among the vertical channel patterns (VCP1, VCP2), the first vertical channel pattern (VCP1) may be formed of a polycrystalline material (e.g., polycrystalline silicon material) while in contact with the inner wall of the data storage pattern (DSP).

[0068] Among the vertical channel patterns (VCP1, VCP2), the second vertical channel pattern (VCP2) can be formed of a monocrystalline material (e.g., a monocrystalline silicon material) through a monocrystallization process after a polycrystalline material (e.g., a polycrystalline silicon material) is deposited in the internal space of the first vertical channel pattern (VCP1).

[0069] The ion barrier film (IB) is interposed between the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2), as illustrated in FIG. 4, and can block ions generated in the single crystallization process for forming the second vertical channel pattern (VCP2) from moving to the data storage pattern (DSP).

[0070] For example, an ion barrier film (IB) is formed of TiO to block metal ions (e.g., nickel ions) generated in a metal-induced crystallization (MILC) process that converts a polycrystalline material (e.g., polycrystalline silicon material) into a single-crystalline material (e.g., single-crystalline silicon material) from migrating to the data storage pattern (DSP). x , GaO x , Al2O3, SiO2 or SiN xIt may be formed by forming a base insulating material, or by doping Ga, Ti, Sn, Zn or In into the insulating material, or by forming a multilayer structure by stacking the insulating material in multiple layers.

[0071] At this time, the ion barrier film (IB) can be formed with a thickness that satisfies the condition of being able to block ions generated in the single crystallization process for forming the second vertical channel pattern (VCP2) from moving to the data storage pattern (DSP).

[0072] For example, the ion barrier film (IB) can be formed with a thinner thickness (e.g., a thickness between 1 nm and 3 nm) than the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2).

[0073] The upper surface of the composite vertical channel pattern (CVCP) can be substantially coplanar with the upper surface of the vertical buried pattern (VFP), and can be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the composite vertical channel pattern (CVCP) can be positioned between the upper and lower surfaces of the third gate electrode (EL3). The lower surface of the composite vertical channel pattern (CVCP) can be coplanar with the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)). However, without being limited thereto, the lower surface of the composite vertical channel pattern (CVCP) can be positioned at a lower level than the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)).

[0074] The vertically filled pattern (VFP) may be surrounded by a second vertical channel pattern (VCP2) of a composite vertical channel pattern (CVCP). An upper surface of the vertically filled pattern (VFP) may be in contact with a capping layer (CAP), and a lower surface of the vertically filled pattern (VFP) may be in contact with an uppermost surface of a substrate (SUB). The vertically filled pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertically filled pattern (VFP) may be electrically floated from the substrate (SUB).

[0075] Although a structure in which a vertically filled pattern (VFP) is positioned within a composite vertical channel pattern (CVCP) has been described, the 3D flash memory is not limited thereto and may have a structure including a back gate (BG; not shown) instead of the vertically filled pattern (VFP). In this case, the back gate (BG) may be formed to be at least partially surrounded by and in contact with the composite vertical channel pattern (CVCP) and to apply a voltage to the composite vertical channel pattern (CVCP) for a memory operation. For this purpose, the back gate (BG) may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials. In addition, in this case, an insulating film (INS; not shown) is disposed between the back gate (BG) and the composite vertical channel pattern (CVCP), thereby preventing the back gate (BG) from directly contacting the composite vertical channel pattern (CVCP). The insulating film (INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the insulating film (INS) may be omitted depending on the implementation example.

[0076] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0077] A capping layer (CAP) may be provided on an upper surface of a composite vertical channel pattern (CVCP). The capping layer (CAP) may be connected to an upper portion of the composite vertical channel pattern (CVCP). A side wall of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap the third gate electrode (EL3) in a horizontal direction.

[0078] The capping layer (CAP) may be formed of a material (e.g., a polycrystalline silicon material or a single-crystal silicon material identical to the first vertical channel pattern (VCP1)) having a lower contact resistance than the contact resistance that the second vertical channel pattern (VCP2) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) may reduce the contact resistance between the bit line (BL) and the composite vertical channel pattern (CVCP), which will be described later.

[0079] A separation trench (TR; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR; not shown) may be provided within a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with a second conductivity type impurity (e.g., an N-type impurity). The common source region (CSR) may correspond to a common source line (CSL) of FIG. 1.

[0080] A common source plug (CSP; not shown) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). An upper surface of the common source plug (CSP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in a second direction (D2) increases as it goes in the third direction (D3).

[0081] Insulating spacers (SP; not shown) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0082] A capping insulating film (CAP-INS) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD), an upper surface of the capping layer (CAP), and an upper surface of the common source plug (CSP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0083] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0084] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a composite vertical channel pattern (CVCP) included in the vertical channel structures (VS).

[0085] A three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes gate electrodes (EL1, EL2, EL3) to which voltages for memory operation are applied, a bit line (BL), a common source line (CSL), and a composite vertical channel pattern (CVCP) forming a channel, and a data storage pattern (DSP) for data storage, according to an implementation example.

[0086] In this way, the structure of the composite vertical channel pattern (CVCP) including vertical channel patterns (VCP1, VCP2) and an ion barrier film (IB) can guarantee memory performance by preventing damage to the data storage pattern (DSP) by blocking ions generated in the single crystallization process for forming the second vertical channel pattern (VCP2) from moving to the data storage pattern (DSP) using the barrier film (IB), as illustrated in FIG. 4.

[0087]

[0088] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment, and FIGS. 6a to 6d are cross-sectional views illustrating the structure of a three-dimensional flash memory to explain the method for manufacturing the three-dimensional flash memory illustrated in FIG. 5.

[0089] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 4, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0090] In step (S510), the manufacturing system can form a composite vertical channel pattern (CVCP) with a first vertical channel pattern (VCP1) formed of a polycrystalline material, a second vertical channel pattern (VCP2) formed of a single-crystal material, and an ion barrier film (IB) interposed between the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2).

[0091] More specifically, the manufacturing system can form a composite vertical channel pattern (CVCP) in the following order: a first step of forming a first vertical channel pattern (VCP1) with a polycrystalline material (e.g., a polycrystalline silicon material) on the inner wall of a data storage pattern (DSP) formed in each of channel holes (CH) as illustrated in FIG. 6a; a second step of forming an ion barrier film (IB) on the inner wall of the first vertical channel pattern (VCP1) as illustrated in FIG. 6b; and a third step of forming a second vertical channel pattern (VCP2) with a single-crystalline material (e.g., a single-crystalline silicon material) on the inner wall of the ion barrier film (IB) as illustrated in FIGS. 6c to 6d.

[0092] Here, the second step may be a step of forming an ion barrier film (IB) that blocks ions generated in the single crystallization process for forming the second vertical channel pattern (VCP2) from moving to the data storage pattern (DSP).

[0093] The third step may include a step 3-1 of depositing a polycrystalline material (e.g., a polycrystalline silicon material) on the inner wall of the ion barrier film (IB) as illustrated in FIG. 6c; and a step 3-2 of performing a metal-induced crystallization (MILC) process to convert the polycrystalline material (e.g., a polycrystalline silicon material) into a single-crystal material (e.g., a single-crystal silicon material) as illustrated in FIG. 6d.

[0094] Therefore, the second step may be a step of forming an ion barrier film (IB) that blocks metal ions generated in a metal-induced crystallization process that converts a polycrystalline material (e.g., polycrystalline silicon material) into a single-crystalline material (e.g., single-crystalline silicon material) from moving to the data storage pattern (DSP).

[0095] Although not depicted as a separate step, in step (S510), the manufacturing system can form a vertical embedded pattern (VFP) on the inner wall of the second vertical channel pattern (VCP2).

[0096] The manufacturing method described above manufactures a three-dimensional flash memory having a structure including a composite vertical channel pattern (CVCP) composed of vertical channel patterns (VCP1, VCP2) and an ion barrier film (IB) interposed between the vertical channel patterns (VCP1, VCP2), and can obviously include manufacturing steps included in a conventional three-dimensional flash memory manufacturing method, while essentially including a step of forming the composite vertical channel pattern (CVCP).

[0097] For example, when a word line replacement manufacturing method is applied, the manufacturing system performs a manufacturing method including a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of removing the sacrificial layers through the channel holes (CH); a fourth step of forming word lines (WL0-WLn) in the spaces from which the sacrificial layers are removed; a fifth step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a sixth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S510 described above), or a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); A manufacturing method can be performed, including a fourth step (step S510 described above) of forming a composite vertical channel pattern (CVCP) on an inner wall of a data storage pattern (DSP); a fifth step of forming an isolation trench (TR) in a semiconductor structure; a sixth step of removing sacrificial layers through the isolation trench (TR); and a seventh step of forming word lines (WL0-WLn) in a space from which the sacrificial layers have been removed.

[0098] As another example, when a gate-first manufacturing method is applied, the manufacturing system can perform a manufacturing method including a first step of preparing a semiconductor structure in which word lines (WL0-WLn) and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a fourth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S510 described above).

[0099]

[0100] FIG. 7 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0101] Referring to FIG. 7, an electronic system (700) including a three-dimensional flash memory according to embodiments may include a main substrate (701), a controller (702) mounted on the main substrate (701), one or more semiconductor packages (703), and a DRAM (704).

[0102] The semiconductor package (703) and DRAM (704) can be connected to the controller (702) by wiring patterns (705) provided on the main substrate (701).

[0103] The main board (701) may include a connector (706) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (706) may vary depending on the communication interface between the electronic system (700) and the external host.

[0104] The electronic system (700) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (700) may operate by power supplied from an external host, for example, through a connector (706). The electronic system (700) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (702) and a semiconductor package (703).

[0105] The controller (702) can write data to the semiconductor package (703) or read data from the semiconductor package (703), and can improve the operating speed of the electronic system (700).

[0106] The DRAM (704) may be a buffer memory to mitigate the speed difference between the semiconductor package (703), which is a data storage space, and an external host. The DRAM (704) included in the electronic system (700) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (703). When the electronic system (700) includes the DRAM (704), the controller (702) may further include a DRAM controller for controlling the DRAM (704) in addition to the NAND controller for controlling the semiconductor package (703).

[0107] The semiconductor package (703) may include first and second semiconductor packages (703a, 703b) spaced apart from each other. The first and second semiconductor packages (703a, 703b) may each be a semiconductor package including a plurality of semiconductor chips (720). Each of the first and second semiconductor packages (703a, 703b) may include a package substrate (710), semiconductor chips (720) on the package substrate (710), adhesive layers (730) disposed on a lower surface of each of the semiconductor chips (720), connection structures (740) electrically connecting the semiconductor chips (720) and the package substrate (710), and a molding layer (750) covering the semiconductor chips (720) and the connection structures (740) on the package substrate (710).

[0108] The package substrate (710) may be a printed circuit board including package upper pads (711). Each of the semiconductor chips (720) may include input / output pads (721). Each of the semiconductor chips (720) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 4. More specifically, each of the semiconductor chips (720) may include gate stack structures (722) and memory channel structures (723). The memory channel structures (723) may correspond to the vertical channel structures (VS) described above.

[0109] The connection structures (740) may be, for example, bonding wires that electrically connect the input / output pads (721) and the package upper pads (711). Accordingly, in each of the first and second semiconductor packages (703a, 703b), the semiconductor chips (720) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (711) of the package substrate (710). According to embodiments, in each of the first and second semiconductor packages (703a, 703b), the semiconductor chips (720) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (740).

[0110] Unlike the illustration, the controller (702) and semiconductor chips (720) may be included in a single package. The controller (702) and semiconductor chips (720) may be mounted on a separate interposer substrate different from the main substrate (701), and the controller (702) and semiconductor chips (720) may be connected to each other by wiring provided on the interposer substrate.

[0111]

[0112] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0113] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Word lines formed to extend horizontally on the substrate and are stacked while being spaced apart from each other in the vertical direction; and Vertical channel structures formed to extend in the vertical direction on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend in the vertical direction and a data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines. Including, The above complex vertical channel pattern is, A three-dimensional flash memory characterized by including a first vertical channel pattern formed of a polycrystalline material, a second vertical channel pattern formed of a single-crystalline material, and an ion barrier film interposed between the first vertical channel pattern and the second vertical channel pattern.

2. In paragraph 1, The above ion barrier film, A three-dimensional flash memory characterized in that ions generated in a single crystallization process forming the second vertical channel pattern are blocked from moving to the data storage pattern.

3. In paragraph 2, The above ion barrier film, A three-dimensional flash memory characterized in that metal ions generated in a metal-induced crystallization (MILC) process for converting the polycrystalline material into the single-crystal material are blocked from moving to the data storage pattern.

4. In paragraph 2, The above ion barrier film, TiO x , GaO x , Al2O3, SiO2 or SiN xA three-dimensional flash memory characterized in that it is formed by forming an insulating material based on a substrate, or by doping Ga, Ti, Sn, Zn or In into the insulating material, or by forming a multilayer structure by stacking the insulating material in multiple layers.

5. In paragraph 2, The above ion barrier film, A three-dimensional flash memory characterized in that it is formed with a thickness that satisfies a condition capable of blocking ions generated in a single crystallization process forming the second vertical channel pattern from moving to the data storage pattern.

6. In paragraph 5, The above ion barrier film, A three-dimensional flash memory characterized by being formed with a thickness between 1 nm and 3 nm.

7. A method for manufacturing a three-dimensional flash memory, comprising: word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines; A step of forming the composite vertical channel pattern by a first vertical channel pattern formed of a polycrystalline material, a second vertical channel pattern formed of a single-crystal material, and an ion barrier film interposed between the first vertical channel pattern and the second vertical channel pattern. A method for manufacturing a three-dimensional flash memory including:

8. In paragraph 7, The steps of forming the above complex vertical channel pattern are: A step of forming the first vertical channel pattern with the polycrystalline material on the inner wall of the data storage pattern; A step of forming the ion barrier film on the inner wall of the first vertical channel pattern; and A step of forming the second vertical channel pattern with the single crystal material on the inner wall of the ion barrier film. Including, The step of forming the above ion barrier film is: A method for manufacturing a three-dimensional flash memory, characterized in that it is a step of forming an ion barrier film that blocks ions generated in a single crystallization process for forming the second vertical channel pattern from moving to the data storage pattern.

9. In paragraph 8, The step of forming the second vertical channel pattern is: A step of depositing the polycrystalline material on the inner wall of the ion barrier film; and A step of performing a metal-induced crystallization (MILC) process to convert the polycrystalline material into the single crystal material. A method for manufacturing a three-dimensional flash memory including:

10. In paragraph 9, The step of forming the above ion barrier film is: A method for manufacturing a three-dimensional flash memory, characterized in that the step of forming the ion barrier film that blocks metal ions generated in the metal-induced crystallization process for converting the polycrystalline material into the single-crystal material from moving to the data storage pattern.

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