Gate drivers and mosfet topologies for high voltage switching

Abstract

A gate driver is provided for switching high voltage switching circuitry. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the high voltage switching circuitry based on the second light.

Description

GATE DRIVERS AND MOSFET TOPOLOGIES FOR HIGH VOLTAGE SWITCHINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to United States Provisional Patent Application Serial No. 63 / 608,794 filed on December 11, 2023, and entitled "GATE DRIVERS AND MOSFET TOPOLOGIES FOR HIGH VOLTAGE SWITCHING,” which is expressly incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

[0002] This invention was made with government support under grant number W911NF-21- P-0040, awarded by the U.S. Army Research Office, and grant number 1830924, awarded by the National Science Foundation. The government has certain rights in the invention.FIELD

[0003] The present disclosure relates generally to gate drivers for driving switching circuitries, and particularly relates to gate drivers for driving high voltage switching circuitries with low electrical energy profile.BACKGROUND

[0004] Switches are ubiquitous in modem electronics and are an integral component of many fundamental building blocks of complex electronic systems: load switches, bridge amplifiers, buck / boost converters, and more. There are myriad applications which specifically demand switching of high voltages (that is to say, potentials of IkV or more, as the definition of “high voltage” varies substantially between contexts), including robotics, manufacturing, electric vehicles, lasers, and magnetic plasma containment systems.

[0005] Not all of these applications have similar design requirements, however, and there are certain niches that have not received much market attention. Notably, there is a shortage of switches capable of handling moderately high voltages (l-10kV), relatively small currents (1-100mA), and occupying a compact footprint suitable for parallelization and untethered operation. For systems like highly agile, untethered soft robots driven by electrostatic robotic muscles, the lack of such technologies is sorely felt, as it hamstrings research and eventual commercialization. Furthermore, many existing high-voltage switches designed for larger systems are bulky, costly, and unsuitable for use in portable or lightweight platforms, such as in drones, prosthetics, and mobile medical devices.

[0006] Advancements in emerging technologies, such as precision manufacturing, quantum computing, and high-speed medical imaging, demand high-voltage switches that are highly reliable, scalable, and capable of operating in environments with fast voltage swings, minimal distortion, and stringent space constraints.

[0007] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some aspects described herein may be practiced.BRIEF SUMMARY

[0008] The present disclosure is related to gate drivers configured for driving high voltage switching circuitries with low electrical energy profile. The electrical energy profile may include a voltage or current. High voltage switching circuitry may block high voltages (e.g., l-10kV) and the gate drivers drive the high voltage switching circuitry with relatively low voltage (e.g., 1-20V) or relatively small current (e.g., l-100mA).

[0009] Further, the gate drivers may utilize optical energy and optical signals in generating power and supplying control signals, respectively. Thereby, it is possible to electronically isolate the high voltage switching circuitry from the gate driver through the use of optical signal transmission.

[0010] According to various aspects, for example, a gate driver is provided for switching high voltage switching circuitry. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the high voltage switching circuitry based on the second light.

[0011] According to various aspects, for example, a high voltage switching circuitry includes metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in series, a voltage balancing circuit coupled to the MOSFETs to ensure uniform voltage distribution across a gate terminal of each MOSFET, and a gate driver coupled to the gate terminal of one MOSFET of the MOSFETs and configured for switching the MOSFETs. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of the one MOSFET based on the second light.

[0012] According to various aspects, for example, a half-bridge switching circuitry includes a first metal-oxide-semiconductor field-effect transistor (MOSFET), a first gate driver coupled toa gate terminal of the first MOSFET and configured for switching the first MOSFET, a second MOSFET, a second gate driver coupled to a gate terminal of the second MOSFET and configured for switching the second MOSFET, and a capacitive load coupled to an output terminal of the first MOSFET and to an input terminal of the second MOSFET. The first MOSFET controls a charge rate of the capacitive load, and the second MOSFET controls a discharge rate of the capacitive load. Each of the first and second gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of respective one of the first or second MOSFET based on the second light.

[0013] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0014] Additional features and advantages will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the teachings herein. Features and advantages of the present disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. Features of the present disclosure will become more fully apparent from the following description and appended claims, or may be learned by the practice of the present disclosure as set forth hereinafter.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to describe the manner in which at least some of the advantages and features of the present disclosure may be obtained, a more particular description of aspects of the present disclosure will be rendered by reference to specific aspects thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical aspects of the present disclosure and are not therefore to be considered to be limiting of its scope, aspects of the present disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings.

[0016] FIG. 1 illustrates a circuit diagram of a common gate driver topology for a PMOS load switch or for use in a bridge-style amplifier configuration.

[0017] FIG. 2 illustrates a circuit diagram of an optical gate driver according to various aspects of the present disclosure.

[0018] FIG. 3 illustrates a circuit diagram of a load switch driven by an optical gate driver according to various aspects of the present disclosure.

[0019] FIG. 4 illustrates a circuit diagram for high voltage switching circuitry according to various aspects of the present disclosure.

[0020] FIG. 5 illustrates a circuit diagram for high voltage switching circuitry driven by an optical gate driver according to various aspects of the present disclosure.

[0021] FIG. 6 illustrates a circuit diagram of half-bridge driver configuration for a capacitive load according to various aspects of the present disclosure.

[0022] FIG. 7 illustrates a circuit diagram of a half-bridge driver configuration for a capacitive load according to various aspects of the present disclosure.

[0023] FIG. 8 illustrates a circuit diagram of full-bridge high voltage switching circuitry driven by optical gate drivers according to various aspects of the present disclosure.

[0024] FIG. 9 illustrates a circuit diagram of a full-bridge driver according to various aspects of the present disclosure.DETAILED DESCRIPTION

[0025] The present disclosure is related to optical gate drivers for driving high voltage switching circuitry with a low voltage or low current. The optical gate drivers may generate power from optical energy and convert modulated optical signals into electrical control signals. Thereby, the high voltage switching circuitry may be electrically isolated from the optical gate drivers, through the use of the optical transmission of signals and power. Further, by using the modulated optical signals, fast switching without excessive energy loss or electromagnetic interference may be possible. Furthermore, by using the optical energy and optical signals, bulky transformers or charge pumps are no longer needed to control the high voltage switching circuits, thereby enabling a decrease in size of the whole electric system.

[0026] The optical gate driver, which is optically powered and optically controlled, may be applied to various electromagnetic devices used in soft robotics, electrostatic actuators, power supply stacks, solid state drivers for electrostatic actuators, semiconductor system integrations, and any other systems, which requires high voltage switching with low voltage or small current controls.

[0027] Further, the present disclosure is related to load switches that can control the electrical connection between a power supply and a load it will drive. As used herein, load switches may comprise a pass transistor or pass FET (typically an N- or P-channel MOSFET), the optical gate driver, and control circuitry required to control the pass FET from a logic-level voltage input to the optical gate driver. Many commercially available load switches also offer additional featureslike overcurrent protection or temperature monitoring. However, these may not be necessary with the disclosed optical gate driver.

[0028] Throughout this disclosure, the following abbreviations or terminologies may be used. HV = high voltage (in this context, IkV-lOkV);LV = low voltage / logic-level voltage (e.g., 3.3V, 5V) or common driving voltages for motors or appliances (e.g., 12V-240V);AC = alternating current;DC = direct current;PSU = power supply unit;HVPSU = high voltage power supply;ESA = electrostatic actuator;FET = field-effect transistor;MOSFET = metal oxide semiconductor FET;PMOS = P-channel MOSFET;NMOS = N-channel MOSFET;CMOS = complementary MOSFET, refers specifically to PMOS and NMOS devices working together;NPN = a bipolar junction transistor where semiconductor junctions share a p-doped region; andPNP = a bipolar junction transistor where semiconductor junctions share a n-doped region.

[0029] Illustrated in FIG. 1 is a conventional load switch 100, which is generally functioning as a voltage-controlled switch, a control sy stem, or a signal amplifier. The load switch 100 may be used as the high-side FET of a CMOS based bridge-style amplifier. The load switch 100 includes an input terminal 110 connected to a high-side rail voltage and an output terminal 120 connected to a load. Through the input terminal 110, an input signal or voltage (e.g., high voltage) is provided to the load switch 100, and through the output terminal 120, controlled output signal or voltage may be delivered to the load connected to the load switch 100.

[0030] The load switch 100 further includes a modulating capacitor 130, which modulates high frequency noise and stabilizes the input signal by transient spikes, and a high-side resistor 135, which functions as a voltage divider. The modulating capacitor 130 and the high-side resistor 135 are connected in parallel and connected to the input terminal 110.

[0031] The load switch 100 also includes a PMOS pass FET 140, of which a source is connected to the input terminal 110, a drain is connected to the output terminal 120, and a gate is connected to the modulating capacitor 130 and the high-side resistor 135. When a sufficientvoltage is supplied to the gate of the PMOS pass FET 140, the PMOS pass FET 140 is turned on and relays the controlled input signal to the output terminal 120 or to the load. The capacitance of the modulating capacitor 130 affects the switching speed of the load switch 100.

[0032] When designing a load switch, the choice of the pass FET 140 may involve making some trade-offs. Due to the realities of manufacturing MOSFETs, it may not be possible to simultaneously maximize blocking voltage, maximize current capacity (minimize on-state resistance), and minimize the size of device footprint. An N-Channel MOSFET (NMOS) may be made with higher blocking voltages and / or lower on-state resistances than a PMOS device in an equivalent footprint. However, PMOSs may be easier to control when used as load switches or high-side switches in a bridge amplifier.

[0033] A control terminal 160 may receive a control signal (e.g., a pulse-width modulation (PWM) signal) to toggle an NMOS gate driver FET 180, which is the main switching component. A gate current limiting resistor 170 is connected between the control terminal 160 and the gate of the NMOS gate driver FET 180, and limits the current to the gate of the NMOS gate driver FET 180. In other words, When the control signal is applied to the control terminal 160, the gate current limiting resistor 170 ensures that the current flowing into the gate of the PMOS pass FET 140 from the source of the NMOS gate driver FET 180 is limited, thereby protecting the NMOS gate driver FET 180 from being damaged due to excessive current.

[0034] A gate pull-down resistor 175 is connected between the gate of the NMOS gate driver FET 180 and the ground 190. When no control signal is applied or the control terminal 160 is floating, the gate pull-down resistor 175 ensures that the gate of the NMOS gate driver FET 180 is pulled to the ground 190, thereby keeping the NMOS gate driver FET 180 in the off state and preventing accidental or unintended switching. Also, without the gate pull-down resistor 175, stray voltages or noise at the gate could turn the MOSFET 180 on unintentionally. The NMOS gate driver FET 180 may be an N-MOS transistor. The ground 190 may provide a common reference point for the load switch 100 and completes the current path. The source of the NMOS gate driver FET 180 is connected to the ground 190.

[0035] The ratio of the gate current limiting resistor 170 and the gate pull-down resistor 175 is selected to set an appropriate gate voltage for the NMOS gate driver FET 180.

[0036] When the control signal is present at the control terminal 160, the NMOS gate dnver FET 180 is turned on and the current passes from the drain of the NMOS gate driver FET 180 to the source of the PMOS pass FET 140. A low-side resistor 150 is positioned between the gate of the PMOS pass FET 140 and the drain of the NMOS gate driver FET 180 and limits the current flowing to the NMOS gate driver FET 180, thereby preventing damage to the NMOS gate driver FET 180 and ensuring stable switching. The ration of the high-side resistor 135 and the low-sideresistor 150 can be selected to set an appropriate gate voltage for the PMOS pass FET 140. When the PMOS pass FET 140 is turned on, the input signal is flowing through the PMOS pass FET 140 to the output terminal 120.

[0037] When the high voltage supply is current-limited, the load switch 100 may bleed substantial current from the high voltage supply. In such cases, NMOS can be used. However, usage of the NMOS devices for this application requires the use of a charge pump, adding bulk, cost, and reducing switching speed.

[0038] Further, generally, NMOS devices require a positive gate-source potential to activate. To set the correct direction of current flow for the NMOS devices, the source pin is connected to the output load. The main challenge of driving these NMOS devices is generating a gate drive potential which constantly remains several volts above the output voltage, regardless of what that output voltage is. This is typically achieved by using the charge pump. However, in applications like driving electrostatic actuators, the output voltage can violently swing by multiple thousands of volts, hundreds to thousands of times per second and designing compact charge pumps which meet these requirements quickly becomes impractical.

[0039] Illustrated aspects in FIG. 2 include an optical gate driver 200, which is optically powered and optically controlled according to various aspects of the present disclosure. The optical gate driver 200 may use optical signals for both power and control, and thus provide electrical isolation between the control / input side and a HV switching circuit or load side. The optical gate driver 200 may include a logic-level gate driver subcircuit 205, which may emit light 230, which is used to generate power, and modulated light 255, which is used to drive the HV switching circuit or the load.

[0040] The logic-level gate driver subcircuit 205 may include a low voltage terminal 210 connected to a low volage (LV) power supply or logic-level voltage (e.g., 3.3V or 5V) and another low voltage terminal 215 connected to a LV power supply. In an aspect, the LV power supply connected to the low volage terminal 210 may be different from or same as the LV power supply connected to the low voltage terminal 215.

[0041] The LV terminal 210 is connected to a resistive element 225 and a light-emitting diode (LED) 220 in series. The resistive element 225 modulates the current passing therethrough, and the LED 220 emits light 230 based on the current. The light 230 emitted from the LED 220 may be continuous light. The LV terminal 215 is also connected to a resistive element 245, an LED 240, and an NMOS FET 260 in series. The gate terminal of the NMOS FET 260 is connected to a control terminal 250, and the NMOS FET 260 may be controlled by the control signal provided through the control terminal 250. The control signal may be a pulse-width modulation (PWM)signal. In an aspect, the low voltage is not the only source of the power for the LEDs 220 and 240. High voltage source or other types of energy may be used to power the LEDs 220 and 240.

[0042] When the gate is turned on by the control signal, the current passes through the LED 240, which then emits light 255. Due to the control signal, the light 255 may be modulated, while the light 230 is continuous. On the other hand, the LED 240 emits the light 255 only when a switch coupled to the LED is operated.

[0043] The optical gate driver 200 may include a power supply 390 and an optical driver 395. The power supply 390 may include one or more photovoltaic element 340. The LED 220 and the photovoltaic element 340 may form a photovoltaic optocoupler, which generates power from the light 230. Due to the continuous light 230, the photovoltaic optocoupler may generate continuous power.

[0044] The photovoltaic element 340 may be connected to a buffer capacitor 350 in parallel. The buffer capacitor 350 may buffer the voltage of the photovoltaic element 340 and supply high peak currents during short-term loads. The photovoltaic element 340 and the buffer capacitor 350 may provide a voltage to the optical driver 395.

[0045] The optical driver 395 may include a phototransistor 360, a transistor 370, a biasing resistor 375, and a leakage resistor 380. The phototransistor 360 with the LED 240 may form a phototransistor optocoupler. The modulated light 240 is used to turn on or off the phototransistor 360. When the phototransistor 360 is turned on, current passes, based on the voltage across the photovoltaic element 340, through the phototransistor 360 to a gate terminal 310 of a MOSFET switch so that the MOSFET switch is turned on and current can pass to a source terminal 320 via the MOSFET switch.

[0046] When the phototransistor 360 is turned off based on the modulated light 240, no current passes through the phototransistor 360. Instead, the transistor 370 draws current from the gate terminal 310 of the MOSFET switch. In this regard, the phototransistor 360 may be a NPN and the transistor 370 may be a PNP. The optical driver 395 may be a push-pull driver.

[0047] The optical driver 395 may further include a biasing resistor 375 and a leakage resistor 380. One end of the biasing resistor 375 may be connected to the gate terminals of the phototransistor 360 and the transistor 370, and the other end of the biasing resistor 375 is connected to the drain terminal of the transistor 370. The biasing resistor 375 may modulate switching behavior of the phototransistor 360 and the transistor 370.[004S] One end of the leakage resistor 380 is connected to the source terminals of the phototransistor 360 and the transistor 370 and to the gate of the MOSFET switch, and the other end of the leakage resistor 380 is connected to the source terminal 320 of the MOSFET switch.When the phototransistor 360 is turned off, electric charge in the gate terminal 310 of the MOSFET switch is discharged through the leakage resistor 380.

[0049] The optical driver 395 and the power supply 390 may form a load-level sub-circuit, which floats along with the source terminal 320 and is completely isolated from the logic-level gate driver subcircuit 205.

[0050] The optical gate driver 200 may drive an insulated-gate bipolar transistor (IGBT). To do such, the gate terminal 310 is connected to the gate pin of the IGBT and the source terminal 320 to the emitter pin of the IGBT. Further, the optical gate driver 200 may drive an NMOS device. Furthermore, the optical driver 395 and the power supply 390 may be modified to drive a PMOS device.

[0051] In aspects, the optical gate driver 200 may be manufactured in a small estate, thereby enabling installation thereof within any other electrical devices in industrial automation, power infrastructure, soft robots, power electronics, high frequency switching circuits for power inverters, converters, or amplifiers, and the likes. Further, the optical gate driver 200 may be easily integrated with and control HV switches based on the small size thereof

[0052] Now referring to FIG. 3, illustrated is a load switch 300 driven by the optical gate driver 200 of FIG. 2 according to aspects of the present disclosure. The load switch 300 may include an NMOS pass FET 330, of which is the drain terminal is connected to an inductive or resistive load 332 and of which the source terminal is connected to an inductive or resistive load 334. The inductive or resistive load 332 is also connected to a high side, which receives a positive voltage +V, and the inductive or resistive load 334 is also connected to a low side, which receives a negative voltage -V. In an aspect, both loads 332 and 334 may be located in either side of the NMOS pass FET 330, or one of the loads 332 and 334 may be optional. Each of the loads 332 and 334 may be a network of resistive and inductive loads and may include other reactive elements such as capacitance. In another case, both loads 332 and 334 may be connected to the ground.

[0053] The gate terminal 310 of the optical gate driver 200 is connected to the gate terminal of the NMOS pass FET 330. When the phototransistor 360 is turned on based on the modulated light 255 and the power supply 390 supplies power to the optical driver 395, the gate terminal of the NMOS pass FET 330 is then turned on so that current passes from +V to -V through the NMOS pass FET 330 and either or both the load 332 and the load 334, depending on which are present. The NMOS pass FET 330 is electrically isolated from low voltage control circuitry by the optical gate driver 200. In particular, the photovoltaic power supply 390 and the push-pull driver 395 are electrically isolated from the logic-level gate driver subcircuit 205.

[0054] Now referring to FIG. 4, illustrated is a gate-coupled series NMOS stack 400 with high voltage blocking capability by stacking multiple transistor switches according to various aspectsof the present disclosure. The gate-coupled series NMOS stack 400 may enable handling high voltage differentials across a positive load-side connection 410 and a negative load-side connection 420. Generally, an NMOS may manage a tens of volts to hundreds of volts or more depending on its specific design. Based on the design of the transistor, when stacked together, for example, about 20 transistors, this circuit may be ablet to manage 20 times its voltage capacity. Thereby, based on the number of transistors, the gate-coupled series NMOS stack 400 may be able to manage a potential of hundreds or tens of thousands of volts across the positive load-side connection 410 and the negative load-side connection 420. Further, by changing the number and the design of transistor switches, the gate-coupled series NMOS stack 400 may be able to meet any design requirements for the whole system (e.g., soft robots, power electronics, renewable energy, signal processing, automation systems, or the likes).

[0055] The gate-coupled series NMOS stack 400 may include a current-limiting resistor 430 and one stack level 440 of the gate-coupled series NMOS stack 400 in series. Hereinafter, when numeral “440” is used, it refers to the stack or the whole switching circuits as a whole, and when numeral “440” is used with alphanumerical subscription (e.g., “440i,” “4402,” ... “440n-i,” and “440n”), it refers to each individual stack. The current-limiting resistor 430 is connected to the positive load-side connection 410 and limits the current passing through the stacks of switching circuits to the negative load-side connection 420. In an aspect, the positive load-side connection 410 does not have to be positive and the negative load-side connection 420 does not have to be negative. The only requirement is that the potential at the positive load-side connection 410 is higher than the potential at the negative load-side connection 420.

[0056] The stack level 440 may be 2, 10, 20, or any number based on the level of voltage blocking requirement. Each stack level 440 may work together with a respective gate-coupled capacitor 450 to evenly distribute the high voltage to the gate terminal of each stack level 440. Each stack level 440 may have the same configuration except the bottom stack level 440n. The first stack level 440i may include aNMOS switch 4451, a coupling capacitor 4501, a Zener diode 455a, and a balancing resistor 4601. The NMOS switch 4451 may include a source terminal , a gate terminal, and a drain terminal. The drain terminal of the NMOS switch 4451 is connected to the current-limiting resistor 430, the source terminal of the NMOS switch 445i is connected to drain terminal of the second stack level 4452. The NMOS switch 4451 may function as switching or blocking elements.

[0057] The coupling capacitor 450i is connected between the gate terminal of the NMOS switch 445i and the gate terminal of the NMOS switch 4452 of the second stack level 4402. Each of the coupling capacitors 450i-450n-i, which is connected to the gate terminal of the corresponding NMOS switch 445, respectively, may provide coupling to the gate terminal of eachNMOS switch 445 and synchronize their switching in response to the state of the bottom NMOS switch 445n.

[0058] One end of the balancing resistor 4601 is connected to the current-limiting resistor 4301 and the drain terminal of the NMOS switch 4451, and the other end of the balancing resistor 460i is connected to Zener diode 455i, and the source terminal of the NMOS switch 4451, and the balancing resistor 4602 of the second stack level 4402. The balancing resistor 460i acts as a voltage divider of the high voltage input and ensures a voltage division during any transients the stack level 440 may experience. Further, the balancing resistor 460i may correct for any charge imbalances resulting from imperfections in switching synchronization. Since the use of the balancing resistor 460i may introduce a leakage current, the Zener diode 4551 may provide voltage clamping and protection for the gate terminal of the NMOS switch 4451 so that the voltage at the gate terminal of the NMOS switch 445i stays within the safe operating range thereof. The anode of the Zener diode 4551 may be connected to the balancing resistor 460i and the cathode of the Zener diode 4551 may be connected to the gate terminal of the NMOS switch 4451.

[0059] When the gate terminal of the NMOS switch 4451 is turned on, the majority of the current flows through the NMOS switch 4451 and a small current flow through the balancing resistor 460i because the resistance of the NMOS switch 4451 is comparatively smaller than that of the balancing resistor 460i. For example, the resistance of the balancing resistor 460 may be in a high range (e.g., a megaohm range), the resistance of the NMOS switch 445i may be in a milliohm range when the gate terminal is on. On the other hand, when the gate terminal is turned off, the current flows through the balancing resistor 460i because the resistance of the NMOS switch 445i is considered infinite in an ideal scenario. In other words, the NMOS switch 4451 may act as an open switch, blocking the current flow through its drain-source channel in the off status, and may act as a closed switch, allowing the current flow through the drain-source channel in the on status.

[0060] The configuration of the first stack level 4401 is the same as that of the other stack levels 4402-440n-i. On the other hand, the bottom stack level 440n has a different configuration from the configuration of the other stack levels 440i-440n-i. The stack level 440nmay include a bottom NMOS switch 445n, a balancing resistor 460n, and a Zener diode 455n. The coupling capacitor may not be included in the stack level 440n.

[0061] One end of the balancing resistor 460nis connected to the balancing resistor 460n-i, and the other end of the balancing resistor 460nis connected to the Zener diode 455n, the source terminal of the bottom NMOS switch 445n, and the output terminal 420. The anode of the Zener diode 455n may be connected to the balancing resistor 460nand the cathode of the Zener diode 455nmay be connected to the gate terminal of the bottom NMOS switch 445n.

[0062] The gate-coupled series NMOS stack 400 may further include a gate terminal 490 and a source terminal 480. The gate terminal 490 is connected to the gate terminal of the bottom NMOS switch 445n, and applies an appropriate voltage to the gate terminal of the bottom NMOS switch 445nto turn on and off the gate terminal of the bottom NMOS switch 445n. The source terminal 480 is connected to the source terminal of the bottom NMOS switch 445n and the output terminal 420, and serves as the ground reference or return path for the gate-driving circuit. Further, the source terminal of the gate driver is also connected to the coupling capacitor 450n-i.

[0063] When the gate terminal 490 of a gate driver (e.g., the optical gate driver 200 of FIG. 2) provides the appropriate voltage to turn on the gate of the bottom NMOS switch 445n, the high voltage between the current-limiting resistor 430 and the negative load-side connection 420 may be evenly distributed across the coupling capacitors 450i— 450n-i so that all the gate terminals of the NMOS switches 445i-445nare synchronously turned on. Thus, the majority of the current flows through the NMOS switches 4451— 445n. In this case, the whole resistance of the stack level 440 of the NMOS switches 445i-445nmay be considered as small, and the high input voltage at the positive load-side connection 410 is divided based on the resistance of the current-limiting resistor 430 and the resistance of the stack level 440 of the NMOS switches 445i-445n. In a configuration that the resistance of the current-limiting resistor 430 is comparatively smaller than the resistance of the stack level 440 of the NMOS circuits 445i-445n, the majority of the high input voltage may be applied to the negative load-side connection 420. In an aspect, the currentlimiting resistor 430 may be optional and can be removed from the gate-coupled series NMOS stack 400.

[0064] The optical gate driver 200 of FIG. 2 and the gate-coupled series NMOS stack 400 of FIG. 4 may be connected together to drive the gate-coupled series NMOS stack 400. Such configuration of a load switch 500 is illustrated in FIG. 5. The load switch 500 may include a first load 510 and a second load 520. The first load 510 and the second load 520 may be inductive or resistive and may include a network of inductive and resistive elements and may include other reactive elements such as capacitance.

[0065] The first load 510 is connected to the positive load-side connection and the drain terminal of the first NMOS switch 4451 or to the current limiting resistor 430 if such an element is present, and the second load 520 is connected to the negative load- side connection and the source terminal of the bottom NMOS switch 445n. The first load 510 and the second load 520 may be interchangeable and optional.

[0066] The gate terminal 310 of the optical gate driver 200 is connected to the gate terminal of the bottom NMOS switch 445nand the source terminal 320 of the optical gate driver 200 is connected to the second load 520.

[0067] When the phototransistor 360 of the optical gate driver 200 is turned on based on the modulated light 255, current passes through the phototransistor 360 so that a voltage is applied to the gate terminal of the bottom NMOS switch 445n. The bottom NMOS switch 445n is then turned on, and, in a cascade way, all the other NMOS switches 445i-445n-i are also turned on so that current passes through all the NMOS switches 445i-445n, thereby input signal, which is modulated, being transmitted to the second load 520.

[0068] Since the optical gate driver 200 is optically powered and optically controlled, the optical gate driver 200 provides electrical isolation between the gate-coupled series NMOS 400 or any load-side connections thereof, and any logic-level connections to the logic-level subcircuit 205.

[0069] Now referring to FIG. 6, illustrated is a half-bridge driver 600 for capacitive loads according to various aspects of the present disclosure. The half-bridge driver 600 may include a top gate-coupled series NMOS stack 400i, a bottom gate-coupled series NMOS stack 4002, a top optical gate driver 200i, and a bottom optical gate driver 2002. The top gated-coupled series NMOS stack 400i may be controlled by the top optical gate driver 200i, and the bottom gated- coupled series NMOS stack 4002 may be controlled by the bottom optical gate driver 2OO2. The source terminal of the bottom MNOS switch 445nis connected to the drain terminal of the first NMOS switch 4451 of the bottom gate-coupled NMOS stack 4002.

[0070] The half-bridge driver 600 may further include a capacitive load 610 and a voltage sensor 620, which is coupled with the capacitive load 610 in parallel. Both the capacitive load 610 and the voltage sensor 620 may be connected to the ground 640 or to V+ or to V-. The capacitive load 610 may include a network of capacitive elements, or a network of capacitive elements and resistive, inductive, or other reactive elements. The voltage sensor 620 may measure the voltage and generate a feedback signal 630, which may be used for a closed loop control.

[0071] The top optical gate driver 200i and the bottom optical gate driver 2002 may drive the top and bottom gate-coupled NMOS stacks 400i and 4002, independently or cooperatively.

[0072] The top gate-coupled NMOS stack 4001 may be connected to a positive voltage and the bottom gate-coupled NMOS stack 4002 may be connected to the negative voltage. In an aspect, either one of the gate-coupled NMOS stacks may be connected to the ground 640. For example, FIG. 7 illustrates a half-bridge driver 700 with a single-ended configuration. Specifically, the bottom gate-coupled NMOS stack 4002 is connected to the ground 740 and the top gate-coupled NMOS stack 400i is connected to the positive voltage. In an aspect, the bottom gate-coupled NMOS stack 4002 is connected to a negative voltage and the top gate-coupled NMOS stack 400i is connected to the ground 740.

[0073] The gate-coupled NMOS stack 400 may be replaced with aNMOS pass FET (e.g., the NMOS pass FET 330 of FIG. 3) to build a half-bridge driver. In an aspect, the number of NMOS pass FETs may be specified based on the requirements for the half-bridge driver. Further, two optical gate driver of the half-bridge drive may be independently or cooperatively executed to drive the NMOS pass FET.

[0074] Now referring to FIG. 8, illustrated is a full-bridge driver 800 according to various aspects of the present disclosure. The full-bridge driver 800 includes to half-bridge drivers 700i and 7002. The configuration of the half-bridge drivers 700i and 7002 may be same or different from each other. The half-bridge drivers 700i and 7002 may have a similar configuration as illustrated in FIG. 7. The half-bridge driver 700i may include a top gate-coupled series NMOS stack 400i, a bottom gate-coupled series NMOS stack 4002, a top optical gate driver 200i, and a bottom optical gate driver 2002. The top gated-coupled series NMOS stack 400i may be controlled by the top optical gate driver 200i, and the bottom gated-coupled series NMOS stack 4002 may be controlled by the bottom optical gate driver 2OO2. The source terminal of the bottom NMOS switch 445nof the top gate-coupled NMOS stack 400i is connected to the drain terminal of the first NMOS switch 4451 of the bottom gate-coupled NMOS stack 4002.

[0075] The top optical gate driver 2001 and the bottom optical gate driver 2OO2 may drive the top and bottom gate-coupled NMOS stacks 400i and 4002, independently or cooperatively. In a case when top optical gate driver 2001 and the bottom optical gate driver 2002 drive the top and bottom gate-coupled NMOS stacks 400i and 4002 cooperatively, the control signals 250i and 2502 may be provided by one controller of the half-bridge 700i. The controller may be a PWM signal generator. In another case, a pair of the NMOS stacks 400i and 4002 may be controlled together and another pair of the NMOS stacks 4003 and 4004 may be controlled together. Furthermore, each gate-coupled NMOS stack 400 may be controlled independently from each other. Any combination of the gate-coupled NMOS stacks 4001-4004 is possible to group-controlled.

[0076] The top gate-coupled NMOS stack 400i may be connected to a positive voltage and the bottom gate-coupled NMOS stack 4002 may be connected to the negative voltage. In an aspect, either one of the gate-coupled NMOS stacks may be connected to the ground.

[0077] Likewise, the half-bridge driver 7002 may include a top gate-coupled series NMOS stack 40(h, a bottom gate-coupled series NMOS stack 4004, a top optical gate driver 2OO3, and a bottom optical gate driver 2004. The top gated-coupled series NMOS stack 4003 may be controlled by the top optical gate driver 2OO3, and the bottom gated-coupled series NMOS stack 4004 may be controlled by the bottom optical gate driver 2004. The source terminal of the bottom NMOS switch 445nis connected to the drain terminal of the first NMOS switch 4451 of the bottom gate- coupled NMOS stack 4004.

[0078] The top optical gate driver 2003 and the bottom optical gate driver 2004 may drive the top and bottom gate-coupled NMOS stacks 4003 and 4004, independently or cooperatively. In a case when top optical gate driver 2003 and the bottom optical gate driver 2004 drive the top and bottom gate-coupled NMOS stacks 4003 and 4004 cooperatively, the control signals 250s and 2504 may be provided by one controller of the half-bridge 7002. The controller may be a PWM signal generator.

[0079] The top gate-coupled NMOS stack 4003 may be connected to a positive voltage and the bottom gate-coupled NMOS stack 4002 may be connected to the negative voltage. In an aspect, either one of the gate-coupled NMOS stacks may be connected to the ground.

[0080] The full-bridge driver 800 may further include a load 810, of which one end is connected to the connection point between the source terminal of the bottom NMOS switch 445nof the top gate-coupled NMOS stack 400i and the drain terminal of the first NMOS switch 4451 of the bottom gate-coupled NMOS stack 4002, and of which the other end is connected to the connection point between the source terminal of the bottom NMOS switch 445nof the top gate- coupled NMOS stack 4003 and the drain terminal of the first NMOS switch 445i of the bottom gate-coupled NMOS stack 4004. The load 810 may include single capacitive element, or a network of capacitive elements, or a network of capacitive elements and resistive, inductive, or other reactive elements.

[0081] In an aspect, each of configurations of the optical gate driver 2001-2004 may be different from each other, and operations of the optical gate drivers 2001-2004 may be individually controlled. In another aspect, the operations of the optical gate drivers 2001-2004 may be controlled by the main controller so that turning on and off may be cooperatively controlled to achieve desired functionalities of the full-bridge driver 800.

[0082] Now referring to FIG. 9, illustrated is a full-bridge driver 900 according to various aspects of the present disclosure. The full-bridge driver 900 may be constructed from four NMOS devices 3301, 3302, 3303, and 3304. Each of gate drivers 2001, 2002, 2003, and 2004 may drive respective one of the NMOSs 3301, 3302, 33 O3, and 3304. Each pair of gate driver 200 and NMOS 330 may have a similar configuration as illustrated in FIG. 3. The source pin of the top NMOS 330i is connected to the drain pin of the bottom NMOS 3302 and the source pin of the top NMOS 330s is connected to the drain pin of the bottom NMOS 3304.

[0083] Each of the NMOS devices 3301, 3302, 330s, and 3304 may be IGBT devices or other types of transistor. They may be individual transistors or networks of transistors and other components. Each of the NMOS devices 330i, 3302, 3303, and 3304 may be identical or different.

[0084] Each of the NMOS devices 330i, 3302, 330s, and 3304 may be driven independently or cooperatively by the respective gate drivers 2001, 2002, 200s, and 2004. The control signals provided to each gate driver 200 may be PWM signals.

[0085] A load 910 may be connected between the top pair of NMOS devices 330i and 330s, and the bottom pair ofNMOS devices 3302 and 3304. The load 910 may be any resistive or reactive element, any network of resistive or reactive elements, or any network composed of combinations thereof.

[0086] The drain pins of the top pair of NMOS devices 330i and 330s may be connected to the positive supply voltage V+. The source pins of the bottom pair of NMOS devices 3302 and 3304 may be connected to the negative supply voltage V-. In an aspect, either one of the supply voltages V+ or V- may be connected to the ground.

[0087] A sensor 620i, which may be a voltage sensor, is connected in between the source terminal of the top NMOS 330i and the drain terminal of the bottom NMOS 3302. The sensor 620i may connect to one terminal of the load 910 and provide a feedback signal 6301, which may be used for feedback control.

[0088] A sensor 6202, which may be a voltage sensor, is connected in between the source terminal of the top NMOS 330s and the drain terminal of the bottom NMOS 3304. The sensor 6202 may connect to one terminal of the load 910 and provide a feedback signal 6302, which may be used for feedback control.

[0089] In an aspect, each of configurations of the optical gate drivers 2001-2004 may be different from each other, and operations of the optical gate drivers 2001-2004 may be individually controlled. In another aspect, the operations of the optical gate drivers 2001-2004 may be controlled by the main controller so that turning on and off may be cooperatively controlled to achieve desired functionalities of the full-bridge driver 900.

[0090] Example Implementations

[0091] In view of the foregoing, the present disclosure relates, for example and without being limited thereto, to the following aspects:

[0092] According to the first aspect, a gate driver is for switching high voltage switching circuitry. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the high voltage switching circuitry based on the second light.

[0093] According to the second aspect as claimed in the first aspect, the optical dnver comprises a phototransistor configured to turn on and off based on the second light.

[0094] According to the third aspect as claimed in any previous aspects, the optical driver is a push-pull driver.

[0095] According to the fourth aspect as claimed in any previous aspects, the push-pull driver comprises a PNP phototransistor and aNPN transistor.

[0096] According to the fifth aspect as claimed in any previous aspects up to the third aspect, the push-pull driver comprises a NPN phototransistor and a PNP transistor.

[0097] According to the sixth aspect as claimed in any previous aspects, the push-pull driver comprises a PNP phototransistor and aNPN transistor.

[0098] According to the seventh aspect as claimed in any previous aspects, the NPN phototransistor drives voltage to a gate terminal of the gate driver, when the push-pull driver is turned on.

[0099] According to the eighth aspect as claimed in any previous aspects, the PNP transistor draws voltage from a gate terminal of the gate driver, when the push-pull driver is turned off.

[0100] According to the nineth aspect as claimed in any previous aspects, the gate driver is electrically isolated from the high voltage switching circuitry.

[0101] According to the tenth aspect as claimed in any previous aspects, the gate driver further includes a capacitor coupled to the power supply in parallel and configured to smoothen out fluctuations in a voltage generated by the power supply.

[0102] According to the eleventh aspect, a high voltage switching circuitry includes metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in series, a voltage balancing circuit coupled to the MOSFETs to ensure uniform voltage distribution across a gate terminal of each MOSFET, and a gate driver coupled to the gate terminal of one MOSFET of the MOSFETs and configured for switching the MOSFETs. The gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of the one MOSFET based on the second light.

[0103] According to the twelfth aspect as claimed in the eleventh aspect, when the optical driver turns on the gate terminal of the one MOSFET, the gate terminals of the other MOSFETs are turned on based on the voltage balancing circuit.

[0104] According to the thirteenth aspect as claimed in any previous aspects from the eleventh aspect, the optical driver is a push-pull driver.

[0105] According to the fourteenth aspect as claimed in any previous aspects from the eleventh aspect, the push-pull driver comprises aNPN phototransistor and a PNP transistor.

[0106] According to the fifteenth aspect as claimed in any previous aspects from the eleventh aspect, the push-pull driver comprises a PNP phototransistor and a NPN transistor.

[0107] According to the sixteenth aspect as claimed in any previous aspects from the eleventh aspect to fifteenth aspect, the NPN phototransistor drives voltage to a gate terminal of the gate driver, when the push-pull driver is turned on.

[0108] According to the seventeenth aspect as claimed in any previous aspects from the eleventh aspect, the PNP transistor draws voltage from a gate terminal of the gate driver, when the push-pull driver is turned off.

[0109] According to the eighteenth aspect as claimed in any previous aspects from the eleventh aspect, the gate driver further includes a capacitor coupled to the power supply in parallel and configured to smoothen out fluctuations in a voltage generated by the power supply.

[0110] According to the nineteenth aspect as claimed in any previous aspects from the eleventh aspect, the HV switching circuitry further comprises a capacitor coupled to the power supplier in parallel and configured to smoothen out fluctuations in a voltage supplied by the power supplier.

[0111] According to the twentieth aspect, a half-bridge switching circuitry includes a first metal -oxide-semiconductor field-effect transistor (MOSFET), a first gate driver coupled to a gate terminal of the first MOSFET and configured for switching the first MOSFET, a second MOSFET, a second gate driver coupled to a gate terminal of the second MOSFET and configured for switching the second MOSFET, and a capacitive load coupled to an output terminal of the first MOSFET and to an input terminal of the second MOSFET. The first MOSFET controls a charge rate of the capacitive load, and the second MOSFET controls a discharge rate of the capacitive load. Each of the first and second gate driver includes a logic level gate driver configured to generate a first light and a second light, which is modulated, a power supply configured to convert the first light into power and supply the power, and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of respective one of the first or second MOSFET based on the second light.

[0112] The present disclosed may be embodied in other specific forms without departing from its spirit or characteristics. The described aspects are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

CLAIMSWhat is claimed is:

1. A gate driver for switching high voltage switching circuitry, the gate driver comprising: a logic level gate driver configured to generate a first light and a second light, which is modulated; a power supply configured to convert the first light into power and supply the power; and an optical driver coupled to the power supply and configured to turn on an off the high voltage switching circuitry based on the second light.

2. The gate driver according to claim 1, wherein the power supply comprises a photovoltaic component configured converting optical energy into the power.

3. The gate driver according to claim 1, wherein the optical driver comprises a phototransistor configured to turn on and off based on the second light.

4. The gate driver according to claim 1, wherein the optical driver is a push-pull driver.

5. The gate driver according to claim 4, wherein the push-pull driver comprises a NPN phototransistor and a PNP transistor.

6. The gate driver according to claim 4, wherein the push-pull driver comprises a PNP phototransistor and a NPN transistor.

7. The gate driver according to claim 5, wherein the NPN phototransistor drives voltage to a gate terminal of the gate driver, when the push-pull driver is turned on.

8. The gate driver according to claim 5, wherein the PNP transistor draws voltage from a gate terminal of the gate driver, when the push-pull driver is turned off.

9. The gate driver according to claim 1, wherein the gate driver is electrically isolated from the high voltage switching circuitry .

10. The gate driver according to claim 1, further comprising: a capacitor coupled to the power supply in parallel and configured to smoothen out fluctuations in a voltage generated by the power supply.

11. A high voltage switching circuitry, comprising: metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in series; a voltage balancing circuit coupled to the MOSFETs to ensure uniform voltage distribution across a gate terminal of each MOSFET; and a gate driver coupled to the gate terminal of one MOSFET of the MOSFETs and configured for switching the MOSFETs, the gate driver comprising: a logic level gate driver configured to generate a first light and a second light, which is modulated; a power supply configured to convert the first light into power and supply the power; and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of the one MOSFET based on the second light.

12. The high voltage switching circuitry according to claim 11, wherein, when the optical driver turns on the gate terminal of the one MOSFET, the gate terminals of the other MOSFETs are turned on based on the voltage balancing circuit.

13. The high voltage switching circuitry according to claim 11, wherein the optical driver is a push-pull driver.

14. The high voltage switching circuitry according to claim 13, wherein the push-pull driver comprises aNPN phototransistor and a PNP transistor.

15. The high voltage switching circuitry according to claim 13, wherein the push-pull dnver comprises a PNP phototransistor and aNPN transistor.

16. The high voltage switching circuitry according to claim 1 , wherein the NPN phototransistor drives voltage to a gate terminal of the gate driver, when the push-pull driver is turned on.

17. The high voltage switching circuitry according to claim 15, wherein the PNP transistor draws voltage from a gate terminal of the gate driver, when the push-pull driver is turned off.

18. The high voltage switching circuitry according to claim 11, wherein the gate driver is electrically isolated from the high voltage switching circuitry.

19. The high voltage switching circuitry according to claim 11, wherein the gate driver further comprises: a capacitor coupled to the power supply in parallel and configured to smoothen out fluctuations in a voltage generated by the power supply.

20. A half-bridge switching circuitry, comprising: a first metal-oxide-semiconductor field-effect transistor (MOSFET); a first gate driver coupled to a gate terminal of the first MOSFET and configured for switching the first MOSFET; a second MOSFET; a second gate driver coupled to a gate terminal of the second MOSFET and configured for switching the second MOSFET; and a capacitive load coupled to an output terminal of the first MOSFET and to an input terminal of the second MOSFET, wherein the first MOSFET controls a charge rate of the capacitive load, wherein the second MOSFET controls a discharge rate of the capacitive load, and wherein each of the first and second gate driver comprises: a logic level gate driver configured to generate a first light and a second light, which is modulated; a power supply configured to convert the first light into power and supply the power; and an optical driver coupled to the power supply and configured to turn on an off the gate terminal of respective one of the first or second MOSFET based on the second light.

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