Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a driving circuit layer (102) and a light-emitting structure layer (103) provided on a substrate (101). The driving circuit layer (102) comprises a plurality of circuit units at least comprising a pixel driving circuit. The light-emitting structure layer (103) comprises a plurality of light-emitting units at least comprising an anode (90). The anode (90) comprises an anode main body part and an anode connection part. An end of the anode connection part is connected to the anode main body part, and another end of the anode connection part is connected to the pixel driving circuit. At least one circuit unit further comprises a shielding electrode (94). An orthographic projection of the shielding electrode (94) on the substrate at least partially overlaps with an orthographic projection of a second anode center line (OY) of at least one anode (90) on the substrate. The second anode center line (OY) is a straight line which bisects the anode main body part in a first direction and extends in a second direction.

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate; the driving circuit layer includes a plurality of circuit units, at least one circuit unit includes at least a pixel driving circuit and a first power line, the first power line is configured to provide a first power line signal to the pixel driving circuit; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit; at least one circuit unit also includes a shielding electrode, the shielding electrode is connected to the first power line, the positive projection of at least one shielding electrode on the substrate at least partially overlaps with the positive projection of the second anode center line of at least one anode on the substrate, the second anode center line is a straight line that bisects the anode main body in the first direction and extends along the second direction, and the first direction and the second direction intersect.

[0006] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0007] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0008] A driving circuit layer is formed on a substrate, wherein the driving circuit layer includes a plurality of circuit units, at least one of which includes at least a pixel driving circuit and a first power line, wherein the first power line is configured to provide a first power line signal to the pixel driving circuit; at least one of the circuit units further includes a shielding electrode, wherein the shielding electrode is connected to the first power line;

[0009] A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit; the positive projection of at least one shielding electrode on the substrate at least partially overlaps with the positive projection of a second anode center line of at least one anode on the substrate, the second anode center line is a straight line that bisects the anode main body in a first direction and extends along a second direction, and the first direction and the second direction intersect.

[0010] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0012] FIG1 is a schematic structural diagram of a display device;

[0013] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0014] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0015] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0016] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0017] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0018] FIG7 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0019] FIG8 is a schematic diagram of an embodiment of the present disclosure after forming a first semiconductor layer pattern;

[0020] 9A and 9B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0021] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0022] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after forming a second semiconductor layer pattern;

[0023] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0024] FIG13 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern;

[0025] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0026] 14C and 14D are schematic diagrams of initial signal lines of the mesh structure in FIG. 14A ;

[0027] FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0028] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0029] FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern;

[0030] 18A and 18B are schematic diagrams of an embodiment of the present disclosure after forming a sixth conductive layer pattern;

[0031] FIG19 is a schematic diagram of an embodiment of the present disclosure after forming a third planar layer pattern;

[0032] 20A and 20B are schematic diagrams of an embodiment of the present disclosure after forming an anode conductive layer pattern.

[0033] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line; 25—light-emission control line; 31—first shielding line; 32—second shielding line; 33—first initial connection electrode; 41—first initial signal line; 42—second initial signal line; 43—third initial signal line; 44—first initial connection line; 45—second initial connection line; 46—third initial connection line; 51—first connection electrode; 52—second connection electrode; 53—third connection electrode; 54—fourth connection electrode; 55—fifth connection electrode; 56—Second initial connection electrode; 61—Eleventh connection electrode; 62—Twelfth connection electrode; 63—Thirteenth connection electrode; 71—First power line; 72—Data connection line; 73—Anode connection electrode; 74—Shielding electrode; 81—First electrode plate; 82—Second electrode plate; 83—Opening; 84—First electrode plate connection line; 85—Second electrode plate connection line; 90—Anode; 101—Substrate; 102—Drive circuit layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0035] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0036] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0037] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0038] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0039] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0040] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0041] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0042] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0043] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0044] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0045] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0046] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0047] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0048] In some possible embodiments, the pixel unit may include three sub-pixels, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light. The three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a triangular pattern, which is not limited in the present disclosure.

[0049] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0050] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0051] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, the display substrate includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate; the driving circuit layer includes a plurality of circuit units, at least one circuit unit includes at least a pixel driving circuit and a first power line, the first power line being configured to provide a first power line signal to the pixel driving circuit; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode including an anode main body and an anode connecting portion, one end of the anode connecting portion being connected to the anode main body, and the other end of the anode connecting portion being connected to the pixel driving circuit; at least one circuit unit further includes a shielding electrode, the shielding electrode being connected to the first power line, the orthographic projection of at least one shielding electrode on the substrate at least partially overlapping with the orthographic projection of a second anode center line of at least one anode on the substrate, the second anode center line being a straight line bisecting the anode main body in a first direction and extending along a second direction, the first direction and the second direction intersecting.

[0052] In an exemplary embodiment, the pixel driving circuit includes at least a second transistor serving as a compensation transistor and a third transistor serving as a driving transistor, a gate electrode of the second transistor being connected to a first scanning signal line, a first electrode of the second transistor being connected to a second electrode of the third transistor via a second node electrode, and a second electrode of the second transistor being connected to a gate electrode of the third transistor via a first node electrode; and an orthographic projection of the anode connection portion on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.

[0053] In an exemplary embodiment, an orthographic projection of the first power line on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.

[0054] In an exemplary embodiment, the shielding electrode is disposed between the second node electrodes of two adjacent circuit units in the first direction.

[0055] In an exemplary embodiment, an orthographic projection of the shield electrode on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.

[0056] In an exemplary embodiment, an orthographic projection of the first node electrode on the substrate at least partially overlaps with an orthographic projection of the first scan signal line on the substrate.

[0057] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line extending along the first direction and a first initial connection line extending along the second direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, the first initial signal connection line being connected to the first initial signal line to form a mesh connectivity structure for transmitting the first initial signal, and / or, at least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connection line extending along the second direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit, the second initial signal connection line being connected to the second initial signal line to form a mesh connectivity structure for transmitting the second initial signal, and / or, at least one circuit unit further includes a third initial signal line extending along the first direction and a third initial connection line extending along the second direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit, the third initial signal connection line being connected to the third initial signal line to form a mesh connectivity structure for transmitting the third initial signal.

[0058] In an exemplary embodiment, at least one of the first initial connection line, the second initial connection line, and the third initial connection line includes a first initial connection electrode and a second initial connection electrode connected to each other; in a direction perpendicular to the substrate, the driving circuit layer includes a plurality of conductive layers, and the first initial connection electrode and the second initial connection electrode are arranged in different conductive layers.

[0059] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0060] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, emission signal line EM, first initial signal line INIT1, second initial signal line INIT1, third initial signal line INIT3, data signal line DATA, and first power line VDD).

[0061] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the eighth transistor T8, respectively; the third node N3 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0062] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0063] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the second node N2 .

[0064] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the second node N2 , and a second electrode of the second transistor T2 is connected to the first node N1 .

[0065] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the third node N3 , and a second electrode of the third transistor T3 is connected to the second node N2 .

[0066] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0067] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3.

[0068] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the second node N2, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0069] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0070] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0071] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode.

[0072] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0073] In some possible exemplary embodiments, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. In other possible exemplary embodiments, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may include a P-type transistor and an N-type transistor.

[0074] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0075] As shown in FIG4 , in this exemplary embodiment, the first transistor T1 and the second transistor T2 in the pixel driving circuit may be oxide transistors (N-type transistors), and the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors (P-type transistors).

[0076] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0077] The first phase A1 can be referred to as a reset phase for the second node N2 and the fourth node N4. The signals on the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are low-level signals, while the signals on the fourth scan signal line S4 and the light-emitting signal line EM are high-level signals, turning on the seventh transistor T7 and the eighth transistor T8, while turning off the other switching transistors.

[0078] The seventh transistor T7 is turned on so that the signal of the second initialization signal line INIT2 is provided to the fourth node N4, thereby initializing (resetting) the first electrode of the light-emitting device EL, clearing the original charge in the first electrode of the light-emitting device EL, and setting the potential of the fourth node N4 to Vinit2. The eighth transistor T8 is turned on so that the signal of the third initialization signal line INIT3 is provided to the second node N2, thereby initializing (resetting) the second node N2, and setting the potential of the second node N2 to Vinit3.

[0079] The second phase A2 can be called the reset phase of the first node N1 and the second transistor T2. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line EM are high-level signals, turning on the first transistor T1 and the second transistor T2, and turning off the other switching transistors.

[0080] The first transistor T1 and the second transistor T2 are turned on so that the signal of the first initial signal line INIT1 is provided to the first node N1 and the second node N2 respectively, initializing (resetting) the first node N1 and the second node N2, clearing the original charge in the first node N1, and the potential of the first node N1 and the second node N2 is Vinit1.

[0081] The third phase A3 can be called the data writing phase. The signal on the third scan signal line S3 is a low-level signal, the signal on the fourth scan signal line S4 is a low-level signal for a short period of time, and the signals on the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line EM are high-level signals, turning on the second transistor T2 and the fourth transistor T4, and turning off the other switching transistors.

[0082] The second transistor T2 is turned on, so that the first node N1 and the second node N2 are turned on. Since the third transistor T3 is continuously turned on during this stage, the fourth transistor T4 is turned on, so that the data signal output by the data signal line DATA is provided to the first node N1 through the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line DATA and Vth is the threshold voltage of the third transistor T3.

[0083] The fourth stage A4 may be referred to as a stage in which the second node N2 , the third node N3 , and the fourth node N4 are reset.

[0084] The signals of the first scanning signal line S1 and the third scanning signal line S3 are low-level signals, the signal of the second scanning signal line S2 is a low-level signal for a short period of time, and the signals of the fourth scanning signal line S4 and the light-emitting signal line EM are high-level signals, so that the seventh transistor T7 and the eighth transistor T8 are turned on, and the other switching transistors are turned off.

[0085] The seventh transistor T7 is turned on, causing the signal of the second initial signal line INIT2 to be supplied to the fourth node N4. Since the third transistor T3 is continuously turned on during this stage, the eighth transistor T8 is turned on, causing the signal of the third initial signal line INIT3 to be supplied to the second node N2 and the third node N3, respectively resetting the second node N2, the third node N3, and the fourth node N4. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3, and the fourth node N4 in this stage can eliminate and reduce hysteresis deviation caused by grayscale differences between adjacent pixels. It can also periodically reset the OLED anode to improve low-frequency flicker.

[0086] The fifth stage A5 can be called the light-emitting stage. The signals on the first scanning signal line S1, the third scanning signal line S3, and the light-emitting signal line EM are low-level signals, and the signals on the second scanning signal line S2 and the fourth scanning signal line S4 are high-level signals, turning on the fifth transistor T5 and the sixth transistor T6, and turning off the other switching transistors.

[0087] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on sixth transistor T6, thereby driving the light-emitting device EL to emit light.

[0088] During the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, thereby ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0089] Figure 6 is a schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of multiple circuit units (2 unit rows and 4 unit columns). In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate of the exemplary embodiment of the present disclosure may include a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate. On a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, at least one of which may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of which may include a light-emitting device, which is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0090] In exemplary embodiments, the circuit unit referred to in this disclosure is a region divided according to the pixel driving circuit. The light-emitting unit referred to in this disclosure is a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0091] In an exemplary embodiment, the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, wherein the plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of unit rows are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, wherein the first direction X intersects the second direction Y.

[0092] As shown in FIG6 , at least one circuit unit may include a pixel driving circuit, and first scan signal lines 21, second scan signal lines 22, third scan signal lines 23, fourth scan signal lines 24, light emitting signal lines 25, first initial signal lines 41, second initial signal lines 42, third initial signal lines 43, first power supply lines 71, and data signal lines 72 connected to the pixel driving circuit. In an exemplary embodiment, the first scan signal lines 21, second scan signal lines 22, third scan signal lines 23, fourth scan signal lines 24, light emitting signal lines 25, first initial signal lines 41, second initial signal lines 42, and third initial signal lines 43 may be in the shape of a straight line with a main portion extending along the first direction X or a zigzag line, and the first power supply lines 71 and data signal lines 72 may be in the shape of a straight line with a main portion extending along the second direction Y or a zigzag line. In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the fourth scan signal line 24 are configured to provide scan signals to the pixel driving circuit, the light-emitting signal line 25 is configured to provide a light-emitting control signal to the pixel driving circuit, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 are configured to provide an initial signal to the pixel driving circuit, the first power line 71 is configured to provide a first power signal to the pixel driving circuit, and the data signal line 72 is configured to provide a data signal to the pixel driving circuit.

[0093] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0094] In an exemplary embodiment, the pixel driving circuit in at least one circuit unit may include a storage capacitor and a plurality of transistors, the storage capacitor may include a stacked first electrode plate and a second electrode plate, and the plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. The first transistor T1 and the second transistor T2 are oxide transistors, and the third transistor T3 to the eighth transistor T8 are low-temperature polysilicon transistors.

[0095] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The gate electrode of the second transistor T2 is connected to the first scan signal line 21, the first electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 via the second connection electrode 52 serving as the second node electrode, and the second electrode of the second transistor T2 is connected to the gate electrode (first plate) of the third transistor T3 via the first connection electrode 51 serving as the first node electrode. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 24, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, the first electrode of the fifth transistor T5 is connected to the first power supply line 71, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 25, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22, the first electrode of the eighth transistor T8 is connected to the third initial signal line 43, and the second electrode of the eighth transistor T8 is connected to the second electrode of the third transistor T3 via the second connecting electrode 52.

[0096] In an exemplary embodiment, the first power lines 71 in two circuit units adjacent to each other in the first direction X may be an integrated structure connected to each other.

[0097] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate at least partially overlaps an orthographic projection of the first connection electrode 51 on the substrate.

[0098] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate at least partially overlaps an orthographic projection of the active layer of the second transistor T2 on the substrate.

[0099] In an exemplary embodiment, an orthographic projection of the first connection electrode 51 on the substrate at least partially overlaps with an orthographic projection of the first scan signal line 21 on the substrate.

[0100] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.

[0101] In an exemplary embodiment, at least one circuit unit further includes a shielding electrode 74 , which is connected to the first power line 71 and disposed between the second connection electrodes 52 of two adjacent circuit units in the first direction X.

[0102] In an exemplary embodiment, the orthographic projection of the shielding electrode 74 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate.

[0103] In an exemplary embodiment, an orthographic projection of the second connection electrode 52 on the substrate does not overlap with an orthographic projection of the fourth scan signal line 24 on the substrate.

[0104] Figure 7 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of the anodes in multiple light-emitting units. In this exemplary embodiment, the light-emitting structure layer may include multiple light-emitting units, at least one of which may include a light-emitting device, and at least one light-emitting device may include an anode 90, which is connected to the pixel driving circuit of the corresponding circuit unit.

[0105] As shown in Figure 7, at least one anode 90 may include an anode main body and an anode connecting part. The shape of the anode main body may be circular or elliptical, and the shape of the anode connecting part may be a strip. One end of the anode connecting part is directly connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit through a via.

[0106] In an exemplary embodiment, the anode body portion of at least one anode may have a first anode centerline OX and a second anode centerline OY, the first anode centerline OX may be a straight line that bisects the anode body portion of the anode in the second direction Y and extends along the first direction X, and the second anode centerline OY may be a straight line that bisects the anode body portion of the anode in the first direction X and extends along the second direction Y.

[0107] In an exemplary embodiment, an orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps an orthographic projection of the second anode centerline OY of the at least one anode 90 on the substrate.

[0108] In an exemplary embodiment, the orthographic projection of the anode body portion of at least one anode 90 on the substrate at least partially overlaps with the orthographic projections of two first power lines 71 in two adjacent circuit units in the first direction X on the substrate, and the two first power lines 71 can be mirror-symmetrical with respect to the second anode center line OY.

[0109] In an exemplary embodiment, an orthographic projection of the anode connection portion of the at least one anode 90 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.

[0110] In an exemplary embodiment, a first power block 71-1 and a second power block 71-2 may be provided on at least one first power line 71, the orthographic projection of the anode body portion of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 on the substrate, and the first power block 71-1 and the second power block 71-2 may be mirror-symmetrical relative to the first anode center line OX.

[0111] In an exemplary embodiment, the orthographic projection of the anode body portion of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of two first power blocks 71-1 in two adjacent circuit units in the first direction X on the substrate, and the two first power blocks 71-1 can be mirror-symmetrical relative to the second anode center line OY.

[0112] In an exemplary embodiment, the orthographic projection of the anode body portion of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of two second power blocks 71-2 in two adjacent circuit units in the first direction X on the substrate, and the two second power blocks 71-2 can be mirror-symmetrical relative to the second anode center line OY.

[0113] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, a second planar layer, a sixth conductive layer, and a third planar layer sequentially disposed on a substrate. The first semiconductor layer may include at least the active layers of the third to eighth transistors T3 to T8, the first conductive layer may include at least the second scan signal line 22, the fourth scan signal line 24, and the first plate of the storage capacitor, the second conductive layer may include at least the second plate of the storage capacitor, the second semiconductor layer may include at least the active layers of the first transistor T1 and the second transistor T2, the third conductive layer may include at least the first scan signal line 21, the third scan signal line 23, and the first initial connection electrode 33, the fourth conductive layer may include at least the second initial connection electrode 46, the fifth conductive layer may include at least a plurality of connection electrodes, and the sixth conductive layer may include at least the first power line 71, the data signal line 72, and the shielding electrode 74.

[0114] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0115] In an exemplary embodiment, taking 8 circuit units (2 unit rows and 4 unit columns) as an example, the preparation process of the display substrate may include the following operations.

[0116] (1) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 8 .

[0117] In an exemplary embodiment, the first semiconductor layer pattern in each circuit unit may include the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 in the circuit unit are an integral structure connected to each other.

[0118] In an exemplary embodiment, in the first direction X, the fourth active layer 14 and the fifth active layer 15 may be located on the same side of the third active layer 13 of the circuit unit, the sixth active layer 16 and the seventh active layer 17 may be located on the same side of the third active layer 13 of the circuit unit, and the fifth active layer 15 and the sixth active layer 16 may be located on different sides of the third active layer 13 of the circuit unit. In the second direction Y, the fourth active layer 14 of the circuit unit in the Mth circuit row may be located on a side of the third active layer 13 away from the M+1th circuit row, and the fifth active layer 15, sixth active layer 16, seventh active layer 17, and eighth active layer 18 of the circuit unit in the Mth circuit row may be located on a side of the third active layer 13 close to the circuit unit in the M+1th unit row.

[0119] In an exemplary embodiment, the third active layer 13 may have an Ω shape, and the fourth to eighth active layers 14 , 15 , 16 , 17 , and 18 may have an I shape.

[0120] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 may be connected to each other, and the first region 13-1 of the third active layer 13 may simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15. The second region 13-2 of the third active layer 13 is connected to the first region 16-1 of the sixth active layer 16, and the second region 13-2 of the third active layer 13 may serve as the first region 16-1 of the sixth active layer 16. The second region 16-2 of the sixth active layer 16 is connected to the second region 17-2 of the seventh active layer 17, and the second region 16-2 of the sixth active layer 16 may serve as the second region 17-2 of the seventh active layer 17. The first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, the first region 17-1 of the seventh active layer 17, the first region 18-1 of the eighth active layer 18, and the second region 18-2 of the eighth active layer 18 may be separately provided.

[0121] In an exemplary embodiment, in a cell row, the first semiconductor layers of two adjacent circuit cells may be symmetrically arranged relative to a column centerline, where the column centerline may be a straight line located between two adjacent circuit cells in the first direction X and extending along the second direction Y. For example, the first semiconductor layers (the third active layer 13 to the eighth active layer 18) of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the first semiconductor layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0122] In example embodiments, the first semiconductor layers in adjacent cell rows may be substantially the same.

[0123] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the third through eighth transistors are LTPS thin-film transistors. In an exemplary embodiment, patterning the first semiconductor thin film through a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon thin film, and then crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, patterning the polycrystalline silicon thin film to form a first semiconductor layer pattern.

[0124] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0125] In an exemplary embodiment, the first conductive layer pattern in each circuit unit includes at least a second scan signal line 22 , a fourth scan signal line 24 , a light emitting control line 25 , and a first plate 81 of a storage capacitor.

[0126] In an exemplary embodiment, the first electrode plate 81 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 81 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0127] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main part extending along the first direction X. The second scanning signal line 22 in the Mth unit row circuit unit can be located on the side of the first electrode 81 of this circuit unit close to the M+1th unit row circuit unit. The area where the second scanning signal line 22 overlaps with the seventh active layer of this circuit unit serves as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 22 overlaps with the eighth active layer of this circuit unit serves as the gate electrode of the eighth transistor T8.

[0128] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main part extending along the first direction X. The fourth scan signal line 24 in the Mth unit row circuit unit can be located on the side of the first electrode 81 of this circuit unit away from the M+1th unit row circuit unit, and the area where the fourth scan signal line 24 overlaps with the fourth active layer of this circuit unit serves as the gate electrode of the fourth transistor T4.

[0129] In an exemplary embodiment, the shape of the light-emitting control line 25 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting control line 25 can be located between the first electrode 81 and the second scanning signal line 22. The area where the light-emitting control line 25 overlaps with the fifth active layer of this circuit unit serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 25 overlaps with the sixth active layer of this circuit unit serves as the gate electrode of the sixth transistor T6.

[0130] In an exemplary embodiment, the first conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the first conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the first conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0131] In example embodiments, the first conductive layers in adjacent cell rows may be substantially the same.

[0132] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the third active layer to the eighth active layer are both conductorized.

[0133] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0134] In an exemplary embodiment, the second conductive layer pattern in each circuit unit includes at least a first shielding line 31 , a second shielding line 32 , and a second plate 82 of the storage capacitor.

[0135] In an exemplary embodiment, the outline of the second electrode plate 82 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 82 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 81 on the substrate. The second electrode plate 82 can serve as another electrode plate of the storage capacitor, and the first electrode plate 81 and the second electrode plate 82 constitute the storage capacitor of the pixel driving circuit.

[0136] In an exemplary embodiment, an opening 83 is provided on the second electrode plate 82. The opening 83 can be block-shaped (e.g., rectangular) and can be located in the middle of the second electrode plate 82, forming an annular structure. The opening 83 exposes the third insulating layer covering the first electrode plate 81, and the orthographic projection of the first electrode plate 81 on the substrate includes the orthographic projection of the opening 83 on the substrate. In an exemplary embodiment, the opening 83 is configured to accommodate a subsequently formed eleventh via. The eleventh via is located within the opening 83 and exposes the first electrode plate 81, allowing a subsequently formed first connecting electrode to be connected to the first electrode plate 81.

[0137] In an exemplary embodiment, the second plate 82 may be provided with a first plate connection line 84 and a second plate connection line 85. The first plate connection line 84 and the second plate connection line 85 may be provided on either side of the second plate 82 in the first direction X, and may be connected to the second plates 82 in adjacent circuit cells in the first direction X, respectively. This interconnects the second plates 82 in adjacent circuit cells within a row. For example, the second plate 82 in the Nth column and the second plate 82 in the N+1th column may be interconnected via the first plate connection line 84. In another example, the second plate 82 in the N+1th column and the second plate 82 in the N+2th column may be interconnected via the second plate connection line 85. Since the second plate 82 in each circuit cell is connected to a subsequently formed first power line, by forming an integrated structure with the second plates 82 of adjacent circuit cells interconnected, the integrated second plates 82 can be reused as power signal lines. This ensures that multiple second plates 82 in a row have the same potential, which helps improve panel uniformity, prevent display defects on the display substrate, and ensure the display quality of the display substrate.

[0138] In an exemplary embodiment, the first plate connection line 84 and the second plate connection line 85 may have different widths, where the width is the dimension in the second direction Y.

[0139] In an exemplary embodiment, the first shielding line 31 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The first shielding line 31 may be located between the second electrode plate 82 and the fourth scan signal line 24. In an exemplary embodiment, the first shielding line 31 may be a zigzag line of varying widths. The width of the first shielding line 31 at the location where it overlaps with the subsequently formed second active layer may be greater than the width at other locations. The first shielding line 31 at the wider location may serve as a shielding layer for the second transistor T2, shielding the channel region of the second transistor T2 and ensuring the electrical performance of the oxide second transistor T2. In an exemplary embodiment, the first shielding line 31 may also serve as the bottom gate electrode of the second transistor T2.

[0140] In an exemplary embodiment, the first shielding line 31 may be a straight line or a broken line of unequal width, and the width is the dimension in the second direction Y. The first shielding line 31 may include at least a first sub-shielding line segment 31-1 and a second sub-shielding line segment 31-2 that are connected to each other, and the width of the first sub-shielding line segment 31-1 is greater than the width of the second sub-shielding line segment 31-2. In an exemplary embodiment, the first sub-shielding line segment 31-1 may be arranged in an area where a second active layer to be formed subsequently is located, and the orthographic projection of the first sub-shielding line segment 31-1 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the second sub-shielding line segment 31-2 may be arranged in an area outside the second active layer to be formed subsequently, and the orthographic projection of the second sub-shielding line segment 31-2 on the substrate does not overlap with the orthographic projection of the second active layer on the substrate.

[0141] In an exemplary embodiment, the second shielding line 32 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The second shielding line 32 may be located on the side of the fourth scan signal line 24 away from the second electrode plate 82. In an exemplary embodiment, the second shielding line 32 may be a zigzag line of varying widths. The width of the second shielding line 32 at the location where it overlaps with the subsequently formed first active layer may be greater than the width at other locations. The wider second shielding line 32 may serve as a shielding layer for the first transistor T1, shielding the channel region of the first transistor T1 and ensuring the electrical performance of the oxide first transistor T1. In an exemplary embodiment, the second shielding line 32 may also serve as the bottom gate electrode of the first transistor T1.

[0142] In an exemplary embodiment, the second conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the second conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the second conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0143] In example embodiments, the second conductive layers in adjacent cell rows may be substantially the same.

[0144] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second semiconductor layer in FIG11A .

[0145] In an exemplary embodiment, the second semiconductor layer pattern in each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2 .

[0146] In an exemplary embodiment, the shape of the first active layer 11 and the second active layer 12 can be "I"-shaped, and the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second shading line 32 on the substrate, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first shading line 31 on the substrate.

[0147] In an exemplary embodiment, the first region 11-1 of the first active layer 11 can be located on the side of the second shielding line 32 away from the second electrode 82, the second region 12-2 of the second active layer 12 can be located on the side of the first shielding line 31 close to the second electrode 82, the second region 11-2 of the first active layer 11 and the first region 12-1 of the second active layer 12 can be connected to each other, and the second region 11-2 of the first active layer 11 can serve as the first region 12-1 of the second active layer 12.

[0148] In an exemplary embodiment, the second semiconductor layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the second semiconductor layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the second semiconductor layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0149] In example embodiments, the second semiconductor layers in adjacent cell rows may be substantially the same.

[0150] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0151] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0152] In an exemplary embodiment, the third conductive layer pattern in each circuit unit includes at least a first scan signal line 21 , a third scan signal line 23 , and a first preliminary connection electrode 33 .

[0153] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X. The first scanning signal line 21 can be located between the second electrode 82 and the fourth scanning signal line 24, and the area where the first scanning signal line 21 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0154] In an exemplary embodiment, the orthographic projection of the first scanning signal line 21 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 31 on the substrate. The first scanning signal line 21 and the first shielding line 31 can be connected to the same signal source, so that the first shielding line 31 can serve as the bottom gate electrode of the second transistor T2, and the first scanning signal line 21 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0155] In an exemplary embodiment, the first scan signal line 21 may be a straight line or a zigzag line of unequal width, where the width is the dimension in the second direction Y. The first scan signal line 21 may include at least a first sub-scan line segment 21-1 and a second sub-scan line segment 21-2 connected to each other, wherein the width of the first sub-scan line segment 21-1 is greater than the width of the second sub-scan line segment 21-2. In an exemplary embodiment, the first sub-scan line segment 21-1 may be disposed in the region where the second active layer is located, with the orthographic projection of the first sub-scan line segment 21-1 on the substrate at least partially overlapping with the orthographic projection of the second active layer on the substrate. The second sub-scan line segment 21-2 may be disposed in a region outside the second active layer, with the orthographic projection of the second sub-scan line segment 21-2 on the substrate not overlapping with the orthographic projection of the second active layer on the substrate.

[0156] In an exemplary embodiment, the orthographic projection of the first sub-scanning line segment 21-1 on the substrate at least partially overlaps with the orthographic projection of the first sub-blocking line segment 31-1 on the substrate, and the orthographic projection of the second sub-scanning line segment 21-2 on the substrate at least partially overlaps with the orthographic projection of the second sub-blocking line segment 31-2 on the substrate.

[0157] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located on the side of the fourth scan signal line 24 away from the second electrode plate 82, and the area where the third scan signal line 23 overlaps with the first active layer serves as the gate electrode of the first transistor T1.

[0158] In an exemplary embodiment, the orthographic projection of the third scan signal line 23 on the substrate at least partially overlaps with the orthographic projection of the second shading line 32 on the substrate, and the third scan signal line 23 and the second shading line 32 can be connected to the same signal source, so that the second shading line 32 can serve as the bottom gate electrode of the first transistor T1, and the third scan signal line 23 can serve as the top gate electrode of the first transistor T1, forming the first transistor T1 with a top-gate and bottom-gate structure.

[0159] In an exemplary embodiment, the first initial connection electrode 33 is shaped like a broken line with the main portion extending along the second direction. The first initial connection electrode 33 is configured to be connected to the second initial connection electrode formed subsequently, and the first initial connection electrode and the second initial connection electrode together constitute an initial connection line.

[0160] In an exemplary embodiment, the first preliminary connection electrode 33 may include a first end 33A, a second end 33B, a first connection block 33-1, a second connection block 33-2, and a third connection block 33-3. The first end 33A of the first preliminary connection electrode 33 is the end of the first preliminary connection electrode 33 close to the first scan signal line 21, and the second end 33B of the first preliminary connection electrode 33 is the end of the first preliminary connection electrode 33 close to the third scan signal line 23. The first connection block 33-1 may be disposed on a side of the first end 33A close to the second end 33B. The first connection block 33-1 is configured to connect to a first preliminary signal line formed later. The second connection block 33-2 may be disposed on a side of the first connection block 33-1 close to the second end 33B. The second connection block 33-2 is configured to connect to a second preliminary signal line formed later. The third connection block 33-3 may be disposed on a side of the second connection block 33-2 close to the second end 33B. The third connection block 33-3 is configured to connect to a third preliminary signal line formed later.

[0161] In an exemplary embodiment, the third conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the third conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the third conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0162] In example embodiments, the third conductive layers in adjacent cell rows may be substantially the same.

[0163] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 13 .

[0164] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a first via V1 to a fourteenth via V14 .

[0165] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.

[0166] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0167] In an exemplary embodiment, a bent portion is provided on the fourth scan signal line 24 in the region where the second via hole V2 is located, and the bent portion protrudes in a direction away from the second electrode plate 82, so that the orthographic projection of the second via hole V2 on the substrate does not overlap with the orthographic projection of the fourth scan signal line 24 on the substrate.

[0168] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the second region of the second active layer through the via hole.

[0169] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fourth via hole V4 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0170] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0171] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via hole V6 are etched away to expose the surface of the first region of the fifth active layer. The sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0172] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the seventh via hole V7 is configured to connect the subsequently formed fifth connecting electrode 55 to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0173] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the seventh active layer, and the eighth via V8 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0174] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first region of the eighth active layer, and the ninth via V9 is configured to connect a subsequently formed third initial signal line to the first region of the eighth active layer through the via.

[0175] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the second region of the eighth active layer, and the tenth via hole V10 is configured to connect a subsequently formed second connecting electrode to the second region of the eighth active layer through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the opening 83 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first electrode 31, and the eleventh via hole V11 is configured to connect a subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0177] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second electrode plate connecting line 85 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twelfth via hole V12 are etched away, exposing the surface of the second electrode connecting line 85, and the twelfth via hole V12 is configured to connect the subsequently formed fourth connecting electrode to the second electrode connecting line 85 through the via hole.

[0178] In an exemplary embodiment, two circuit units adjacent to each other in some first directions X may share the same twelfth via V12. For example, two circuit units in the N-1th and Nth unit columns may share the same twelfth via V12. For another example, two circuit units in the N+1th and N+2th unit columns may share the same twelfth via V12. For another example, two circuit units in the N+3th and N+4th unit columns may share the same twelfth via V12.

[0179] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first end 33A of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the thirteenth via hole V13 is etched away, exposing the surface of the first end 33A, and the thirteenth via hole V13 is configured to connect the subsequently formed second initial connection electrode to the first end 33A through the via hole.

[0180] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second end 33B of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the second end 33B, and the fourteenth via hole V14 is configured to connect the subsequently formed second initial connection electrode to the second end 33B through the via hole.

[0181] In an exemplary embodiment, the plurality of via holes in the at least one circuit unit may further include a fifteenth via hole V15 , a sixteenth via hole V16 , and a seventeenth via hole V17 .

[0182] In an exemplary embodiment, the fifteenth via V15 can be arranged in the circuit units of the Nth unit column and the N+3th unit column, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first connection block 33-1 of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first connection block 33-1, and the fifteenth via V15 is configured to connect the subsequently formed first initial signal line to the first connection block 33-1 through the via.

[0183] In an exemplary embodiment, the sixteenth via V16 can be arranged in the circuit unit of the N+1th unit column, and the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second connection block 33-2 of the first initial connection electrode 33 on the substrate. The sixth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second connection block 33-2. The sixteenth via V16 is configured to connect the subsequently formed second initial signal line to the second connection block 33-2 through the via.

[0184] In an exemplary embodiment, the seventeenth via V17 can be arranged in the circuit unit of the N+2th unit column, and the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third connection block 33-3 of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away to expose the surface of the third connection block 33-3, and the sixteenth via V16 is configured to connect the subsequently formed third initial signal line to the third connection block 33-3 through the via.

[0185] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 14A and FIG. 14B , where FIG. 14B is a plan view schematic diagram of the fourth conductive layer in FIG. 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0186] In an exemplary embodiment, the fourth conductive layer in each circuit unit includes at least: a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55 and a second initial connection electrode 56.

[0187] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the second active layer via a third via hole V3, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 via an eleventh via hole V11. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the second electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit. In an exemplary embodiment, the first connection electrode 51 may be referred to as a first node electrode.

[0188] In an exemplary embodiment, the orthographic projection of the first connection electrode 51 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 on the substrate. Because the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first connection electrode 51 can increase the parasitic capacitance between the first scan signal line 21 and the first node N1. In an exemplary embodiment, after the fourth scan signal line 24 outputs an on signal, the parasitic capacitance can lower the potential of the first node N1 by utilizing the falling edge of the first scan signal line 21, thereby increasing current and effectively improving display brightness.

[0189] In an exemplary embodiment, a first compensation block 51-1 may be provided on the first connecting electrode 51, a first end of the first compensation block 51-1 is connected to the first end of the first connecting electrode 51, a second end of the first compensation block 51-1 extends toward the direction of the first scanning signal line 21, and an orthographic projection of the first compensation block 51-1 on the substrate at least partially overlaps with an orthographic projection of the first scanning signal line 21 on the substrate.

[0190] In an exemplary embodiment, the first connection electrode 51 and the first compensation block 51 - 1 may be an integral structure connected to each other.

[0191] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via V2, and to the second region of the second active layer via a third via V3. A second end of the second connection electrode 52 is connected to the second region of the eighth active layer via a tenth via V10. The area between the first and second ends of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fourth via V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit. In an exemplary embodiment, the second connection electrode 52 may be referred to as a second node electrode.

[0192] In the exemplary embodiment, a curved portion is provided on the fourth scan signal line 24 in the region where the second via V2 is located. The curved portion protrudes away from the second electrode plate 82, allowing the fourth scan signal line 24 to avoid the second connection electrode 52. The orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projection of the fourth scan signal line 24 on the substrate. Because the second connection electrode 52 serves as the second node N2 of the pixel driving circuit, the parasitic capacitance between the second node N2 and the fourth scan signal line 24 can be effectively reduced. This not only reduces the parasitic capacitance of the second node N2, but also minimizes the impact on the data signal writing process.

[0193] In the exemplary embodiment, a curved portion is provided on the fourth scan signal line 24 to avoid the second connection electrode 52, and a curved portion is provided on the third scan signal line 23 to avoid the first initial connection electrode 33. This allows the orthographic projection of the fourth scan signal line 24 on the substrate to at least partially overlap with the orthographic projection of the third scan signal line 23 on the substrate, thereby increasing the parasitic capacitance between the third scan signal line 23 and the fourth scan signal line 24. Because the third scan signal line 23 outputs an on-signal during the second period, this on-signal does not affect the output of the on-signal by the fourth scan signal line 24 during the third period, nor does it affect the data signal writing process.

[0194] In an exemplary embodiment, the orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projection of the first sub-scanning line segment 21-1 in the first scanning signal line 21 on the substrate, the orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projection of the first sub-blocking line segment 31-1 in the first blocking line 31 on the substrate, the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning line segment 21-2 in the first scanning signal line 21 on the substrate, and the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning line segment 21-2 in the first blocking line 31 on the substrate. Since the width of the second sub-blocking line segment 31-2 is smaller than the width of the first sub-blocking line segment 31-1, the width of the second sub-scanning line segment 21-2 is smaller than the width of the first sub-scanning line segment 21-1, and thus the parasitic capacitance between the second connecting electrode 52 and the first scanning signal line 21 (first blocking line 31) can be effectively reduced. On the one hand, the parasitic capacitance of the second node N2 can be reduced, and on the other hand, the impact on the first scanning signal line can be reduced.

[0195] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (such as a rectangle), and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5. The third connection electrode 53 is configured to be connected to the subsequently formed twelfth connection electrode.

[0196] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a strip extending along the second direction Y. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer via a sixth via hole V6, and a second end of the fourth connection electrode 54 is connected to the second plate connection line 85 via a twelfth via hole V12. The fourth connection electrode 54 is configured to be connected to an eleventh connection electrode to be formed later. In an exemplary embodiment, because the second plate connection line 85 is connected to the second plate 82, the fourth connection electrode 54 ensures that the first electrode of the fifth transistor T5 in the circuit unit and the second plate 82 of the storage capacitor have the same potential.

[0197] In an exemplary embodiment, the fourth connection electrodes 54 of two circuit units adjacent to each other in the first direction X may be interconnected as an integral structure. For example, the fourth connection electrodes 54 of the two circuit units in the N-1th and Nth unit columns may be interconnected as an integral structure. For another example, the fourth connection electrodes 54 of the two circuit units in the N+1th and N+2th unit columns may be interconnected as an integral structure. For another example, the fourth connection electrodes 54 of the two circuit units in the N+3th and N+4th unit columns may be interconnected as an integral structure.

[0198] In an exemplary embodiment, the fifth connection electrode 55 may be in a block shape (e.g., a rectangle), and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a seventh via hole V7. In an exemplary embodiment, the fifth connection electrode 55 is configured to be connected to a subsequently formed thirteenth connection electrode to form a fourth node N4 of the pixel driving circuit.

[0199] In an exemplary embodiment, the shape of the second initial connection electrode 56 can be a broken line with the main portion extending along the second direction Y, the first end of the second initial connection electrode 56 is connected to the first end 33A of the first initial connection electrode 33 through the thirteenth via hole V13, and the second end of the second initial connection electrode 56 is connected to the second end 33B of the first initial connection electrode 33 through the fourteenth via hole V14.

[0200] In an exemplary embodiment, the first initial signal line 41 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed on a side of the third scan signal line 23 away from the second electrode plate 82. In each circuit unit, the first initial signal line 41 is connected to the first region of the first active layer through the first via V1, thereby connecting the first initial signal line 41 to the first electrode of the first transistor T1. The first initial signal line 41 may write the transmitted first initial signal into the first electrode of the first transistor T1.

[0201] In the exemplary embodiment, in the circuit cells of the Nth and N+3th cell columns, the first initial signal line 41 is further connected to the first connection block 33-1 via the fifteenth via V15. Since the first connection block 33-1 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent cell rows are interconnected via the second initial connection electrode 56. The interconnected first initial connection electrodes 33 and second initial connection electrodes 56 in the Nth and N+3th cell columns form a first initial connection line, connecting the first initial signal line 41 extending along the first direction X with the first initial connection line extending along the second direction Y. This allows the first initial signal line 41 and the first initial connection line to form a mesh structure in the display area that transmits the first initial signal. This effectively reduces the resistance of the first initial signal line and the voltage drop of the first initial signal, and also effectively improves the uniformity of the first initial signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0202] In an exemplary embodiment, the second initial signal line 42 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed on a side of the second scanning signal line 22 away from the second electrode plate 82. In each circuit unit, the second initial signal line 42 is connected to the first region of the seventh active layer through the eighth via V8, thereby connecting the second initial signal line 42 to the first electrode of the seventh transistor T7. The second initial signal line 42 may write the transmitted second initial signal into the first electrode of the seventh transistor T7.

[0203] In an exemplary embodiment, in the circuit cells of the N+1th unit column, the second initial signal line 42 is further connected to the second connection block 33-2 via the sixteenth via V16. Since the second connection block 33-2 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent unit rows are interconnected via the second initial connection electrode 56. The interconnected first initial connection electrode 33 and the second initial connection electrode 56 in the N+1th unit column form a second initial connection line, thereby connecting the second initial signal line 42 extending along the first direction X with the second initial connection line extending along the second direction Y. This allows the second initial signal line 42 and the second initial connection line to form a mesh structure in the display area for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line and the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0204] In an exemplary embodiment, the third initial signal line 43 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed between the second scanning signal line 22 and the second initial signal line 42. In each circuit unit, the third initial signal line 43 is connected to the first region of the eighth active layer through the ninth via hole V9, thereby connecting the third initial signal line 43 to the first electrode of the eighth transistor T8. The third initial signal line 43 may write the transmitted third initial signal into the first electrode of the eighth transistor T8.

[0205] In an exemplary embodiment, in the circuit cells of the (N+2)th unit column, the third initial signal line 43 is further connected to the third connection block 33-3 via the seventeenth via V17. Since the third connection block 33-3 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent unit rows are interconnected via the second initial connection electrode 56. The interconnected first initial connection electrode 33 and second initial connection electrode 56 in the (N+2)th unit column form a third initial connection line, thereby connecting the third initial signal line 43 extending along the first direction X with the third initial connection line extending along the second direction Y. This allows the third initial signal line 43 and the third initial connection line to form a mesh structure in the display area for transmitting the third initial signal. This not only effectively reduces the resistance of the third initial signal line and the voltage drop of the third initial signal, but also effectively improves the uniformity of the third initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0206] Figures 14C and 14D are schematic diagrams of the initial signal lines of the mesh structure in Figure 14A. As shown in Figures 14C and 14D, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can be arranged in each unit row, the first initial connection line 44 can be arranged in the Nth unit column and the N+3th unit column, the second initial connection line 45 can be arranged in the N+1th unit column, and the third initial connection line 46 can be arranged in the N+2th unit column. The initial connection lines in each unit column are composed of a first initial connection electrode 33 and a second initial connection electrode 56 that are interconnected. The first initial connection electrode 33 and the second initial connection electrode 56 are arranged in different conductive layers and are interconnected through vias.

[0207] In an exemplary embodiment, the first initial connection line 44 located in the Nth unit column and the N+3th unit column is connected to the first initial signal line 41 in multiple circuit units through the fifteenth via V15 in multiple circuit units, forming a mesh structure for transmitting the first initial signal in the display area.

[0208] In an exemplary embodiment, the second initial connection line 45 located in the N+1th unit column is connected to the second initial signal line 42 in multiple circuit units through the sixteenth via V16 in multiple circuit units, forming a mesh structure for transmitting the second initial signal in the display area.

[0209] In an exemplary embodiment, the third initial connection line 46 located in the N+2th unit column is connected to the third initial signal line 43 in multiple circuit units through the seventeenth via V17 in multiple circuit units, forming a mesh structure for transmitting the third initial signal in the display area.

[0210] In an exemplary embodiment, the first initial connection line 44, the second initial connection line 45 and the third initial connection line 46 can be periodically arranged in multiple unit columns, with the second initial connection line 45 and the third initial connection line 46 arranged between two adjacent first initial connection lines 44, the first initial connection line 44 and the third initial connection line 46 arranged between two adjacent second initial connection lines 45, and the first initial connection line 44 and the second initial connection line 45 arranged between two adjacent third initial connection lines 46.

[0211] In an exemplary embodiment, the first initial connection lines 44, the second initial connection lines 45, and the third initial connection lines 46 may be arranged in a plurality of cell columns in various ways. For example, two first initial connection lines 44 may be arranged in two adjacent cell columns, two second initial connection lines 45 may be arranged in two other adjacent cell columns, and two third initial connection lines 46 may be arranged in yet another two adjacent cell columns. This is not a limitation of the present disclosure.

[0212] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 15 .

[0213] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0214] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the fourth connecting electrode 54 through the via hole.

[0215] In an exemplary embodiment, two circuit units adjacent to each other in some first directions X may share the same 21st via hole V21. For example, two circuit units in the N-1th and Nth unit columns may share the same 21st via hole V21. For another example, two circuit units in the N+1th and N+2th unit columns may share the same 21st via hole V21. For another example, two circuit units in the N+3th and N+4th unit columns may share the same 21st via hole V21.

[0216] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect the subsequently formed twelfth connecting electrode to the third connecting electrode 53 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the fifth connecting electrode 55, and the twenty-third via hole V23 is configured to connect the subsequently formed thirteenth connecting electrode to the fifth connecting electrode 55 through the via hole.

[0218] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG16A and FIG16B , where FIG16B is a planar schematic diagram of the fifth conductive layer in FIG16A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0219] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least an eleventh connecting electrode 61 , a twelfth connecting electrode 62 , and a thirteenth connecting electrode 63 .

[0220] In an exemplary embodiment, the eleventh connection electrode 61 may be in a strip shape extending along the first direction X. The eleventh connection electrode 61 is connected to the fourth connection electrode 54 through the twenty-first via hole V21 and is configured to be connected to a first power line formed subsequently.

[0221] In an exemplary embodiment, the eleventh connection electrodes 61 of two circuit cells adjacent to each other in the first direction X may be interconnected as an integral structure. For example, the eleventh connection electrodes 61 of the two circuit cells in the N-1th and Nth cell columns may be interconnected as an integral structure. For another example, the eleventh connection electrodes 61 of the two circuit cells in the N+1th and N+2th cell columns may be interconnected as an integral structure. For another example, the eleventh connection electrodes 61 of the two circuit cells in the N+3th and N+4th cell columns may be interconnected as an integral structure.

[0222] In an exemplary embodiment, the twelfth connection electrode 62 may be in a block shape (eg, rectangular), connected to the third connection electrode 53 through the 22nd via hole V22 , and configured to be connected to a subsequently formed data signal line.

[0223] In an exemplary embodiment, the thirteenth connection electrode 63 may be in a block shape (eg, rectangular), connected to the fifth connection electrode 55 through the twenty-third via hole V23 , and configured to be connected to a subsequently formed anode connection electrode.

[0224] (10) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate having the aforementioned pattern formed thereon, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 17 .

[0225] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a thirty-first via V31 , a thirty-second via V32 , and a thirty-third via V33 .

[0226] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the eleventh connecting electrode 61 on the substrate, the second flat layer in the thirty-first via hole V31 is etched away to expose the surface of the eleventh connecting electrode 61, and the thirty-first via hole V31 is configured to connect a subsequently formed first power line to the eleventh connecting electrode 61 through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 62 on the substrate, the second flat layer in the thirty-second via hole V32 is etched away to expose the surface of the twelfth connecting electrode 62, and the thirty-second via hole V32 is configured to connect a subsequently formed data signal line to the twelfth connecting electrode 62 through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the thirteenth connecting electrode 63 on the substrate, the second flat layer in the thirty-third via hole V33 is etched away to expose the surface of the thirteenth connecting electrode 63, and the thirty-third via hole V33 is configured to connect the subsequently formed anode connecting electrode to the thirteenth connecting electrode 63 through the via hole.

[0229] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a sixth conductive layer disposed on the second flat layer, as shown in FIG. 18A and FIG. 18B , where FIG. 18B is a plan view schematic diagram of the sixth conductive layer in FIG. 18A . In an exemplary embodiment, the sixth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0230] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .

[0231] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 71 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31. Since the eleventh connection electrode 61 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first electrode of the fifth transistor T5 and the second plate 82 of the storage capacitor, the first power line 71 can write the first power signal to the fifth transistor T5 and the second plate 82 of the storage capacitor.

[0232] In an exemplary embodiment, the first power line 71 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0233] In an exemplary embodiment, the first power lines 71 of two circuit units adjacent to each other in the first direction X may be interconnected as an integral structure. For example, the first power lines 71 of the two circuit units in the N-1th and Nth unit columns may be interconnected as an integral structure. For another example, the first power lines 71 of the two circuit units in the N+1th and N+2th unit columns may be interconnected as an integral structure. For another example, the first power lines 71 of the two circuit units in the N+3th and N+4th unit columns may be interconnected as an integral structure.

[0234] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. The first power line 71 with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.

[0235] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate includes the orthographic projection of the first connection electrode 51 on the substrate, that is, the first power line 71 completely covers the first connection electrode 51 .

[0236] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps the orthographic projection of the second active layer on the substrate. In this exemplary embodiment, the first power line 71 can block the light emitted by the light-emitting device and the light reflected by the film from reaching the second oxide transistor, thereby preventing the characteristics of the second oxide transistor from drifting due to light exposure and improving the electrical characteristics of the second oxide transistor.

[0237] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate, which can effectively reduce the parasitic capacitance of the second node N2.

[0238] In an exemplary embodiment, a shielding electrode 74 is provided on the first power line 71. The shielding electrode 74 may be in the shape of a strip extending along the second direction Y. The first end of the shielding electrode 74 is connected to the first power line 71, and the second end of the shielding electrode 74 extends toward the direction of the anode connection electrode 73 in this circuit unit.

[0239] In an exemplary embodiment, the shielding electrode 74 may be disposed in the middle of the first power line 71 of the integral structure, and the first power line 71 of the integral structure may be substantially mirror-symmetrical with respect to the shielding electrode 74 .

[0240] In an exemplary embodiment, an orthographic projection of the shielding electrode 74 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate, so as to effectively reduce the parasitic capacitance of the second node N2 .

[0241] In an exemplary embodiment, a portion of the shielding electrode 74 may be disposed between adjacent second connection electrodes 52 in the first direction X. The shielding electrode 74, having a constant potential, can effectively reduce the mutual influence of the second nodes N2 in adjacent circuit units, thereby improving the driving performance of the pixel driving circuit. For example, the shielding electrode 74 may be disposed between the second connection electrode 52 of the circuit unit in the Nth unit column and the second connection electrode 52 of the circuit unit in the N+1th unit column. For another example, the shielding electrode 74 may be disposed between the second connection electrode 52 of the circuit unit in the N+2th unit column and the second connection electrode 52 of the circuit unit in the N+3th unit column.

[0242] In an exemplary embodiment, the shield electrode 74 is also configured to improve the planarity of the anode.

[0243] In an exemplary embodiment, a first power block 71-1 and a second power block 71-2 may also be provided on the first power line 71. The first power block 71-1 and the second power block 71-2 may be block-shaped (e.g., trapezoidal) and may be provided on a side of the first power line 71 close to the shielding electrode 74, respectively corresponding to the two ends of the shielding electrode 74. In an exemplary embodiment, the first power block 71-1 and the second power block 71-2 are configured to improve the flatness of the anode.

[0244] The first power line 71 , the first power block 71 - 1 , the second power block 71 - 2 , and the shielding electrode 74 may be an integrated structure connected to each other.

[0245] In an exemplary embodiment, the data signal line 72 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 72 is connected to the twelfth connection electrode 62 through the thirty-second via hole V32. Since the twelfth connection electrode 62 is connected to the third connection electrode 53, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 is connected to the first electrode of the fourth transistor T4. The data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.

[0246] In an exemplary embodiment, the anode connection electrode 73 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 73 is connected to the thirteenth connection electrode 63 via a thirty-third via hole V33. The anode connection electrode 73 is configured to be connected to a subsequently formed anode. Since the anode connection electrode 73 is connected to the fifth connection electrode 55, and the fifth connection electrode 55 is connected to the second region of the sixth active layer and the second region of the seventh active layer via a via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0247] (12) Forming a third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate having the aforementioned pattern formed thereon, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of vias are provided on the third planar layer, as shown in FIG. 19 .

[0248] In an exemplary embodiment, the via holes in each circuit unit include at least a forty-first via hole V41 .

[0249] In an exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the third flat layer in the forty-first via hole V41 is removed to expose the surface of the anode connecting electrode 73, and the forty-first via hole V41 is configured to connect a subsequently formed anode to the anode connecting electrode 73 through the via hole.

[0250] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting control line, a first initial signal line, a second initial signal line, a third initial signal line, a data signal line, and a first power line connected to the pixel driving circuit. In a direction perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer, which are sequentially arranged on the substrate. The first semiconductor layer may include at least the active layers of the third to eighth transistors, the first conductive layer may include at least the second scan signal line, the fourth scan signal line and the first plate of the storage capacitor, the second conductive layer may include at least the second plate of the storage capacitor, the second semiconductor layer may include at least the active layers of the first transistor and the second transistor, the third conductive layer may include at least the first scan signal line and the third scan signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, the fifth conductive layer may include at least a plurality of connecting electrodes, and the sixth conductive layer may include at least a data signal line, a first power line and an anode connecting electrode.

[0251] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0252] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first insulating layer can be called a buffer layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be called a gate insulating (GI) layer, the sixth insulating layer can be called an interlayer insulating (ILD) layer, and the seventh insulating layer can be called a passivation (PVX) layer. The first planar layer, the second planar layer and the third planar layer can be made of organic materials, such as resin.

[0253] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a column centerline. For example, the pixel driving circuit in the Nth column and the pixel driving circuit in the N+1th column may be mirror-symmetrical with respect to the column centerline. For another example, the pixel driving circuit in the N+1th column and the pixel driving circuit in the N+2th column may be mirror-symmetrical with respect to the column centerline.

[0254] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0255] (13) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the third flat layer. The anode conductive layer may include at least a plurality of anode patterns, as shown in FIG20A and FIG20B , where FIG20B is a planar schematic diagram of the anode conductive layer in FIG20A .

[0256] In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A for a red light-emitting device, a second anode 90B for a blue light-emitting device, a third anode 90C for a first green light-emitting device, and a fourth anode 90D for a second green light-emitting device. The first anode 90A may be located at a red sub-pixel emitting red light, the second anode 90B may be located at a blue sub-pixel emitting blue light, the third anode 90C may be located at a first green sub-pixel emitting green light, and the fourth anode 90D may be located at a second green sub-pixel emitting green light.

[0257] In an exemplary embodiment, the first anode 90A and the second anode 90B may be sequentially arranged along the first direction X, the third anode 90C and the fourth anode 90D may be sequentially arranged along the first direction X, and the third anode 90C and the fourth anode 90D may be respectively arranged on one side of the first anode 90A and the second anode 90B in the second direction Y. Alternatively, the first anode 90A and the second anode 90B may be sequentially arranged along the second direction Y, the third anode 90C and the fourth anode 90D may be sequentially arranged along the second direction Y, and the third anode 90C and the fourth anode 90D may be arranged on one side of the first anode 90A and the second anode 90B in the first direction X.

[0258] In an exemplary embodiment, the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D can be respectively connected to the anode connection electrode 73 of the corresponding circuit unit through the forty-first via V41, and the anode shape and area of ​​the four sub-pixels in a pixel unit can be the same, or can be different.

[0259] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting portion that are connected to each other. The shape of the anode main body may be circular or elliptical, and the shape of the anode connecting portion may be a bar. The anode connecting portion is connected to the anode connecting electrode 73 through the forty-first via V41, thereby enabling the connection between the anode and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0260] In an exemplary embodiment, the anode body portion and the anode connection portion of at least one anode may be an integral structure connected to each other.

[0261] In an exemplary embodiment, the anode body portion of at least one anode may have a first anode centerline OX and a second anode centerline OY. The first anode centerline OX may be a straight line that bisects the anode body portion of the anode in the second direction Y and extends along the first direction X. The second anode centerline OY may be a straight line that bisects the anode body portion of the anode in the first direction X and extends along the second direction Y. For example, the third anode 90C and the fourth anode 90D may each have a first anode centerline OX and a second anode centerline OY.

[0262] In an exemplary embodiment, the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of two first power lines 71 in two adjacent circuit units in the first direction X on the substrate, and the two first power lines 71 can be mirror-symmetrical relative to the second anode center line OY of the anode.

[0263] In an exemplary embodiment, the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of at least one first power line 71 on the substrate. For example, the orthographic projection of the anode body of the third anode 90C on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of one first power line 71 on the substrate. For another example, the orthographic projection of the anode body of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of another first power line 71 on the substrate.

[0264] In an exemplary embodiment, the positions and shapes of the first power block 71-1 and the second power block 71-2 of at least one first power line 71 may be substantially mirror-symmetrical with respect to the first anode centerline OX of at least one anode. For example, the positions and shapes of the first power block 71-1 and the second power block 71-2 of one first power line 71 may be substantially mirror-symmetrical with respect to the first anode centerline OX of the third anode 90C. For another example, the positions and shapes of the first power block 71-1 and the second power block 71-2 of another first power line 71 may be substantially mirror-symmetrical with respect to the first anode centerline OX of the fourth anode 90D.

[0265] In an exemplary embodiment, in at least one first power line 71, the orthographic projection of the first power block 71-1 on the substrate and the orthographic projection of the anode main body on the substrate have a first overlapping region, and the orthographic projection of the second power block 71-2 on the substrate and the orthographic projection of the anode main body on the substrate have a second overlapping region. The position and shape of the first overlapping region and the position and shape of the second overlapping region can be substantially mirror-symmetrical with respect to the first anode centerline OX of the anode. For example, the position and shape of the first overlapping region and the position and shape of the second overlapping region can be substantially mirror-symmetrical with respect to the first anode centerline OX of the third anode 90C. For another example, the position and shape of the first overlapping region and the position and shape of the second overlapping region can be substantially mirror-symmetrical with respect to the first anode centerline OX of the fourth anode 90D.

[0266] In an exemplary embodiment, in the two first power lines 71 in the two adjacent circuit units in the first direction X, the orthographic projection of the first power block 71-1 in one first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a first overlapping area, and the orthographic projection of the first power block 71-1 in the other first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a third overlapping area, and the position and shape of the first overlapping area and the position and shape of the third overlapping area can be basically mirror-symmetrical relative to the second anode center line OY of the anode.

[0267] In an exemplary embodiment, in the two first power lines 71 in the two adjacent circuit units in the first direction X, the orthographic projection of the second power block 71-2 in one first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a second overlapping area, and the orthographic projection of the second power block 71-2 in the other first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a fourth overlapping area, and the position and shape of the second overlapping area and the position and shape of the fourth overlapping area can be basically mirror-symmetrical relative to the second anode center line OY of the anode.

[0268] In an exemplary embodiment, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of at least one anode on the substrate. For example, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of the third anode 90C on the substrate. For another example, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of the fourth anode 90D on the substrate.

[0269] In an exemplary embodiment, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode centerline OY of the at least one anode on the substrate. For example, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode centerline OY of the third anode 90C on the substrate. For another example, the orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode centerline OY of the fourth anode 90D on the substrate.

[0270] In an exemplary embodiment, an orthographic projection of the anode connection portion of the at least one anode on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.

[0271] In an exemplary embodiment, the anode connection portion of at least one anode may include a first connection sub-portion 90 - 1 and a second connection sub-portion 90 - 2 configured to avoid overlapping with the second connection electrode 52 .

[0272] In an exemplary embodiment, the anode connecting portion of the first anode 90A and the second anode 90B may include at least a first connecting sub-portion 90-1 and a second connecting sub-portion 90-2, wherein the first end of the first connecting sub-portion 90-1 is connected to the anode main body, the second end of the first connecting sub-portion 90-1 extends along the first direction X toward a direction away from the anode main body, and is then connected to the first end of the second connecting sub-portion 90-2, and the second end of the second connecting sub-portion 90-2 extends along the second direction Y toward a direction away from the first connecting sub-portion 90-1, so that the anode connecting portions of the first anode 90A and the second anode 90B avoid the area where the second connecting electrode 52 is located.

[0273] In an exemplary embodiment, the orthographic projection of the first connecting sub-portion 90-1 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and the orthographic projection of the second connecting sub-portion 90-2 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, so as to effectively reduce the parasitic capacitance of the second node N2.

[0274] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0275] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0276] A display substrate suffers from a problem where a high instantaneous current flows when the luminescent signal line provides an on-signal, affecting the display effect. Research has found that the high instantaneous current is caused by the large parasitic capacitance of the second node N2. Because the third initial signal line in the pixel drive circuit is connected to the second node N2 via the eighth transistor T8, when the parasitic capacitance of the second node N2 is large, it is equivalent to the presence of a large capacitor at the second node N2 that stores the bias voltage (on bias) of the third initial signal line. When the luminescent signal line provides an on-signal (the sixth transistor T6 is turned on), the charge in the parasitic capacitance of the second node N2 is preferentially released, resulting in a high instantaneous current.

[0277] The exemplary embodiments of the present disclosure provide a display substrate that effectively reduces the parasitic capacitance of the second node N2 by 9.35f through layout adjustment and structural optimization, effectively avoiding the problem of instantaneous high current and greatly reducing the transient current when the sixth transistor T6 is turned on, thereby improving display quality and display effect.

[0278] The present disclosure sets the second connection electrode and the fourth scan signal line to have no overlap, thereby reducing not only the parasitic capacitance of the second node N2 but also the influence on the data signal writing process.

[0279] The present disclosure sets the first scan signal line and the first shielding line to have unequal widths, and the second connecting electrode overlaps with the first scan signal line and the first shielding line of smaller width, thereby effectively reducing the parasitic capacitance between the second node N2 and the first scan signal line and the first shielding line.

[0280] The present disclosure can minimize the parasitic capacitance of the second node N2 by ensuring that the first power line does not overlap with the second connection electrode, the shielding electrode does not overlap with the second connection electrode, and the anode connection portion does not overlap with the second connection electrode.

[0281] In the present disclosure, a shielding electrode is arranged between adjacent second connection electrodes. The shielding electrode with a constant potential can effectively prevent the mutual influence of the second nodes N2 in adjacent circuit units, thereby improving the driving performance of the pixel driving circuit.

[0282] The present disclosure increases the parasitic capacitance between the first scanning signal line and the first node N1 by setting the first connecting electrode to overlap with the first scanning signal line, and uses the falling edge of the first scanning signal line to lower the potential of the first node N1, thereby increasing the current and effectively improving the display brightness.

[0283] By arranging the first power line to overlap with the first connection electrode, the present disclosure effectively prevents data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit. By arranging the first power line to overlap with the active layer of the second transistor, the present disclosure prevents the characteristics of the oxide second transistor from drifting due to light, thereby improving the electrical characteristics of the oxide second transistor.

[0284] The present invention arranges the shielding electrode to overlap with the second anode center line of the anode, and arranges the first power line, the first power block and the second power block to be mirror-symmetrical relative to the second anode center line, and the first power block and the second power block 71 to be mirror-symmetrical relative to the first anode center line, thereby effectively improving the flatness of the anode, avoiding anode height differences, and ensuring that the luminous performance of the light-emitting devices in various areas is basically the same, which not only avoids large viewing angle color deviation, but also avoids defects such as off-screen watermarks, thereby improving the quality of the display substrate.

[0285] The present disclosure forms a mesh-like connection structure by arranging a first initial signal line extending along a first direction in the main body and a first initial connection line extending along a second direction in the main body, by arranging a second initial signal line extending along the first direction in the main body and a second initial connection line extending along the second direction in the main body, and by arranging a third initial signal line extending along the first direction in the main body and a second initial connection line extending along a third direction in the main body, so that the first initial signal line, the second initial signal line and the third initial signal line respectively form a mesh-like connection structure, which not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0286] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0287] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0288] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0289] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0290] A driving circuit layer is formed on a substrate, wherein the driving circuit layer includes a plurality of circuit units, at least one of which includes at least a pixel driving circuit and a first power line, wherein the first power line is configured to provide a first power line signal to the pixel driving circuit; at least one of the circuit units further includes a shielding electrode, wherein the shielding electrode is connected to the first power line;

[0291] A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit; the positive projection of at least one shielding electrode on the substrate at least partially overlaps with the positive projection of a second anode center line of at least one anode on the substrate, the second anode center line is a straight line that bisects the anode main body in a first direction and extends along a second direction, and the first direction and the second direction intersect.

[0292] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0293] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate; the driving circuit layer comprises a plurality of circuit units, at least one circuit unit comprises at least a pixel driving circuit and a first power line, the first power line being configured to provide a first power line signal to the pixel driving circuit; the light-emitting structure layer comprises a plurality of light-emitting units, at least one light-emitting unit comprises at least an anode, the anode comprising an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit; at least one circuit unit further comprises a shielding electrode, the shielding electrode is connected to the first power line, the orthographic projection of at least one shielding electrode on the substrate at least partially overlaps with the orthographic projection of a second anode center line of at least one anode on the substrate, the second anode center line being a straight line that bisects the anode main body in a first direction and extends along a second direction, the first direction and the second direction intersecting.

2. The display substrate according to claim 1, wherein The orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projections of two first power lines in two adjacent circuit units in the first direction on the substrate, and the two first power lines are mirror-symmetrical with respect to the second anode center line.

3. The display substrate according to claim 1, wherein A first power block and a second power block are provided on at least one first power line, the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projections of the first power block and the second power block on the substrate, the first power block and the second power block are mirror-symmetrical with respect to the first anode center line, and the first anode center line is a straight line that bisects the anode body in the second direction Y and extends along the first direction.

4. The display substrate according to claim 3, wherein: The orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of two first power blocks in two circuit units adjacent in the first direction on the substrate, and the two first power blocks are mirror-symmetrical with respect to the center line of the second anode; the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of two second power blocks in two circuit units adjacent in the first direction on the substrate, and the two second power blocks are mirror-symmetrical with respect to the center line of the second anode.

5. The display substrate according to claim 1, wherein The pixel driving circuit includes at least a second transistor serving as a compensation transistor and a third transistor serving as a driving transistor, wherein a gate electrode of the second transistor is connected to a first scanning signal line, a first electrode of the second transistor is connected to a second electrode of the third transistor via a second node electrode, and a second electrode of the second transistor is connected to a gate electrode of the third transistor via a first node electrode; and an orthographic projection of the anode connection portion on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate. The display substrate according to claim 5 , wherein: An orthographic projection of the first power line on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.

7. The display substrate according to claim 5, wherein: The shielding electrode is disposed between the second node electrodes of two adjacent circuit units in the first direction.

8. The display substrate according to claim 5, wherein: An orthographic projection of the shielding electrode on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.

9. The display substrate according to claim 5, wherein: The pixel driving circuit also includes a fourth transistor serving as a data writing transistor, a gate electrode of the fourth transistor being connected to a fourth scanning signal line, a first electrode of the fourth transistor being connected to a data signal line, a second electrode of the fourth transistor being connected to a first electrode of the third transistor, and an orthographic projection of the second node electrode on the substrate and an orthographic projection of the fourth scanning signal line on the substrate not overlapping.

10. The display substrate according to claim 5, wherein: The first scanning signal line at least includes a first sub-scanning line segment and a second sub-scanning line segment connected to each other, the width of the first sub-scanning line segment is greater than the width of the second sub-scanning line segment, and the width is the size in the second direction; The orthographic projection of the second node electrode on the substrate does not overlap with the orthographic projection of the first sub-scan line segment on the substrate, and the orthographic projection of the second node electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-scan line segment on the substrate.

11. The display substrate according to claim 5, wherein: At least one circuit unit also includes a first shielding line, the first shielding line includes at least a first sub-shielding line segment and a second sub-shielding line segment connected to each other, the width of the first sub-shielding line segment is greater than the width of the second sub-shielding line segment, and the width is the dimension in the second direction; the orthographic projection of the second node electrode on the substrate does not overlap with the orthographic projection of the first sub-shielding line segment on the substrate, and the orthographic projection of the second node electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning line segment on the substrate.

12. The display substrate according to claim 5, wherein: An orthographic projection of the first node electrode on the substrate at least partially overlaps with an orthographic projection of the first scan signal line on the substrate.

13. The display substrate according to claim 12, wherein: The first end of the first node electrode is connected to the second electrode of the second transistor, and the second end of the first node electrode is connected to the gate electrode of the third transistor; the first end of the first node electrode is connected to a first compensation block, and the orthographic projection of the first compensation block on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the substrate.

14. The display substrate according to claim 5, wherein: An orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the first node electrode on the substrate.

15. The display substrate according to claim 5, wherein: An orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the active layer of the second transistor on the substrate.

16. The display substrate according to any one of claims 1 to 15, wherein: At least one circuit unit also includes a first initial signal line extending along the first direction and a first initial connection line extending along the second direction, the first initial signal line is configured to provide a first initial signal to the pixel driving circuit, and the first initial signal connection line is connected to the first initial signal line to form a mesh connection structure for transmitting the first initial signal, and / or, at least one circuit unit also includes a second initial signal line extending along the first direction and a second initial connection line extending along the second direction, the second initial signal line is configured to provide a second initial signal to the pixel driving circuit, and the second initial signal connection line is connected to the second initial signal line to form a mesh connection structure for transmitting the second initial signal, and / or, at least one circuit unit also includes a third initial signal line extending along the first direction and a third initial connection line extending along the second direction, the third initial signal line is configured to provide a third initial signal to the pixel driving circuit, and the third initial signal connection line is connected to the third initial signal line to form a mesh connection structure for transmitting the third initial signal.

17. The display substrate according to claim 16, wherein: At least one of the first initial connection line, the second initial connection line and the third initial connection line includes a first initial connection electrode and a second initial connection electrode connected to each other; in a direction perpendicular to the substrate, the driving circuit layer includes multiple conductive layers, and the first initial connection electrode and the second initial connection electrode are arranged in different conductive layers.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for preparing a display substrate, comprising: forming a driving circuit layer on a substrate, wherein the driving circuit layer includes a plurality of circuit units, at least one of which includes at least a pixel driving circuit and a first power line, wherein the first power line is configured to provide a first power line signal to the pixel driving circuit; At least one circuit unit further includes a shielding electrode, wherein the shielding electrode is connected to the first power line; forming a light-emitting structure layer on the driving circuit layer, wherein the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main portion and an anode connecting portion, one end of the anode connecting portion is connected to the anode main portion, and the other end of the anode connecting portion is connected to the pixel driving circuit; The orthographic projection of at least one shield electrode on the substrate at least partially overlaps with the orthographic projection of a second anode center line of at least one anode on the substrate, wherein the second anode center line is a straight line that bisects the anode body in a first direction and extends along a second direction, and the first direction and the second direction intersect.

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