Multi-layer substrate, electronic device including same, and method for manufacturing multi-layer substrate

Abstract

Provided are: a multi-layer substrate in which in case that a via is formed through a multi-layer substrate, a sub-via is formed to partially overlap a main via to mitigate the level of undercut inside a via; a method for manufacturing a multi-layer substrate; and an electronic device including a multi-layer substrate. The multi-layer substrate includes: a base substrate; a first circuit wire layer and a first via pad formed on the base substrate; an interlayer insulation layer for covering the first circuit wire layer and the first via pad; a via part which penetrates the interlayer insulation layer and is formed to be in contact with the first via pad; a plating part for filling the via part; a second circuit wire layer formed on the interlayer insulation layer; and a second via pad formed on the plating part, wherein the via part includes a main via and a sub-via partially overlapping the main via.

Description

Multilayer substrate and electronic device including the same, and method for manufacturing the multilayer substrate

[0001] The present invention relates to a multilayer substrate applicable to a flexible circuit board or coil substrate, a method for manufacturing a multilayer substrate, and an electronic device including a multilayer substrate.

[0002] Vias can be formed in a multilayer substrate according to the following sequence. First, a single-layer circuit pattern and a lower via pad are formed on a base substrate, and an interlayer insulating layer is applied thereon. Then, the interlayer insulating layer applied on the lower via pad is laser processed to form a via hole. Then, carbides generated during the laser processing are removed through a desmear process or an etching process. Then, in order to fill the undercut structure generated when a portion of the upper surface of the lower via pad that was in contact with the inner side of the interlayer insulating layer is etched, a Ni / Cr (nickel / chromium) underlayer is formed on the upper side and inner side of the interlayer insulating layer and the upper surface of the lower via pad. Then, a resist pattern for forming a two-layer circuit pattern is formed on the interlayer insulating layer. Thereafter, the gaps between the resist patterns and the inside of the via hole are plated.

[0003] However, when a via is formed in the above order, a Ni / Cr underlayer may be formed on a lower via pad containing Cu (copper), a via hole may be filled to contain Cu again on the Ni / Cr underlayer, and an upper via pad may be formed on top of it. Therefore, a dissimilar metal layer of Cu and Ni / Cr may be formed inside the via hole, which may weaken the bonding strength between the metals and lower the reliability of the via interface.

[0004] Meanwhile, to form a homogeneous metal layer composed solely of Cu inside a via hole, the thickness at which the undercut structure is formed can be expanded by strengthening the desmear or etching level. However, if a via is formed using this method, it becomes difficult to apply current to the lower or inner side of the undercut structure during the plating process, which may result in the generation of a void region where Cu is not filled, such as inside the via hole. This may act as a factor in the interface separation of the via, ultimately reducing the reliability of the via interface.

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a multilayer substrate, which forms a sub-via so as to partially overlap with a main via when forming a via in a multilayer substrate, thereby alleviating the level of undercut inside the via, and a multilayer substrate manufactured according to the method and an electronic device including the same.

[0006] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0007] One aspect of a multilayer substrate of the present invention for achieving the above technical task includes: a base substrate; a first circuit wiring layer and a first via pad formed on the base substrate; an interlayer insulating layer covering the first circuit wiring layer and the first via pad; a via portion formed to penetrate the interlayer insulating layer and contact the first via pad; a plating portion filling the via portion; a second circuit wiring layer formed on the interlayer insulating layer; and a second via pad formed on the plating portion, wherein the via portion includes a main via and a sub-via partially overlapping the main via.

[0008] One aspect of the electronic device of the present invention for achieving the above technical task includes the multilayer substrate.

[0009] One aspect of a method for manufacturing a multilayer substrate of the present invention for achieving the above technical task includes the steps of forming a first circuit wiring layer and a first via pad on a base substrate; forming an interlayer insulating layer to cover the first circuit wiring layer and the first via pad; forming a main via to penetrate a surface of the interlayer insulating layer and contact the first via pad; forming a sub-via partially overlapping the main via; performing an etching process or a desmear process including the main via and the sub-via; forming a base layer covering the interlayer insulating layer, the main via, and the sub-via; and forming a plating portion in the main via, and forming a second circuit wiring layer and a second via pad on the interlayer insulating layer and the plating portion.

[0010] Specific details of other embodiments are included in the detailed description and drawings.

[0011] The present invention can obtain the following effects by forming a sub-via to partially overlap with a main via and thereby alleviating the level of undercut inside the via.

[0012] First, a stable conductive state can be maintained between the via wall and the inner pad, and during electroplating, current can be applied simultaneously to the via wall and the inner pad to deposit copper. Accordingly, the present invention can suppress the possibility of void generation.

[0013] Second, after via processing, the spacing between the via, the via pad, and the insulating layer can be controlled. Accordingly, the present invention can ensure interface reliability between the via and the via pad.

[0014] Third, to prevent degradation of via interface reliability, a homogeneous metal layer may be formed within the via hole. The present invention can improve the bonding strength between homogeneous metals.

[0015] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0016] FIG. 1 is a flowchart illustrating a method for manufacturing a multilayer substrate according to one embodiment of the present invention.

[0017] FIG. 2 is an exemplary diagram illustrating step S110 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0018] FIG. 3 is an exemplary diagram illustrating step S120 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0019] FIG. 4 is an exemplary diagram illustrating step S130 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0020] FIG. 5 is an exemplary diagram illustrating step S140 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0021] FIG. 6 is a first exemplary diagram for explaining step S150 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0022] FIG. 7 is a second exemplary diagram for explaining step S150 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0023] FIG. 8 is a third exemplary diagram for explaining step S150 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0024] FIG. 9 is a fourth exemplary diagram for explaining step S150 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0025] FIG. 10 is an exemplary diagram illustrating step S160 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0026] FIG. 11 is an exemplary diagram illustrating step S180 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0027] FIG. 12 is a first exemplary diagram for explaining step S190 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0028] FIG. 13 is a second exemplary diagram for explaining step S190 of a multilayer substrate manufacturing method according to one embodiment of the present invention.

[0029] Figure 14 is a flowchart illustrating a method for manufacturing a multilayer substrate according to another embodiment of the present invention.

[0030] FIG. 15 is an exemplary diagram illustrating step S430 of a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0031] FIG. 16 is a first exemplary diagram for explaining step S440 of a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0032] FIG. 17 is a second exemplary diagram for explaining step S440 of a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0033] FIG. 18 is a third exemplary diagram for explaining step S440 of a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0034] FIG. 19 is a fourth exemplary diagram for explaining step S440 of a multilayer substrate manufacturing method according to another embodiment of the present invention.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are designated by the same reference numerals, and redundant descriptions thereof will be omitted.

[0036] The multilayer substrate of the present invention forms a sub-via so as to partially overlap with a main via, thereby reducing the level of undercut inside the via, thereby suppressing the possibility of void generation, improving the bonding strength between similar metals, and enhancing the reliability of the via interface. A method for manufacturing a multilayer substrate is described below.

[0037] FIG. 1 is a flowchart illustrating a method for manufacturing a multilayer substrate according to one embodiment of the present invention.

[0038] First, a first circuit wiring layer and a first via pad are formed on one surface of the base substrate (S110).

[0039] FIG. 2 is an exemplary diagram illustrating step S110 of a method for manufacturing a multilayer substrate according to an embodiment of the present invention. The first direction (D1) and the second direction (D2) form a plane in a horizontal direction. For example, the first direction (D1) may be a front-back direction, and the second direction (D2) may be a left-right direction. Alternatively, the first direction (D1) may be a left-right direction, and the second direction (D2) may be a front-back direction. The third direction (D3) is a height direction, and is a direction perpendicular to the plane formed by the first direction (D1) and the second direction (D2). The third direction (D3) may be an up-down direction.

[0040] Referring to FIG. 2, the first circuit wiring layer (220) may be formed on the wiring area (CL) of the base substrate (210), and the first via pad (230) may be formed on the pad area (PL) of the base substrate (210). The first circuit wiring layer (220) and the first via pad (230) may be formed simultaneously, but are not limited thereto, and may be formed at different times. In addition, the first circuit wiring layer (220) and the first via pad (230) may be formed of the same metal, but may also be formed of different metals.

[0041] The first circuit wiring layer (220) may be formed in linear wiring shapes on a base substrate (210) composed of an insulating material. Alternatively, the first circuit wiring layer (220) may be formed in a coil shape that is spirally wound on the base substrate (210). In the former case, the multilayer substrate of the present invention may be provided as a flexible circuit substrate. In the latter case, the multilayer substrate of the present invention may be provided as a coil substrate.

[0042] The first circuit wiring layer (220) may be formed using a photolithography method. However, the present invention is not limited thereto, and the first circuit wiring layer (220) may also be formed using various methods such as printing, bonding, coating, and plating. The first circuit wiring layer (220) may be formed to have a thickness of 5 μm to 200 μm. Preferably, the first circuit wiring layer (220) may be formed to have a thickness of 30 μm to 100 μm. More preferably, the first circuit wiring layer (220) may be formed to have a thickness of 40 μm to 80 μm.

[0043] This is explained again with reference to Figure 1.

[0044] After forming a first circuit wiring layer (220) and a first via pad (230) on a base substrate (210), an interlayer insulating layer is formed to cover the first circuit wiring layer (220) and the first via pad (230) (S120). The interlayer insulating layer (240) can be formed in various ways, such as lamination or hot press.

[0045] FIG. 3 is an exemplary diagram illustrating step S120 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. Referring to FIG. 3, the interlayer insulating layer (240) may be formed to cover all of the upper surface and side surfaces of the first circuit wiring layer (220), the upper surface and side surfaces of the first via pad (230), and the portion of the base substrate (210) where the first circuit wiring layer (220) and the first via pad (230) are not formed. However, the present invention is not limited thereto, and the interlayer insulating layer (240) may also be formed to selectively cover a portion as needed. For example, the interlayer insulating layer (240) may be formed to cover only the first circuit wiring layer (220) and the first via pad (230).

[0046] This is explained again with reference to Figure 1.

[0047] After forming an interlayer insulating layer (240) on the base material (210), a main via is formed by processing the interlayer insulating layer (240) (S130).

[0048] FIG. 4 is an exemplary diagram illustrating step S130 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. Referring to FIG. 4, a main via (250a) may be formed to penetrate from an upper surface of the interlayer insulating layer (240) in the thickness direction (D3) of the interlayer insulating layer (240) and contact a first via pad (230). The main via (250a) may be formed to have a size corresponding to the first via pad (230). For example, the main via (250a) may be formed to have the same size as the first via pad (230). Alternatively, the main via (250a) may be formed to have a smaller size than the first via pad (230).

[0049] The main via (250a) can be formed using a laser drill. In this case, the main via (250a) can be formed using a UV laser. Alternatively, the main via (250a) can be formed using a CO2 laser.

[0050] The lower diameter of the main via (250a) may be formed to have a different width from its upper diameter. Specifically, the lower diameter of the main via (250a) may be formed to have a narrower width than its upper diameter. The width (W2) of the lower diameter may be formed to have a value that is 75% or more and less than 100% of the width (W1) of the upper diameter (0.75 * W1 ≤ W2 < 1 * W1). However, the present invention is not limited thereto, and the width (W2) of the lower diameter may be formed to be 75% or less of the width (W1) of the upper diameter. When the width (W2) of the lower diameter is formed to be 75% or less of the width (W1) of the upper diameter, the width (W2) of the lower diameter may be selected as an appropriate value depending on the size of the upper diameter. Meanwhile, the lower diameter of the main via (250a) may be formed to have the same width as its upper diameter.

[0051] This is explained again with reference to Figure 1.

[0052] After forming a main via (250a) in the interlayer insulating layer (240), a sub-via is formed by processing in the edge area of ​​the main via (250a) (S140).

[0053] FIG. 5 is an exemplary diagram illustrating step S140 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. Referring to FIG. 5 , a sub-via (250b) may be formed such that a portion thereof overlaps a main via (250a). In the following description, the main via (250a) and the sub-via (250b) are collectively defined as a via portion (250).

[0054] The sub-via (250b) may be formed in the same shape as the main via (250a). However, the present invention is not limited thereto, and the sub-via (250b) may also be formed in a different shape from the main via (250a). The planar shapes of the main via (250a) and the sub-via (250b) may be selected from polygons such as triangles and squares, circles, ovals, and lines.

[0055] The thickness (T2) of the sub-via (250b) may be smaller than the thickness (T1) of the main via (250a). Therefore, after the sub-via (250b) is formed by processing, the interlayer insulating layer (240) may remain without being etched underneath. For example, the remaining insulating layer (241) remaining within the via portion (250) may be formed thinly to a level of less than 5 μm.

[0056] The upper diameter of the sub-via (250b) may be formed to have a width that is the same as or different from the upper diameter of the main via (250a). The width (W3) of the upper diameter of the sub-via (250b) may be formed to have a value of 45% to 100% of the width (W1) of the upper diameter of the main via (250a) (0.45 * W1 ≤ W3 ≤ 1.0 * W1).

[0057] If the width (W3) of the upper diameter of the sub-via (250b) is formed to be less than 45% of the width (W1) of the upper diameter of the main via (250a), the area of ​​the residual insulating layer (241) remaining within the via portion (250) may become narrower than an appropriate value. In this case, the residual insulating layer (241) may not be deformed in the upper direction of the first via pad (230) where the undercut is formed during the etching process. Alternatively, even if the residual insulating layer (241) is deformed, it may not be bonded to the upper portion of the first via pad (230) where the undercut is formed.

[0058] If the width (W3) of the upper diameter of the sub-via (250b) is formed to exceed 100% of the width (W1) of the upper diameter of the main via (250a), the area of ​​the residual insulating layer (241) remaining within the via portion (250) may become wider than an appropriate value. In this case, the residual insulating layer (241) remains in a state of strong durability against the etching agent during the etching process step, and may not be deformed in the upper direction of the first via pad (230) where the undercut is formed. In other words, the undercut structure may persist within the via portion (250), and the void problem caused by the undercut structure cannot be resolved.

[0059] The upper area of ​​the residual insulating layer (241) may be formed to be 1% to 30% of the lower area of ​​the main via (250a). Preferably, the upper area of ​​the residual insulating layer (241) may be formed to be 5% to 20% of the lower area of ​​the main via (250a). More preferably, the upper area of ​​the residual insulating layer (241) may be formed to be 9% to 15% of the lower area of ​​the main via (250a).

[0060] If the upper area of ​​the residual insulating layer (241) is less than 1%, the area of ​​the residual insulating layer (241) may be narrower than the appropriate value. In this case, the residual insulating layer (241) may not be deformed in the upper direction of the first via pad (230) where the undercut is formed during the etching process. Alternatively, even if the residual insulating layer (241) is deformed, it may not be bonded to the upper portion of the first via pad (230) where the undercut is formed.

[0061] If the upper area of ​​the residual insulating layer (241) exceeds 30%, the area of ​​the residual insulating layer (241) may become wider than the appropriate value. In this case, the residual insulating layer (241) remains in a state of high durability against the etching agent during the etching process, and may not be deformed in the upper direction of the first via pad (230) where the undercut is formed. In other words, the undercut structure may persist within the via portion (250), and the void problem caused by the undercut structure cannot be resolved.

[0062] This is explained again with reference to Figure 1.

[0063] After sequentially forming a main via (250a) and a sub via (250b) in the interlayer insulating layer (240), an etching process is performed (S150) to clean or modify the surface to form the sublayer to be described in step S160. Alternatively, a desmear process can also be performed.

[0064] The surface of the first via pad (230) exposed to the outside may be etched to a thickness of 1 μm or more and 5 μm or less from the lower portion of the interlayer insulating layer (240) in an etching process or a desmear process. At this time, an undercut may occur in which the etching extends to the interlayer insulating layer (240) adjacent to the lower boundary of the main via (250a).

[0065] In the above, if etching is performed to a depth of less than 1 μm, the distribution of the homogeneous metal region inside the via portion (250) may be insufficient, which may cause an interface reliability problem due to the occurrence of a dissimilar metal layer. In addition, if etching is performed to a depth of more than 5 μm, an undercut structure may additionally occur, making it difficult to bond between the interlayer insulating layer (240) and the first via pad (230). In addition, when performing an etching process, the durability or strength of the remaining insulating layer (241) may be weakened by the etching agent, and as a result, the remaining insulating layer (241) may be deformed into a shape that bonds with the upper portion of the first via pad (230) where the undercut is formed.

[0066] As a result, the vertical cross-section and the horizontal cross-section of the via portion (250) are as shown in FIGS. 6 and 7, respectively. FIG. 6 is a first exemplary diagram for explaining step S150 of the method for manufacturing a multilayer substrate according to an embodiment of the present invention. FIG. 7 is a second exemplary diagram for explaining step S150 of the method for manufacturing a multilayer substrate according to an embodiment of the present invention. Referring to FIGS. 6 and 7, the residual insulating layer (241) is bonded along the profile of the upper edge region of the first via pad (230) where the undercut occurs, so that one end of the residual insulating layer (241) is bonded to the upper portion of the first via pad (230) (A). On the other hand, in the region where the sub-via (250b) is not formed, the lower portion of the residual insulating layer (241) and the upper portion of the first via pad (230) are formed with a distance equal to the undercut thickness (B). That is, the cross-sections on both sides of the via portion (250) can be formed in an asymmetrical structure.

[0067] The example of Fig. 7 is an example in which a single sub-via (250b) is formed around a main via (250a). However, the present invention is not limited thereto, and it is also possible for multiple sub-vias to be formed around a main via (250a).

[0068] A plurality of sub-vias can be formed simultaneously when forming the sub-vias in the edge area of ​​the main via (250a). However, this is not limited to this, and a plurality of sub-vias can also be formed sequentially with a time difference when forming the sub-vias in the edge area of ​​the main via (250a).

[0069] Referring to Fig. 8, a plurality of sub-vias (250ba, 250bb, …, 250bn) may be formed along the periphery of the main via (250a) in a partially overlapping state. However, the present embodiment is not limited thereto. Referring to Fig. 9, a plurality of sub-vias (250ba, 250bb, …, 250bn) may also be formed along the periphery of the main via (250a) in a spaced apart state. Fig. 8 is a third exemplary diagram for explaining step S150 of a method for manufacturing a multilayer substrate according to an embodiment of the present invention. Fig. 9 is a fourth exemplary diagram for explaining step S150 of a method for manufacturing a multilayer substrate according to an embodiment of the present invention.

[0070] This is explained again with reference to Figure 1.

[0071] After the etching process or desmear process is completed, an underlayer (260) is formed on the inner side of the via (250), the upper surface and side surfaces of the interlayer insulating layer (240), etc. (S160). The underlayer (260) can be formed by a dry conductive process such as sputtering or a wet conductive process such as conductive coating. In this embodiment, a case where the underlayer (260) is formed using a sputtering process will be described as an example.

[0072] FIG. 10 is an exemplary diagram illustrating step S160 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. The first via pad (230) and the underlying layer (260) described above may be formed using metal. In the following description, the metal used to form the first via pad (230) is defined as the first metal, and the metal used to form the underlying layer (260) is defined as the second metal.

[0073] The underlayer (260) may be formed at a level of 20 nm to 30 nm. However, in the present invention, the underlayer (260) is not necessarily formed at the above level. The underlayer (260) may be formed in a structure in which some areas are not continuous and are cut off. The underlayer (260) may not be continuous in a portion where an undercut occurs between the interlayer insulating layer (240) and the first via pad (230).

[0074] The second metal used to form the lower layer (260) may include at least one of Ni and Cr. However, the present invention is not limited thereto, and the second metal may be selected from Cu, Ag (silver), Ti (titanium), etc. in addition to Ni and Cr. However, the second metal in the present invention is not necessarily limited thereto.

[0075] The first metal used to form the first via pad (230) may be different from the second metal. For example, the first metal may be Cu, and the second metal may be Ni / Cr. However, the present invention is not limited thereto, and the first metal may be the same as the second metal. For example, the first metal and the second metal may be Cu.

[0076] This is explained again with reference to Figure 1.

[0077] After forming a base layer (260) on the via portion (250), interlayer insulating layer (240), etc., a resist pattern is formed on the upper portion of the interlayer insulating layer (240) (S170). The resist pattern may be formed on the upper portion of the interlayer insulating layer (240) to form a second circuit wiring layer, a second via pad, etc. on the upper portion of the interlayer insulating layer (240).

[0078] After forming a resist pattern on the upper portion of the interlayer insulating layer (240), plating is performed on the gaps between the resist patterns, via portions (250), etc. (S180). By performing the plating, a second circuit wiring layer, a second via pad, etc. can be formed on the upper portion of the interlayer insulating layer (240).

[0079] Fig. 11 is an exemplary diagram for explaining step S180 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. Referring to Fig. 11, the plating portion (270) filled in the via portion (250) by plating has different thicknesses at both ends that come into contact with the inner side of the interlayer insulating layer (240), and may have an asymmetrical structure in which both ends are different from each other based on an imaginary central axis.

[0080] The underlayer (260) is formed along the inner surface where the first via pad (230) and the interlayer insulating layer (240) are in contact, and can serve as an incoming wiring. In the conventional case, since the side surface of the interlayer insulating layer (240) and the first via pad (230) were not in contact due to the undercut, the underlayer (260) had a short-circuited structure. Therefore, the application of current through the underlayer (260) was not performed properly, and as a result, the plating of the second via pad was completed before Cu was completely plated to the inner side of the undercut structure, resulting in the generation of voids and the deterioration of the via interface reliability.

[0081] On the other hand, in the present invention, when an inner region where the side surface of the interlayer insulating layer (240) and the first via pad (230) are joined is generated, the underlayer (260) is formed along the side surface of the interlayer insulating layer (240) and can be continuous with the underlayer (260) formed on the upper surface of the first via pad (230). Accordingly, a path through which current can be applied is formed, and Cu is completely plated up to the inner surface of the remaining undercut structure, thereby suppressing the generation of voids and improving the reliability of the via interface.

[0082] This is explained again with reference to Figure 1.

[0083] After plating is completed, the resist pattern is peeled off from the interlayer insulating layer (240) (S190).

[0084] Fig. 12 is a first exemplary diagram for explaining step S190 of a method for manufacturing a multilayer substrate according to one embodiment of the present invention. When the resist pattern is peeled off, the multilayer substrate (200) can be formed into a two-layer structure including a base substrate (210), a first circuit wiring layer (220), a first via pad (230), an interlayer insulating layer (240), a base layer (260), a plating portion (270), a second circuit wiring layer (320), and a second via pad (330).

[0085] The first circuit wiring layer (220) can be electrically connected to the first via pad (230) formed at the same level. Similarly, the second circuit wiring layer (320) can be electrically connected to the second via pad (330) formed at the same level. The first via pad (230) can be electrically connected to the second via pad (330) through the plating portion (270) filled in the via portion (250). Accordingly, the first circuit wiring layer (220) and the second circuit wiring layer (320) can be electrically connected through the first via pad (230), the plating portion (270), and the second via pad (330).

[0086] Referring to Fig. 13, when the multilayer substrate (200) is formed in a two-layer structure, the second circuit wiring layer (320) and the second via pad (330) may be covered by a protective layer (380) formed thereon. At this time, the external connection terminal may be exposed without being covered. Fig. 13 is a second exemplary diagram for explaining step S190 of the multilayer substrate manufacturing method according to one embodiment of the present invention.

[0087] The multilayer substrate (200) can also be formed with a structure of three or more layers. For example, when the multilayer substrate (200) is formed with a three-layer structure, an insulating layer, a via section including a main via and a sub via, a base layer, a resist pattern, a plating section, a third circuit wiring layer, a third via pad, a protective layer, etc. can be sequentially formed on the second circuit wiring layer (320) and the second via pad (330). The insulating layer, the via section, the base layer, the resist pattern, the plating section, the third circuit wiring layer, the third via pad, the protective layer, etc. can be sequentially formed on the second circuit wiring layer (320) and the second via pad (330) according to the method described above with reference to FIGS. 1 to 13. Even when the multilayer substrate (200) is formed with a structure of four or more layers, it goes without saying that the same method can be repeatedly applied.

[0088] Referring to FIGS. 1 to 13, a case in which a single main via (250a) and a single sub-via (250b) are formed on a first via pad (230) has been described. In addition, a case in which a single main via (250a) and a plurality of sub-vias (250ba, 250bb, …, 250bn) are formed on a first via pad (230) has been described.

[0089] However, the present invention is not limited thereto, and it is also possible to form a plurality of main vias and a single sub-via (250b) on the first via pad (230). Alternatively, it is also possible to form a plurality of main vias and a plurality of sub-vias (250ba, 250bb, …, 250bn) on the first via pad (230). This will be described below.

[0090] Fig. 14 is a flowchart illustrating a method for manufacturing a multilayer substrate according to another embodiment of the present invention. The example of Fig. 14 illustrates a case in which two main vias and a single sub-via (250b) are formed on a first via pad (230).

[0091] First, a first circuit wiring layer (220) and a first via pad (230) are formed on one surface of the base substrate (210) (S410). Since step S410 can be performed in the same manner as step S110 described above, a detailed description thereof is omitted here.

[0092] Thereafter, an interlayer insulating layer (240) is formed to cover the first circuit wiring layer (220) and the first via pad (230) (S420). Since step S420 can be performed in the same manner as step S120 described above, a detailed description thereof is omitted here.

[0093] Afterwards, two main vias, i.e., a first main via (250c) and a second main via (250d), are formed through processing in the interlayer insulating layer (240) (S430).

[0094] FIG. 15 is an exemplary diagram illustrating step S430 of a method for manufacturing a multilayer substrate according to another embodiment of the present invention. Referring to FIG. 15, the first main via (250c) and the second main via (250d) can be formed using the same processing method as the main via (250a) described above. For example, the first main via (250c) and the second main via (250d) can be formed using a laser drill using a UV laser. Alternatively, the first main via (250c) and the second main via (250d) can be formed using a laser drill using a C)2 laser.

[0095] The first main via (250c) and the second main via (250d) may be formed to have the same shape as the main via (250a) described above. That is, the first main via (250c) and the second main via (250d) may be formed to have the same shape. For example, the first main via (250c) and the second main via (250d) may be formed to have a lower diameter that is different from a width of the upper diameter. Alternatively, the first main via (250c) and the second main via (250d) may be formed to have a lower diameter that is the same width as the upper diameter. However, the present invention is not limited thereto, and the first main via (250c) and the second main via (250d) may also be formed to have different shapes.

[0096] The first main via (250c) and the second main via (250d) may be formed to have the same size as the main via (250a) described above. That is, the first main via (250c) and the second main via (250d) may be formed to have the same size. In addition, the first main via (250c) and the second main via (250d) may be formed simultaneously. However, the present invention is not limited thereto, and the first main via (250c) and the second main via (250d) may also be formed sequentially.

[0097] The first main via (250c) and the second main via (250d) may be formed to be spaced apart from each other. The distance between the first main via (250c) and the second main via (250d) is preferably 10 μm to 50 μm, but it is to be understood that the distance may be changed to various values ​​depending on the size of the first via pad (230).

[0098] Meanwhile, when three or more main vias are formed on the first via pad (230), the nth main via (where n is a natural number greater than or equal to 3) can be formed in the same manner as the first main via (250c) or the second main via (250d).

[0099] This is explained again with reference to Figure 14.

[0100] After forming a first main via (250c) and a second main via (250d) in the interlayer insulating layer (240), a sub-via (250b) is formed by processing in the space between the first main via (250c) and the second main via (250d) (S440).

[0101] FIG. 16 is a first exemplary diagram illustrating step S440 of a method for manufacturing a multilayer substrate according to another embodiment of the present invention. Referring to FIG. 16, a sub-via (250b) may be formed such that a portion thereof overlaps with each of a first main via (250c) and a second main via (250d). In the following description, the first main via (250c), the second main via (250d), and the sub-via (250b) are collectively defined as a via portion (250).

[0102] The shape and size of the sub-via (250b) and the level of the residual insulating layer (241) remaining in the via portion (250) depending on the size of the sub-via (250b) are the same as those described with reference to FIG. 1, so a detailed description thereof is omitted here.

[0103] The upper diameter of the sub-via (250b) may be formed to have a different width from the upper diameters of the first main via (250c) and the second main via (250d). Specifically, the upper diameter of the sub-via (250b) may be formed to be narrower than the upper diameters of the first main via (250c) and the second main via (250d). The width (W6) of the upper diameter of the sub-via (250b) may be formed to have a value of 40% to 80% of the width (W4) of the upper diameter of the first main via (250c) and the width (W5) of the upper diameter of the second main via (250d) (0.4 * W4, W5 ≤ W6 ≤ 0.8 * W4, W5).

[0104] If the width (W6) of the upper diameter of the sub-via (250b) is formed to be less than 40% of the widths (W4, W5) of the upper diameters of the first main via (250c) and the second main via (250d), the area of ​​the residual insulating layer (241) remaining within the via portion (250) may become narrower than an appropriate value. In this case, the residual insulating layer (241) may not be deformed in the upper direction of the first via pad (230) where the undercut is formed during the etching process. Alternatively, even if the residual insulating layer (241) is deformed, it may not be bonded to the upper portion of the first via pad (230) where the undercut is formed.

[0105] When the width (W3) of the upper diameter of the sub-via (250b) is formed to exceed 80% of the width (W4, W5) of the upper diameter of the first main via (250c) and the second main via (250d), bonding between the residual insulating layer (241) and the first via pad (230) may be possible, but the productivity of the product may be reduced.

[0106] The first main via (250c), the second main via (250d), and the sub-via (250b) may overlap with each other by 10% to 30% of the lower area of ​​the first main via (250c). If the overlapping area between the first main via (250c) and the sub-via (250b) and / or the overlapping area between the second main via (250d) and the sub-via (250b) is less than 10%, the same problem as the case where the overlapping area between the main via (250a) and the sub-via (250b) is less than 1% as described above may occur. Likewise, if the overlapping area between the first main via (250c) and the sub-via (250b) and / or the overlapping area between the second main via (250d) and the sub-via (250b) exceeds 30%, the same problem as the case where the overlapping area between the main via (250a) and the sub-via (250b) exceeds 30% described above may occur.

[0107] The sub-via (250b) may be formed in various shapes, such as circular, polygonal, and linear. Depending on the width, thickness, area, etc. of the sub-via (250b), the lower center of the sub-via (250b) may have a higher laser processing level than other areas. Accordingly, the upper part of the first via pad (230) corresponding to the lower center area of ​​the sub-via (250b) may be partially exposed, and there is a possibility that an undercut structure may occur.

[0108] When forming a sub-via (250b), processing is performed by scanning the laser multiple times depending on the area or thickness of the sub-via (250b). In this case, the laser changes its position and processes multiple times, resulting in overlapping processing areas. A high laser processing level means that the overlapping processing area is processed more deeply than other areas.

[0109] In order to solve this problem in the present invention, the sub-via (250b) can be formed in a ring shape. Here, being formed in a ring shape means that the sub-via (250b) is formed to be simultaneously connected to the first main via (250c) and the second main via (250d). That is, the sub-via (250b) can be formed to partially overlap the first main via (250c) and the second main via (250d). As will be described later, when the sub-via (250b) is formed in a ring shape, the sub-via (250b) can be formed like the first sub-via (250ba) or the second sub-via (250bb) of FIG. 17. Alternatively, the sub-via (250b) can be formed like the first sub-via (250ba) of FIG. 18. By forming the sub-via (250b) in a ring shape, the area where processing overlaps (e.g., the lower center of the sub-via (250b)) can be minimized, and it becomes possible to control the upper exposure of the first via pad (230).

[0110] This is explained again with reference to Figure 14.

[0111] After sequentially forming a first main via (250c), a second main via (250d), and a sub-via (250b) on the interlayer insulating layer (240), an etching process is performed (S450) to clean or modify the surface for forming the underlying layer to be described in step S460. In the present invention, a desmear process may also be performed instead of the etching process. Since step S450 can be performed in the same manner as step S150 described above, a detailed description thereof is omitted here.

[0112] After completing the etching process or desmear process, a sublayer (260) is formed on the inner side of the via (250), the upper surface and side surfaces of the interlayer insulating layer (240), etc. (S460). Since step S460 can be performed in the same manner as step S160 described above, a detailed description thereof is omitted here.

[0113] After forming the sublayer (260) on the via (250), interlayer insulating layer (240), etc., a resist pattern is formed on the upper part of the interlayer insulating layer (240) (S470). Since step S470 can be performed in the same manner as step S170 described above, a detailed description thereof is omitted here.

[0114] After forming a resist pattern on the upper part of the interlayer insulating layer (240), plating is performed on the gaps between the resist patterns, vias (250), etc. (S480). Since step S480 can be performed in the same manner as step S180 described above, a detailed description thereof is omitted here.

[0115] After plating is completed, the resist pattern is peeled off from the interlayer insulating layer (240) (S490). Step S490 can be performed in the same manner as step S190 described above, and thus a detailed description thereof is omitted here.

[0116] As previously described, a plurality of main vias and a plurality of sub-vias may be formed on the first via pad (230). In this case, each of the plurality of sub-vias may overlap with a plurality of main vias. For example, referring to FIG. 17, a portion of the first sub-via (250ba) and the second sub-via (250bb) may overlap with the first main via (250c) and the second main via (250d), respectively. FIG. 17 is a second exemplary diagram for explaining step S440 of a method for manufacturing a multilayer substrate according to another embodiment of the present invention.

[0117] However, the present invention is not limited thereto, and among the plurality of sub-vias, some of the sub-vias may overlap with the plurality of main vias, and the remaining sub-vias may not overlap with the plurality of main vias. For example, referring to FIG. 18, a part of the first sub-via (250ba) may overlap with the first main via (250c) and the second main via (250d), and a part of the second sub-via (250bb) may overlap only with the first main via (250c). FIG. 18 is a third exemplary diagram for explaining step S440 of a method for manufacturing a multilayer substrate according to another embodiment of the present invention.

[0118] Alternatively, the plurality of sub-vias may not overlap the plurality of main vias. For example, referring to FIG. 19, a portion of the first sub-via (250ba) may overlap only the first main via (250c), and a portion of the second sub-via (250bb) may overlap only the second main via (250d). FIG. 19 is a fourth exemplary diagram illustrating step S440 of a method for manufacturing a multilayer substrate according to another embodiment of the present invention.

[0119] Hereinafter, a method for manufacturing a multilayer substrate according to various embodiments of the present invention has been described with reference to FIGS. 1 to 19. Hereinafter, the method for manufacturing a multilayer substrate described in the background art is defined as prior art, the method for manufacturing a multilayer substrate described with reference to FIG. 1 is defined as a first embodiment, and the method for manufacturing a multilayer substrate described with reference to FIG. 14 is defined as a second embodiment.

[0120] To demonstrate the effectiveness of the present invention, a comparative via interface reliability experiment was conducted using a bending test and a thermal cycle test. The experimental conditions for the bending test were as follows.

[0121] - Test Scale: 400g

[0122] - Test Point: Additional analysis location

[0123] - Number of bends: 100 times (1 repetition of 90° left / right axes is counted as 1 time.)

[0124] - Film fixing jig R value: 0.5mm

[0125] - 1 repetition of 90° left / right axis = 1 count (180°)

[0126] Next, the experimental conditions for the thermal cycle test are as follows.

[0127] - Temperature: -40℃ ~ 125℃ / 20min

[0128] - Cycle: 50 times

[0129] According to the results of bending tests and thermal cycle tests, interface separation occurred in the prior art, but interface separation did not occur in the first and second embodiments. Therefore, the present invention can achieve the effect of improving via interface reliability compared to the prior art.

[0130] As described above, the multilayer substrate (200) of the present invention may be formed as a flexible circuit board or a coil substrate. When the multilayer substrate (200) is formed as a flexible circuit board, the electronic device may be formed as a device including the multilayer substrate (200) and a semiconductor chip mounted on the multilayer substrate (200). Furthermore, when the multilayer substrate (200) is formed as a coil substrate, the electronic device may be formed as a device that includes the multilayer substrate (200) and is utilized in a field requiring electromagnetic force.

[0131] Although embodiments of the present invention have been described with reference to the attached drawings, the present invention is not limited to the above embodiments, but can be manufactured in various different forms. Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

[0132] The present invention relates to a multilayer substrate. The present invention can be applied to a flexible circuit board or a coil substrate.

Claims

1. Base material; A first circuit wiring layer and a first via pad formed on the above base substrate; An interlayer insulating layer covering the first circuit wiring layer and the first via pad; A via portion formed to penetrate the interlayer insulating layer and contact the first via pad; A plating part for filling the above via part; A second circuit wiring layer formed on the interlayer insulating layer; and A second via pad formed on the above plating portion is included, A multilayer substrate including a main via and a sub-via partially overlapping the main via.

2. In paragraph 1, A multilayer substrate wherein the lower diameter of the main via is smaller than the upper diameter of the main via.

3. In paragraph 1, A multilayer substrate in which the depth of the above sub-via is shallower than the depth of the above main via.

4. In paragraph 1, A multilayer substrate wherein the upper diameter of the sub-via is smaller than the upper diameter of the main via.

5. In paragraph 1, The above main via is a multilayer substrate formed in multiple layers.

6. In paragraph 5, A multilayer substrate in which multiple main vias are formed spaced apart from each other.

7. In paragraph 5, A multilayer substrate in which the above sub-vias partially overlap with multiple main vias.

8. In paragraph 1, A multilayer substrate in which the above sub-via is formed in a ring shape with respect to the above main via.

9. In paragraph 5, The above sub-via is a multilayer substrate formed in multiple layers.

10. In paragraph 9, A multilayer substrate where each sub-via partially overlaps each main via.

11. In paragraph 9, A multilayer substrate, wherein at least one of the plurality of sub-vias partially overlaps the plurality of main vias.

12. In paragraph 1, A multilayer substrate further comprising a sublayer formed between the main via and the plating portion, and formed between the sub-via and the plating portion.

13. In paragraph 12, The above-mentioned sublayer is a multilayer substrate including discontinuous portions.

14. In paragraph 12, A multilayer substrate, wherein the first via pad comprises a first metal, and the sublayer comprises a second metal.

15. An electronic device comprising a multilayer substrate according to any one of claims 1 to 14.

16. A step of forming a first circuit wiring layer and a first via pad on a base substrate; A step of forming an interlayer insulating layer to cover the first circuit wiring layer and the first via pad; A step of forming a main via so as to penetrate the surface of the interlayer insulating layer and contact the first via pad; A step of forming a sub-via partially overlapping with the main via; A step of performing etching treatment or desmear treatment including the above main via and the above sub via; A step of forming a sublayer covering the interlayer insulating layer, the main via, and the sub via; and A method for manufacturing a multilayer substrate, comprising the steps of forming a plating portion within the main via and forming a second circuit wiring layer and a second via pad on the interlayer insulating layer and the plating portion.

17. In paragraph 16, The step of forming the above sub-via is: A method for manufacturing a multilayer substrate, wherein the depth of the sub-via is formed shallower than the depth of the main via, so that an interlayer insulating layer remains under the sub-via in an area that does not overlap with the main via.

18. In paragraph 16, The above etching or desmearing step is, A method for manufacturing a multilayer substrate, wherein a surface of a first via pad exposed at a lower portion of the main via is etched, a depth of a sub-via is formed shallower than the depth of the main via, and an interlayer insulating layer remains at a lower portion of the sub-via in an area that does not overlap with the main via.

19. In paragraph 16, A method for manufacturing a multilayer substrate further comprising the step of forming an underlying layer covering the interlayer insulating layer, the main via, and the sub via after the etching treatment or the desmear treatment.

20. In paragraph 16, A step of forming a resist pattern on the substrate layer before forming the plating portion, the second circuit wiring layer and the second via pad; and A method for manufacturing a multilayer substrate, further comprising the step of peeling off the resist pattern after forming the plating portion, the second circuit wiring layer, and the second via pad.

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