Autoranging configuration

Abstract

Circuitry on an integrated circuit has performance characteristics that depend on a combination of configuration parameters (e.g., PLL loop filter cutoff frequency, PLL loop divider ratio, etc.) and a reference clock signal frequency. A frequency of the input signal is measured. Based on the frequency measurement, the circuit is configured with first parameters associated with a first frequency band that the measured frequency lies within. Based on the measured frequency lying within the first frequency band, the range of the first frequency band is adjusted. In particular, the range of the first frequency band is enlarged. This enlargement of the first frequency band introduces hysteresis into the selection of the frequency band. In this manner, the measurement errors of measured frequencies that lie near a frequency band boundary will result in the selection of the first frequency band and use of the first parameters.

Description

AUTORANGING CONFIGURATION BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a block diagram illustrating an autoranging configuration system.

[0002] Figure 2 is a block diagram illustrating an autoranging phase-locked loop (PLL) system.

[0003] Figure 3 flowchart illustrating a method of configuring a phase-locked loop.

[0004] Figure 4 is a diagram illustrating configuration band adjustments.

[0005] Figure 5 is a diagram illustrating a configuration band adjustment across a context change.

[0006] Figures 6A-6B are diagrams illustrating an example effect of configuration band adjustment.

[0007] Figure 7 is a diagram illustrating a memory module.

[0008] Figure 8 is a flowchart illustrating a method of operating a memory module.

[0009] Figure 9 is a flowchart illustrating a method of configuring circuitry.

[0010] Figure 10 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In an embodiment, circuitry (e.g., PLL) on an integrated circuit has performance characteristics (e.g., jitter) that depend on a combination of configuration parameters (e.g., PLL loop filter cutoff frequency, PLL loop divider ratio, etc.) and a reference clock signal frequency (e.g., input signal to PLL). Accordingly, the circuit is configured with different circuit configuration parameters when the input signal is within different frequency ranges (configuration bands). A frequency of the input signal is measured. Based on the frequency measurement, the circuit is configured with first parameters associated with a first frequency band that the measured frequency lies within. Based on the measured frequency lying within the first frequency band, the range of the first frequency band is adjusted. In particular, the range of the first frequency band is enlarged. This enlargement of the first frequency band introduces hysteresis into the selection of the frequency band. In this manner, the measurement errors of measured frequencies that lie near a frequency band boundary will result in the selection of the first frequency band and use of the first parameters. This improves repeatability of the performance characteristics of the circuitry being configured in a frequency-dependent manner.

[0012] Figure l is a block diagram illustrating an autoranging configuration system. In Figure 1, system 100 comprises configuration and frequency-dependent circuitry 110 andcontrol circuitry 120. Control circuitry 120 includes oscillator circuitry 121, frequency detector circuitry 122, threshold circuitry 123, configuration parameters circuitry 124, threshold setting circuitry 125, and last configuration band memory circuitry 126. In an embodiment, oscillator circuitry 121 is calibrated during manufacturing / test to within a specified error (e.g., 2.5%). In an embodiment, oscillator circuitry 121 may be, or comprise, free-running oscillator circuitry that generates a signal oscillating at a target frequency without relying upon a reference clock signal. Circuitry 110 and control circuitry 120 receive a reference clock signal RCK. In particular, frequency detector circuitry 122 of control circuitry 120 receives reference clock signal RCK. Circuitry 110 may also receive other inputs - e.g., other signals, voltages, etc.

[0013] Oscillator circuitry 121 is operatively coupled to frequency detector circuitry 122. Oscillator circuitry 121 is operatively coupled to frequency detector circuitry 122 to provide frequency detector circuitry 122 with a calibrated (e.g., calibrated during manufacturing and / or test processes) clock signal OCK. Frequency detector circuitry 122 uses the calibrated clock signal OCK from oscillator circuitry 121 to determine an indicator of the frequency of reference clock RCK. Frequency detector circuitry 122 is operatively coupled to threshold circuitry 123. Threshold circuitry 123 is operatively coupled to configuration parameter circuitry 124, threshold setting circuitry 125, and band memory circuitry 126. Band memory circuitry is also operatively coupled to threshold setting circuitry 125.

[0014] Threshold setting circuitry 125 is operatively coupled to threshold circuitry 123 to set one or more threshold indicators used by threshold circuitry 123 that determine one or more boundaries between non-overlapping configuration frequency ranges (i.e., configuration bands). Band memory circuitry 126 is operatively coupled to threshold circuitry 123 to store one or more indicators of configuration bands. Band memory circuitry 126 is operatively coupled to threshold circuitry 123 to store one or more indicators of configuration bands that threshold circuitry 123 has determined that the measured frequency (i.e., by frequency detector circuitry 122) RCK has been, or is, within. Band memory circuitry 126 is operatively coupled to threshold setting circuitry 125 to provide one or more indicators of configuration bands that threshold circuitry 123 has determined that the measured frequency (i.e., by frequency detector circuitry 122) RCK has been within. Based on the one or more indicators of configuration bands that threshold circuitry 123 has determined that the measured frequency (i.e., by frequency detector circuitry 122) RCK has been within, threshold setting circuitry 125 may set the one or more threshold indicators used by thresholdcircuitry 123 that determine one or more boundaries between configuration frequency ranges (i.e., configuration bands).

[0015] Control circuitry 120 is operatively coupled to circuitry 110. Control circuitry 120 is operatively coupled to circuitry 110 to provide configuration parameters to circuitry 110. The output characteristics of one or more signals output by circuitry 110 (i.e., OUT) is dependent at least in part on both the configuration parameters provided by control circuitry 120 and the frequency of RCK. For example, a voltage, a clock signal frequency, clock jitter, signal magnitude, frequency locking range, etc. of one or more signals output by circuitry 110 may be affected by both the frequency of RCK and one or more configuration parameters provided by control circuitry 120 to circuitry 110. In particular, for example, circuitry 110 may be or comprise a phase-locked loop (PLL) that has a variable locking range of frequencies that are affected by one or more configuration parameters such as PLL loop filter cutoff frequency, PLL loop divider ratio, and the like. Control circuitry 120 is operatively coupled to circuitry 110 to provide configuration parameters to circuitry 110 based at least in part on a measurement of the frequency of RCK.

[0016] In an embodiment, oscillator circuitry 121 generates a calibrated clock signal OCK. OCK is provided to frequency detector circuitry 122. Frequency detector circuitry 122 generates, based on a comparison of the frequency of reference clock RCK and the frequency of oscillator circuitry 121 generated clock OCK an indicator of the frequency of reference clock RCK. The indicator of the frequency of reference clock RCK is provided to threshold circuitry 123. Threshold circuitry 123 uses the indicator of the frequency of reference clock RCK to select a configuration frequency range (band) that corresponds to the frequency of reference clock RCK. An indicator of the selected configuration frequency range is provided to configuration parameter circuitry 124. Based on the indicator of the selected configuration frequency range, configuration parameter circuitry 124 configures circuitry 110 to operate using parameters that are associated with, applicable, and / or optimized for the range of frequencies in the indicated configuration frequency band.

[0017] To illustrate, consider some examples where, in order to reduce output voltage error (or other performance characteristic) for an output of circuitry 110 (e.g., clock signal), circuitry 110 is to be configured to use a power supply voltage of 3.0 Volts when RCK is between 1 GHz and 2 GHz (i.e., a configuration band of 1-2 GHz as set by threshold setting circuitry 125 based on an indicator from band memory circuitry 126), and is to be configured to use a power supply voltage of 3.5 Volts when RCK is between 2 GHz and 3 GHz (i.e., aconfiguration band of 2-3 GHz as set by threshold setting circuitry 125 based on an indicator from band memory circuitry 126).

[0018] Thus, in a first example, when frequency detector circuitry 122 measures RCK to be between 1-2 GHz, threshold circuitry 123 would provide configuration parameter circuitry with an indicator corresponding to the 1-2 GHz configuration band. Based on the indicator of the 1-2 GHz configuration band, control circuitry 120 would configure circuitry 110 to use a power supply voltage of 3.0 Volts. Similarly, in a second example, when frequency detector circuitry 122 measures RCK to be between 2-3 GHz, threshold circuitry 123 would provide configuration parameter circuitry with an indicator corresponding to the 2-3 GHz configuration band. Based on the indicator of the 2-3 GHz configuration band, control circuitry 120 would configure circuitry 110 to use a power supply voltage of 3.5 Volts.

[0019] In an embodiment, system 100 may be operated in conditions that comprise multiple “frequency contexts”. As used herein, frequency contexts are conditions (e.g., RCK frequency ranges) or sets of conditions within which it is anticipated that the system 100 may transition between without requiring a full system 100 re-initialization. Thus, system 100 configuration parameters (setting) may be stored to allow for seamless transitions between operating frequencies.

[0020] In an embodiment, when system 100 is initialized for the first time in a given frequency context, band memory circuitry 126 has yet to store a frequency band for that context that a measured frequency for RCK has been within since no frequency measurements have been made for that frequency context yet. Thus, threshold setting circuitry 125 configures threshold circuitry 123 with a set of nominal (e.g., predetermined) threshold values and / or indicators. After RCK has been measured to be within a first frequency band, one or more thresholds that determine the boundaries of the first frequency band are adjusted. In an embodiment, the thresholds determining the boundaries of the first frequency band are adjusted to expand the frequency range associated with the first frequency band. In an embodiment, the thresholds determining the boundaries of the first frequency band are adjusted to expand the frequency range associated with the first frequency band by an amount that is greater than the worst-case error in the detection of the RCK clock frequency. The new threshold(s) and / or an indicator of the first frequency band are stored by last band circuitry so that the next time system 100 is initialized, the new thresholds will be used to detect whether the frequency of RCK lies within the first frequency band. Thus, it should be understood that adjusting the thresholds (i.e., boundaries) of the first frequencyband introduces hysteresis into the selection, by threshold circuitry 123, of the frequency band that determines the values of the configuration parameters provided to circuitry 110.

[0021] In an embodiment, circuitry 110 may be, or comprise, phase-locked loop circuitry and / or delay -locked loop circuitry. In an embodiment, circuitry 110 may be, or comprise, rate-dependent trim circuitry (e.g., producing one or more phase interpolator bias currents). In an embodiment, circuitry 110 may be, or comprise, cycle-based finite state machine wait interval circuitry (e.g., for calibration circuitry and / or calibration processes). In an embodiment, circuitry 110 may be, or comprise, circuitry to control frequency-dependent device features (e.g., low frequency test mode circuitry).

[0022] Figure 2 is a block diagram illustrating an autoranging phase-locked loop (PLL) system. In Figure 2, PLL system 200 comprises PLL circuitry 210, control circuitry 220, and host 250. Control circuitry 220 includes free-running oscillator circuitry 221, frequency detector circuitry 222, threshold circuitry 223, frequency-dependent PLL configuration parameter circuitry 224, threshold setting circuitry 225, last configuration band memory circuitry 226, and PLL context circuitry 227. In an embodiment, oscillator circuitry 221 is calibrated during manufacturing / test to within a specified error (e.g., 2.5%). PLL circuitry 210 and control circuitry 220 receive a reference clock signal RCK. In particular, frequency detector circuitry 222 of control circuitry 220 receives reference clock signal RCK.

[0023] Oscillator circuitry 221 is operatively coupled to frequency detector circuitry 222. Oscillator circuitry 221 is operatively coupled to frequency detector circuitry 222 to provide frequency detector circuitry 222 with a calibrated (e.g., calibrated during manufacturing and / or test processes) clock signal OCK. Frequency detector circuitry 222 uses the calibrated clock signal OCK from oscillator circuitry 221 to determine an indicator of the frequency of reference clock RCK. Frequency detector circuitry 222 is operatively coupled to threshold circuitry 223. Threshold circuitry 223 is operatively coupled to configuration parameter circuitry 224, threshold setting circuitry 225, band memory circuitry 226, and PLL context circuitry 227. Band memory circuitry is also operatively coupled to threshold setting circuitry 225 and PLL context circuitry 227.

[0024] Threshold setting circuitry 225 is operatively coupled to threshold circuitry 223 to set one or more threshold indicators used by threshold circuitry 223 that determine one or more boundaries between non-overlapping configuration frequency ranges (i.e., configuration bands). Band memory circuitry 226 is operatively coupled to threshold circuitry 223 to store one or more indicators of configuration bands. Band memory circuitry 226 is operatively coupled to threshold circuitry 223 to store one or more indicators per frequency context (e.g.,as indicated by context circuitry 227) of configuration bands that threshold circuitry 223 has determined that the measured frequency (i.e., by frequency detector circuitry 222) RCK has been, or is, within for each respective frequency context. Band memory circuitry 226 is operatively coupled to threshold setting circuitry 225 to provide one or more indicators of configuration bands that, for the current frequency context, threshold circuitry 223 has determined that the measured frequency (i.e., by frequency detector circuitry 222) RCK has been within. Based on the one or more indicators of configuration bands that threshold circuitry 223 has determined that the measured frequency (i.e., by frequency detector circuitry 222) RCK has been within, threshold setting circuitry 225 may set the one or more threshold indicators used by threshold circuitry 223 that determine one or more boundaries between configuration frequency ranges (i.e., configuration bands).

[0025] Host 250 is operatively coupled to control circuitry 220. Host 250 is operatively coupled to control circuitry 220 (and PLL context circuitry 227, in particular) to set a frequency context 251 for the operation of PLL circuitry 210. Control circuitry 220 is operatively coupled to PLL circuitry 210. Control circuitry 220 is operatively coupled to PLL circuitry 210 to provide configuration parameters to PLL circuitry 210. The output characteristics of a clock signal and / or timing reference signal output by PLL circuitry 210 (i.e., OUT) is affected at least in part by both the configuration parameters provided by control circuitry 220 and the frequency of RCK. For example, the locking range of PLL circuitry 210, clock jitter of an output, signal magnitude, duty cycle, etc. of a signal output by PLL circuitry 210 may be affected by both the frequency of RCK and one or more configuration parameters provided by control circuitry 220 to PLL circuitry 210. Control circuitry 220 is operatively coupled to PLL circuitry 210 to provide configuration parameters to PLL circuitry 210 based at least in part on a measurement of the frequency of RCK.

[0026] In an embodiment, oscillator circuitry 221 generates a calibrated clock signal OCK. OCK is provided to frequency detector circuitry 222. Frequency detector circuitry 222 generates, based on a comparison of the frequency of reference clock RCK and the frequency of oscillator circuitry 221 generated clock OCK an indicator of the frequency of reference clock RCK. The indicator of the frequency of reference clock RCK is provided to threshold circuitry 223. Threshold circuitry 223 uses the indicator of the frequency of reference clock RCK to select a configuration frequency range (band) for the current frequency context that corresponds to the frequency of reference clock RCK. An indicator of the selected configuration frequency range is provided to configuration parameter circuitry 224. Based on the indicator of the selected configuration frequency range and frequencycontext, configuration parameter circuitry 224 configures PLL circuitry 210 to operate using parameters that are associated with, applicable, and / or optimized to the current frequency context and range of frequencies in the indicated configuration frequency band.

[0027] In an embodiment, when system 200 is initialized for the first time in a given frequency context, band memory circuitry 226 has yet to store a frequency band for that context that a measured frequency for RCK has been within since no frequency measurements have been made for that frequency context yet. Thus, threshold setting circuitry 225 configures threshold circuitry 223 with a set of nominal (e.g., predetermined) threshold values and / or indicators. After RCK has been measured to be within a first frequency band, one or more thresholds that determine the boundaries of the first frequency band are adjusted. In an embodiment, the thresholds determining the boundaries of the first frequency band are adjusted to expand the frequency range associated with the first frequency band. In an embodiment, the thresholds determining the boundaries of the first frequency band are adjusted to expand the frequency range associated with the first frequency band by an amount that is greater than the worst-case error in the detection of the RCK clock frequency. The new threshold(s) and / or an indicator of the first frequency band are stored by last band circuitry so that the next time system 200 is initialized, the new thresholds will be used to detect whether the frequency of RCK lies within the first frequency band. Thus, it should be understood that adjusting the thresholds (i.e., boundaries) of the first frequency band introduces hysteresis into the selection, by threshold circuitry 223, of the frequency band that determines the values of the configuration parameters provided to PLL circuitry 210.

[0028] Figure 3 flowchart illustrating a method of configuring a phase-locked loop. One or more steps illustrated in Figure 3 may be performed by, for example, system 100, system 200, module 700, and / or their components. Context information and last used configuration band information is read (302). For example, based on information from context circuitry 227, band memory circuitry 226 may read one or more indicators of the last used configuration band for the current frequency context.

[0029] Configuration band thresholds are set based on the last used configuration band information (304). For example, control circuitry 220 may set one or more indicators in threshold circuitry 223 such that the last used frequency band for the current context has an expanded frequency range when compared to nominal frequency boundaries (thresholds). A reference clock frequency is measured (306). For example, when PLL system 200 is initializing, frequency detector circuitry 222 may, based on clock signal OCK from oscillatorcircuitry 221, determine one or more indicators of the frequency of reference clock signal RCK. The measured reference clock frequency is compared to the configuration band thresholds (308). For example, threshold circuitry 223 compares the one or more indicators of the frequency of reference clock RCK to threshold frequencies (with the last used configuration band having an expanded frequency range) that determine the configuration band ranges of the configuration bands for the current context to determine which configuration band that the frequency of RCK lies within.

[0030] The selected configuration band is set as the current configuration band (310). For example, threshold circuitry 223 may provide an indicator to configuration parameter circuitry 224 of the selected configuration band (which is different from the last used configuration band.) If the frequency of the reference clock was measured to lie within the last used configuration band, flow proceeds to box 318. If the frequency of the reference clock was measured to lie within a different configuration band from the last used configuration band, flow proceeds to box 316 (312). The selected configuration band is stored as the last used configuration for the current context (316). For example, control circuitry 220 may store, in band memory circuitry 226, an indicator that the selected configuration band has been selected and the current configuration band.

[0031] Based on the current configuration band, frequency-dependent configuration values are set (318). For example, based on the current configuration band indicator provided by threshold circuitry 223 to configuration parameter circuitry 224, control circuitry 220 may configure PLL circuitry 210 with configuration configures PLL circuitry 210 to operate using parameters that are associated with, applicable, and / or optimized for the range of frequencies in the current configuration frequency band. The PLL is then initialized (320). For example, after being configured to operate using parameters that are associated with, applicable, and / or optimized for the range of frequencies in the current configuration frequency band, PLL circuitry 210 may lock to reference clock signal RCK to produce one or more output signals.

[0032] Figure 4 is a diagram illustrating configuration band adjustments. The configuration band adjustments illustrated in Figure 4 may be examples of adjustments made by, for example, system 100, system 200, and / or their components. In Figure 4, example notional configuration band diagrams 401-403 are illustrated. In diagrams 401-403, the frequency of RCK (IRCK) is illustrated along the vertical direction. Band diagram 401 illustrates example configuration bands A-C for a frequency context before RCK is measured to be within a configuration band (e.g., before the frequency is first used). In diagram 401, configuration frequency band “B” is illustrated separated from a higher frequencyconfiguration frequency band “A” at threshold frequency ftab init. Similarly, configuration frequency band “B” is illustrated separated from a lower frequency configuration frequency band “C” at threshold frequency ftbcjnit.

[0033] After RCK is detected (measured) to be within frequency band B, the threshold frequencies to determine the boundaries between frequency bands A and B, and between B and C are adjusted to expand the range of frequencies of RCK that result in RCK being indicated to be within frequency band B. This is illustrated by diagram 402 with frequency band B being indicated to run from ftab b to ftbc b, where ftab b is a higher frequency than ftab init by Aab b and ftbc b is a lower frequency than ftbc init by Abe b.

[0034] After RCK is detected (measured) to be within frequency band A, the threshold frequencies to determine the boundaries between frequency bands A and B, and between B and C are adjusted to reduce the range of frequencies of RCK that result in RCK being indicated to be within frequency band B and to increase the range of frequencies of RCK that result in RCK being indicated to be within frequency band A. This is illustrated by diagram 403 with frequency band B being indicated to run from ftab a to ftbc init, where ftab a is a lower frequency than ftab init by Aab a.

[0035] Figure 5 is a diagram illustrating a configuration band adjustment across a context change. Figure 5 is a diagram illustrating configuration band adjustments. The configuration band adjustments illustrated in Figure 5 may be examples of adjustments made by, for example, system 100, system 200, and / or their components. In Figure 5, example notional configuration band diagrams 501-502 are illustrated. In diagrams 501-502, the frequency of RCK (facK) is illustrated along the vertical direction. Band diagram 501 illustrates example configuration bands A0-C0 for a frequency context (e.g., frequency context 0) after RCK has measured to be within configuration band B0. In diagram 501, configuration frequency band “B0” is illustrated separated from a higher frequency configuration frequency band “A0” at threshold frequency ftab bo which is greater than ftab inito. Similarly, configuration frequency band “B0” is illustrated separated from a lower frequency configuration frequency band “CO” at threshold frequency at threshold frequency ftbc bo which is less than ftbc inito.

[0036] After a context change (e.g., to frequency context 1), the threshold frequencies to initially determine the boundaries between frequency bands Al and Bl, and between Bl and Cl are set, based on the last used frequency band of configuration band Al while in this context, to an expanded the range of frequencies of RCK that result in RCK being indicated to be within frequency band Al . This is illustrated by diagram 502 with frequency band B 1 being indicated to run from ftab ai to ftbc initi, where ftab ai is a lower frequency than ftab initi byAab ai. In an embodiment, ftbcjniti may a different (e.g., higher or lower - not illustrated in Figure 5) frequency than ftbcjnito.

[0037] Figures 6A-6B are diagrams illustrating an example effect of configuration band adjustment. Illustrated in Figures 6A-6B is a nominal RCK frequency and an associated range of detected frequencies (e.g., due to measurement error, noise, etc.) for measurements of RCK when RCK is at that nominal frequency. In Figures 6A-6B, the nominal RCK frequency and an associated range of detected frequencies should be understood to be the same for both Figures 6A-6B.

[0038] Figure 6A illustrates a configuration band diagram 601 where configuration frequency band “B” is illustrated separated from a higher frequency configuration frequency band “A” at threshold frequency ftab init and separated from a lower frequency configuration frequency band “C” at threshold frequency ftbcjnit. Note that the range of detected RCK frequencies lies in both frequency band A and frequency band B. Thus, with the configuration band thresholds illustrated in Figure 6A, the nominal RCK frequency illustrated in Figures 6A-6B may sometimes be measured as being within configuration frequency band A, and sometimes be measure as being within configuration frequency band B - thereby resulting in different, possibly random, selections between configuration frequency band A and configuration frequency band B.

[0039] Figure 6B illustrates a configuration band diagram 602 where configuration frequency band “B” is illustrated with an expanded frequency range that is separated from higher frequency configuration frequency band “A” at threshold frequency ftab b which is at a higher frequency than ftab init. Note that the range of detected RCK frequencies in diagram 602 lies completely within frequency band B. Thus, with the configuration band thresholds illustrated in Figure 6B, the nominal RCK frequency illustrated in Figures 6A should always be measured as being within configuration frequency band B - thereby resulting in consistent and repeatable selections of configuration frequency band B.

[0040] In an embodiment, a host may select, or gives a hint of, (e.g., a bit in a command) the selection of the frequency context. For example, if two contexts are managed, the host may communicate a field (e.g., one-bit, two-bits, etc.) that indicates to the device which context to use for the next initialization event. Specific rate information may not be indicated by the host since the current RCK frequency is measured and compared against thresholds determined by the previously selected configuration band in that context.

[0041] Figure 7 is a diagram illustrating a memory module. In Figure 7, memory module 700 comprises registering clock driver integrated circuit (IC) 710, first rank of memorydevices 740-748, second rank of memory devices 750-758, DQ (data) buffers 760-768, DQ connections 770, and command / address (C / A) connections 780. Registering clock driver integrated circuit (IC) 710, memory devices 740-749, memory devices 750-758, and / or DQ buffers 760-769 may include circuitry that implements, functions like, and / or corresponds to, system 100, system 200, and / or their components.

[0042] In the configuration shown in Figure 7, C / A signals received at C / A connections 780 are buffered by IC 710 and sent to memory devices 750-758 via links. C / A signals received at C / A connections 780 are also buffered by IC 710 and sent to memory devices 740-748 via links. Thus, IC 710 necessarily includes command / address interfaces (not explicitly shown in Figure 7) configured to connect to memory devices 740-748 and memory devices 750-758. DQ signals received / sent by DQ buffers 760-768 from DQ connections 770 are sent / received to / from memory devices 750-758 via links. DQ signals received / sent by DQ buffers 760-768 from DQ connections 770 are sent / received to / from memory devices 740-748 via links. One or more reference clock signals (e.g., RCK) may be transmitted by IC 710 to DQ buffers 760-768 via links. One or more control signals may be transmitted by IC 710 to DQ buffers 760-768 via links. The one or more control signals may be transmitted by IC 710 to DQ buffers 760-768 may be used to change / set frequency contexts of DQ buffers 760-768.

[0043] In an embodiment, it should be understood that memory module 700 includes a memory interface (e.g., C / A connections 780) configured to interface to a memory controller. Memory module 700 includes an integrated circuit device (e.g., IC 710) that is coupled to the memory interface. Memory module 700 also includes the first plurality of dynamic memory integrated circuits (e.g., memory devices 750-758), the second plurality of dynamic memory integrated circuits (e.g., memory devices 740-748), and at least one data buffer integrated circuit (e.g., one or more of DQ buffers 760-768). The first plurality of dynamic memory integrated circuits are coupled to the first command / address interface. The second plurality of dynamic memory integrated circuits are coupled to the second command / address interface. The at least one data buffer integrated circuit is coupled to the first plurality of dynamic memory integrated circuits and the second plurality of dynamic memory integrated circuits. The at least one data buffer integrated circuit is coupled to the memory interface (e.g., DQ connections 770). The at least one data buffer integrated circuit are each coupled to the integrated circuit device by at least a command link and a reference clock signal link.

[0044] Figure 8 is a flowchart illustrating a method of operating a memory module. One or more steps illustrated in Figure 8 may be performed by, for example, system 100, system200, module 700, and / or their components. By a command an integrated circuit and to a buffer integrated circuit, a first reference clock signal having a first frequency is transmitted (802). For example, registering clock driver integrated circuit 710 may transmit, to at least one of DQ buffer integrated circuits 760-768, a reference clock signal having a first frequency. In another example, a host integrated circuit may transmit, to RCE 710 and via CA interface 780, a reference clock signal having a first frequency.

[0045] By the buffer integrated circuit, it is determined that the first frequency is within a first frequency range associated with a first configuration parameter value to be provided to first circuitry that has an operational characteristic that is based on the first configuration parameter value and the first frequency (804). For example, a PLL system 200 in data buffer integrated circuit 740 may determine that the first frequency is within a first frequency range (e.g., frequency range B illustrated in Figure 4). In another example, a PLL system 200 in RCD 710 may determine that the first frequency is within a first frequency range (e.g., frequency range B illustrated in Figure 4). Based on the first frequency being within the first frequency range, the first configuration parameter value is provided, by the buffer integrated circuit, to the first circuitry (806). For example, based on determining that the first frequency is within the first frequency range associated with the first parameter value (e.g., loop filter coefficient), data buffer integrated circuit 740 may configure PLL circuitry 210 with the first parameter value. In another example, based on determining that the first frequency is within the first frequency range associated with the first parameter value (e.g., loop filter coefficient), RCD 710 may configure PLL circuitry 210 with the first parameter value.

[0046] Based on the first frequency being with the first frequency range, a second frequency range is associated by the buffer integrated circuit and in place of the first frequency range with the first parameter value to be provided to the first circuitry, where the second frequency range includes the first frequency and is larger than the first frequency range (808). For example, data buffer integrated circuit 740 may, based on determining that the first frequency is within the first frequency range, associate the first parameter value with an expanded version of the first frequency range to be used in place of the original first frequency range. In another example, RCD 710 may, based on determining that the first frequency is within the first frequency range, associate the first parameter value with an expanded version of the first frequency range to be used in place of the original first frequency range.

[0047] Figure 9 is a flowchart illustrating a method of configuring circuitry. One or more steps illustrated in Figure 9 may be performed by, for example, system 100, system 200,module 700, and / or their components. A first reference clock signal is transmitted at a first frequency (902). For example, registering clock driver integrated circuit 710 may transmit, to at least one of DQ buffer integrated circuits 760-768, a first reference clock signal that has a first frequency.

[0048] It is determined that the first frequency is within a first frequency range associated with a first configuration parameter value to be provided to first circuitry (904). For example, a PLL system 200 in data buffer integrated circuit 740 may determine that the first frequency is within a first frequency range (e.g., frequency range B illustrated in Figure 4) associated by configuration parameter circuitry 224 with a first configuration parameter value. Based on the first frequency being within the first frequency range, the first configuration parameter value is provided to the first circuitry (906). For example, based on determining that the first frequency is within the first frequency range associated with the first parameter value (e.g., a first loop filter coefficient value), data buffer integrated circuit 740 may configure PLL circuitry 210 with the first parameter value.

[0049] Based on the first frequency being within the first frequency range, a second frequency range is associated in place of the first frequency range with the first parameter value to be provided to the first circuitry, where the second frequency range includes the first frequency and is larger than the first frequency range (908). For example, data buffer integrated circuit 740 may, based on determining that the first frequency is within the first frequency range, associate the first parameter value with an expanded version of the first frequency range to be used in place of the original first frequency range.

[0050] A second reference clock signal is transmitted at a second frequency (910). For example, registering clock driver integrated circuit 710 may transmit, to at least one of DQ buffer integrated circuits 760-768, a second reference clock signal that has a second frequency.

[0051] It is determined that the second frequency is within a third frequency range associated with a second configuration parameter value to be provided to first circuitry (912). For example, PLL system 200 in data buffer integrated circuit 740 may determine that the second frequency is within a second frequency range (e.g., frequency range A illustrated in Figure 4) associated by configuration parameter circuitry 224 with a second configuration parameter value. Based on the second frequency being within the third frequency range, the second configuration parameter value is provided to the first circuitry (914). For example, based on determining that the second frequency is within the third frequency range associatedwith the second parameter value (e.g., a second loop filter coefficient value), data buffer integrated circuit 740 may configure PLL circuitry 210 with the second parameter value.

[0052] Based on the second frequency being within the third frequency range, a fourth frequency range is associated in place of the third frequency range with the second parameter value to be provided to the first circuitry, where the fourth frequency range includes the second frequency and is larger than the third frequency range (916). For example, data buffer integrated circuit 740 may, based on determining that the second frequency is within the third frequency range, associate the second parameter value with an expanded version of the third frequency range to be used in place of the original third frequency range.

[0053] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system 100, system 200, and / or module 700, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry -level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0054] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0055] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communications devices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0056] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of system 100, system 200, and / or module 700, and their components, as shown in the Figures.

[0057] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0058] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

[0059] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0060] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0061] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0062] Implementations discussed herein include, but are not limited to, the following examples:

[0063] Example 1: An integrated circuit, comprising: a first circuit having a performance characteristic that based on a combination of a first configuration parameter and a reference clock signal frequency; frequency band detection circuitry to, based on a first reference clock signal and a clock signal, determine that a first frequency of the first reference clock signal lies within a first configuration frequency range associated with a first configuration parameter value for the first configuration parameter and to determine that the first frequency of the first reference clock signal does not lie within a second configuration frequency range associated with a second configuration parameter value for the first configuration parameter, the first configuration parameter value and the second configuration parameter value to be not equal; and frequency band adjusting circuitry to, based on the first frequency being within the first configuration frequency range, select a first adjusted frequency range to be associated with the first configuration parameter value for the first configuration parameter.

[0064] Example 2: The integrated circuit of example 1, wherein the frequency band adjusting circuitry is to, based on the first frequency being within the first configuration frequency range, select a second adjusted frequency range to be associated with the second configuration parameter value for the first configuration parameter.

[0065] Example 3: The integrated circuit of example 1, wherein the first circuit comprises a phase-locked loop circuit.

[0066] Example 4: The integrated circuit of example 3, wherein the performance characteristic is a frequency lock range for the phase-locked loop circuit.

[0067] Example 5: The integrated circuit of example 1, further comprising: calibrated free-running oscillator circuitry to generate the clock signal.

[0068] Example 6: The integrated circuit of example 2, wherein the frequency band detection circuitry is to, based on a second reference clock signal and the clock signal, determine that a second frequency of the second reference clock signal lies within the second adjusted frequency range and to determine that the second frequency of the second reference clock signal does not lie within the first adjusted frequency range.

[0069] Example 7: The integrated circuit of example 1, wherein the performance characteristic further based on a combination of a second configuration parameter and the reference clock signal frequency, a host set value for the second configuration parameter to be provided by a host system coupled to a memory module that includes the integrated circuit.

[0070] Example 8: A memory module, comprising: a first integrated circuit device to transmit a reference clock signal having a plurality of frequencies; and a second integrated circuit having a first circuit having an operational characteristic dependent on a first configuration parameter and the plurality of frequencies of the reference clock signal, the second integrated circuit also having first configuration parameter selection circuitry to, based on the reference clock signal having a first frequency that is within a first frequency range, select a first value for the first configuration parameter and select an adjusted first frequency range to be used by the first configuration parameter selection circuitry to select the first value for the first configuration parameter.

[0071] Example 9: The memory module of example 8, wherein the first configuration parameter selection circuitry is to, based on the reference clock signal having a second frequency that is within a second frequency range, select a second value for the first configuration parameter and select an adjusted second frequency range to be used by the first configuration parameter selection circuitry to select the second value for the first configuration parameter.

[0072] Example 10: The memory module of example 9, the first configuration parameter selection circuitry is to, based on the reference clock signal having a second frequency that is within the second frequency range, select a third frequency range to be used by the first configuration parameter selection circuitry to select the first value for the first configuration parameter, the third frequency range and the adjusted second frequency range to be nonoverlapping.

[0073] Example 11 : The memory module of example 9, wherein the second frequency range and the first adjusted frequency range are to be non-overlapping.

[0074] Example 12: The memory module of example 8, wherein the first integrated circuit device is a registering clock driver integrated circuit.

[0075] Example 13: The memory module of example 12, wherein the second integrated circuit is a data buffer integrated circuit.

[0076] Example 14: The memory module of example 9, wherein the second integrated circuit further comprises oscillator circuitry to provide a clock signal that is to be used to determine whether the reference clock signal has a frequency that is within the first frequency range and to determine whether the reference clock signal has a frequency that is within the second frequency range.

[0077] Example 15: A method, comprising: transmitting, by an address buffer integrated circuit and to a data buffer integrated circuit, a first reference clock signal having a firstfrequency; determining, by the data buffer integrated circuit, that the first frequency is within a first frequency range associated with a first configuration parameter value to be provided to first circuitry that has an operational characteristic that is based on the first configuration parameter value and the first frequency; based on the first frequency being within the first frequency range, providing, by the data buffer integrated circuit, the first configuration parameter value to the first circuitry; and based on the first frequency being within the first frequency range, associating, by the data buffer integrated circuit and in place of the first frequency range, a second frequency range with the first configuration parameter value to be provided to the first circuitry, the second frequency range being larger than the first frequency range and the second frequency range including the first frequency.

[0078] Example 16: The method of example 15, further comprising: transmitting, by the address buffer integrated circuit and to the data buffer integrated circuit, a second reference clock signal having a second frequency; determining, by the data buffer integrated circuit, that the second frequency is within a third frequency range associated with a second configuration parameter value to be provided to the first circuitry where the operational characteristic is based on the second configuration parameter value and the second frequency; based on the second frequency being within the third frequency range, providing, by the data buffer integrated circuit, the second configuration parameter value to the first circuitry; and based on the second frequency being within the third frequency range, associating, by the data buffer integrated circuit and in place of the third frequency range, a fourth frequency range with the second configuration parameter value to be provided to the first circuitry, the fourth frequency range being larger than the third frequency range and the fourth frequency range including the second frequency.

[0079] Example 17: The method of example 16, wherein the first circuitry comprises a phase-locked loop having a first frequency lock range when provided with the first configuration parameter value and a second frequency lock range when provided with the second configuration parameter value, the first frequency lock range and the second frequency lock range being at least partially nonoverlapping.

[0080] Example 18: The method of example 16, further comprising: determining, by the data buffer integrated circuit, that the first frequency is not within a third frequency range associated with a second configuration parameter value to be provided to the first circuitry where the operational characteristic will be based on the second configuration parameter value; and based on the first frequency not being within the third frequency range, associating, by the data buffer integrated circuit and in place of the third frequency range, afourth frequency range with the second configuration parameter value to be provided to the first circuitry, the fourth frequency range being non-overlapping with the first frequency range.

[0081] Example 19: The method of example 18, further comprising: generating, by the data buffer integrated circuit, a measurement clock signal; determining, based on the measurement clock signal and by the data buffer integrated circuit, a first frequency indicator associated with the first reference clock signal; and determining, based on the measurement clock signal and by the data buffer integrated circuit, a second frequency indicator associated with the second reference clock signal.

[0082] Example 20: The method of example 19, wherein the data buffer integrated circuit generates the measurement clock signal using free-running oscillator circuitry.

[0083] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit, comprising: a first circuit having a performance characteristic that based on a combination of a first configuration parameter and a reference clock signal frequency; frequency band detection circuitry to, based on a first reference clock signal and a clock signal, determine that a first frequency of the first reference clock signal lies within a first configuration frequency range associated with a first configuration parameter value for the first configuration parameter and to determine that the first frequency of the first reference clock signal does not lie within a second configuration frequency range associated with a second configuration parameter value for the first configuration parameter, the first configuration parameter value and the second configuration parameter value to be not equal; and frequency band adjusting circuitry to, based on the first frequency being within the first configuration frequency range, select a first adjusted frequency range to be associated with the first configuration parameter value for the first configuration parameter.

2. The integrated circuit of claim 1, wherein the frequency band adjusting circuitry is to, based on the first frequency being within the first configuration frequency range, select a second adjusted frequency range to be associated with the second configuration parameter value for the first configuration parameter.

3. The integrated circuit of claim 1, wherein the first circuit comprises a phase-locked loop circuit.

4. The integrated circuit of claim 3, wherein the performance characteristic is a frequency lock range for the phase-locked loop circuit.

5. The integrated circuit of claim 1, further comprising: calibrated free-running oscillator circuitry to generate the clock signal.

6. The integrated circuit of claim 2, wherein the frequency band detection circuitry is to, based on a second reference clock signal and the clock signal, determine that a second frequency of the second reference clock signal lies within the second adjusted frequency range and to determine that the second frequency of the second reference clock signal does not lie within the first adjusted frequency range.

7. The integrated circuit of claim 1, wherein the performance characteristic further based on a combination of a second configuration parameter and the reference clock signal frequency, a host set value for the second configuration parameter to be provided by a host system coupled to a memory module that includes the integrated circuit.

8. A memory module, comprising: a first integrated circuit device to transmit a reference clock signal having a plurality of frequencies; and a second integrated circuit having a first circuit having an operational characteristic dependent on a first configuration parameter and the plurality of frequencies of the reference clock signal, the second integrated circuit also having first configuration parameter selection circuitry to, based on the reference clock signal having a first frequency that is within a first frequency range, select a first value for the first configuration parameter and select an adjusted first frequency range to be used by the first configuration parameter selection circuitry to select the first value for the first configuration parameter.

9. The memory module of claim 8, wherein the first configuration parameter selection circuitry is to, based on the reference clock signal having a second frequency that is within a second frequency range, select a second value for the first configuration parameter and select an adjusted second frequency range to be used by the first configuration parameter selection circuitry to select the second value for the first configuration parameter.

10. The memory module of claim 9, the first configuration parameter selection circuitry is to, based on the reference clock signal having a second frequency that is within the second frequency range, select a third frequency range to be used by the first configuration parameter selection circuitry to select the first value for the first configuration parameter, the third frequency range and the adjusted second frequency range to be nonoverlapping.

11. The memory module of claim 9, wherein the second frequency range and the first adjusted frequency range are to be non-overlapping.

12. The memory module of claim 8, wherein the first integrated circuit device is a registering clock driver integrated circuit.

13. The memory module of claim 12, wherein the second integrated circuit is a data buffer integrated circuit.

14. The memory module of claim 9, wherein the second integrated circuit further comprises oscillator circuitry to provide a clock signal that is to be used to determine whether the reference clock signal has a frequency that is within the first frequency range and to determine whether the reference clock signal has a frequency that is within the second frequency range.

15. A method, comprising: transmitting, by an address buffer integrated circuit and to a data buffer integrated circuit, a first reference clock signal having a first frequency; determining, by the data buffer integrated circuit, that the first frequency is within a first frequency range associated with a first configuration parameter value to be provided to first circuitry that has an operational characteristic that is based on the first configuration parameter value and the first frequency; based on the first frequency being within the first frequency range, providing, by the data buffer integrated circuit, the first configuration parameter value to the first circuitry; and based on the first frequency being within the first frequency range, associating, by the data buffer integrated circuit and in place of the first frequency range, a second frequency range with the first configuration parameter value to be provided to the first circuitry, the second frequency range being larger than the first frequency range and the second frequency range including the first frequency.

16. The method of claim 15, further comprising:transmitting, by the address buffer integrated circuit and to the data buffer integrated circuit, a second reference clock signal having a second frequency; determining, by the data buffer integrated circuit, that the second frequency is within a third frequency range associated with a second configuration parameter value to be provided to the first circuitry where the operational characteristic is based on the second configuration parameter value and the second frequency; based on the second frequency being within the third frequency range, providing, by the data buffer integrated circuit, the second configuration parameter value to the first circuitry; and based on the second frequency being within the third frequency range, associating, by the data buffer integrated circuit and in place of the third frequency range, a fourth frequency range with the second configuration parameter value to be provided to the first circuitry, the fourth frequency range being larger than the third frequency range and the fourth frequency range including the second frequency.

17. The method of claim 16, wherein the first circuitry comprises a phase-locked loop having a first frequency lock range when provided with the first configuration parameter value and a second frequency lock range when provided with the second configuration parameter value, the first frequency lock range and the second frequency lock range being at least partially nonoverlapping.

18. The method of claim 16, further comprising: determining, by the data buffer integrated circuit, that the first frequency is not within a third frequency range associated with a second configuration parameter value to be provided to the first circuitry where the operational characteristic will be based on the second configuration parameter value; and based on the first frequency not being within the third frequency range, associating, by the data buffer integrated circuit and in place of the third frequency range, a fourth frequency range with the second configuration parameter value to be provided to the first circuitry, the fourth frequency range being nonoverlapping with the first frequency range.

19. The method of claim 18, further comprising:generating, by the data buffer integrated circuit, a measurement clock signal; determining, based on the measurement clock signal and by the data buffer integrated circuit, a first frequency indicator associated with the first reference clock signal; and determining, based on the measurement clock signal and by the data buffer integrated circuit, a second frequency indicator associated with the second reference clock signal.

20. The method of claim 19, wherein the data buffer integrated circuit generates the measurement clock signal using free-running oscillator circuitry.

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