Semiconductor module, charger and electric vehicle

Abstract

The present application discloses a semiconductor module, a charger and an electric vehicle. The semiconductor module comprises: a first substrate area, a second substrate area and a third substrate area which extend along a same plane, the second substrate area and the third substrate area being located on a same side of the first substrate area, the first substrate area comprising a first region and a second region, and the second substrate area comprising a third region and a fourth region, and the third region being located between the second region and the fourth region; a switching circuit of a power factor correction circuit, which is formed on the first substrate area; a switching circuit of a resonant conversion circuit, comprising a switching circuit of a resonant conversion primary side circuit formed on the second region and a switching circuit of a resonant conversion secondary side circuit formed on the third region; and a switching circuit of a DC / DC conversion circuit, comprises a switching circuit of a DC / DC conversion primary side circuit formed on the fourth region and a switching circuit of a DC / DC conversion secondary side circuit formed on the third substrate area.

Description

Semiconductor modules, chargers, and electric vehicles

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202323667131.9 and application name “Semiconductor module for charger, charger and electric vehicle”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chargers, and in particular to a semiconductor module, a charger, and an electric vehicle. Background Art

[0003] Electric vehicles are increasingly popular in recent years due to their green and environmentally friendly nature, as they are charged using charging stations. However, the layout of the chargers in electric vehicles requires wiring harness management, which is complex due to the large number of wires.

[0004] In addition, the existing charger modules are arranged in a top-center-bottom arrangement, which takes up a lot of space and affects the aesthetics of the front cabin interior. Furthermore, the charger installation location has limited freedom of choice. Summary of the Invention

[0005] The purpose of the present application is to propose a semiconductor module, a charger and an electric vehicle, in which the various circuit modules of the semiconductor module are integrated into one module. Compared with the charger semiconductor module in the prior art in which the various circuit modules are divided into an upper, middle and lower structure and connected by a wiring harness, it not only avoids complex wiring harness connection and complex wiring harness management, but also takes up less space in the electric vehicle, provides a larger space for the maintenance of the charger and provides a greater freedom of space selection for the installation of the charger.

[0006] According to an embodiment of the present application, a semiconductor module includes: a first substrate area, a second substrate area, and a third substrate area, wherein the first substrate area, the second substrate area, and the third substrate area extend along the same plane, the second substrate area and the third substrate area are located on the same side of the first substrate area, the first substrate area includes a first region and a second region, the second substrate area includes a third region and a fourth region, and the third region is located between the second region and the fourth region; a switching circuit of a power factor correction circuit, wherein the switching circuit of the power factor correction circuit is formed on the first region of the first substrate area; and a switching circuit of a resonant conversion circuit, wherein the switching circuit of the resonant conversion circuit is formed on the first region of the first substrate area. The switching circuit of the resonant conversion circuit includes a switching circuit of the resonant conversion primary circuit and a switching circuit of the resonant conversion secondary circuit, the switching circuit of the resonant conversion primary circuit is formed on the second area, and the switching circuit of the resonant conversion secondary circuit is formed on the third area; the switching circuit of the DC / DC conversion circuit, the switching circuit of the DC / DC conversion circuit includes a switching circuit of the DC / DC conversion primary circuit and a switching circuit of the DC / DC conversion secondary circuit, the switching circuit of the DC / DC conversion primary circuit is formed on the fourth area, and the switching circuit of the DC / DC conversion secondary circuit is formed on the third substrate area.

[0007] A charger according to an embodiment of the present application includes: a semiconductor module according to the present application; a first capacitor, the first capacitor being included in the power factor correction circuit, and the two ends of the first capacitor being connected in parallel with the switching circuit of the resonant conversion primary circuit; a first transformer, the first transformer being connected between the switching circuit of the resonant conversion primary circuit and the switching circuit of the resonant conversion secondary circuit; and a second transformer, the second transformer being connected between the switching circuit of the DC / DC conversion primary circuit and the switching circuit of the DC / DC conversion secondary circuit.

[0008] An electric vehicle according to an embodiment of the present application includes the charger described in the present application.

[0009] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a schematic structural diagram of a semiconductor module according to an embodiment of the present application;

[0011] FIG2 is a top view of the semiconductor module shown in FIG1 ;

[0012] 3 is a top view of a first substrate region of the semiconductor module shown in FIG1 and a circuit structure provided on the first substrate region;

[0013] 4 is a top view of the second substrate region of the semiconductor module shown in FIG1 and a circuit structure provided on the second substrate region;

[0014] 5 is a top view of the third substrate region of the semiconductor module shown in FIG. 1 and a circuit structure provided on the third substrate region;

[0015] FIG6 is a schematic structural diagram of the first semiconductor chip and the third semiconductor chip shown in FIG1 ;

[0016] FIG7 is a schematic structural diagram of the second semiconductor chip as an FRD shown in FIG1 ;

[0017] FIG8 is a schematic structural diagram of the second semiconductor chip as an IGBT shown in FIG1 ;

[0018] FIG9 is a schematic structural diagram of the fourth semiconductor chip and the fifth semiconductor chip shown in FIG1 ;

[0019] FIG10 is a schematic structural diagram of the sixth semiconductor chip shown in FIG1 ;

[0020] FIG11 is a schematic structural diagram of the gate resistor shown in FIG1 ;

[0021] FIG12 is a schematic structural diagram of the thermistor shown in FIG1 ;

[0022] 13 is a schematic diagram of electrical connection lines when the first semiconductor chip or the third semiconductor chip is a SiC MOS chip;

[0023] 14 is a schematic diagram of electrical connection lines when the second semiconductor chip is an IGBT chip;

[0024] FIG15 is a schematic diagram of electrical connection lines when the fourth semiconductor chip is a Si MOS chip;

[0025] FIG16 is a schematic diagram of electrical connection lines when the fifth semiconductor chip is a Si MOS chip;

[0026] FIG17 is a schematic diagram of electrical connection lines when the sixth semiconductor chip is a Si MOS chip;

[0027] FIG18 is a schematic diagram of the electrical connection lines of the thermistor;

[0028] FIG19 is a schematic diagram of the electrical connection lines of the gate resistor;

[0029] FIG20 is a schematic topological diagram of a charger according to an embodiment of the present application;

[0030] FIG21 is a schematic block diagram of an electric vehicle according to an embodiment of the present application;

[0031] FIG22 is a schematic diagram of an electric vehicle according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following describes in detail embodiments of the present application, and the embodiments described with reference to the accompanying drawings are exemplary.

[0033] The following describes a semiconductor module 1000 according to an embodiment of the present application, with reference to Figures 1 to 19. This semiconductor module 1000 can be, for example, a semiconductor module for an on-board integrated charger. Semiconductor module 1000 can be installed in an electric vehicle charger and connected to an electric vehicle charging station via a charging cable, thereby charging the electric vehicle and providing energy for driving the electric vehicle.

[0034] 1-5 , a semiconductor module 1000 according to an embodiment of the present application includes a first substrate region 1, a second substrate region 2, and a third substrate region 3. The first, second, and third substrate regions 1, 2, and 3 extend along the same plane; in other words, the first, second, and third substrate regions 1, 2, and 3 are located in the same layer. Alternatively, the first, second, and third substrate regions 1, 2, and 3 may be different regions of the same substrate; or alternatively, the first, second, and third substrate regions 1, 2, and 3 may be defined on different substrates. For example, in either of these two optional cases, the substrate may be a ceramic copper-clad substrate, but is not limited thereto.

[0035] As shown in Figures 1-5 , the second substrate region 2 and the third substrate region 3 are located on the same side of the first substrate region 1. The first substrate region 1 includes a first area 11 and a second area 12, and the second substrate region 2 includes a third area 21 and a fourth area 22. The third area 21 is located between the second area 12 and the fourth area 22. For example, as shown in Figure 1 , the first substrate region 1 is located on the left side of the semiconductor module 1000, while the second substrate region 2 and the third substrate region 3 are located on the right side of the semiconductor module 1000. The third area 21 is located to the right of the second area 12, and the fourth area 22 is located to the right of the third area 21.

[0036] As shown in Figures 1-5, the semiconductor module 1000 further includes a switching circuit 40 for a power factor correction (PFC) circuit, a switching circuit 50 for a resonant conversion circuit (inductor-inductor-capacitor, LLC), and a switching circuit 60 for a DC / DC conversion circuit. Specifically, the switching circuit 40 for the power factor correction circuit is disposed on the first region 11 of the first substrate area 1. The switching circuit 50 for the resonant conversion circuit includes a switching circuit 501 for a primary resonant conversion circuit and a switching circuit 502 for a secondary resonant conversion circuit. The switching circuit 501 for the primary resonant conversion circuit is disposed on the second region 12, and the switching circuit 502 for the secondary resonant conversion circuit is disposed on the third region 21. The switching circuit 60 of the DC / DC conversion circuit includes a switching circuit 601 for the DC / DC conversion primary circuit and a switching circuit 602 for the DC / DC conversion secondary circuit. The switching circuit 601 for the DC / DC conversion primary circuit is disposed on the fourth region 22, and the switching circuit 602 for the DC / DC conversion secondary circuit is disposed on the third substrate region 3. It can be seen that the switching circuit 40 of the power factor correction circuit, the switching circuit 50 of the resonant conversion circuit, and the switching circuit 60 of the DC / DC conversion circuit are all integrated on a substrate region located on the same layer. Compared to the related art in which each circuit is disposed on a different module, these modules are arranged in a top-down order, and these modules are connected together by wiring harnesses to form a semiconductor module, the layout of the semiconductor module 1000 of the present application achieves a highly integrated design, avoids complex wiring harness connections and management, and is capable of operating in a high-power range.

[0037] The second substrate area 2 and the third substrate area 3 are located on the same side of the first substrate area 1 in the semiconductor module 1000. The switching circuit 40 of the power factor correction circuit is arranged on the first area 11 of the first substrate area 1. The switching circuit 501 of the resonant conversion primary circuit of the switching circuit 50 of the resonant conversion circuit is arranged on the second area 12 of the first substrate. The switching circuit 502 of the resonant conversion secondary circuit of the switching circuit 50 of the resonant conversion circuit is arranged on the third area 21 adjacent to the second area 12. The switching circuit 601 of the DC / DC conversion primary circuit of the switching circuit 60 of the DC / DC conversion circuit is arranged on the fourth area 22 adjacent to the third area 21. The switching circuit 602 of the DC / DC conversion secondary circuit is arranged on the third substrate area 3. The layout of the various circuits in these substrate areas achieves efficient utilization of the various areas in the first substrate area 1, the second substrate area 2, and the third substrate area 3, and realizes miniaturization of the semiconductor module 1000. This can reduce the space occupied by the entire semiconductor module 1000 and thereby reduce the space occupied by the entire charger. For example, when the semiconductor module 1000 is used in a charger, such as a charger for an electric vehicle, for example, the charger is installed in the front compartment of the electric vehicle. This can provide greater freedom of choice for the specific installation location of the charger including the semiconductor module 1000, and when a component in the charger is damaged, more space can be left in the front compartment to facilitate maintenance personnel to inspect the charger.

[0038] Therefore, according to the semiconductor module 1000 of the embodiment of the present application, through the above-mentioned layout of its various circuits, complex wiring harness connections and wiring harness management can be avoided, and the miniaturization of the entire charger can be achieved, occupying a small space, and the freedom of choice of its installation position is relatively high. Moreover, when installed on, for example, an electric vehicle, a larger maintenance space can be left for maintenance personnel when the charger needs maintenance, thereby facilitating the maintenance personnel's operation.

[0039] According to some embodiments of the present application, the first region 11 and the second region 12 are arranged along a first direction, the second region 12, the third region 21, and the fourth region 22 are arranged along a second direction perpendicular to the first direction, and the third substrate area 3 and the second substrate area 2 are arranged along the first direction. Taking Figures 1-5 as an example, along the first direction AA, in the first substrate area 1, the first region 11 and the second region 12 are arranged sequentially; the third substrate area 3 and the second substrate area 2 are arranged to the right of the first substrate area 1, and the third substrate area 3 and the second substrate area 2 are arranged sequentially along the first direction AA; the second region 12 of the first substrate area 1, the third region 21 of the second substrate area 2, and the fourth region 22 of the second substrate area 2 are arranged sequentially along the second direction BB perpendicular to the first direction AA. In other words, on the page showing Figure 1, the first region 11 is located above the second region 12, the third substrate area 3 and the second substrate area 2 are located to the right of the first region 11 and the second region 12, and the third substrate area 3 is located above the second substrate area 2. The third region 21 of the second substrate area 2 is located to the right of the second region 12 and to the left of the fourth region 22. With this arrangement, when the total areas of the first substrate area 1, the second substrate area 2 and the third substrate area 3 are the same, the size of the semiconductor module 1000 in any direction is avoided to be too large, which not only facilitates the layout of various circuits, but also makes it easier to flexibly select the installation position of the semiconductor module 1000 and the charger including the semiconductor module 1000 in an electric vehicle, such as the front cabin of an electric vehicle.

[0040] Optionally, as shown in FIG. 1 to FIG. 5 , the first substrate region 1 , the second substrate region 2 and the third substrate region 3 all have a substantially rectangular shape.

[0041] Optionally, in the case where the first substrate region 1 , the second substrate region 2 and the third substrate region 3 are formed on the same substrate, the substrate also substantially has a rectangular shape.

[0042] According to some optional embodiments of the present application, referring to Figures 1-5, the first region 11 includes a first sub-region 111 and a second sub-region 112 arranged along a first direction, with the second sub-region 112 located between the first sub-region 111 and the second region 12. For example, in Figures 1-3, the first sub-region 111, the second sub-region 112, and the second region 12 are arranged sequentially along the first direction AA. The switch circuit 40 of the power factor correction circuit includes multiple pairs of first semiconductor chips 41. These multiple pairs of first semiconductor chips 41 are located in the first sub-region 111 and arranged sequentially along the second direction BB. The two first semiconductor chips 41 in each pair of first semiconductor chips 41 are spaced apart along the second direction BB and connected in series with each other. With this arrangement, the multiple pairs of first semiconductor chips 41 in the first sub-region 111 implement the PFC fast tube function, and the overall layout of the various semiconductor chips in the switch circuit 40 of the power factor correction circuit is regular.

[0043] For example, as shown in Figures 1-3, each source of the multiple pairs of first semiconductor chips 41 is electrically connected to a respective first source signal detection terminal 1a (e.g., detection pin) via an electrical connection line 7 (e.g., a bonding wire). The first source signal detection terminal 1a is used to detect the signal at the source of the first semiconductor chip 41. In addition, the gates of the multiple pairs of first semiconductor chips 41 are electrically connected to respective first gate signal detection terminals 1b via the electrical connection line 7. The first gate signal detection terminals 1b are used to detect the signal at the gate of the first semiconductor chip 41. The first source signal detection terminals 1a are arranged at intervals along the second direction BB on the first sub-region 111. The first gate signal detection terminals 1b are arranged at intervals along the second direction BB on the first sub-region 111 and are spaced apart from the first source signal detection terminals 1a in the first direction AA. For example, as shown in Figures 1-3, the first source signal detection terminals 1a are arranged in a row along the second direction BB, and the first gate signal detection terminals 1b are arranged in a row along the second direction BB, with the first source signal detection terminals 1a being located on a side of the first gate signal detection terminals 1b that is away from the second region 12. Thus, the arrangement of the first source signal detection terminals 1a and the first gate signal detection terminals 1b is relatively regular, facilitating the installation of these detection terminals and ensuring a relatively regular connection between the first source signal detection terminals 1a and the source of the first semiconductor chip 41, as well as between the first gate signal detection terminals 1b and the gate of the first semiconductor chip 41. Due to the regular arrangement of the signal detection terminals and the relatively regular connection between the signal detection terminals and the chips, the internal structure of the semiconductor module 1000 is neatly laid out.

[0044] According to some embodiments of the present application, as shown in Figures 1 to 3, the semiconductor module 1000 also includes a plurality of first power signal positive DC transmission terminals 1c, 1e, and a first power signal AC terminal 1d for each pair of first semiconductor chips 41 located in the first sub-region 111, wherein, in each pair of first semiconductor chips 41, the source of one first semiconductor chip 41 is connected to the drain of another first semiconductor chip 41 through an electrical connection line 7, the drain of the one first semiconductor chip 41 is electrically connected to one of the multiple first power signal positive DC transmission terminals 1c, the source of the other first semiconductor chip 41 is electrically connected to the first power signal negative DC transmission terminal 1e among the multiple first power signal positive DC transmission terminals, and the first power signal AC terminal 1d is connected between the source of the one first semiconductor chip 41 and the drain of the other first semiconductor chip 41. With such a setting, it is possible to provide an AC signal to each pair of first semiconductor chips 41 through the first power signal AC terminal 1d, provide a DC input to the pair of first semiconductor chips 41 through the first power signal positive DC transmission terminal 1c and the first power signal negative DC transmission terminal 1e, and obtain a DC output of the pair of first semiconductor chips 41, thereby realizing the circuit function.

[0045] According to some embodiments of the present application, with reference to Figures 1 to 12, the switching circuit 40 of the power factor correction circuit also includes multiple pairs of second semiconductor chips 42 located in the second sub-area 112, and the two second semiconductor chips 42 in the same pair of second semiconductor chips 42 are connected in parallel, one of the two second semiconductor chips 42 is an IGBT (Insulated gate bipolar transistor) chip, and the other of the two second semiconductor chips 42 is an FRD (Fast recovery diode) chip, and different pairs of second semiconductor chips 42 are connected in series in sequence. For example, the drain of the IGBT chip is connected to the positive electrode of the FRD chip, and the source of the IGBT is connected to the negative electrode of the FRD. In this way, the multiple pairs of second semiconductor chips 42 in the second sub-area 112 realize the PFC slow tube function, and the multiple pairs of second semiconductor chips 42 in the second sub-area 112 realize the PFC slow tube function.

[0046] According to some embodiments of the present application, referring to FIG1-FIG3 , the source of one second semiconductor chip 42 in each pair of second semiconductor chips 42 is electrically connected to a second source signal detection terminal 2a located in the second sub-region 112 via an electrical connection line 7, and the gate of one second semiconductor chip 42 in each pair of second semiconductor chips 42 is electrically connected to a second gate signal detection terminal 2b located in the second sub-region 112 via an electrical connection line 7. Specifically, in the example of FIG1 , the source of the IGBT chip is connected to a second source signal detection terminal 2a located in the second sub-region 112. The second source signal detection terminal 2a is used to detect a signal at the source of the IGBT chip and can also detect a signal at the negative electrode of an FRD connected in parallel with the IGBT. The gate of the IGBT chip is connected to a second gate signal detection terminal 2b located in the second sub-region 112. The second gate signal detection terminal 2b is used to detect a signal at the gate of the IGBT chip.

[0047] As shown in Figures 1 to 3, the semiconductor module 1000 also includes a second power signal AC terminal 2d and a plurality of second power signal negative DC transmission terminals 2c and 2e for the multiple pairs of second semiconductor chips 42 located in the first area 11. One of the second power signal positive DC transmission terminals 2c among the multiple second power signal negative DC transmission terminals in the first area 11 is electrically connected to the drain of the second semiconductor chip 42 in the first pair of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series, and one of the second power signal negative DC transmission terminals 2e is electrically connected to the source of the second semiconductor chip 42 in the last pair of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series. The second power signal AC terminal 2d is connected between two adjacent pairs of second semiconductor chips 42 among the multiple pairs of second semiconductor chips 42 connected in series.

[0048] According to some embodiments of the present application, as shown in Figures 1-12, the first semiconductor chip 41 is a MOS chip, the multiple pairs of first semiconductor chips 41 are three pairs of first semiconductor chips 41, and the multiple pairs of second semiconductor chips 42 are two pairs of second semiconductor chips 42. It is understood that the number of the multiple pairs of first semiconductor chips 41 is not limited to three, and the number of the multiple pairs of second semiconductor chips 42 is not limited to two. For the sake of brevity, this application does not provide examples one by one.

[0049] By way of example, the first semiconductor chip 41 is a SiC MOS chip.

[0050] According to some embodiments of the present application, referring to Figures 1-4 , the switch circuit 501 of the resonant conversion primary circuit includes multiple pairs of third semiconductor chips 511, with the two third semiconductor chips 511 in each pair 511 connected in series. The switch circuit 502 of the resonant conversion secondary circuit includes multiple pairs of fourth semiconductor chips 521, with the two fourth semiconductor chips 521 in each pair 521 connected in series. The switch circuit 501 of the resonant conversion primary circuit and the switch circuit 502 of the resonant conversion secondary circuit together constitute the switch circuit 50 of the resonant conversion circuit.

[0051] According to some embodiments of the present application, referring to Figures 1-4, each source of the multiple pairs of third semiconductor chips 511 is electrically connected to a respective third source signal detection terminal 3a located in the second region 12 via an electrical connection line 7. The third source signal detection terminal 3a is used to detect the signal of the source of the third semiconductor chip 511. Each gate of the multiple pairs of third semiconductor chips 511 is electrically connected to a respective third gate signal detection terminal 3b located in the second region 12 via an electrical connection line 7. The third gate signal detection terminal 3b is used to detect the signal of the gate of the third semiconductor chip 511. Each source of the multiple pairs of fourth semiconductor chips 521 is electrically connected to a respective fourth source signal detection terminal 4a located in the third region 21 via an electrical connection line 7. The fourth source signal detection terminal 4a is used to detect the signal of the source of the fourth semiconductor chip 521. Each gate of the plurality of pairs of fourth semiconductor chips 521 is electrically connected to a respective fourth gate signal detection terminal 4 b located in the third region 21 via an electrical connection line 7 . The fourth gate signal detection terminal 4 b is used to detect a signal of the gate of the fourth semiconductor chip 521 .

[0052] According to some embodiments of the present application, as shown in FIG1-FIG4 , the semiconductor module 1000 further includes a third power signal AC terminal 3d and a plurality of third power signal negative DC transmission terminals 3c and 3e for each pair of third semiconductor chips 511 located in the second region 12. In each pair of third semiconductor chips 511, the source of one third semiconductor chip 511 is connected to the drain of another third semiconductor chip 511 via an electrical connection line 7, the drain of the one third semiconductor chip 511 is electrically connected to one third power signal positive DC transmission terminal 3c among the plurality of third power signal negative DC transmission terminals, the source of the other third semiconductor chip 511 is electrically connected to one third power signal negative DC transmission terminal 3e among the plurality of third power signal negative DC transmission terminals, and the third power signal AC terminal 3d is connected between the source of the one third semiconductor chip 511 and the drain of the other third semiconductor chip 511. With such a configuration, it is possible to provide an AC signal to each pair of third semiconductor chips 511 through the third power signal AC terminal 3d, provide a DC input to the pair of third semiconductor chips 511 through the third power signal positive DC transmission terminal 3c and the third power signal negative DC transmission terminal 3e, and obtain a DC output for the pair of third semiconductor chips 511.

[0053] According to some embodiments of the present application, as shown in FIG1-3 , the semiconductor module 1000 further includes a fourth power signal AC terminal 4 d and a plurality of fourth power signal positive DC transmission terminals 4 c and 4 e for each pair of fourth semiconductor chips 521 located in the third region 21. In each pair of fourth semiconductor chips 521, the source of one fourth semiconductor chip 521 is connected to the drain of another fourth semiconductor chip 521 via an electrical connection line 7 , the drain of the one fourth semiconductor chip 521 is electrically connected to one fourth power signal positive DC transmission terminal 4 c among the plurality of fourth power signal positive DC transmission terminals, the source of the other fourth semiconductor chip 521 is electrically connected to one fourth power signal negative DC transmission terminal 4 e among the plurality of fourth power signal positive DC transmission terminals, and the fourth power signal AC terminal 4 d is connected between the source of the one fourth semiconductor chip 521 and the drain of the other fourth semiconductor chip 521 . With such a configuration, it is possible to provide an AC signal to each pair of fourth semiconductor chips 521 through the fourth power signal AC terminal 4d, provide a DC input to the pair of fourth semiconductor chips 521 through the fourth power signal positive DC transmission terminal 4c and the fourth power signal negative DC transmission terminal 4e, and obtain a DC output for the pair of fourth semiconductor chips 521.

[0054] According to some embodiments of the present application, as shown in Figures 1-12, the multiple pairs of third semiconductor chips 511 are two pairs of third semiconductor chips 511, and the multiple pairs of fourth semiconductor chips 521 are two pairs of fourth semiconductor chips 521. The third semiconductor chips 511 and the fourth semiconductor chips 521 are MOS chips. It is understood that the number of the multiple pairs of third semiconductor chips 511 is not limited to two pairs, and the number of the multiple pairs of fourth semiconductor chips 521 is not limited to two pairs. For the purpose of brevity, this application does not provide examples one by one.

[0055] By way of example, the third semiconductor chip 511 is a SiC MOS chip, and the fourth semiconductor chip 521 is a Si MOS chip.

[0056] According to some embodiments of the present application, the switching circuit 601 of the DC / DC conversion main side circuit includes multiple pairs of fifth semiconductor chips 611, and the two fifth semiconductor chips 611 in each pair of fifth semiconductor chips 611 are connected in series with each other, wherein the source of one of the two fifth semiconductor chips 611 is connected to the drain of the other fifth semiconductor chip 611.

[0057] For example, according to some embodiments of the present application, each source electrode in the multiple pairs of fifth semiconductor chips 611 is electrically connected to a fifth source signal detection terminal 5a located in the fourth region 22 via an electrical connection line 7. The fifth source signal detection terminal 5a is used to detect the signal of the source electrode of the fifth semiconductor chip 611. Each gate electrode in the multiple pairs of fifth semiconductor chips 611 is electrically connected to a fifth gate signal detection terminal 5b located in the fourth region 22 via an electrical connection line 7. The fifth gate signal detection terminal 5b is used to detect the signal of the gate electrode of the fifth semiconductor chip 611.

[0058] According to some embodiments of the present application, as shown in Figures 1-5, a switch circuit 602 of a secondary-side DC / DC converter circuit includes a first group of gate resistors 621, a first group of sixth semiconductor chips 622, a second group of gate resistors 623, and a second group of sixth semiconductor chips 624 arranged along a first direction AA. The number of sixth semiconductor chips 6221 in each group of sixth semiconductor chips is equal to the number of gate resistors in each group of gate resistors. The sixth semiconductor chips 6221 in the first group of sixth semiconductor chips 622 are arranged at intervals along a second direction BB. The gate resistors in the first group of gate resistors 621 are arranged at intervals along the second direction BB. Each sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622 is connected in series with a corresponding gate resistor in the first group of gate resistors 621 to form a first chip-gate resistor pair 625. Each first chip-gate resistor pair 625 is connected in parallel with each other. The sixth semiconductor chips 6221 in the second group of sixth semiconductor chips 624 are spaced apart along the second direction BB. The gate resistors in the second group of gate resistors 623 are spaced apart along the second direction BB. Each sixth semiconductor chip 6221 in the second group of sixth semiconductor chips 624 is connected in series with a corresponding gate resistor in the second group of gate resistors 623 to form a second chip-gate resistor pair 626. Each second chip-gate resistor pair 626 is connected in parallel with each other. This arrangement provides a more regular arrangement of the components of the switching circuit of the secondary DC / DC converter circuit, facilitating the wiring of the switching circuit of the secondary DC / DC converter circuit and thus facilitating the manufacture of the semiconductor module 1000 and the entire charger. Furthermore, the gate resistors protect the gates of the sixth semiconductor chips 6221, achieving current sharing. This prevents large oscillations in the sixth semiconductor chip 6221 during its on / off operation, thereby ensuring circuit stability of the charger including the semiconductor module 1000.

[0059] For example, in FIG1 , a first group of gate resistors 621 is arranged in a row along the second direction BB, a first group of sixth semiconductor chips 622 is arranged in a row along the second direction BB, a second group of gate resistors 623 is arranged in a row along the second direction BB, and a second group of sixth semiconductor chips 624 is arranged in a row along the second direction BB. In each first chip-gate resistor pair 625 and each second chip-gate resistor pair 626, one end of the gate resistor is connected to the gate of the sixth semiconductor chip 6221, while the other ends of the gate resistors in different first chip-gate resistor pairs 625 are electrically connected to each other via electrical connection lines 7, and the other ends of the gate resistors in different second chip-gate resistor pairs 626 are electrically connected to each other via electrical connection lines 7.

[0060] According to some embodiments of the present application, the fifth semiconductor chip 611 is a MOS chip, the sixth semiconductor chip 6221 is a MOS chip, the first group of sixth semiconductor chips 622 and the second group of sixth semiconductor chips 624 each include four sixth semiconductor chips 6221, and the multiple pairs of fifth semiconductor chips 611 constitute two pairs of fifth semiconductor chips 611. It will be understood that the number and type of the fifth semiconductor chips and the sixth semiconductor chips 6221 are not limited thereto, and for the sake of brevity, this application does not provide examples one by one.

[0061] By way of example, the fifth semiconductor chip 611 is a Si MOS chip, and the sixth semiconductor chip 6221 is a Si MOS chip.

[0062] According to some embodiments of the present application, referring to Figures 1-5, a semiconductor module 1000 includes a fifth power signal AC terminal 5d and a plurality of fifth power signal positive DC transmission terminals 5c and 5e for each pair of fifth semiconductor chips 611. One of the plurality of fifth power signal positive DC transmission terminals 5c is connected to the drain of one of the fifth semiconductor chips 611, one of the plurality of fifth power signal negative DC transmission terminals 5e is connected to the source of another fifth semiconductor chip 611, and the fifth power signal AC terminal 5d is connected between the source of one of the fifth semiconductor chips and the drain of the other fifth semiconductor chip 611. This configuration enables, for each pair of fifth semiconductor chips 611, an AC signal to be provided to the pair of fifth semiconductor chips 611 via the first power signal AC terminal 1d, and a DC input and a DC output to be provided to the pair of fifth semiconductor chips 611 via the fifth power signal positive DC transmission terminal 5c and the fifth power signal negative DC transmission terminal 5e.

[0063] According to some embodiments of the present application, referring to Figures 1-5 , the switch circuit 60 of the DC / DC converter circuit includes a first DC electrode output terminal 6a, a second DC electrode output terminal 6b, and a third DC electrode output terminal 6c. The first DC electrode output terminal 6a, the second DC electrode output terminal 6b, and the third DC electrode output terminal 6c are located on the third substrate region 3 and spaced apart along the first direction. The first DC electrode output terminal 6a is electrically connected to the drain of the sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622, the second DC electrode output terminal 6b is electrically connected to the source of the sixth semiconductor chip 6221 in the first group of sixth semiconductor chips 622 and the second group of sixth semiconductor chips 624, and the third DC electrode output terminal 6c is electrically connected to the drain of the sixth semiconductor chip 6221 in the second group of sixth semiconductor chips 624. The second DC electrode output terminal 6b is configured to connect to a transformer external to the semiconductor module 1000. After being connected to the transformer, the second DC electrode output terminal 6b outputs its output signal to the power battery.

[0064] Further, referring to Figures 1 to 5, a first DC signal detection terminal 10a, a second DC signal detection terminal 10b, and a third DC signal detection terminal 10c are provided in the third substrate area 3. The first DC signal detection terminal 10a, the second DC signal detection terminal 10b, and the third DC signal detection terminal 10c are electrically connected to the first DC electrode output terminal 6a, the second DC electrode output terminal 6b, and the third DC electrode output terminal 6c, respectively, and detect the DC signals at these output terminals accordingly.

[0065] According to some embodiments of the present application, referring to Figures 1 to 5, the semiconductor module 1000 further includes a thermistor 8 respectively arranged on the first substrate area 1, the second substrate area 2, and the third substrate area 3. At least two thermistor terminals 9 are respectively provided on the first substrate area 1, the second substrate area 2, and the third substrate area 3. The two thermistor terminals 9 in the first substrate area 1, the second substrate area 2, and the third substrate area 3 are respectively connected to the two ends of the corresponding thermistor 8.

[0066] Further, referring to Figures 1 to 5, a thermistor 8 is provided in each of the first substrate area 1, the second substrate area 2 and the third substrate area 3, and the two ends of each thermistor 8 are respectively connected to corresponding thermistor terminals 9, thereby realizing the detection of the temperature conditions of the first substrate area 1, the second substrate area 2 and the third substrate area 3.

[0067] For details on the electrical connections between the various components in semiconductor module 1000, see Figures 13 to 19 . Specifically, the source S and gate G of the SiC MOS chip are electrically connected, the source S and gate G of the IGBT chip are electrically connected, the source S and gate G of the Si MOS chip are electrically connected, the two ends of the thermistor 8 are electrically connected, and the two ends of the gate resistor are electrically connected.

[0068] According to some embodiments of the present application, as shown in Figures 1 and 2 , thermistors 8 in the first substrate area 1 are located on a side of the first region 11 near the second and third substrate areas 2 and 3. Thermistors 8 in the second substrate area 2 are located on a side of the second substrate area 2 near the third substrate area 3. Thermistors 8 in the third substrate area 3 are located on a side of the third substrate area 3 near the second substrate area 2. Compared to prior art thermistors located on the housing of a semiconductor module or a charger, the thermistors 8 of the present application are located on the semiconductor substrate, resulting in a more accurate measurement closer to the junction temperature of the circuitry in the semiconductor module.

[0069] According to an embodiment of the second aspect of the present application, a charger 2000, with reference to FIG20 and in combination with FIG1-FIG19, includes: a semiconductor module 1000 according to any embodiment of the first aspect of the present application and a first capacitor C1, wherein the first capacitor C1 is included in a power factor correction circuit, and the two ends of the first capacitor C1 are connected in parallel with the switch circuit 501 of the resonant converter primary circuit. The charger 2000 also includes a first transformer T1, which is connected between the switch circuit 501 of the resonant converter primary circuit and the switch circuit 502 of the resonant converter secondary circuit. The charger 2000 also includes a second transformer T2, which is connected between the switch circuit 601 of the DC / DC converter primary circuit and the switch circuit 602 of the DC / DC converter secondary circuit.

[0070] Therefore, the charger 2000 according to the embodiment of the present application, by including the above-mentioned semiconductor module, can avoid complex wiring harness connection and wiring harness management, and can realize the miniaturization of the entire charger 2000, occupying a small space, and having a high freedom of choice of its installation position. Moreover, when installed on, for example, an electric vehicle, when the charger 2000 needs maintenance, a larger maintenance space can be left for maintenance personnel, thereby facilitating the operation of the maintenance personnel.

[0071] According to some embodiments of the present application, referring to FIG. 20 , the plurality of pairs of third semiconductor chips 511 comprise two pairs of third semiconductor chips 511, and the plurality of pairs of fourth semiconductor chips 521 comprise two pairs of fourth semiconductor chips 521. The charger 2000 further includes a first inductor L1, a second capacitor C2, a second inductor L2, and a third capacitor C3. A first end of the first inductor L1 is connected between two third semiconductor chips 511 in one pair of the two pairs of third semiconductor chips 511, and a second end of the first inductor L1 is connected to a first end of the primary coil T11 of the first transformer T1. A first end of the second capacitor C2 is connected between two third semiconductor chips 511 in the other pair of the two pairs of third semiconductor chips 511, and a second end of the second capacitor C2 is connected to a second end of the primary coil T11 of the first transformer T1. A first end of the second inductor L2 is connected between the two fourth semiconductor chips 521 of one pair of the two pairs of fourth semiconductor chips 521, and a second end of the second inductor L2 is connected to the first end of the secondary winding T12 of the first transformer T1. A first end of the third capacitor C3 is connected between the two fourth semiconductor chips 521 of the other pair of the two pairs of fourth semiconductor chips 521, and a second end of the third capacitor C3 is connected to the second end of the secondary winding T12 of the first transformer T1.

[0072] For example, referring to FIG. 20 , the charger 2000 further includes a fourth capacitor C4 , which is connected in parallel to the switch circuit 502 of the resonant conversion secondary circuit.

[0073] According to some embodiments of the present application, referring to FIG. 20 and in combination with FIG. 1-FIG . 2 , the charger 2000 further includes: a third inductor L3 , wherein a first end of the third inductor L3 is connected to the secondary coil T22 of the second transformer T2 , and a second end of the third inductor L3 is connected between the first group of sixth semiconductor chips 622 and the second group of sixth semiconductor chips 624 .

[0074] According to some embodiments of the present application, referring to FIG. 20 in conjunction with FIG. 1 and FIG. 2 , the plurality of pairs of first semiconductor chips 41 include a first pair of first semiconductor chips 41, a second pair of first semiconductor chips 41, and a third pair of first semiconductor chips 41. The charger 2000 further includes a fourth inductor L4, a fifth inductor L5, and a sixth inductor L6. A first end of the fourth inductor L4 is connected to the external power grid, and the other end of the fourth inductor L4 is connected between the two first semiconductor chips 41 of the first pair of first semiconductor chips 41. A first end of the fifth inductor L5 is connected to the external power grid, and the other end of the fifth inductor L5 is connected between the two first semiconductor chips 41 of the second pair of first semiconductor chips 41. Furthermore, a first end of the sixth inductor L6 is connected to the external power grid, and the other end of the sixth inductor L6 is connected between the two first semiconductor chips 41 of the third pair of first semiconductor chips 41.

[0075] The electric vehicle 3000 according to the embodiment of the third aspect of the present application, as shown in FIG21 , includes the charger 2000 according to any one of the embodiments of the second aspect of the present application.

[0076] Therefore, the electric vehicle 3000 according to the embodiment of the present application can avoid complicated wiring harness connection and wiring harness management by including the charger 2000 according to the embodiment of the first aspect of the present application. The freedom of selection of the installation position on the electric vehicle 3000 is relatively high, and when the charger 1000 needs to be repaired, a larger maintenance space can be left for the maintenance personnel, which is convenient for the maintenance personnel to operate.

[0077] According to some embodiments of the present application, as shown in FIG. 22 , electric vehicle 3000 further includes an electronic control system 5000 and a battery 4000. The electronic control system 5000 is connected to a charger 2000 and battery 4000, which in turn is connected to battery 4000. The electronic control system 5000 can monitor the status of battery 4000 and control the charging parameters of charger 2000 based on the status of battery 4000. Charger 2000 then charges the battery according to the charging parameters. Because the various circuit modules of the semiconductor module in charger 2000 are integrated into a single module, the space occupied by the semiconductor module, and thus the space occupied by charger 2000, is effectively reduced. This provides more space for battery 4000 and electronic control system 5000, allowing for the installation of larger capacity batteries, thereby increasing the range of electric vehicle 3000. Furthermore, the electronic components and heat dissipation system provided by electronic control system 5000 can improve the performance and reliability of electronic control system 5000.

[0078] For example, the electronic control system 5000 may include a battery management system (BMS), which is used to monitor the status of the battery 4000, such as voltage, current, temperature, charging status, etc. The battery management system can also communicate with the charger 2000 to enable the charger 2000 to adjust charging parameters.

[0079] The electronic control system may also include a vehicle control unit (VCU), which is responsible for overall vehicle management and coordination, including powertrain control, energy management, regenerative braking, thermal management, etc. It may also include a motor controller, which controls the operation of the drive motor, including regulating current and voltage to control the motor's speed and torque.

[0080] It should be noted that the above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Any technical personnel in this field, without departing from the scope of the technical solution of the present application, may make any brief modifications, equivalent changes and modifications to the above embodiments based on the technical essence of the present application, which are still within the scope of the technical solution of the present application.

[0081] In the description of this application, the terms "comprise", "include" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The term "or" and its variations may refer to "and / or". In the embodiments of this application, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. In the embodiments of this application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0082] It should be understood that the terms "center", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "horizontal", "longitudinal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0083] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0084] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0085] Reference numerals:

[0086] Semiconductor module 1000; first substrate region 1; second substrate region 2; third substrate region 3;

[0087] A first semiconductor chip 41; a second semiconductor chip 42; a third semiconductor chip 511; and a fourth semiconductor chip 521;

[0088] Fifth semiconductor chip 611; first group of gate resistors 621; first group of sixth semiconductor chips 622; second group of gate resistors 623; second group of sixth semiconductor chips 624; sixth semiconductor chip 6221; first chip-gate resistor pair 625; second chip-gate resistor pair 626; first direction AA; second direction BB;

[0089] Electrical connection line 7; first source signal detection terminal 1a; first gate signal detection terminal 1b; first power signal positive DC transmission terminals 1c, 1e; first power signal AC terminal 1d;

[0090] Second source signal detection terminal 2a; second gate signal detection terminal 2b; second power signal positive DC transmission terminals 2c, 2e; second power signal AC terminal 2d;

[0091] A third source signal detection terminal 3a; a third gate signal detection terminal 3b; third power signal positive DC transmission terminals 3c, 3e; a third power signal AC terminal 3d;

[0092] Fourth source signal detection terminal 4a; fourth gate signal detection terminal 4b; fourth power signal positive DC transmission terminals 4c, 4e, fourth power signal AC terminal 4d;

[0093] A fifth source signal detection terminal 5a; a fifth gate signal detection terminal 5b; fifth power signal positive DC transmission terminals 5c, 5e; a fifth power signal AC terminal 5d;

[0094] First DC electrode output terminal 6a, second DC electrode output terminal 6b; third DC electrode output terminal 6c;

[0095] Thermistor 8; thermistor terminal 9; first DC signal detection terminal 10a; second DC signal detection terminal 10b; third DC signal detection terminal 10c;

[0096] First capacitor C1; first transformer T1; primary coil T11 of the first transformer; secondary coil T12 of the first transformer; second transformer T2; primary coil T21 of the second transformer; secondary coil T22 of the second transformer; first inductor L1; second capacitor C2; second inductor L2; third capacitor C3; fourth capacitor C4; third inductor L3; fourth inductor L4; fifth inductor L5; sixth inductor L6; charger 2000; electric vehicle 3000.

Claims

1. A semiconductor module, comprising: A first substrate region (1), a second substrate region (2), and a third substrate region (3), the first substrate region (1), the second substrate region (2), and the third substrate region (3) extending along the same plane, the second substrate region (2) and the third substrate region (3) being located on the same side of the first substrate region (1), the first substrate region (1) including a first region (11) and a second region (12), the second substrate region (2) including a third region (21) and a fourth region (22), the third region (21) being located between the second region (12) and the fourth region (22); A switching circuit (40) of a power factor correction circuit, the switching circuit (40) of the power factor correction circuit being disposed on the first region (11) of the first substrate region (1); A switching circuit (50) of a resonant conversion circuit, the switching circuit (50) of the resonant conversion circuit including a switching circuit (501) of a resonant conversion primary side circuit and a switching circuit (502) of a resonant conversion secondary side circuit, the switching circuit (501) of the resonant conversion primary side circuit being disposed on the second region (12), and the switching circuit (502) of the resonant conversion secondary side circuit being disposed on the third region (21); A switching circuit (60) of a DC / DC conversion circuit, the switching circuit (60) of the DC / DC conversion circuit including a switching circuit (601) of a DC / DC conversion primary side circuit and a switching circuit (602) of a DC / DC conversion secondary side circuit, the switching circuit (601) of the DC / DC conversion primary side circuit being disposed on the fourth region (22), and the switching circuit (602) of the DC / DC conversion secondary side circuit being disposed on the third substrate region (3).

2. The semiconductor module according to claim 1, wherein The first region (11) and the second region (12) are disposed along a first direction (AA), the second region (12), the third region (21), and the fourth region (22) are disposed along a second direction (BB) perpendicular to the first direction (AA), and the third substrate region (3) and the second substrate region (2) are disposed along the first direction (AA).

3. The semiconductor module according to claim 1 or 2, wherein, The first region (11) includes a first sub-region (111) and a second sub-region (112) arranged along the first direction (AA), and the second sub-region (112) is located between the first sub-region (111) and the second region (12). Wherein, the switching circuit (40) of the power factor correction circuit includes multiple pairs of first semiconductor chips (41), the multiple pairs of first semiconductor chips (41) are located in the first sub-region (111) and are sequentially arranged along the second direction (BB), and the two first semiconductor chips (41) in each pair of first semiconductor chips (41) are spaced apart along the second direction (BB) and are connected in series with each other.

4. The semiconductor module according to claim 3, wherein, Each of the sources of the multiple pairs of first semiconductor chips (41) is electrically connected to respective first source signal detection terminals (1a) through electrical connection lines (7). Each of the gates of the multiple pairs of first semiconductor chips (41) is electrically connected to respective first gate signal detection terminals (1b) through electrical connection lines. Each of the first source signal detection terminals (1a) is arranged at intervals along the second direction (BB) on the first sub-region (111). Each of the first gate signal detection terminals (1b) is arranged at intervals along the second direction (BB) on the first sub-region (111) and is spaced apart from each of the first source signal detection terminals (1a) in the first direction (AA).

5. The semiconductor module according to claim 3 or 4, wherein, The semiconductor module further includes first power signal AC terminals (1d) for each pair of first semiconductor chips (41) and a plurality of first power signal DC transmission terminals (1c / 1e) located in the first sub-region (111). Among each pair of first semiconductor chips (41), the source of one of the first semiconductor chips (41) is connected to the drain of the other first semiconductor chip (41) through an electrical connection line (7). The drain of the one first semiconductor chip (41) is electrically connected to one of the plurality of first power signal DC transmission terminals (1c / 1e). The source of the other first semiconductor chip (41) is electrically connected to another one of the plurality of first power signal DC transmission terminals (1c / 1e). The first power signal AC terminal (1d) is connected between the source of the one first semiconductor chip (41) and the drain of the other first semiconductor chip (41).

6. The semiconductor module according to any one of claims 3 to 5, wherein, The switching circuit (40) of the power factor correction circuit further includes multiple pairs of second semiconductor chips (42) located in the second sub-region (112). Two second semiconductor chips (42) in the same pair of second semiconductor chips (42) are connected in parallel. One of the two second semiconductor chips (42) is an IGBT (Insulated gate bipolar transistor) chip, and the other of the two second semiconductor chips (42) is an FRD (Fast recovery diode) chip. Different pairs of second semiconductor chips (42) are connected in series.

7. The semiconductor module according to claim 6, wherein, The source of one of the second semiconductor chips (42) in each pair of second semiconductor chips (42) is electrically connected to a second source signal detection terminal (2a) located in the second sub-region (112) through an electrical connection line (7). The gate of one of the second semiconductor chips (42) in each pair of second semiconductor chips (42) is electrically connected to a second gate signal detection terminal (2b) located in the second sub-region (112) through an electrical connection line (7).

8. The semiconductor module according to claim 6 or 7, wherein The semiconductor module further includes a second power signal AC terminal (2d) for the multiple pairs of second semiconductor chips (42) and a plurality of second power signal DC transmission terminals (2c / 2e) located in the first region (11). One of the plurality of second power signal DC transmission terminals (2c / 2e) in the first region (11) is electrically connected to the drain of the first pair of second semiconductor chips (42) connected in series in sequence among the multiple pairs of second semiconductor chips (42), and the other of the plurality of second power signal DC transmission terminals (2c / 2e) is electrically connected to the source of the last pair of second semiconductor chips (42) connected in series in sequence among the multiple pairs of second semiconductor chips (42). The second power signal AC terminal (2d) is connected between adjacent pairs of the multiple pairs of second semiconductor chips (42) connected in series.

9. The semiconductor module according to any one of claims 6 - 8, wherein, The first semiconductor chip (41) is a MOS chip. The multiple pairs of first semiconductor chips (41) are 3 pairs of first semiconductor chips (41), and the multiple pairs of second semiconductor chips (42) are 2 pairs of second semiconductor chips (42).

10. The semiconductor module according to any one of claims 6-9, wherein, The switching circuit (50) of the resonant conversion primary side circuit includes multiple pairs of third semiconductor chips (511), and the two third semiconductor chips (511) in each pair of third semiconductor chips (511) are connected in series with each other; The switching circuit (502) of the resonant conversion secondary side circuit includes multiple pairs of fourth semiconductor chips (521), and the two fourth semiconductor chips (521) in each pair of fourth semiconductor chips (521) are connected in series with each other.

11. The semiconductor module according to claim 10, wherein, Each source of the multiple pairs of third semiconductor chips (511) is electrically connected to respective third source signal detection terminals (3a) located in the second region (12) through electric connection lines (7), and each gate of the multiple pairs of third semiconductor chips (511) is electrically connected to respective third gate signal detection terminals (3b) located in the second region (12) through electric connection lines (7); And Each source of the multiple pairs of fourth semiconductor chips (512) is electrically connected to respective fourth source signal detection terminals (4a) located in the third region (21) through electric connection lines (7), and each gate of the multiple pairs of fourth semiconductor chips (512) is electrically connected to respective fourth gate signal detection terminals (4b) located in the third region (21) through electric connection lines (7).

12. The semiconductor module according to claim 10 or 11, wherein, The semiconductor module further includes a third power signal AC terminal (3d) for each pair of third semiconductor chips (511) and a plurality of third power signal DC transmission terminals (3c / 3e) located in the second region (12), wherein, for each pair of the third semiconductor chips (511), the source of one of the third semiconductor chips (511) is connected to the drain of the other third semiconductor chip (511) through an electrical connection line (7), the drain of the one third semiconductor chip (511) is electrically connected to one of the plurality of third power signal DC transmission terminals (3c / 3e), the source of the other third semiconductor chip (511) is electrically connected to another one of the plurality of third power signal DC transmission terminals (3c / 3e), and the third power signal AC terminal (3d) is connected between the source of the one third semiconductor chip (511) and the drain of the other third semiconductor chip (511); The semiconductor module further includes a fourth power signal AC terminal (4d) for each pair of fourth semiconductor chips (512) and a plurality of fourth power signal DC transmission terminals (4c / 4e) located in the third region (21), wherein, for each pair of the fourth semiconductor chips (512), the source of one of the fourth semiconductor chips (512) is connected to the drain of the other fourth semiconductor chip (512) through an electrical connection line (7), the drain of the one fourth semiconductor chip (512) is electrically connected to one of the plurality of fourth power signal DC transmission terminals (4c / 4e), the source of the other fourth semiconductor chip (512) is electrically connected to another one of the plurality of fourth power signal DC transmission terminals (4c / 4e), and the fourth power signal AC terminal (4d) is connected between the source of the one fourth semiconductor chip (512) and the drain of the other fourth semiconductor chip (512).

13. The semiconductor module according to any one of claims 10 to 12, wherein, The plurality of pairs of third semiconductor chips (511) are 2 pairs of third semiconductor chips (511), the plurality of pairs of fourth semiconductor chips (512) are 2 pairs of fourth semiconductor chips (512), and the third semiconductor chips (511) and the fourth semiconductor chips (512) are MOS chips.

14. The semiconductor module according to any one of claims 10 to 13, wherein, The switching circuit (601) of the DC / DC conversion primary side circuit includes a plurality of pairs of fifth semiconductor chips (611), and the two fifth semiconductor chips (611) in each pair of fifth semiconductor chips (611) are connected in series with each other, wherein the source of one of the two fifth semiconductor chips (611) is connected to the drain of the other fifth semiconductor chip (611).

15. The semiconductor module according to claim 14, wherein, Each of the sources of the plurality of pairs of fifth semiconductor chips (611) is electrically connected to a fifth source signal detection terminal (5a) located in the fourth region (22) through an electrical connection line (7), and each of the gates of the plurality of pairs of fifth semiconductor chips (611) is electrically connected to a fifth gate signal detection terminal (5b) located in the fourth region (22) through an electrical connection line (7).

16. The semiconductor module according to claim 14 or 15, wherein, The switching circuit (602) of the secondary side circuit of the DC / DC conversion includes a first group of gate resistors (621), a first group of sixth semiconductor chips (622), a second group of gate resistors (623), and a second group of sixth semiconductor chips (624) arranged along the first direction (AA). The number of the sixth semiconductor chips (6221) in each group of sixth semiconductor chips is equal to the number of the gate resistors in each group of gate resistors. Among them, the sixth semiconductor chips (6221) in the first group of sixth semiconductor chips (622) are arranged at intervals along the second direction (BB). The gate resistors in the first group of gate resistors (621) are arranged at intervals along the second direction (BB). Each sixth semiconductor chip (6221) in the first group of sixth semiconductor chips (622) is connected in series with a corresponding gate resistor in the first group of gate resistors (621) and forms a first chip-gate resistor pair (625). Each of the first chip-gate resistor pairs (625) is connected in parallel with each other, and Among them, the sixth semiconductor chips (6221) in the second group of sixth semiconductor chips (624) are arranged at intervals along the second direction (BB). The gate resistors in the second group of gate resistors (623) are arranged at intervals along the second direction (BB). Each sixth semiconductor chip (6221) in the second group of sixth semiconductor chips (624) is connected in series with a corresponding gate resistor in the second group of gate resistors (623) and forms a second chip-gate resistor pair (626). Each of the second chip-gate resistor pairs (626) is connected in parallel with each other.

17. The semiconductor module according to claim 16, wherein, The fifth semiconductor chip (611) is a MOS chip. The sixth semiconductor chip (6221) is a MOS chip. The first group of sixth semiconductor chips (622) and the second group of sixth semiconductor chips (624) include four sixth semiconductor chips (6221). The multiple pairs of fifth semiconductor chips (611) are 2 pairs of fifth semiconductor chips.

18. The semiconductor module according to any one of claims 14-17, wherein, The semiconductor module includes a fifth power signal AC terminal (5d) for each pair of fifth semiconductor chips (611) and a plurality of fifth power signal DC transmission terminals (5c / 5e). One of the plurality of fifth power signal DC transmission terminals (5c / 5e) is connected to the drain of one of the fifth semiconductor chips (611). The other of the plurality of fifth power signal DC transmission terminals (5c / 5e) is connected to the source of the other fifth semiconductor chip (611). The fifth power signal AC terminal (5c / 5e) is connected between the drain of one of the fifth semiconductors (611) and the source of the other fifth semiconductor chip (611).

19. The semiconductor module according to claim 18, wherein, The switching circuit (60) of the DC / DC conversion circuit includes a first DC electrode output terminal (6a), a second DC electrode output terminal (6b), and a third DC electrode output terminal (6c). The first DC electrode output terminal (6a), the second DC electrode output terminal (6b), and the third DC electrode output terminal (6c) are located on the third substrate region (3) and are spaced apart along the first direction (AA). The first DC electrode output terminal (6a) is electrically connected to the drain of the sixth semiconductor chip (6221) in the first group of sixth semiconductor chips (622). The second DC electrode output terminal (6b) is electrically connected to the sources of the sixth semiconductor chips (6221) in the first group of sixth semiconductor chips (622) and the second group of sixth semiconductor chips (624). The third DC electrode output terminal (6c) is electrically connected to the drain of the sixth semiconductor chip (6221) in the second group of sixth semiconductor chips (624). Among them, the second DC electrode output terminal (6b) is used to be connected to a transformer outside the semiconductor module.

20. The semiconductor module according to any one of claims 1-19, wherein, It further includes thermistors (8) respectively disposed on the first substrate region (1), the second substrate region (2), and the third substrate region (3). At least two thermistor terminals (9) are respectively provided on the first substrate region (1), the second substrate region (2), and the third substrate region (3). Two of the thermistor terminals (9) in the first substrate region (1), the second substrate region (2), and the third substrate region (3) are connected to both ends of the corresponding thermistor (8).

21. The semiconductor module according to claim 20, wherein, The thermistor (8) in the first substrate region (1) is disposed on one side of the first region (11) close to the second substrate region (2) and the third substrate region (3). The thermistor (8) in the second substrate region (2) is disposed on one side of the second substrate region (2) close to the third substrate region (3). The thermistor (8) in the third substrate region (3) is disposed on one side of the third substrate region (3) close to the second substrate region (2).

22. A charger, wherein, It includes: The semiconductor module (1000) according to any one of claims 1 - 21; A first capacitor (C1), the first capacitor (C1) is included in the power factor correction circuit, and both ends of the first capacitor (C1) are connected in parallel with the switching circuit (501) of the resonant conversion primary side circuit; A first transformer (T1), the first transformer (T1) is connected between the switching circuit (501) of the resonant conversion primary side circuit and the switching circuit (502) of the resonant conversion secondary side circuit; And A second transformer (T2), the second transformer is connected between the switching circuit (601) of the DC / DC conversion primary side circuit and the switching circuit (602) of the DC / DC conversion secondary side circuit.

23. The charger according to claim 22, wherein, The multiple pairs of third semiconductor chips (511) are 2 pairs of third semiconductor chips (511), and the multiple pairs of fourth semiconductor chips (521) are 2 pairs of fourth semiconductor chips (521). Among them, the charger further includes: A first inductor (L1), a first end of the first inductor (L1) is connected between two of the third semiconductor chips (511) in a pair of the third semiconductor chips (511) among the 2 pairs of third semiconductor chips (511), and a second end of the first inductor (L2) is connected to a first end of a primary coil (T11) of the first transformer (T1); A second capacitor (C2), a first end of the second capacitor (C2) is connected between two of the third semiconductor chips (511) in another pair of the third semiconductor chips (511) among the 2 pairs of third semiconductor chips (511), and a second end of the second capacitor (C2) is connected to a second end of the primary coil (T11) of the first transformer (T1); A second inductor (L2), a first end of the second inductor (L2) is connected between two of the fourth semiconductor chips (521) in a pair of the fourth semiconductor chips (521) among the 2 pairs of fourth semiconductor chips (521), and a second end of the second inductor (L2) is connected to a first end of a secondary coil (T12) of the first transformer (T1); and A third capacitor (C3), a first end of the third capacitor (C3) is connected between two of the fourth semiconductor chips (521) in another pair of the fourth semiconductor chips (521) among the 2 pairs of fourth semiconductor chips (521), and a second end of the third capacitor (C3) is connected to a second end of the secondary coil (T12) of the first transformer (T1).

24. The charger according to claim 23, wherein, It further includes: A fourth capacitor (C4), the fourth capacitor (C4) is connected in parallel with a switching circuit (502) of the resonant conversion secondary side circuit.

25. The charger according to any one of claims 22-24, wherein, The charger further includes: A third inductor (L3), a first end of the third inductor (L3) is connected to a secondary coil (T22) of the second transformer (T2), and a second end of the third inductor (L3) is connected between a first group of sixth semiconductor chips (622) and a second group of sixth semiconductor chips (624).

26. The charger according to any one of claims 22-24, wherein, The multiple pairs of first semiconductor chips (41) include a first pair of first semiconductor chips (41), a second pair of first semiconductor chips (41), and a third pair of first semiconductor chips (41). Among them, the charger further includes: A fourth inductor (L4), a first end of the fourth inductor (L4) is connected to an external power grid, and the other end of the fourth inductor (L4) is connected between two of the first semiconductor chips (41) of the first pair of first semiconductor chips (41); A fifth inductor (L5), a first end of the fifth inductor (L5) is connected to an external power grid, and the other end of the fifth inductor (L5) is connected between two of the first semiconductor chips (41) of the second pair of first semiconductor chips (41); and A sixth inductor (L6), a first end of the sixth inductor (L6) is connected to an external power grid, and the other end of the sixth inductor (L6) is connected between two first semiconductor chips (41) of the third pair of first semiconductor chips (41).

27. An electric vehicle, wherein, Comprising a charger (2000) according to any one of claims 22-26.

28. The electric vehicle according to claim 27, wherein, Further comprising: an electronic control system (5000) and a battery (4000); The electronic control system (5000) is connected to the charger (2000) and the battery (4000), and the charger (2000) is connected to the battery (4000); The electronic control system (5000) monitors the state of the battery (4000) and controls the charging parameters of the charger (2000) according to the state of the battery (4000); The charger (2000) charges the battery (4000) according to the charging parameters.

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