Clock synchronization method and system, and electronic device and storage medium

Abstract

The embodiments of the present application relate to the technical field of clock synchronization. Disclosed are a clock synchronization method and system, and an electronic device and a storage medium. The clock synchronization method comprises: synchronizing a clock frequency of a master chip with that of a slave chip, wherein the master chip interacts with the slave chip by means of an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and performing clock calibration on the basis of the clock calibration value, so as to synchronize a clock of the master chip with that of the slave chip. Therefore, an improvement in the synchronization precision of a master chip and slave chip is at least facilitated while no additional interface is introduced onto the master chip and the slave chip.

Description

Clock synchronization method, system, electronic device and storage medium CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on the Chinese patent application with application number "202311870038.X" and application date of December 29, 2023, and claims the priority of the above-mentioned Chinese patent application. The entire content of the above-mentioned Chinese patent application is hereby incorporated into this application by introduction. Technical Field

[0002] The embodiments of the present application relate to the field of clock synchronization technology, and in particular to a clock synchronization method, system, electronic device, and storage medium. Background Art

[0003] Radar is an electronic device that uses electromagnetic waves to detect targets. It transmits electromagnetic waves to the target and receives the echoes, thereby obtaining information such as the distance from the target to the point of emission, the rate of change of distance (radial velocity), direction, and altitude.

[0004] To provide better performance, multi-chip cascading technology is increasingly being used in radars. Multi-chip cascading requires that each chip use the same time base and that the data collected by each chip remain synchronized.

[0005] However, current clock synchronization methods for master and slave chips either always have deviations and low precision, or require the introduction of new interfaces on the master and / or slave chips. Summary of the Invention

[0006] The embodiments of the present application provide a clock synchronization method, system, electronic device and storage medium, which are at least beneficial for improving the synchronization accuracy of the master chip and the slave chip without introducing additional interfaces on the master chip and the slave chip.

[0007] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a clock synchronization method, including: synchronizing the clock frequencies of a master chip and a slave chip, wherein the master chip interacts with the slave chip through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used to characterize the clock difference between the master chip and the slave chip; and performing clock calibration according to the clock calibration value to synchronize the clocks of the master chip and the slave chip.

[0008] In some embodiments, determining the clock calibration value includes: determining the clock calibration value according to timestamp information during a read operation initiated by the master chip to the slave chip.

[0009] In some embodiments, the clock calibration value is used to synchronize the clock of the slave chip to the clock of the master chip; performing clock calibration according to the clock calibration value includes: writing the clock calibration value into the clock register of the slave chip through a write operation initiated by the master chip.

[0010] In some embodiments, determining the clock calibration value based on the timestamp information during the read operation initiated by the master chip to the slave chip includes: determining the clock calibration value through the following expression: T = (t3-t1) / 2-(t2-t1)+t4; wherein T is the clock calibration value, t1 is the timestamp when the master chip initiates the read command, t2 is the timestamp when the slave chip returns the read data, t3 is the timestamp when the master chip receives the read data, and t4 is the timestamp when the master chip initiates the write operation.

[0011] In some embodiments, the clock calibration value is used to synchronize the clock of the master chip to the clock of the slave chip; performing clock calibration according to the clock calibration value includes: modifying the clock register of the master chip according to the clock calibration value.

[0012] In some embodiments, determining the clock calibration value based on the timestamp information during the read operation initiated by the master chip to the slave chip includes: determining the clock calibration value through the following expression: T' = (t3-t1) / 2+t2; wherein, T' is the clock calibration value, t1 is the timestamp of the master chip initiating the read command, t2 is the timestamp of the slave chip returning the read data, and t3 is the timestamp of the master chip receiving the read data.

[0013] In some embodiments, synchronizing the clock frequencies of the master chip and the slave chip includes: modifying the clock frequency and division coefficient of the slave chip according to the global clock frequency and division coefficient of the master chip; or modifying the clock frequency and division coefficient of the master chip according to the global clock frequency and division coefficient of the slave chip.

[0014] In some embodiments, the inter-chip communication channel includes a C2C channel.

[0015] In some embodiments, determining the clock calibration value includes: determining the clock calibration value based on the PTP protocol on the C2C channel.

[0016] In some embodiments, synchronizing the clock frequencies of the master chip and the slave chip includes: modifying the clock frequency and division coefficient of the slave chip according to the global clock frequency and division coefficient of the master chip; or modifying the clock frequency and division coefficient of the master chip according to the global clock frequency and division coefficient of the slave chip.

[0017] In some embodiments, the clock synchronization method is performed in at least two data communication processes between the master chip and the slave chip.

[0018] In some embodiments, before synchronizing the clock frequencies of the master chip and the slave chip, the method further includes: triggering a step of synchronizing the clock frequencies of the master chip and the slave chip according to a clock synchronization request initiated by the slave chip.

[0019] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a system, including: at least two cascaded chips, one chip of the at least two cascaded chips and the cascaded lower chip cooperate with each other as a master-slave chip to implement the clock synchronization method as described in any one of the above items.

[0020] According to some embodiments of the present application, on the other hand, embodiments of the present application further provide an electronic device, including: the system as described above.

[0021] According to some embodiments of the present application, on the other hand, embodiments of the present application further provide a computer-readable storage medium storing a computer program, which implements the clock synchronization method as described in any one of the above items when executed by a processor.

[0022] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0023] In addition to synchronizing the clock frequencies of the master and slave chips, a clock calibration value is also determined. This allows for precise clock calibration based on the clock calibration value, achieving precise clock synchronization between the master and slave chips and improving synchronization accuracy. Interaction between the master and slave chips occurs via an inter-chip communication channel, eliminating the need for clock software intervention and eliminating the need for additional interfaces on the master and slave chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] FIG1 is a flow chart of a clock synchronization method provided in an embodiment of the present application;

[0026] FIG2 is an interactive flow chart of a master chip initiating a read operation from a slave chip according to an embodiment of the present application;

[0027] FIG3 is another interactive flow chart of a master chip initiating a read operation to a slave chip provided in an embodiment of the present application;

[0028] FIG4 is an interactive flow chart of a clock synchronization method provided in an embodiment of the present application;

[0029] FIG5 is a schematic diagram of the structure of the system provided in an embodiment of the present application;

[0030] FIG6 is a diagram showing an example of the structure of a system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] As known from the background art, the current clock synchronization methods of the master chip and the slave chip either always have deviations and low precision, or require the introduction of new interfaces on the master chip and / or the slave chip.

[0032] Analysis revealed that the cause of this problem is that the actual startup times and processes of the cascaded chips differ, resulting in differences in the time bases and operating frequencies of each chip. This discrepancy renders the data collected by the cascaded chips unusable. To address this issue, the following two clock calibration solutions have been proposed:

[0033] Solution 1: Through communication channels such as Ethernet and Controller Area Network (CAN), according to the clock synchronization solution provided by the Precision Time Protocol (PTP), the master chip's clock information (such as timestamp) is first sent to the slave chip through the communication channel. The slave chip then parses the information based on the slave chip's clock domain (i.e., the slave clock domain). The slave chip then loads the master clock timestamp into the local clock as the clock baseline after taking into account the transmission delay. Through the delay of the handshake signal or data, the master chip records the system delay and uses it as a reference for future data. This solution requires the master chip's clock timestamp to be packaged as data and sent to the slave chip. The slave chip then needs to parse the data through software and then use the master chip's clock timestamp as the time baseline.

[0034] Solution 2: The slave clock synchronizes with the master clock by sampling the Primary Synchronization Signal (PSS) generated by the Global Navigation Satellite System (GNSS) from the master clock using a general-purpose input / output (GPIO). This process requires the slave clock to evaluate channel and processing delays and configure registers related to the slave clock's time baseline based on the rising edge of the sampled PSS.

[0035] In solution 1, timestamps are packaged in the communication channel, and the software parsing process takes time. Therefore, this solution introduces a certain degree of deviation, affecting the accuracy of clock synchronization. Solution 2 requires additional GPIO, slave clock software intervention, slave clock synchronization delay estimation, and clock baseline register configuration.

[0036] To address the aforementioned technical issues, embodiments of the present application provide a clock synchronization method, system, electronic device, and storage medium. In addition to synchronizing the clock frequencies of master and slave chips, a clock calibration value is determined. This allows for precise clock calibration based on the clock calibration value, achieving precise synchronization of the master and slave clocks, and improving synchronization accuracy. Interaction between the master and slave chips occurs via an inter-chip communication channel, eliminating the need for clock software intervention and eliminating the need for additional interfaces on the master and slave chips.

[0037] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in each embodiment of the present application to help readers better understand the present application. However, even without these technical details and various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0038] The following embodiments are divided for the convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0039] In one aspect, embodiments of the present application provide a clock synchronization method for use in a device having a master chip and a slave chip, such as a multi-chip cascade system. In some embodiments, the clock synchronization method includes the following steps, as shown in FIG1 :

[0040] Step 101 : Synchronize clock frequencies of a master chip and a slave chip, wherein the master chip and the slave chip interact through an inter-chip communication channel.

[0041] Step 102: Determine a clock calibration value.

[0042] Step 103: Perform clock calibration according to the clock calibration value to synchronize the clocks of the master chip and the slave chip.

[0043] In this way, in addition to synchronizing the clock frequencies of the master and slave chips, a clock calibration value is also determined. This allows for precise clock calibration based on the clock calibration value, achieving precise clock synchronization between the master and slave chips and improving synchronization accuracy. Interaction between the master and slave chips occurs via an inter-chip communication channel, eliminating the need for clock software intervention and eliminating the need for additional interfaces on the master and slave chips.

[0044] To help those skilled in the art better understand the clock synchronization method shown in FIG1 , it will be explained below.

[0045] In step 101, the clock frequencies of the master chip and the slave chip are synchronized. The master chip and the slave chip are relative. For example, in a cascade of three chips A, B, and C, chip B is the slave chip of chip A (in this case, chip A is the master chip), and it is also the master chip of chip C (in this case, chip C is the slave chip).

[0046] It's understood that the master chip's clock (also known as the "master clock") is the system's timing initiator and the sole clock baseline. This master clock can be generated by the default clock after system startup, or by the host computer (or host control system, etc.) using the PTP protocol. The slave chip's clock (also known as the "slave clock") is the system's timing receiver. Generally speaking, the master and slave chips have asynchronous clocks, and their clocks are likely to differ. Therefore, their clocks must be synchronized to meet the requirements of multi-chip cascade radar applications.

[0047] The inter-chip communication channel is an existing communication channel between chips. In the clock synchronization method provided in the embodiment of the present application, the interaction between the master chip and the slave chip is realized through the inter-chip communication channel. Therefore, there is no need to add other additional interfaces.

[0048] In some examples, the inter-chip communication channel can be an inter-chip (Chip to Chip, C2C) channel, which is a specially defined channel for multi-chip cascading. At this time, the master chip initiates read and write operations to access the address space (including but not limited to memory and registers) in the multi-level slave chip. This access uses direct address mapping to directly achieve real-time access to the address on the slave chip through read and write operations on the address mapping of the slave chip on the master chip (local address mapping plus the offset address of the slave chip on the master chip bus) without the need for additional slave chip operations. The channel integrates a high-speed SerDes (Serializer / Deserializer) interface to achieve a high-bandwidth, low-latency communication channel.

[0049] In some examples, synchronizing the clock frequencies of a master chip and a slave chip can be achieved by modifying the clock frequency and division factor of the slave chip based on the master chip's global clock frequency and division factor. In other words, the clock frequency and division factor of the slave chip are adjusted based on the master chip's clock frequency so that the slave chip's clock frequency is synchronized with the master chip's clock frequency.

[0050] In some cases, the clock frequency synchronization can be achieved by the master chip directly writing the corresponding clock frequency and division coefficient into the clock register of the slave chip through the inter-chip communication channel, thereby modifying the clock frequency of the slave chip to be consistent with the clock frequency of the master chip.

[0051] In some examples, synchronizing the clock frequencies of the master and slave chips can also be achieved by modifying the master chip's clock frequency and division factor based on the slave chip's global clock frequency and division factor. In other words, the master chip's clock frequency and division factor are adjusted based on the slave chip's clock frequency, so that the master chip's clock frequency is synchronized with the slave chip's clock frequency.

[0052] It is understandable that the above is only an exemplary description. In some examples, the clock frequency of the master chip and the clock frequency of the slave chip can be adjusted to be consistent with the reference clock frequency, etc., which will not be described in detail here.

[0053] It's important to note that since the master and slave chips interact through inter-chip communication during clock synchronization, they must establish a connected inter-chip communication channel before clock synchronization can begin. For example, after the master and slave chips are booted up and each initializes its local clock configuration and inter-chip communication channel, the master chip then uses the inter-chip communication channel to handshake with the slave chip to confirm that the channel is functioning properly and ready for use.

[0054] In step 102, a clock calibration value is determined, wherein the clock calibration value is used to represent the clock difference between the master chip and the slave chip.

[0055] In some embodiments, the clock calibration value can be determined by using timestamp information from a read operation initiated by the master chip to the slave chip. In other words, the clock calibration value is determined by directly utilizing the read and write functionality provided by inter-chip communication. This simplifies the clock calibration value determination process and eliminates the need for additional parsing, enabling more efficient clock synchronization.

[0056] In order to facilitate those skilled in the art to better understand clock synchronization based on direct communication between chips, an example is given below to illustrate the clock synchronization.

[0057] It is understood that the clock calibration target can be either the master chip or the slave chip. Therefore, the clock calibration value can be the value by which the master chip's clock needs to be offset relative to the slave chip's clock to synchronize the master chip's clock with the slave chip's clock; the clock calibration value can also be the value by which the slave chip's clock needs to be offset relative to the master chip's clock to synchronize the slave chip's clock with the master chip's clock.

[0058] Therefore, the following description will be based on the above two situations.

[0059] In some cases, a clock calibration value is used to synchronize the slave chip's clock with the master chip's clock. Clock calibration can be performed based on the clock calibration value by initiating a write operation from the master chip to the slave chip's clock register. This modifies the slave chip's clock configuration and synchronizes the slave chip's clock with the master chip's clock.

[0060] Furthermore, the clock calibration value determined at this time determines the value by which the slave chip's clock needs to be offset relative to the master chip's clock. Therefore, the clock calibration value can be determined based on the timestamp information during the read operation initiated by the master chip to the slave chip, which can be achieved through the following expression:

[0061] T = (t3 - t1) / 2 - (t2 - t1) + t4;

[0062] Among them, T is the clock calibration value, t1 is the timestamp when the master chip initiates the read command, t2 is the timestamp when the slave chip returns the read data, t3 is the timestamp when the master chip receives the read data, and t4 is the timestamp when the master chip initiates the write operation.

[0063] To facilitate those skilled in the art to better understand the above expression, the following description is given with reference to the flowchart of the read operation initiated by the master chip to the slave chip shown in FIG2 .

[0064] As shown in Figure 2, the master chip sends a read command to the slave chip through the C2C channel at time t1 (clock timestamp of the master chip). Due to transmission and response delays, the slave chip receives the read command and responds, and then returns the read data to the master chip at time t2 (clock timestamp of the slave chip). Due to transmission delays, the master chip receives the read data at time t3 (clock timestamp of the master chip). Among them, the C2C channel is only an example of an inter-chip communication channel. In other embodiments, other inter-chip communication channels can be used to replace the C2C channel, etc., which will not be described here or later. In addition, the clock of the master chip in Figure 2 is used to illustrate that t1 and t3 on the same line with it are both provided with corresponding timestamp information based on the clock of the master chip, and the clock of the slave chip in Figure 2 is used to illustrate that t2 on the same line with it is provided with corresponding timestamp information based on the clock of the slave chip.

[0065] It can be understood that the read operation consists of a read command and read data, and the read command and read data are in opposite directions but have the same path. Therefore, it can be assumed that the time it takes for the read command to reach the slave chip register is half the read operation time, that is, (t3-t1) / 2. Therefore, the delay of the write operation is (t3-t1) / 2-(t2-t1).

[0066] Furthermore, after determining the write operation delay, the master chip writes the clock calibration value to the slave chip's clock register. The corresponding accurate master chip clock timestamp is the master chip timestamp when the master chip initiates the write operation + the write operation delay. That is, T = (t3-t1) / 2-(t2-t1)+t4.

[0067] It should be noted that in some cases, the writing of T is based on an already synchronized time baseline. That is, as shown in Figure 3, before time t1, the master chip records the local current timestamp t0, initiates a C2C channel write operation, writes this timestamp t0 into the slave chip clock register, and updates the slave chip's local time baseline to ensure that the master and slave chip clock synchronization and time baseline are consistent. Similar to the content shown in Figure 2, the master chip sends a read command to the slave chip at time t1 (the master chip's clock timestamp). Due to transmission and response delays, the slave chip receives the read command and responds, and then returns the read data to the master chip at time t2 (the slave chip's clock timestamp). Due to transmission delays, the master chip receives the read data at time t3 (the master chip's clock timestamp). In addition, the timestamp of the master chip clock in Figure 3 is used to indicate that the corresponding timestamp information t0, t1, and t3 on the same line are provided based on the master chip's clock. The timestamp of the slave chip clock in Figure 3 is used to indicate that the corresponding timestamp information t2 on the same line is provided based on the slave chip's clock.

[0068] To facilitate those skilled in the art to better understand the clock synchronization method provided by the above example, it will be described below with reference to FIG4 .

[0069] As shown in Figure 4, at time t0 (the timestamp of the master chip's clock), the master chip initiates a write operation on the slave chip to write the timestamp of the master chip's clock, where the master chip initiated the write operation, into the slave chip's clock register, aligning the master and slave chips. Subsequently, at time t1, the master chip sends a read command to the slave chip. The slave chip then receives the read command from the master chip at time t2 and returns the read data to the master chip. Subsequently, the master chip receives the read data at time t3 and, based on the above expression, determines the time calibration value to be t5 ((t3-t1) / 2-(t2-t1)). At time t4, the master chip initiates a write operation on the slave chip to write t4+t5 (the aforementioned "T") into the slave chip's clock register, thus synchronizing the master and slave chip's clocks.

[0070] In other examples, the clock calibration value is used to synchronize the master chip's clock with the slave chip's clock. In this case, clock calibration based on the clock calibration value can also be achieved by modifying the master chip's clock register based on the clock calibration value. In other words, the master chip's clock configuration is modified to synchronize the master chip's clock with the slave chip's clock.

[0071] Furthermore, the clock calibration value determined at this time determines the value by which the master chip's clock needs to be offset relative to the slave chip's clock. Therefore, based on the timestamp information during the read operation initiated by the master chip to the slave chip, the clock calibration value can be determined using the following expression:

[0072] T' = (t3 - t1) / 2 + t2;

[0073] Among them, T' is the clock calibration value, t1 is the timestamp when the master chip initiates the read command, t2 is the timestamp when the slave chip returns the read data, and t3 is the timestamp when the master chip receives the read data.

[0074] As mentioned above, the time it takes for the read command to reach the slave chip register is half of the read operation time, that is, (t3-t1) / 2. Therefore, the moment when the master chip receives the read data (under the clock of the slave chip) is half of the time it takes for the slave chip to send the read data + the read operation time, that is, when the master chip receives the read data at the moment T'=(t3-t1) / 2+t2, the information written to the local clock register should be T'.

[0075] Of course, the above is merely an exemplary description of clock synchronization achieved through direct interaction over a C2C channel. In some embodiments, determining the clock calibration value can also be achieved by determining the clock calibration value over the C2C channel based on the PTP protocol. Specifically, a PTP-based connection is established over the C2C channel, and the clock calibration value is determined and calibrated according to the clock synchronization scheme provided by the PTP protocol. The clock synchronization scheme provided by the PTP protocol is already provided in the PTP protocol and will not be further elaborated here.

[0076] It should be noted that when the clock calibration value is determined based on the PTP protocol, the C2C channel actually achieves multiplexing. On the one hand, based on the data communication function of the C2C channel itself, it can provide a communication method for interaction between the master chip and the slave chip. On the other hand, the C2C channel is used as the communication channel of the PTP protocol, and system synchronization can be achieved on this channel through the software handshake mechanism.

[0077] In some embodiments, a clock calibration value is used to synchronize the slave chip's clock with the master chip's clock. Clock calibration based on the clock calibration value can be achieved by writing the clock calibration value and the master chip's current clock time to the slave chip's clock register via a write operation initiated by the master chip. This allows the slave chip to directly restart timing based on the time indicated by the combination of the clock calibration value and the master chip's current clock time, thereby synchronizing the slave chip's clock with the master chip's clock. In this case, the clock calibration value is the difference between the master chip's clock and the slave chip's clock.

[0078] In some implementations, a clock calibration value is used to synchronize the master chip's clock with the slave chip's clock. Clock calibration based on the clock calibration value can be achieved by modifying the master chip's clock register based on the clock calibration value and the timestamp of the read data returned by the slave chip. This allows the master chip to directly restart timing based on the time indicated by the combination of the clock calibration value and the timestamp of the read data returned by the slave chip (without requiring an additional interactive step to obtain the slave chip's current clock time), thereby synchronizing the master chip's clock with the slave chip's clock. In this case, the clock calibration value is the difference between the master chip's clock and the slave chip's clock.

[0079] In addition, this embodiment does not limit the timing of clock synchronization. In some cases where the deviation requirements for clock synchronization are not high, or the accuracy of the master and slave chips is high, a specific timing can be set to trigger clock synchronization, such as using the master-slave chip startup process as the timing of clock synchronization. In some cases, in order to ensure the synchronization accuracy of the master chip and the slave chip in real time, the clock synchronization method provided by the embodiment of the present application can be executed in the absence of data communication. For example, the clock synchronization method is executed in at least two data communication processes between the master chip and the slave chip, or even in each data communication process, the data synchronization method provided by the embodiment of the present application is periodically executed. It is understandable that due to the frequency deviation of different chips under the same clock configuration, the master chip and the slave chip need to be resynchronized regularly during use to ensure the accuracy of the system synchronization clock. According to the description of the aforementioned embodiment, the clock synchronization method only writes the clock register of the object whose clock calibration value is calibrated (writes T to the clock register of the slave chip, or writes T' to the clock register of the master chip), thereby achieving complete synchronization of the clocks of the master chip and the slave chip. Therefore, the master chip can intersperse write operations during data transmission intervals (i.e., the aforementioned non-data communication period, or in other words, the data communication intervals) to update the slave clock register to complete resynchronization. Therefore, the clock synchronization method provided in the embodiments of the present application, if executed during at least two data communication processes between the master chip and the slave chip, does not affect data transmission efficiency, while achieving synchronization during the data transmission process, etc.

[0080] It can also be understood that clock synchronization should have an initiator. In some embodiments, the initiator can be the master chip, that is, the master chip autonomously triggers the step of synchronizing the clock frequency; in some embodiments, the initiator can also be the slave chip, that is, before synchronizing the clock frequencies of the master chip and the slave chip, the clock synchronization method also includes: triggering the step of synchronizing the clock frequencies of the master chip and the slave chip according to the clock synchronization request initiated by the slave chip.

[0081] It should be noted that the clock synchronization request can be transmitted through the C2C channel or through other master-slave high-speed data interfaces (such as low-voltage differential signaling (LVDS)), which will not be described in detail here.

[0082] The step division of the above various methods is only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0083] On the other hand, an embodiment of the present application further provides a system, as shown in FIG5 , comprising: at least two cascaded chips.

[0084] Among them, one chip in at least two cascaded chips cooperates with the lower-level chip in the cascade as a master-slave chip to implement the clock synchronization method as described in any of the above embodiments.

[0085] To help those skilled in the art better understand the method for implementing clock synchronization through chip coordination, the following describes the system shown in FIG6 as an example. As shown in FIG6 , the system includes cascaded chips 1, 2, and 3, wherein chip 2 is a lower-level chip in the cascade of chip 1, and chip 3 is a lower-level chip in the cascade of chip 2.

[0086] First, chip 1 acts as the master chip and chip 2 acts as the slave chip. According to the clock synchronization method provided in the previous embodiment of this application, the clock of chip 2 is synchronized to the clock of chip 1. Then, chip 2 acts as the master chip and chip 3 acts as the slave chip. According to the clock synchronization method provided in the previous embodiment of this application, the clock of chip 3 is synchronized to the clock of chip 2 (at this time, according to the previous step, the clock of chip 2 has already been synchronized to the clock of chip 1). Finally, the clocks of chip 2 and chip 3 are both synchronized to the clock of chip 1, so that the entire system is synchronized to the same clock.

[0087] It is not difficult to find that this embodiment is a system embodiment corresponding to the method embodiment, and this embodiment can be implemented in conjunction with the method embodiment. The relevant technical details mentioned in the method embodiment are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the method embodiment.

[0088] In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems raised by this application, but this does not mean that there are no other units in this embodiment.

[0089] On the other hand, an embodiment of the present application further provides an electronic device, such as the system described in the above embodiment, or used to execute the clock synchronization method provided in any of the above embodiments.

[0090] The device can be a component or product used in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and health care. For example, the terminal can be intelligent transportation equipment (such as cars, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as bracelets, glasses, etc.), smart home devices (such as sweeping robots, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as gates, smart traffic lights, smart signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs and various devices equipped with the instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, smart medical equipment, consumer electronic devices, etc.

[0091] Alternatively, when the above-mentioned equipment is applied to an Advanced Driving Assistance System (ADAS), the radio device as an on-board sensor can provide ADAS systems with various functional safety guarantees such as autonomous emergency braking (AEB), blind spot detection (BSD), lane change assist (LCA), and rear cross traffic alert (RCTA).

[0092] It is not difficult to find that this embodiment is a device embodiment corresponding to the system embodiment, and this embodiment can be implemented in conjunction with the system embodiment. The relevant technical details mentioned in the system embodiment are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the system embodiment.

[0093] Another aspect of the present application is to provide a computer-readable storage medium storing a computer program that implements the above method embodiment when executed by a processor.

[0094] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0095] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A clock synchronization method, comprising: Synchronizing the clock frequencies of a master chip and a slave chip, wherein the master chip and the slave chip interact through an inter-chip communication channel; Determining a clock calibration value, which is used to characterize the clock difference between the master chip and the slave chip; Performing clock calibration according to the clock calibration value to synchronize the clocks of the master chip and the slave chip.

2. The clock synchronization method according to claim 1, wherein The determining the clock calibration value includes: Determining the clock calibration value according to the timestamp information during the read operation initiated by the master chip to the slave chip.

3. The clock synchronization method according to claim 2, wherein, The clock calibration value is used to synchronize the clock of the slave chip to the clock of the master chip; The performing clock calibration according to the clock calibration value includes: Writing the clock calibration value into the clock register of the slave chip through a write operation initiated by the master chip.

4. The clock synchronization method according to claim 2 or 3, wherein The determining the clock calibration value according to the timestamp information during the read operation initiated by the master chip to the slave chip includes: Determining the clock calibration value through the following expression: T = (t3 - t1) / 2 - (t2 - t1) + t4; wherein, T is the clock calibration value, t1 is the timestamp when the master chip issues a read command, t2 is the timestamp when the slave chip returns the read data, t3 is the timestamp when the master chip receives the read data, and t4 is the timestamp when the master chip initiates a write operation.

5. The clock synchronization method according to claim 2, wherein, The clock calibration value is used to synchronize the clock of the master chip to the clock of the slave chip; The performing clock calibration according to the clock calibration value includes: Modifying the clock register of the master chip according to the clock calibration value.

6. The clock synchronization method according to claim 5, wherein, The determining the clock calibration value according to the timestamp information during the read operation initiated by the master chip to the slave chip includes: Determining the clock calibration value through the following expression: T' = (t3 - t1) / 2 + t2; wherein, T' is the clock calibration value, t1 is the timestamp when the master chip issues a read command, t2 is the timestamp when the slave chip returns the read data, and t3 is the timestamp when the master chip receives the read data.

7. The clock synchronization method according to any one of claims 1 to 6, wherein, The inter-chip communication channel includes a C2C channel.

8. The clock synchronization method according to claim 1 or 7, wherein, The determining the clock calibration value includes: Determining the clock calibration value based on the PTP protocol on the C2C channel.

9. The clock synchronization method according to any one of claims 1 to 8, wherein, The synchronizing the clock frequencies of the master chip and the slave chip includes: Modifying the clock frequency and division coefficient of the slave chip according to the global clock frequency and division coefficient of the master chip; or, Modifying the clock frequency and division coefficient of the master chip according to the global clock frequency and division coefficient of the slave chip; Or, Adjusting the clock frequencies of the master chip and the slave chip to a reference clock frequency.

10. The clock synchronization method according to any one of claims 1 to 9, wherein, The clock synchronization method is executed during at least two data communication processes between the master chip and the slave chip.

11. The clock synchronization method according to any one of claims 1 to 10, wherein, Before synchronizing the clock frequencies of the master chip and the slave chip, the method further includes: Triggering the step of synchronizing the clock frequencies of the master chip and the slave chip according to the clock synchronization request initiated by the slave chip.

12. A system, comprising: At least two cascaded chips, one of the at least two cascaded chips and the cascaded lower-level chip cooperate with each other as master-slave chips to implement the clock synchronization method according to any one of claims 1 to 11.

13. An electronic device, comprising the system according to claim 12, or for executing the clock synchronization method according to any one of claims 1 to 11.

14. A computer-readable storage medium storing a computer program, which implements the clock synchronization method according to any one of claims 1 to 11 when executed by a processor.

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