Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that enables miniaturization, thinning, and improved moisture resistance. A multilayer ceramic capacitor 1 according to the present invention comprises two end-surface external electrodes 3 respectively disposed on two end surfaces C of a laminate 2. The laminate 2 includes an inner layer part 11 and an outer layer part 12 disposed so as to sandwich the inner layer part 11 in a lamination direction. The inner layer part 11 includes a plurality of end-surface-exposed internal electrodes 15 and a plurality of internal dielectric layers 14. The outer layer part 12 includes a first outer layer part 12a positioned on a first principal surface A1 side and a second outer layer part 12b positioned on a second principal surface A2 side. The outer layer part 12 is disposed so as to wrap around to a gap region D1 between the end-surface-exposed inner electrodes 15 and a side surface, wherein the amount of wraparound of the first outer layer part 12a to the gap region D1 is greater than the amount of wraparound of the second outer layer part 12b to the gap region D1.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors generally have inner layer sections in which internal electrodes and dielectric layers are alternately stacked. Outer layer sections are arranged on both sides of the inner layer sections in the stacking direction, and gap sections that do not contribute to capacitance formation are provided on the outer periphery of the effective layers that contribute to capacitance formation in the inner layer sections, in a direction perpendicular to the stacking direction. These outer layer sections and gap sections contribute to reliability such as moisture resistance.

[0003] In recent years, there has been a demand for multilayer ceramic capacitors to be smaller and thinner, while at the same time increasing their capacitance. However, there is a limit to how much the inner layers can be miniaturized because they contribute to capacitance. Therefore, in order to achieve overall miniaturization and thinning, efforts are being made to further thin the outer layers and gap areas.

[0004] However, thinning the outer layer and gap portions may result in a decrease in reliability, so there is a conventional technique in which an insulating layer is disposed to cover the outside of the outer layer (see Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2023-113923

[0006] However, when an insulating layer is disposed so as to cover the outside of the outer layer portion as in the above-mentioned conventional technology, an additional step of disposing the insulating layer is required, and the thickness of the laminate increases by the amount of the insulating layer.

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that can be made smaller and thinner and that can have improved moisture resistance.

[0008] In order to solve the above problem, the present invention provides a multilayer ceramic capacitor comprising: a laminate having a first main surface and a second main surface opposing each other in a stacking direction, two end surfaces opposing each other in a vertical direction intersecting the stacking direction, and two side surfaces opposing each other in a horizontal direction intersecting the stacking direction and the vertical direction; and two end surface external electrodes respectively arranged on the two end surfaces of the laminate, wherein the laminate comprises an inner layer portion and outer layer portions arranged to sandwich the inner layer portion in the stacking direction, the inner layer portion including a plurality of end surface exposed internal electrodes and a plurality of internal dielectric layers, and the outer layer portions include a first outer layer portion located on the first main surface side and a second outer layer portion located on the second main surface side, the outer layer portions being arranged to wrap around into a gap region between the end surface exposed internal electrodes and the side surfaces, and the amount of wrapping around into the gap region of the first outer layer portion is greater than the amount of wrapping around into the gap region of the second outer layer portion.

[0009] Furthermore, in order to achieve the above object, the present invention provides a laminate having a first main surface and a second main surface opposing each other in a lamination direction, two end surfaces opposing each other in a vertical direction intersecting the lamination direction, and two side surfaces opposing each other in a horizontal direction intersecting the lamination direction and the vertical direction, two end surface external electrodes respectively arranged on the two end surfaces of the laminate, and two side surface external electrodes respectively arranged on the two side surfaces of the laminate, wherein the laminate comprises an internal layer portion and external layer portions arranged so as to sandwich the internal layer portion in the lamination direction, the external layer portions including a first external layer portion located on the first main surface side and a second external layer portion located on the second main surface side, the internal layer portions including a plurality of end surface exposed internal electrodes, a plurality of side surface exposed internal electrodes, and a plurality of internal dielectric layers, and the end surface exposed internal electrodes are connected to the side surface exposed internal electrodes and the a multilayer ceramic capacitor including end face opposing portions opposing each other in a stacking direction and an end face drawn portion drawn from the end face opposing portion to the end face of the laminate, wherein the side face exposed internal electrode has a side face opposing portion opposing the end face exposed internal electrode in the stacking direction and a side face drawn portion drawn from the side face opposing portion to the side face of the laminate, wherein, in the inner layer portion, when a region in the stacking direction where the end face drawn portion overlaps is defined as an end face drawn region, a region where the side face drawn portion overlaps is defined as a side face drawn region, and a region between the end face exposed internal electrode and the side face and which does not overlap with the side face drawn region is defined as a three-terminal gap region, the outer layer portion is arranged to wrap around to the three-terminal gap region, and a wrapping amount of the first outer layer portion in the three-terminal gap region is greater than a wrapping amount of the second outer layer portion.

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can be made smaller and thinner and that can have improved moisture resistance.

[0011] 1. A schematic perspective view of a multilayer ceramic capacitor. 2. A cross-sectional view taken along line II-II in FIG. 1. 3. A cross-sectional view taken along line III-III in FIG. 1. 4. An enlarged view of an area Q enclosed by a dotted square in FIG. 3. 5. A formula showing how to determine the degree of distortion. 6. A schematic perspective view of a multilayer ceramic capacitor 100. 7. A cross-sectional view taken along line V-V in FIG. 6. 8. A cross-sectional view taken along line VI-VI in FIG. 6. 9. A cross-sectional view taken along line VII-VII in FIG. 6. 10. A view of an inner layer portion 11 of the multilayer ceramic capacitor 100 seen from the first main surface A1 side, with the positions of an end face exposed internal electrode 16 and a side face exposed internal electrode 17 indicated by dotted lines.

[0012] First Embodiment A multilayer ceramic capacitor 1 according to a first embodiment of the present invention will now be described. The multilayer ceramic capacitor 1 according to the first embodiment is a two-terminal multilayer ceramic capacitor. FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1.

[0013] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of end surface external electrodes 3 provided on both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which a plurality of internal dielectric layers 14 and a plurality of end surface exposed internal electrodes 15 are laminated, and an outer layer portion 12.

[0014] In the following description, the direction in which the internal dielectric layers 14 and the end surface exposed internal electrodes 15 are stacked is referred to as the stacking direction T, and the direction in which the pair of end surface external electrodes 3 are arranged is referred to as the longitudinal direction L. The direction that intersects with the stacking direction T and with which the pair of end surface external electrodes 3 are arranged is referred to as the transverse direction W. In the embodiment, the transverse direction W is perpendicular to both the longitudinal direction L and the stacking direction T.

[0015] (Laminate 2) In the following description, of the six outer peripheral surfaces of the laminate 2 shown in Fig. 2 , a pair of outer peripheral surfaces facing each other in the stacking direction T will be referred to as a first main surface A1 and a second main surface A2, and when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A. A pair of outer peripheral surfaces facing each other in the transverse direction W of the laminate 2 will be referred to as a first side surface B1 and a second side surface B2, and when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B. A pair of outer peripheral surfaces facing each other in the longitudinal direction L of the laminate 2 will be referred to as a first end surface C1 and a second end surface C2, and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0016] It is preferable that both or either of the first and second principal surfaces A1, A2 be flat. If the principal surface A is flat, the stress received from the nozzle when picking up the multilayer ceramic capacitor 1 can be dispersed by the flat principal surface A, thereby improving the strength of the multilayer ceramic capacitor 1 during mounting. However, this is not limiting, and both the first and second principal surfaces A1, A2 of the laminate 2 may be roughened.

[0017] The intersection of two of the first main surface A1, the second main surface A2, the first end surface C1, the second end surface C2, the first side surface B1, and the second side surface B2 is called a ridge, and the intersection of three of these surfaces is called a corner. The ridges and corners are preferably rounded, as this rounding can prevent chipping and cracking. When the ridges and corners are rounded, the main surface may be flat on the surfaces excluding the corners and ridges.

[0018] (Inner layer portion 11) The inner layer portion 11 includes end-exposed internal electrodes 15 and inner dielectric layers 14 alternately stacked with the end-exposed internal electrodes 15. The thickness of the end-exposed internal electrodes 15 and the inner electrodes 15 is preferably 0.25 μm or more and 0.6 μm or less.

[0019] (End Face Exposed Internal Electrode 15) The end face exposed internal electrode 15 includes a first end face exposed internal electrode 15A having one end exposed on the first end face C1 and a second end face exposed internal electrode 15B having one end exposed on the second end face C2. The first end face exposed internal electrodes 15A and the second end face exposed internal electrodes 15B are alternately stacked.

[0020] The end-face exposed internal electrode 15 may be made of, but is not limited to, an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, if the end-face exposed internal electrode 15 contains Sn, the electric field concentration at the interface between the end-face exposed internal electrode 15 and the internal dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the end-face exposed internal electrodes 15, either the first end-face exposed internal electrode 15A or the second end-face exposed internal electrode 15B.

[0021] The first end surface exposed internal electrode 15A has a first opposing portion 15Aa facing the second end surface exposed internal electrode 15B and a first lead portion 15Ab drawn from the first opposing portion 15Aa onto the first end surface C1. The second end surface exposed internal electrode 15B has a second opposing portion 15Ba facing the first end surface exposed internal electrode 15A and a second lead portion 15Bb drawn from the second opposing portion 15Ba onto the second end surface C2.

[0022] The first opposing portion 15Aa and the second opposing portion 15Ba face each other, and a capacitance is formed between the first opposing portion 15Aa and the second opposing portion 15Ba, thereby causing the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0023] In addition, when it is not necessary to distinguish between the first opposing portion 15Aa and the second opposing portion 15Ba, they will be collectively referred to as opposing portion 15a. In addition, when it is not necessary to distinguish between the first drawn-out portion 15Ab and the second drawn-out portion 15Bb, they will be collectively referred to as drawn-out portion 15b.

[0024] (Internal Dielectric Layer 14) The internal dielectric layer 14 contains barium titanate as a main component and Si as a secondary component. The thickness of the internal dielectric layer 14 in the stacking direction T is 0.45 μm or less.

[0025] (Ceramic Grains) The internal dielectric layers 14 constituting the inner layer portion 11 of the multilayer ceramic capacitor 1 contain ceramic grains. The ceramic grain diameter D50 of the internal dielectric layers 14 is preferably 0.15 μm or less. This allows the number of ceramic grains contained in the internal dielectric layers 14 to be increased, increasing the number of interfaces between the ceramic grains and improving high-temperature reliability.

[0026] 3, the region between the end-face exposed internal electrode 15 and the side surface B in the inner layer portion 11 is defined as a gap region D1. Also, as shown in FIG. 2, the region between the first end-face exposed internal electrode 15A and the second end surface C2 and the region between the second end-face exposed internal electrode 15B and the first end surface C1, i.e., the region in the inner layer portion 11 where the lead portion 15b exists in the stacking direction T, is defined as a lead region D2.

[0027] In this embodiment, the Si content of the internal dielectric layer 14 located in the gap region D1 and near the center in the stacking direction T is preferably 0.2 at % (atomic percent) or more and 5.0 at % or less.

[0028] If the Si content in the dielectric ceramic in the gap region D1 is less than 0.2 at %, sintering will be difficult. However, in the present application, the Si content in the dielectric ceramic in the gap region D1 is 0.2 at % or more, which improves the sinterability of the internal dielectric layer 14. This reduces the possibility that moisture will penetrate from the first side face B1 and the second side face B2, which are not covered by the end face external electrode 3, and reach the end face exposed internal electrode 15, thereby improving moisture resistance.

[0029] Furthermore, if the Si content in the dielectric ceramic in the gap region D1 is more than 5.0 at %, the capacitance will decrease significantly due to the decrease in the dielectric constant, which is not desirable. However, in the present invention, the Si content in the dielectric ceramic in the gap region D1 is 5.0 at % or less, so the problem of capacitance decrease due to the decrease in the dielectric constant is unlikely to occur.

[0030] In the embodiment, the Si content of the internal dielectric layer 14 located near the center of the stacking direction T in the gap region D1 is set to 0.2 at% or more and 5.0 at% or less, but this is not limited to this. As long as the Si content of the internal dielectric layer 14 located at least near the center of the stacking direction T in the gap region D1 is 0.2 at% or more and 5.0 at% or less, it is possible to reduce the possibility of moisture penetrating from the first side surface B1 and the second side surface B2 that are not covered by the end face external electrode 3 and reaching the end face exposed internal electrode 15.

[0031] The Si content can be measured as follows. For example, in the case of the gap region D1, in the cross section near the center in the vertical direction L shown in Fig. 3, a region P is defined as a φ1 μm region located 5 μm outward in the horizontal direction W (toward the side surface B) from the end of the end-face-exposed internal electrode 15 at a position approximately halfway in the stacking direction T. The Si content is calculated from the X-ray intensity spectrum detected by a WDX (wavelength dispersive X-ray fluorescence analyzer) within this region P.

[0032] (Outer layer portion 12) The laminate 2 has an inner layer portion 11 and two outer layer portions 12 arranged to sandwich the inner layer portion 11 in the stacking direction T. Of the two outer layer portions 12, the outer layer portion 12 on the first main surface A1 side is referred to as the first outer layer portion 12a, and the outer layer portion 12 on the second main surface A2 side is referred to as the second outer layer portion 12b. The first outer layer portion 12a and the second outer layer portion 12b are each formed from an insulating material.

[0033] (Wrapping of Outer Layer Portions 12) In the multilayer ceramic capacitor 1 of the embodiment, the first outer layer portion 12a and the second outer layer portion 12b are arranged by being pressed so as to wrap around the gap region D1 and the lead-out region D2.

[0034] Figure 4 is an enlarged view of the region Q enclosed by the dotted line in Figure 3. Both the outer layer portion 12 and the gap region D1 contain voids q. The porosity of the outer layer portion 12 is lower than that of the gap region D1. The porosity is the ratio of the area of ​​voids q per unit cross-sectional area. The porosity is measured by binarizing the voids q and other areas in an observation image of a 10 µm square observation field of view.

[0035] (Effect of Wrapping Around) The outer layer portions 12 are laminated on both sides of the gap region D1 in the lamination direction T. Therefore, even after firing in the manufacturing process of the multilayer ceramic capacitor, some kind of interface exists between the gap region D1 and the outer layer portions 12. The interface has weaker bonding strength than other portions, and in particular, when multilayer ceramic capacitors are miniaturized, the dimension of the gap region D1 in the lateral direction W becomes smaller in the case of multilayer ceramic capacitors with a conventional structure, making it easier for moisture to penetrate through this interface to the internal electrode 15.

[0036] However, in the multilayer ceramic capacitor 1 of the embodiment, the outer layer portions 12 are arranged while being pressed so as to wrap around the gap region D1, and therefore the interface between the gap region D1 and the outer layer portions 12 is pressure-bonded, which reduces the possibility that moisture from the outside will penetrate along the interface and reach the internal electrode 15, thereby improving moisture resistance.

[0037] 3, the gap region D1 has no internal electrode 15. Therefore, compared to the corresponding region in the center where the internal electrode 15 and the internal dielectric layer 14 are laminated, the thickness in the stacking direction T is thinner by the amount of the internal electrode 15. This results in a step between the gap region D1 and the corresponding region.

[0038] In the embodiment, the thickness of the internal dielectric layer 14 in the stacking direction T is 0.45 μm or less. When the thickness of each internal dielectric layer 14 is small in this way, the overall capacitance is improved.

[0039] However, when the internal dielectric layer 14 is relatively thin compared to the internal electrode 15, the proportion of the internal electrode 15 in the overall thickness of the opposing portion in the stacking direction T increases. As a result, the influence of the step caused by the presence or absence of the internal electrode 15 on the overall thickness of the laminate 2 in the stacking direction T increases. Therefore, when the laminate sheet is pressed in the stacking direction T, as described below, the adhesion between the internal dielectric layer 14 and the outer layer portion 12 at the step portion tends to be insufficient.

[0040] However, in the multilayer ceramic capacitor 1 of the embodiment, the outer layer portions 12 are pressed so as to extend into the gap region D1. Therefore, the interface between the outer layer portions 12 and the gap region D1 is strongly pressed even at the step portion. This further reduces the possibility that moisture from the outside will penetrate along the interface and reach the internal electrode 15, thereby improving moisture resistance.

[0041] Furthermore, the outer layer portion 12 is arranged so as to wrap around to the gap region D1, so that the interface between the outer layer portion 12 and the gap region D1 is curved rather than linear, and the distance to the interface is longer than when the outer layer portion 12 does not wrap around. This also reduces the possibility that moisture from the outside will travel along the interface and infiltrate the internal electrode 15, improving moisture resistance.

[0042] (Difference in Wrap-around Amount Between First Outer Layer 12a and Second Outer Layer 12b) In the embodiment, the wrap-around amount D11 of the first outer layer 12a into the gap region D1 is greater than the wrap-around amount D12 of the second outer layer 12b into the gap region D1. For example, it is preferable that the wrap-around amount D12 of the second outer layer 12b be 90% or less of the wrap-around amount D11 of the first outer layer 12a.

[0043] The moisture resistance can be improved by increasing the wraparound amount D11 of the outer layer portion 12 into the gap region D1. However, if the wraparound amount D12 of one of the outer layer portions 12 on the main surface side (the second outer layer portion 12b in this embodiment), which is the side on which the substrate is mounted, is too large, it is difficult to maintain flatness during mounting, which is not preferable.

[0044] However, for the other main surface side outer layer 12 (first outer layer 12a in this embodiment) that is not the substrate mounting side, there is no problem with mounting even if the wraparound amount D11 is increased, and the moisture resistance improves as the wraparound amount D11 increases.

[0045] Therefore, in the multilayer ceramic capacitor 1 of this embodiment, the wraparound amount D11 of the first outer layer portion 12 a is set larger than the wraparound amount D12 of the second outer layer portion 12 b, thereby making it possible to maximize moisture resistance while maintaining flatness during mounting.

[0046] (Difference in Wrap-around Amount Between Gap Region D1 and Pull-out Region D2) The wrap-around amount D11 of the first outer layer portion 12a into the gap region D1 shown in Fig. 3 is greater than the wrap-around amount D21 into the pull-out region D2, which is the pull-out region, shown in Fig. 2. The wrap-around amount D12 of the second outer layer portion 12b into the gap region D1 shown in Fig. 3 is greater than the wrap-around amount D22 into the pull-out region D2 shown in Fig. 2.

[0047] According to the embodiment, the current paths D21 and D22 of the outer layer portion 12 into the lead-out region D2 are smaller than the current paths D11 and D12 into the gap region D1, which prevents the current path from the mounting land to the lead-out region D2 from becoming too long. This improves the moisture resistance reliability without significantly increasing the ESL (equivalent series inductance).

[0048] (Definition of Wrap-around Amount) The wrap-around amounts D11 and D12 of each outer layer portion 12 into the gap region D1 are defined as follows. First, in the cross section shown in Fig. 3, two parallel lines are drawn: a line TW1 extending from the outermost surface of the internal electrode 15 closest to the first principal surface A1 to the horizontal direction W, and a line TW2 extending from the outermost surface of the internal electrode 15 closest to the second principal surface A2 to the horizontal direction W. Then, two parallel lines are drawn that are orthogonal to the lines TW1 and TW2 and pass through the end of the internal electrode 15 in the horizontal direction W, and a line passing through the end of the laminate 2 in the horizontal direction W. Within the region surrounded by these four lines, the area of ​​the first outer layer portion 12a that extends into the gap region D1 is the wrap-around amount D11 of the first outer layer portion 12a into the gap region D1. Similarly, the area of ​​the second outer layer portion 12b located inside the gap region D1 is the wraparound amount D12 of the second outer layer portion 12b into the gap region D1.

[0049] The wraparound amounts D21 and D22 of each outer layer portion 12 into the lead-out region D2 are defined as follows. First, in the cross section shown in Fig. 2, two parallel lines are drawn: a line TL1 extending from the outermost surface of the internal electrode 15 closest to the first principal surface A1 to the longitudinal direction L, and a line TL2 extending from the outermost surface of the internal electrode 15 closest to the second principal surface A2 to the longitudinal direction L. Then, two parallel lines are drawn that are orthogonal to the lines TL1 and TW2 and pass through the end of the internal electrode 15 in the longitudinal direction L, and a line passing through the end of the laminate 2 in the longitudinal direction L. Within the region surrounded by these four lines, the area of ​​the first outer layer portion 12a extending into the lead-out region D2 is the wraparound amount D21 of the first outer layer portion 12a into the lead-out region D2. Similarly, the area of ​​the second outer layer portion 12b that extends into the drawn-out region D2 is the wraparound amount D22 of the second outer layer portion 12b into the drawn-out region D2.

[0050] (Detection of Wraparound Amount) The boundary between the outer layer portion 12 and the inner dielectric layer 14 can be detected by observation using, for example, an FE-WDX (field emission electron microanalyzer). For example, if the amount of Si contained in the inner dielectric layer 14 located in the gap region D1 differs from the amount of Si contained in the outer layer portion 12, the boundary can be detected by the segregation of Si using an FE-WDX or the like. The boundary between the outer layer portion 12 and the inner dielectric layer 14 can also be detected by the difference in porosity between the outer layer portion 12 and the inner dielectric layer 14.

[0051] In the embodiment, the outer layer portion 12 contains barium titanate as a main component and Si and Mn as secondary components.

[0052] (Strain) In the embodiment, the strain of Si contained in the outer layer portion 12 and the internal dielectric layer 14 in the gap region D1 is preferably 0 or more and 0.5 or less. This improves moisture resistance without adversely affecting high-temperature reliability. The possibility that moisture penetrates from the outer layer portion 12, the first side surface B1, and the second side surface B2 and reaches the end-face exposed internal electrode 15 can be reduced, thereby improving moisture resistance.

[0053] (Definition of Skewness) The skewness of Si was calculated using the following method. First, the cross section of the multilayer ceramic capacitor 1 was polished to the position shown in FIG. 3, and the detected intensity of Si in each square was measured using WDX. More specifically, the observation field of view, 5 μm square, was divided into 38 × 38 squares, and the Si content was measured from the X-ray intensity spectrum of each square. Then, the calculation formula shown in FIG. 5 was used to calculate the skewness of Si. The calculation formula shown in FIG. 5 can also be calculated automatically. The calculation formula shown in FIG. 5 represents the degree to which the distribution is distorted from a normal distribution and is an index of left-right symmetry. In the calculation formula, n represents the sampling size, x represents the average value of each data xi (i: 1, 2, 3, ..., n), and s represents the standard deviation.

[0054] (Skewness of outer layer portion 12) Furthermore, the skewness of Si contained in the internal dielectric layer 14 in the gap region D1 is greater than the skewness of Si contained in the external layer portion 12. That is, the grain size of Si contained in the internal dielectric layer 14 in the gap region D1 varies more than the grain size of Si contained in the external layer portion 12. In other words, the grain size of Si contained in the external layer portion 12 is more uniform than the grain size of Si contained in the internal dielectric layer 14 in the gap region D1. In other words, the Si contained in the internal dielectric layer 14 in the gap region D1 has more significant segregation than the Si contained in the external layer portion 12.

[0055] The strain of Si contained in the internal dielectric layer 14 in the gap region D1 is preferably set to be 0.5% or more larger than the strain of Si contained in the outer layer portion 12. The larger the strain of Si, the better the moisture resistance, and therefore the moisture resistance of the internal dielectric layer 14 can be improved.

[0056] (Mn Content) Furthermore, in the embodiment, the Mn content contained in the outer layer portion 12 is greater than the Mn content of the internal dielectric layer 14 located in the gap region D1 and near the center in the stacking direction T. This can further improve the high-temperature reliability of the outer layer portion 12. Increasing the Mn content contained in the outer layer portion 12 can improve the density of the outer layer portion and improve the moisture resistance reliability. Note that, since increasing the moisture resistance reliability of only the outer layer with Mn would relatively increase the porosity of the gap region D1 and reduce the moisture resistance, the moisture resistance reliability of the gap region D1 is improved by the segregation of Si.

[0057] (End Face External Electrode 3) The end face external electrode 3 includes a first end face external electrode 3A and a second end face external electrode 3B. The first end face external electrode 3A is connected to the first end face exposed internal electrode 15A and is disposed on the first end face C1. The first end face external electrode 3A also includes a folded portion extending to the main face and part of the side face B. The second end face external electrode 3B is connected to the second end face exposed internal electrode 15B and is disposed on the second end face C2. The second end face external electrode 3B also includes a folded portion extending to the main face and part of the side face B. Hereinafter, unless it is necessary to particularly distinguish between the first end face external electrode 3A and the second end face external electrode 3B, they will be collectively referred to as the end face external electrode 3.

[0058] The end surface external electrode 3 includes a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The base electrode layer 31 includes, for example, a metal and a glass component. The metal includes, for example, at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc., and is copper in this embodiment. The glass component includes, for example, boron and silicon. The plating layer 32 may include a Ni (nickel) plating layer disposed on the base electrode layer 31 and a Sn (tin) plating layer disposed on the Ni plating layer.

[0059] (Method for manufacturing multilayer ceramic capacitor 1) (Method for adjusting the degree of distortion of Si) The degree of distortion of Si in the outer layer portion 12 and in the gap region D1 can be made different by making a difference in the particle size of the Si-containing particles, for example, glass particles, contained in the dielectric paste for the outer layer portion and the dielectric paste for the internal dielectric layer.

[0060] Specifically, when the standard glass particles in the dielectric paste for the outer dielectric layer are set to 0.005 μm or more and 0.5 μm or less, glass particles having a particle size larger than that by about 1.0 μm are mixed into the dielectric paste for the inner dielectric layer at 0.01 vol% or more and 40 vol% or less. On the other hand, the glass particles in the dielectric paste for the outer layer portion are contained with a particle size of 0.005 μm or more and 0.5 μm or less.

[0061] Then, the conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet prepared using the dielectric paste for the internal dielectric layers, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0062] Next, a predetermined number of second outer layer dielectric sheets prepared using the outer layer dielectric paste are laminated. Then, dielectric sheets for inner layer portions, on which internal electrode patterns are printed, are laminated in order. Finally, a predetermined number of first outer layer dielectric sheets prepared using the outer layer dielectric paste are laminated on top of these. This completes the laminated sheet process.

[0063] Next, the laminated sheet is pressed in the lamination direction T by means of a hydrostatic press or the like to produce a laminated block.

[0064] During this isostatic pressing, for example, a rubber that is thicker than the other parts is placed between adjacent laminates 2 so as to sandwich the laminated sheet in the stacking direction T, and by pressing, the outer layer 12 can be made to wrap around the gap region D1 and the pull-out region D2.

[0065] Furthermore, by using rubber with different hardness and thickness on the first principal surface A1 side and the second principal surface A2 side during isostatic pressing, the amount of intrusion of the first outer layer portion 12a can be made greater than the amount of intrusion of the second outer layer portion 12b. For example, if the rubber on the second principal surface A2 side is made harder, it will not be able to sufficiently press the regions closer to the second principal surface A2 side, thereby controlling the amount of flow. Furthermore, the amount of flow can also be changed by performing a pre-press after stacking multiple layers in the lamination process to harden the regions closer to the second principal surface A2 side. The method for intruding the outer layer portion 12 into the gap region D1 and the withdrawal region D2 and making the amount of intrusion of the first outer layer portion 12a greater than the amount of intrusion of the second outer layer portion 12b is not limited to the method described above and may be other methods.

[0066] Next, the laminated block is cut to a predetermined size to cut out laminated chips.

[0067] The laminated chip is then fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric and the end-face exposed internal electrodes 15, but is preferably 900°C or higher and 1400°C or lower.

[0068] Next, using a dipping method, the first end surface C1 of the laminate 2 is immersed in the conductive paste, which is the electrode material for the base electrode layer 31, to apply the conductive paste for the base electrode layer 31 to the first end surface C1. Similarly, the second end surface C2 of the laminate 2 is immersed in the conductive paste, which is the electrode material for the base electrode layer 31, to apply the conductive paste for the base electrode layer 31 to the second end surface C2. The conductive paste is then fired to form the fired layer, the base electrode layer 31. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0069] Thereafter, a plating layer 32 is formed on the surface of the base electrode layer 31 to form the end surface external electrodes 3. Through the above steps, the multilayer ceramic capacitor 1 of this embodiment is obtained.

[0070] Second Embodiment Next, a multilayer ceramic capacitor 100 according to a second embodiment of the present invention will be described. The multilayer ceramic capacitor 100 according to the second embodiment is a three-terminal multilayer ceramic capacitor 100. Hereinafter, in the multilayer ceramic capacitor 100 of the second embodiment, parts common to the multilayer ceramic capacitor 1 of the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0071] Fig. 6 is a schematic perspective view of the multilayer ceramic capacitor 100. Fig. 7 is a cross-sectional view taken along line VV in Fig. 6. Fig. 8 is a cross-sectional view taken along line VI-VI in Fig. 6. Fig. 9 is a cross-sectional view taken along line VII-VII in Fig. 6.

[0072] The multilayer ceramic capacitor 100 has a substantially rectangular parallelepiped shape and includes a pair of end surface external electrodes 3 provided on both ends of the laminate 2 as well as side surface external electrodes 4 .

[0073] (Inner layer portion 11) The inner layer portion 11 includes end surface exposed internal electrodes 16 and side surface exposed internal electrodes 17. Fig. 10 is a view of the inner layer portion 11 of the multilayer ceramic capacitor 100 as viewed from the first main surface A1 side, and the positions of the end surface exposed internal electrodes 16 (16a, 16b) and the side surface exposed internal electrodes 17 (17a, 17b) are indicated by dotted lines.

[0074] The end-exposed internal electrode 16 extends between both end faces C of the laminate 2 in the longitudinal direction L and is spaced a certain distance from both side faces B in the transverse direction W. The end-exposed internal electrode 16 has an end-facing portion 16a located in the center between the end faces C and end-drawn portions 16b extending from the end-facing portion 16a to both end faces C. The end-drawn portions 16b extend to both end faces C, are exposed at the end faces C of the laminate 2, and are connected to the end external electrodes 3 provided on both end faces in the longitudinal direction L of the laminate 2. The dimension of the end-facing portion 16a in the transverse direction W is smaller than the dimension of the end-drawn portion 16b in the transverse direction. The end-drawn portion 16b may have a tapered shape so that its width (dimension in the longitudinal direction L) gradually decreases from the connection point with the end-facing portion 16a.

[0075] The side surface exposed internal electrode 17 extends between both side surfaces B in the horizontal direction W of the laminate 2 and is spaced from both end surfaces C in the vertical direction L. The side surface exposed internal electrode 17 has a side surface facing portion 17a located in the center between the both side surfaces B and side surface drawn portions 17b extending from the side surface facing portion 17a to both side surfaces B. Although not limited thereto, the dimension of the side surface drawn portion 17b in the vertical direction L is smaller than the dimension of the side surface facing portion 17a in the vertical direction L. The side surface drawn portions 17b extend to both side surfaces B, are exposed at the side surfaces B of the laminate 2, and are connected to the side surface external electrodes 4 provided on both side surfaces in the horizontal direction W of the laminate 2.

[0076] 6, 7, and 8, the end face facing portion 16a of the end face exposed internal electrode 16 and the side face facing portion 17a of the side face exposed internal electrode 17 face each other, and a capacitance is formed between the end face facing portion 16a and the side face facing portion 17a. This allows the multilayer ceramic capacitor 100 to exhibit capacitor characteristics.

[0077] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. End face drawn portions 16b of the end face exposed internal electrodes 16 are connected to the end face external electrodes 3. The end face external electrodes 3 cover not only the end faces C but also parts of the main faces A and side faces B on the end face C side.

[0078] (Side surface external electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. The side surface external electrodes 4 are connected to the side surface drawn-out portions 17b of the side surface exposed internal electrodes 17. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the main surface A on the side surface B side.

[0079] 10, the region of the inner layer portion 11 where the end surface drawn-out portion 16b is laminated is referred to as an end surface drawn-out region E1. The region where the side surface drawn-out portion 17b is laminated is referred to as a side surface drawn-out region E2. The region between the end surface exposed internal electrode 16 and the side surface B, other than the side surface drawn-out region E2, is referred to as a three-terminal gap region E3.

[0080] According to this embodiment, the outer layer portion 12 is arranged so as to extend around the three-terminal gap region E3, the end surface drawing region E1, and the side surface drawing region E2.

[0081] As shown in Fig. 9, the wraparound amount E31 of the first outer layer portion 12a in the three-terminal gap region E3 is greater than the wraparound amount E32 of the second outer layer portion 12b. As shown in Fig. 7, the wraparound amount E11 of the first outer layer portion 12a in the end-face extension region E1 is greater than the wraparound amount E12 of the second outer layer portion 12b. As shown in Fig. 8, the wraparound amount E21 of the first outer layer portion 12a in the side-face extension region E2 is greater than the wraparound amount E22 of the second outer layer portion 12b.

[0082] Furthermore, the amount of wraparound E31 of the first outer layer portion 12a into the three-terminal gap region E3 shown in Figure 9 is greater than the amount of wraparound E11 of the first outer layer portion 12a into the end face extraction region E1 shown in Figure 7 or the amount of wraparound E21 into the side face extraction region E2 shown in Figure 8.

[0083] The amount of wraparound E32 of the second outer layer portion 12b into the three-terminal gap region E3 shown in Figure 9 is greater than the amount of wraparound E12 of the second outer layer portion 12b into the end face extraction region E1 shown in Figure 7 or the amount of wraparound E22 into the side face extraction region E2 shown in Figure 8.

[0084] As described above, the multilayer ceramic capacitor 100 of the second embodiment can also provide the following effects similar to those of the first embodiment.

[0085] That is, the outer layer portion 12 is pressed so as to extend around the three-terminal gap region E3, the end surface lead region E1, and the side surface lead region E2, thereby crimping the interfaces between the three-terminal gap region E3, the end surface lead region E1, and the side surface lead region E2 and the outer layer portion 12. This reduces the possibility that moisture from the outside will penetrate through the interfaces and reach the internal electrodes 16, 17, improving moisture resistance.

[0086] Furthermore, since the wraparound amount of the first outer layer portion 12a is greater than the wraparound amount of the second outer layer portion 12b, it is possible to maximize moisture resistance while maintaining flatness during mounting.

[0087] Furthermore, since the amount of current flowing into the end-face extraction region E1 and the side-face extraction region E2 of the outer layer portion 12 is smaller than the amount of current flowing into the three-terminal gap region E3, it is possible to prevent the current path from the mounting land to the end-face extraction region E1 and the side-face extraction region E2 from becoming too long, thereby improving the moisture resistance reliability without significantly increasing the ESL (equivalent series inductance).

[0088] Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various changes and modifications can be made as follows.

[0089] <1> A multilayer ceramic capacitor comprising: a laminate having first and second main surfaces opposed to each other in a stacking direction, two end surfaces opposed to each other in a vertical direction intersecting the stacking direction, and two side surfaces opposed to each other in a horizontal direction intersecting the stacking direction and the vertical direction; and two end surface external electrodes respectively arranged on the two end surfaces of the laminate, wherein the laminate comprises: an inner layer portion; and outer layer portions arranged to sandwich the inner layer portion in the stacking direction, the inner layer portion including a plurality of end surface exposed internal electrodes and a plurality of internal dielectric layers, the outer layer portions including a first outer layer portion located on the first main surface side and a second outer layer portion located on the second main surface side, the outer layer portions being arranged to wrap around into a gap region between the end surface exposed internal electrodes and the side surfaces, and a wraparound amount of the first outer layer portion into the gap region being greater than a wraparound amount of the second outer layer portion into the gap region.

[0090] <2> The multilayer ceramic capacitor according to <1>, wherein the amount of wraparound into the gap region of the second outer layer portion is 90% or less of the amount of wraparound into the gap region of the first outer layer portion.

[0091] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the Si content in the gap region near the center in the stacking direction is 0.2 at % or more and 5.0 at % or less.

[0092] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the Mn content of the outer layer portion is greater than the Mn content in the gap region near the center in the lamination direction.

[0093] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the end surface exposed internal electrode has an opposing portion opposing the adjacent end surface exposed internal electrode in the stacking direction, and a lead portion led from the opposing portion to one of the two end surfaces, and when a region in the laminate where the lead portion exists in the stacking direction is defined as a lead region, the outer layer portion is arranged to wrap around to the lead region, and a wraparound amount of the first outer layer portion into the gap region is larger than a wraparound amount of the first outer layer portion into the lead region.

[0094] <6> A laminate having a first main surface and a second main surface opposing each other in a stacking direction, two end surfaces opposing each other in a vertical direction intersecting the stacking direction, and two side surfaces opposing each other in a horizontal direction intersecting the stacking direction and the vertical direction, two end surface external electrodes respectively arranged on the two end surfaces of the laminate, and two side surface external electrodes respectively arranged on the two side surfaces of the laminate, wherein the laminate comprises an inner layer portion and outer layer portions arranged to sandwich the inner layer portion in the stacking direction, the outer layer portions including: a first outer layer portion located on the first main surface side; and a second outer layer portion located on the second main surface side, the inner layer portions including: a plurality of end surface exposed internal electrodes; a plurality of side surface exposed internal electrodes; and a plurality of internal dielectric layers, and the end surface exposed internal electrodes have an end surface opposing portion opposing the side surface exposed internal electrode in the stacking direction, and an end surface drawn portion drawn from the end surface opposing portion to the end surface of the laminate, the side surface exposed internal electrode has a side surface facing portion facing the end surface exposed internal electrode in the stacking direction, and a side surface drawn portion drawn from the side surface facing portion to the side surface of the laminate, wherein in the inner layer portion, in the stacking direction, a region where the end surface drawn portion overlaps is defined as an end surface drawn region, a region where the side surface drawn portion overlaps is defined as a side surface drawn region, and a region between the end surface exposed internal electrode and the side surface and where the region does not overlap with the side surface drawn region is defined as a three-terminal gap region, the outer layer portion is arranged to wrap around to the three-terminal gap region, and a wrapping amount of the first outer layer portion in the three-terminal gap region is greater than a wrapping amount of the second outer layer portion.

[0095] <7> The multilayer ceramic capacitor according to <6>, wherein the outer layer portion is arranged so as to wrap around the end surface drawn-out region and the side surface drawn-out region, and the amount of wrapping of the outer layer portion around the three-terminal gap region is greater than the amount of wrapping of the outer layer portion around the end surface drawn-out region or the side surface drawn-out region.

[0096] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein the ceramic grain diameter D50 of the internal dielectric layers is 0.15 μm or less.

[0097] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the thickness of the internal dielectric layer in the lamination direction is 0.45 μm or less.

[0098] <10> The multilayer ceramic capacitor according to any one of <1> to <9>, wherein the porosity of the outer layer portion is lower than the porosity of the gap region or the three-terminal gap region.

[0099] D1 Gap region D2 Lead-out region E1 End-face lead-out region E2 Side-surface lead-out region E3 Three-terminal gap region 1 Multilayer ceramic capacitor 2 Laminated body 3 End surface external electrode 3A First end surface external electrode 3B Second end surface external electrode 4 Side surface external electrode 11 Inner layer portion 12 Outer layer portion 12a First outer layer portion 12b Second outer layer portion 14 Internal dielectric layer 15 End surface exposed internal electrode 15A First end surface exposed internal electrode 15B Second end surface exposed internal electrode 16 End surface exposed internal electrode 17 Side surface exposed internal electrode

Claims

1. A multilayer ceramic capacitor comprising: a laminate having first and second main surfaces opposed in a lamination direction, two end surfaces opposed in a vertical direction intersecting the lamination direction, and two side surfaces opposed in a horizontal direction intersecting the lamination direction and the vertical direction; and two end surface external electrodes respectively arranged on the two end surfaces of the laminate, wherein the laminate comprises: an inner layer portion; and an outer layer portion arranged to sandwich the inner layer portion in the lamination direction, the inner layer portion including a plurality of end surface exposed internal electrodes and a plurality of internal dielectric layers, the outer layer portion including a first outer layer portion located on the first main surface side and a second outer layer portion located on the second main surface side, the outer layer portions being arranged to wrap around into a gap region between the end surface exposed internal electrodes and the side surfaces, and an amount of wrapping around the gap region of the first outer layer portion is greater than an amount of wrapping around the gap region of the second outer layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the amount of wraparound of said second outer layer portion into said gap region is 90% or less of the amount of wraparound of said first outer layer portion into said gap region.

3. The multilayer ceramic capacitor according to claim 1, wherein the Si content in the gap region near the center in the lamination direction is 0.2 at % or more and 5.0 at % or less.

4. The multilayer ceramic capacitor according to claim 1, wherein the Mn content of the outer layer portion is greater than the Mn content of the gap region near the center in the lamination direction.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the end face exposed internal electrode has an opposing portion opposing the adjacent end face exposed internal electrode in the stacking direction, and a lead portion led out from the opposing portion to one of the two end faces, and when a region in the laminate in the stacking direction in which the lead portion exists is defined as a lead region, the outer layer portion is arranged to wrap around to the lead region, and an amount of wraparound of the first outer layer portion into the gap region is greater than an amount of wraparound of the first outer layer portion into the lead region.

6. A laminate having a first main surface and a second main surface opposed to each other in a lamination direction, two end surfaces opposed to each other in a vertical direction intersecting the lamination direction, and two side surfaces opposed to each other in a horizontal direction intersecting the lamination direction and the vertical direction, two end surface external electrodes respectively arranged on the two end surfaces of the laminate, and two side surface external electrodes respectively arranged on the two side surfaces of the laminate, wherein the laminate comprises an inner layer portion and an outer layer portion arranged to sandwich the inner layer portion in the lamination direction, wherein the outer layer portion includes a first outer layer portion located on the first main surface side and a second outer layer portion located on the second main surface side, wherein the inner layer portion includes a plurality of end surface exposed internal electrodes, a plurality of side surface exposed internal electrodes, and a plurality of internal dielectric layers, and the end surface exposed internal electrodes have an end surface opposing portion opposed to the side surface exposed internal electrodes in the lamination direction, and an end surface drawn portion drawn from the end surface opposing portion to the end surface of the laminate, a side surface exposed internal electrode having a side surface facing portion facing the end surface exposed internal electrode in the stacking direction, and a side surface drawn portion drawn from the side surface facing portion to the side surface of the laminate, wherein, in the inner layer portion, in the stacking direction, a region where the end surface drawn portion overlaps is defined as an end surface drawn region, a region where the side surface drawn portion overlaps is defined as a side surface drawn region, and a region between the end surface exposed internal electrode and the side surface and not overlapping with the side surface drawn region is defined as a three-terminal gap region, wherein the outer layer portion is arranged to wrap around to the three-terminal gap region, and a wrapping amount of the first outer layer portion in the three-terminal gap region is greater than a wrapping amount of the second outer layer portion.

7. The multilayer ceramic capacitor according to claim 6, wherein the outer layer portion is arranged so as to wrap around the end face drawn-out region and the side face drawn-out region, and the amount of wrapping of the outer layer portion around the three-terminal gap region is greater than the amount of wrapping of the outer layer portion around the end face drawn-out region or the side face drawn-out region.

8. The multilayer ceramic capacitor according to claim 1, wherein the ceramic grain diameter D50 of the internal dielectric layer is 0.15 μm or less.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein the thickness of the internal dielectric layer in the lamination direction is 0.45 µm or less.

10. A multilayer ceramic capacitor according to any one of claims 1 to 9, wherein the porosity of the outer layer portion is lower than the porosity of the gap region or the three-terminal gap region.

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