Method for optimizing delay time on basis of transistor characteristics and device therefor

Abstract

According to various embodiments of the present invention, by applying a method for optimizing a delay time on the basis of transistor characteristics and a device therefor, it is possible to optimize a delay time of an electronic circuit and improve the performance and efficiency of the circuit. By classifying each transistor into one of a plurality of types and determining a delay time model according to the characteristics thereof, precise optimization is enabled.

Description

Transistor characteristic-based delay time optimization method and device therefor

[0001] The present invention relates to a method for optimizing delay time based on transistor characteristics and a device therefor.

[0002] This research is related to the "Research and Development of Neurochip Design Technology and Neurocomputing Platform Mimicking the Human Nervous System (No. RS-2022-00156225)" project, which was supported by the National IT Industry Promotion Agency (NIPA) and funded by the Ministry of Science and ICT (MSIT). The project identification number is 1711179305, and the lead organization for this project is the Industry-Academic Cooperation Foundation of Kwangwoon University.

[0003] Furthermore, the research of the present invention is related to the "Development of a Non-Volatile PIM Memory Module and Memory Compiler Optimized for the Data Characteristics and Data Access Characteristics of AI Processors (No. RS-2023-00222085)" project, a core development project for PIM artificial intelligence semiconductors supported by the National IT Industry Promotion Agency (NIPA) and funded by the Ministry of Science and ICT. The project identification number is 1711195784, and the lead organization for this project is the Yonsei University Industry-Academic Cooperation Foundation.

[0004] The content described in this section merely provides background information for the present embodiment and does not constitute prior art.

[0005] A netlist is a data structure that represents the physical or logical connections between circuit components. Netlists can be used to model and simulate circuits in computer-aided design (CAD) tools.

[0006] A netlist can typically contain information about components, nets, pins, values, and attributes. Components represent various components in a circuit. Examples include resistors, capacitors, transistors, and ICs. Nets represent connections between the pins of each component in a circuit. A "net" represents an electrical connection from one point to another in a circuit. Each component has one or more pins, which serve as connection points to other components in the netlist.

[0007] Each component can have specific values ​​(e.g., the resistance of a resistor) and characteristics (e.g., voltage rating, current rating). The format of a netlist can vary, from a simple text file to a complex XML or JSON structure.

[0008] Netlists can be used to verify the logical correctness of a design, track design changes, and serve as a data exchange format between various design tools. Various specialized software programs related to electronic circuit design support their own netlist formats, and sometimes even use netlist conversion tools to ensure compatibility between different formats.

[0009] The delay time of an integrated circuit comprised of numerous transistors varies depending on the size of the transistors, making it difficult to accurately predict the delay time. Finding the combination of transistor sizes that minimizes delay time is difficult during the circuit design process, requiring significant investment in optimization.

[0010] Recently, active research and development has been conducted on optimization methods using reinforcement learning. However, these methods require an average of over 5,000 simulations, making them time-consuming. To address this issue, research and development are needed to develop technologies that can quickly optimize circuits by modeling delay times based on transistor size characteristics (e.g., width).

[0011] (Patent Document 0001) Republic of Korea Patent Publication No. 10-2023-0144396 (October 16, 2023)

[0012] The purpose of the present invention is to provide a transistor characteristic-based delay time optimization method and a device therefor that can optimize the delay time of an electronic circuit and improve the performance and efficiency of the circuit.

[0013] In addition, the purpose of the present invention is to provide a transistor characteristic-based delay time optimization method and a device therefor, which enable precise optimization by classifying each transistor into one of a plurality of types and determining a delay time model according to the characteristics thereof.

[0014] Additional, unspecified, purposes of the present invention can be additionally considered within the scope that can be easily inferred from the detailed description and effects thereof below.

[0015] According to one embodiment of the present invention for achieving the above-described object, a transistor characteristic-based delay time optimization device includes a memory storing one or more programs for optimizing the delay time of an electronic circuit, and one or more processors for performing operations according to the one or more programs, wherein the processor receives information about the electronic circuit from the outside, classifies at least one transistor included in the electronic circuit into at least one of a plurality of transistor types based on a change in the electrical characteristics of a node directly or indirectly connected to the transistor, determines a circuit delay time model based on a classification result of the transistor, and determines a characteristic value of the transistor capable of optimizing the delay time based on the circuit delay time model.

[0016] The processor is characterized in that the transistor is classified into at least one of the plurality of transistor types in such a way that a transistor that adjusts a voltage of a node directly or indirectly connected to the transistor is classified as a driver transistor.

[0017] The above processor is characterized in that it determines the circuit delay time model using a first variable determined based on a proportional relationship between the width and delay time of a transistor classified as the driver transistor.

[0018] The processor is characterized in that the transistor is classified as at least one of the plurality of transistor types in such a way that a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor is classified as a load transistor.

[0019] The above processor is characterized in that it determines the circuit delay time model using a second variable determined based on the inverse relationship between the width and delay time of a transistor classified as the load transistor.

[0020] The above processor is characterized in that it obtains a delay time value through simulation for each transistor classified into the plurality of transistor types, and obtains a weight for use in the circuit delay time model by using the width of each transistor classified into the plurality of transistor types and the delay time value as a data set.

[0021] The above processor is characterized in that it obtains the weight in the form of a set of weight values ​​corresponding to the number of transistors classified into the plurality of transistor types.

[0022] The above processor is characterized in that it obtains a loss function that uses the circuit delay time model and the delay time value as variables, and determines the width of a transistor having a minimum delay time obtained using the loss function as a characteristic value of the transistor.

[0023] According to one embodiment of the present invention for achieving the above-described object, a method performed in a device including a memory storing one or more programs for optimizing a delay time of an electronic circuit; and one or more processors performing operations according to the one or more programs may include the steps of: receiving information about the electronic circuit from an external source; classifying at least one transistor included in the electronic circuit into at least one of a plurality of transistor types based on a change in electrical characteristics of a node directly or indirectly connected to the transistor; determining a circuit delay time model based on a classification result of the transistor; and determining a characteristic value of the transistor capable of optimizing the delay time based on the circuit delay time model.

[0024] The step of classifying at least one of the plurality of transistor types is characterized in that the transistor is classified as at least one of the plurality of transistor types in a manner that a transistor that adjusts a voltage of a node directly or indirectly connected to the transistor is classified as a driver transistor.

[0025] The step of determining a circuit delay time model based on the classification result of the transistor is characterized in that the circuit delay time model is determined using a first variable determined based on a proportional relationship between the width and delay time of the transistor classified as the driver transistor.

[0026] The step of classifying the transistor into at least one of the plurality of transistor types is characterized in that the transistor is classified into at least one of the plurality of transistor types in a manner that a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor is classified as a load transistor.

[0027] The step of determining a circuit delay time model based on the classification result of the transistor is characterized in that the circuit delay time model is determined using a second variable determined based on an inverse relationship between the width and delay time of the transistor classified as the load transistor.

[0028] The step of determining a circuit delay time model based on the classification result of the transistor includes the step of obtaining a delay time value through simulation for each of the transistors classified into the plurality of transistor types; and the step of obtaining a weight for use in the circuit delay time model by using the width of each of the transistors classified into the plurality of transistor types and the delay time value as a data set.

[0029] A computer program according to one embodiment of the present invention for achieving the above-described purpose is stored in a computer-readable recording medium and executes one of the above-described transistor characteristic-based delay time optimization methods on a computer.

[0030] As described above, according to one embodiment of the present invention, by applying a method for optimizing delay time based on transistor characteristics and a device therefor, the delay time of an electronic circuit can be optimized and the performance and efficiency of the circuit can be improved.

[0031] In addition, by applying a transistor characteristic-based delay time optimization method and a device therefor, precise optimization is possible by classifying each transistor into one of multiple types and determining a delay time model based on its characteristics.

[0032] Even if the effect is not explicitly mentioned herein, the effect and its provisional effect described in the following specification expected by the technical features of the present invention are treated as described in the specification of the present invention.

[0033] FIG. 1 is a drawing for explaining the configuration of a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0034] FIG. 2 is a drawing for explaining distinguishing the transistor type of a transistor included in an electronic circuit and determining a circuit delay time model in a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0035] FIG. 3 is a diagram for explaining obtaining a delay time value, obtaining a weight, and using a loss function through simulation in a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0036] FIG. 4 is a drawing for explaining the operation result of a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0037] FIG. 5 is a flowchart illustrating a transistor characteristic-based delay time optimization method according to one embodiment of the present invention.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the present invention of the scope of the invention, and the present invention is defined only by the scope of the claims. Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in a meaning that can be commonly understood by those skilled in the art of the present invention. In addition, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined.

[0039] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms “have,” “may have,” “include,” or “may include” specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Terms including ordinal numbers such as second, first, etc. may be used to describe various components, but the components are not limited by the terms.

[0040] The above terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component could be referred to as a first component, and similarly, a first component could also be referred to as a second component. The term "and / or" includes any combination of multiple related items described herein or any one of multiple related items described herein.

[0041] In this specification, the identification numbers (e.g., a, b, c, etc.) for each step are used for convenience of explanation and do not describe the order of each step. Each step may occur in a different order than specified unless the context clearly indicates a specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the opposite order.

[0042] Hereinafter, various embodiments of a transistor characteristic-based delay time optimization method and a device therefor according to the present invention will be described in detail with reference to the attached drawings.

[0043] The increasing use of cutting-edge systems such as mobile phones, computers, and self-driving cars is driving the growth of integrated circuits. As the demand for high speeds in integrated circuits grows, interest in reducing delays continues.

[0044] The embodiments described in this specification can be used in the manufacture or design of SoCs (System-on-Chips), SRAMs (Static Random Access Memory), and DRAMs (Dynamic Random Access Memory), and more broadly, can be applied to mobile phones, wireless earphones, IoT home appliances, computers, and autonomous vehicles.

[0045] FIG. 1 is a drawing for explaining the configuration of a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0046] A transistor characteristic-based delay time optimization device (100) includes at least one processor (110), a computer-readable storage medium (120), a communication bus (150), and an artificial intelligence-based processing unit (160).

[0047] The processor (110) can be controlled to operate as a transistor characteristic-based delay time optimization device (100). For example, the processor (110) can execute one or more programs (121) stored in a computer-readable storage medium (120). The one or more programs (121) can include one or more computer-executable instructions, and the computer-executable instructions, when executed by the processor (110), can be configured to cause the transistor characteristic-based delay time optimization device (100) to perform operations according to an exemplary embodiment.

[0048] A computer-readable storage medium (120) is configured to store computer-executable instructions or program code, program data, and / or other suitable forms of information. The computer-executable instructions or program code, program data, and / or other suitable forms of information may also be provided via an input / output interface (130) or a communication interface (140). A program (121) stored in the computer-readable storage medium (120) includes a set of instructions executable by the processor (110). In one embodiment, the computer-readable storage medium (120) may be a memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or any other form of storage medium that can be accessed by the transistor characteristic-based delay time optimization device (100) and store desired information, or a suitable combination thereof.

[0049] A communication bus (150) interconnects various other components of the transistor characteristic-based delay time optimization device (100), including a processor (110) and a computer-readable storage medium (120).

[0050] The transistor characteristic-based delay optimization device (100) may also include one or more input / output interfaces (130) and one or more communication interfaces (140) that provide interfaces for one or more input / output devices. The input / output interfaces (130) and the communication interfaces (140) are connected to a communication bus (150). The input / output devices (not shown) may be connected to other components of the transistor characteristic-based delay optimization device (100) via the input / output interfaces (130).

[0051] The processor (110) receives information about an electronic circuit from the outside, classifies at least one transistor included in the electronic circuit into at least one of a plurality of transistor types based on changes in electrical characteristics of a node directly or indirectly connected to the transistor, determines a circuit delay time model based on the classification result of the transistor, and determines characteristic values ​​of the transistor that can optimize the delay time based on the circuit delay time model.

[0052] Information about an electronic circuit can include information about various components and characteristics within the circuit. This information can be in the form of a netlist. For example, information about an electronic circuit can include detailed information about all transistors and other components (e.g., resistors and capacitors) within the circuit, including the type, size, location, and connection information for each component. Furthermore, information about an electronic circuit can include information about each node in the circuit and the connections between them. Furthermore, information about an electronic circuit can include information about the electrical characteristics of transistors and other components. For example, this can include information about voltage, current, capacitance, and resistance values.

[0053] The artificial intelligence-based processing unit (160) may perform operations necessary for the transistor characteristic-based delay time optimization method in conjunction with the processor (110). For example, the artificial intelligence-based processing unit (160) may perform operations related to artificial intelligence in conjunction with the processor (110) while the processor (110) performs operations necessary for the transistor characteristic-based delay time optimization method.

[0054] The AI-based processing unit (160) can analyze and preprocess information about electronic circuits received from external sources. The AI-based processing unit (160) calculates weights to be used in the circuit delay time model, thereby determining the width of the transistor with the minimum delay time. During this process, a loss function can be used to identify optimal parameters.

[0055] The AI-based processing unit (160) continuously fits new data obtained through simulations to the model, thereby identifying the optimal transistor width combination for minimizing latency. During this process, the AI ​​algorithm can concentrate data acquisition near the point where latency is minimized, thereby improving model accuracy.

[0056] FIG. 2 is a drawing for explaining distinguishing the transistor type of a transistor included in an electronic circuit and determining a circuit delay time model in a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0057] The processor may classify a transistor into at least one of a plurality of transistor types, such that a transistor that regulates a voltage at a node directly or indirectly connected to the transistor is classified as a driver transistor.

[0058] The processor can determine a circuit delay time model using a first variable determined based on a proportional relationship between the width and delay time of a transistor classified as a driver transistor.

[0059] The first variable may be x, which indicates that the width of the transistor is proportional to the delay time, but is not necessarily limited to this. 2 , x 3 It can be a variety of variables whose function value increases as the value of x increases.

[0060] The processor may classify a transistor into at least one of a plurality of transistor types by classifying a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor as a load transistor.

[0061] The processor can determine the circuit delay time model using a second variable determined based on the inverse relationship between the width and delay time of a transistor classified as a load transistor.

[0062] The second variable can be, but is not limited to, 1 / x, which indicates that the width and delay time of the transistor are inversely proportional. 2 , 1 / x 3It can be a variety of variables whose function values ​​decrease as the x value decreases.

[0063] Fig. 2 (a) is a drawing showing an inverter chain, and Fig. 2 (b) is a graph showing a delay time according to a change in width classified according to the transistor type.

[0064] Because capacitance and current fluctuate with the width of the transistor, delay times can increase or decrease. This change in delay time is determined by whether the transistor's role is to change the node voltage by flowing current or to change the node's capacitance. Therefore, to model the delay time of integrated circuits at the transistor level, considering these trends, transistors are divided into driver transistors and load transistors.

[0065] A driver transistor can be a transistor that changes the voltage of a node connected to its drain by passing current through it. A load transistor can be a transistor connected to the rear of the driver transistor and that affects capacitance. Here, the rear may refer to the direction of current flow or the circuit's operating sequence, but is not necessarily limited thereto.

[0066] In the inverter chain of Fig. 2 (a), the nFET constituting the second inverter (INV2) can be determined as a load transistor based on the in2 node. As shown in Fig. 2 (b), it can be confirmed that as the width of the nFET, which is the load transistor, increases, the delay from the in1 node to the in2 node increases linearly.

[0067] On the other hand, the nFET of INV2 is defined as a driver transistor because it changes the voltage of the in3 node by flowing current based on the in3 node. As shown in Fig. 2 (b), it can be confirmed that as the width of the nFET, which is the driver transistor, increases, the delay from the in2 node to the in3 node decreases in an inversely proportional relationship.

[0068] As can be seen in the graph of (b) of Fig. 2, the relationship between the width of the load transistor and the delay time is proportional, so it can be defined as having the form of x (i.e., the first variable can be determined as x), and the relationship between the width of the driver transistor and the delay is inversely proportional, so the delay time according to the change in the width of the driver transistor can be defined as having the form of 1 / x (i.e., the second variable can be determined as 1 / x).

[0069] FIG. 3 is a diagram for explaining obtaining a delay time value, obtaining a weight, and using a loss function through simulation in a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0070] The processor can obtain delay time values ​​through simulation for each transistor classified into multiple transistor types, and can obtain weights for use in a circuit delay time model by using the width and delay time values ​​of each transistor classified into multiple transistor types as a data set.

[0071] The processor may obtain weights in the form of a set of weight values ​​corresponding to the number of transistors classified into multiple transistor types. For example, the weight values ​​may be obtained in the same number as the number of transistors, but is not necessarily limited thereto. The weight values ​​may also be obtained in the form of a number that is an integer multiple of the number of transistors, or may be obtained in the form of an integer less or more than the number of transistors.

[0072] The processor can obtain a circuit delay model and a loss function that uses delay values ​​as variables. Using the loss function, the processor can determine the width of the transistor with the minimum delay as a characteristic value of the transistor. These determined transistor characteristics can then be used in electronic circuit design.

[0073] By distinguishing the roles of transistors, we can infer what waveforms the inter-node delay time will take as the widths of various transistors change. Therefore, a circuit delay time model can be formed that predicts the waveform using a vector x composed of variables corresponding to the widths of the transistor roles and a weight (W, weight). This delay time can then be modeled by fitting the circuit delay time model to the acquired simulation data and calculating the weights.

[0074] For example, when modeling the delay time from in1 to out for the circuit (a) of Fig. 2, the driver transistors are P1, N2, and P3, and the load transistors are N2 and P3. In particular, the transistors N2 and P3 act as both driver transistors and load transistors when determining the delay from the in1 to out node. Therefore, if the widths of the transistors P1, N2, and P3 are defined as x1, x2, and x3, respectively, the circuit delay time model f(x, W) can be determined as in the following mathematical expression 1.

[0075]

[0076] Here, x1, x2, and x3 may represent the widths of transistors included in the corresponding electronic circuit, respectively, and w1, w2, w3, w4, w5, and w6 may represent weight values, respectively. x may mean a vector whose components are a first variable, a second variable, or a constant, and W may mean a vector whose components are weight values.

[0077] That is, the circuit delay time model may be a Hadamard product of a vector x whose components include a first variable or a second variable determined based on the width of a transistor included in an electronic circuit, and a vector W whose components include weight values ​​corresponding to the width of a transistor included in an electronic circuit.

[0078] Here, the vector x may include not only the first variable or the second variable, but also a constant value (e.g., 1) as in Equation 1. Correspondingly, the vector W may include an adjustment weight (w6 in the example above) corresponding to the constant value of the vector x.

[0079] The reason for including a constant in the last element of vector x may be to represent a bias term. In machine learning and statistical modeling, bias terms can be used to adjust models when data do not pass through the origin. The adjustment weights included in vector W can be used to adjust this bias value.

[0080] The circuit delay model can also be the inner product of vector x and vector W.

[0081] As the formed circuit delay time model gradually acquires simulation data, a loss function is defined as in Equation 2 below, and weights are calculated as values ​​that minimize the loss function, so that the circuit delay time model is increasingly accurately fitted to the simulation data.

[0082] The loss function for obtaining the weights of the circuit delay time model can be determined as shown in the mathematical expression 2 below.

[0083]

[0084] Here, f(x i , W) represents the circuit delay time model, and y i represents the time delay value, and Loss represents the loss function.

[0085] The processor gradually acquires simulation data concentrated near the point where latency is minimal, enabling accurate model fitting near the minimum value. The algorithm for acquiring data at the minimum point and forming a circuit latency model is shown in Figure 3.

[0086] First, to model the circuit delay time, transistors existing in the delay path are selected, and each transistor is classified into a driver transistor and a load transistor according to its role to form a circuit delay time model f(x, W). To obtain W, the weight required to form the circuit delay time model, the initial data set is determined randomly or according to the user's input, and the circuit delay time y is obtained through SPICE simulation. i Secure. Secured (x i , y i ) After adding the data pair to the data set U, the weight W of the circuit delay model is calculated.

[0087] Afterwards, the circuit delay time model f(x i , W) is the minimum of x i Extract and simulate, repeating the previous process to gradually (x i , y i ) is obtained. According to the algorithm, data pairs (x i , y i ) is intensively secured near the minimum value, and this allows for the optimal transistor width combination with the minimum delay time to be obtained with a small amount of simulation by accurately modeling the model near the minimum value.

[0088] FIG. 4 is a drawing for explaining the operation result of a transistor characteristic-based delay time optimization device according to one embodiment of the present invention.

[0089] Among the circuits that generate XOR and XNOR with 10 transistors, optimization was performed on two transistors that form the critical path. To verify that the algorithm finds the minimum delay time, the delay was extracted by simulating the range of 100 nm to 3000 nm at intervals of 50 nm, and visualized as Reference Data in the graph (a) of Fig. 4.

[0090] The results of the three random samplings performed to secure initial data are shown as Initial Random data in the graph (a) of Fig. 4, and the values ​​are listed in Random Sampling in the table (b) of Fig. 4. A circuit delay time model is created by the weight calculated with the data set secured as sampling data, and x, which creates the minimum value of the circuit delay time model i The recommended data in Fig. 4 (a) is obtained through a repetitive process of performing simulations to the next sampling point, and it can be confirmed that the minimum point of delay time is gradually found with a small amount of simulations.

[0091] FIG. 5 is a flowchart illustrating a transistor characteristic-based delay time optimization method according to one embodiment of the present invention.

[0092] A method for optimizing delay time based on transistor characteristics can be performed in a device including a memory storing one or more programs for optimizing delay time of an electronic circuit and one or more processors for performing operations according to one or more programs. For example, the method for optimizing delay time based on transistor characteristics can be performed by a transistor characteristic-based delay time optimization device described with reference to FIG. 1.

[0093] At step S100, the processor can receive information about the electronic circuit from an external source.

[0094] At step S200, the processor can classify at least one transistor included in the electronic circuit into at least one of a plurality of transistor types based on a change in electrical characteristics of a node directly or indirectly connected to the transistor.

[0095] At step S300, the processor can determine a circuit delay time model based on the classification results of the transistors.

[0096] At step S400, the processor can determine the characteristics of the transistors that can optimize the delay time based on the circuit delay time model.

[0097] In the step (S200) of classifying the transistor into at least one of the plurality of transistor types, the processor may classify the transistor into at least one of the plurality of transistor types by classifying a transistor that adjusts a voltage of a node directly or indirectly connected to the transistor as a driver transistor.

[0098] In the step (S300) of determining a circuit delay time model based on the classification result of the transistor, the processor can determine the circuit delay time model using a first variable determined based on the proportional relationship between the width and delay time of the transistor classified as a driver transistor.

[0099] In the step (S200) of classifying the transistor into at least one of the plurality of transistor types, the processor may classify the transistor into at least one of the plurality of transistor types by classifying a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor as a load transistor.

[0100] In the step (S300) of determining a circuit delay time model based on the classification result of the transistor, the processor can determine the circuit delay time model using a second variable determined based on the inverse relationship between the width and delay time of the transistor classified as a load transistor.

[0101] In the step (S300) of determining a circuit delay time model based on the classification result of the transistor, the processor may include a step of obtaining a delay time value through simulation for each transistor classified into a plurality of transistor types, and a step of obtaining a weight for use in the circuit delay time model by using the width and delay time value of each transistor classified into a plurality of transistor types as a data set.

[0102] Although FIG. 5 describes each process as being executed sequentially, this is merely an example, and those skilled in the art may modify and apply various modifications and variations, such as changing the order described in FIG. 5, executing one or more processes in parallel, or adding other processes, without departing from the essential characteristics of the embodiments of the present invention.

[0103] The present invention discloses a high-speed circuit optimization methodology through transistor-level circuit delay modeling. The present invention describes a method for finding optimal combinations of transistor widths that minimize delay with a small amount of simulation by modeling delays caused by variations in transistor width.

[0104] This methodology models circuits at the transistor level and improves model accuracy by intensively acquiring data near the point where delay is minimized. Therefore, by identifying the optimal transistor width combination that minimizes circuit delay with minimal simulation, this methodology, when applied to delay optimization of existing transistor-level integrated circuits, can achieve delay optimization in a short period of time with minimal simulation. Further development of this methodology could provide a powerful tool for reducing design optimization time in industrial settings.

[0105] The present application also provides a computer storage medium. The computer storage medium stores program instructions, and when the program instructions are executed by a processor, the aforementioned transistor characteristic-based delay time optimization method is realized.

[0106] A computer storage medium according to one embodiment of the present invention may be, but is not necessarily limited to, a U disk, an SD card, a PD optical drive, a mobile hard disk, a large-capacity floppy drive, a flash memory, a multimedia memory card, a server, etc.

[0107] Even though all components constituting the embodiments of the present invention described above are described as being combined as one or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all of the components may be selectively combined and operated one or more times. In addition, although all of the components may be implemented as individual independent hardware, some or all of the components may be selectively combined and implemented as a computer program having program modules that perform some or all of the functions of the combined hardware in one or more pieces. In addition, such a computer program may be stored in a computer-readable medium such as a USB memory, a CD disk, or a flash memory, and read and executed by a computer, thereby implementing the embodiments of the present invention. The recording medium of the computer program may include a magnetic recording medium, an optical recording medium, etc.

[0108] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications, changes, and substitutions may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention and the accompanying drawings are not intended to limit the technical idea of ​​the present invention, but rather to explain it, and the scope of the technical idea of ​​the present invention is not limited by these embodiments and the accompanying drawings. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A memory storing one or more programs for optimizing the delay time of an electronic circuit and one or more processors performing operations according to the one or more programs, wherein the processors, Input information about the above electronic circuit from the outside, Classifying at least one transistor included in the above electronic circuit into at least one of a plurality of transistor types based on changes in electrical characteristics of a node directly or indirectly connected to the transistor, A transistor characteristic-based delay time optimization device, which determines a circuit delay time model based on the classification result of the above transistor, and determines a characteristic value of the transistor capable of optimizing the delay time based on the circuit delay time model.

2. In paragraph 1, The above processor, A transistor characteristic-based delay time optimization device characterized in that the transistor is classified into at least one of the plurality of transistor types in such a way that a transistor that adjusts the voltage of a node directly or indirectly connected to the transistor is classified as a driver transistor.

3. In paragraph 2, The above processor, A transistor characteristic-based delay time optimization device, characterized in that the circuit delay time model is determined using a first variable determined based on a proportional relationship between the width and delay time of a transistor classified as the driver transistor.

4. In paragraph 1, The above processor, A transistor characteristic-based delay time optimization device characterized in that the transistor is classified into at least one of the plurality of transistor types in such a way that a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor is classified as a load transistor.

5. In paragraph 4, The above processor, A transistor characteristic-based delay time optimization device, characterized in that the circuit delay time model is determined using a second variable determined based on the inverse relationship between the width and delay time of a transistor classified as the load transistor.

6. In paragraph 1, The above processor, For each transistor classified into the above multiple transistor types, a delay time value is obtained through simulation, A transistor characteristic-based delay time optimization device characterized in that the width and delay time values ​​of each transistor classified into the above-mentioned plurality of transistor types are used as a data set to obtain weights for use in the circuit delay time model.

7. In paragraph 6, The above processor, A transistor characteristic-based delay time optimization device, characterized in that the weights are obtained in the form of a set of weight values ​​corresponding to the number of transistors classified into the plurality of transistor types.

8. In paragraph 7, The above processor, A transistor characteristic-based delay time optimization device characterized in that it obtains a loss function that uses the circuit delay time model and the delay time value as variables, and determines the width of a transistor having a minimum delay time obtained using the loss function as a characteristic value of the transistor.

9. A method performed in a device including a memory storing one or more programs for optimizing the delay time of an electronic circuit; and one or more processors performing operations according to the one or more programs; A step of receiving information about the electronic circuit from the outside; A step of classifying at least one transistor included in the electronic circuit into at least one of a plurality of transistor types based on a change in electrical characteristics of a node directly or indirectly connected to the transistor; A step of determining a circuit delay time model based on the classification result of the above transistor; and A method for optimizing delay time based on transistor characteristics, comprising: a step of determining a characteristic value of the transistor capable of optimizing the delay time based on the circuit delay time model.

10. In paragraph 9, The step of classifying at least one of the above plurality of transistor types is: A method for optimizing delay time based on transistor characteristics, characterized in that the transistor is classified into at least one of the plurality of transistor types in such a way that a transistor that adjusts the voltage of a node directly or indirectly connected to the transistor is classified as a driver transistor.

11. In paragraph 10, The step of determining the circuit delay time model based on the classification result of the above transistor is: A transistor characteristic-based delay time optimization method, characterized in that the circuit delay time model is determined using a first variable determined based on a proportional relationship between the width and delay time of a transistor classified as the driver transistor.

12. In paragraph 9, The step of classifying at least one of the above plurality of transistor types is: A method for optimizing delay time based on transistor characteristics, characterized in that the transistor is classified as at least one of the plurality of transistor types in such a way that a transistor that adjusts the capacitance of a node directly or indirectly connected to the transistor is classified as a load transistor.

13. In paragraph 12, The step of determining the circuit delay time model based on the classification result of the above transistor is: A transistor characteristic-based delay time optimization method, characterized in that the circuit delay time model is determined using a second variable determined based on the inverse relationship between the width and delay time of a transistor classified as the load transistor.

14. In paragraph 9, The step of determining the circuit delay time model based on the classification result of the above transistor is: A step of obtaining a delay time value through simulation for each transistor classified into the above plural transistor types; and A method for optimizing delay time based on transistor characteristics, characterized by comprising: a step of obtaining weights for use in the circuit delay time model by using the width and delay time values ​​of each transistor classified into the plurality of transistor types as a data set.

15. A computer program stored in a computer-readable recording medium for executing the transistor characteristic-based delay time optimization method described in any one of claims 9 to 14 on a computer.

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