Multi-layer wiring board

Abstract

This multi-layer wiring board comprises: a glass substrate including a reinforcement part on a surface part; and a wiring laminate disposed on the reinforcement part, and including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors. Characteristics of the glass substrate can be sufficiently utilized while the durability of the glass substrate is enhanced through the reinforcing part.

Description

multilayer wiring board

[0001] The present invention relates to a multilayer wiring board. More specifically, it relates to a multilayer wiring board including multiple insulating layers and wiring layers.

[0002]

[0003] For example, a multilayer wiring board, such as a printed circuit board, is used to connect semiconductor chips such as an AP (Application Processor) chip and memory devices included in a smart phone to a circuit. The multilayer wiring board may include a plurality of insulating layers and a plurality of wiring layers repeatedly laminated therein. The AP chip or semiconductor chip can be mounted on the multilayer wiring board through soldering, wire connection, etc. using the outermost insulating layer and wiring layer.

[0004] Recently, as electronic components become more highly integrated, multilayer wiring boards may include a greater number of wiring layers. In this case, substrate warpage may occur due to differences in the coefficients of thermal expansion of the insulating and wiring layers. Furthermore, the heat generated during signal transmission to the AP chip or semiconductor chip may exacerbate this substrate warpage.

[0005] In addition, when passive elements such as capacitors, inductors, and resistors are included in the substrate, substrate warpage, substrate cracks, etc. may occur more easily due to differences in thermal expansion coefficients between the passive elements and the multilayer wiring substrate.

[0006]

[0007] An object of the present invention is to provide a multilayer wiring board having improved mechanical stability and electrical efficiency.

[0008]

[0009] 1. A multilayer wiring board comprising a glass substrate including a reinforcing portion on a surface portion; and a wiring laminate disposed on the reinforcing portion and including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.

[0010] 2. A multilayer wiring board in the above 1, wherein the reinforcing member has compressive force and has the same glass material as a portion of the glass substrate excluding the reinforcing member.

[0011] 3. In the above 2, the reinforcing member has a compressive force of 15 MPa to 50 MPa, a multilayer wiring board.

[0012] 4. A multilayer wiring board having a glass material having a higher potassium ion content than a portion of the glass substrate excluding the reinforcing portion, wherein the reinforcing portion has a compressive force in the above 2.

[0013] 5. A multilayer wiring board further comprising a through glass via (TGV) penetrating the glass substrate in the above 1.

[0014] 6. In the above 5, the through glass via (TGV) is a multilayer wiring board that penetrates the reinforcement part.

[0015] 7. In the above 5, the glass substrate includes a through via hole in which the through glass via is formed, and the reinforcement member is formed on the surface portion of the glass substrate and the side wall portion of the through via hole, a multilayer wiring board.

[0016] 8. A multilayer wiring board in which the compressive force of the reinforcement formed on the side wall of the through via hole in the above 7 is smaller than the compressive force of the reinforcement formed on the surface.

[0017] 9. A multilayer wiring board in the above 8, wherein the difference between the compressive force of the reinforcing portion formed on the surface portion and the compressive force of the reinforcing portion formed on the side wall portion of the through via hole is 3 MPa to 20 MPa.

[0018] 10. In the above 7, the reinforcing member includes a first reinforcing member formed on the upper surface of the glass substrate, a second reinforcing member formed on the lower surface of the glass substrate, and a third reinforcing member formed on the side wall of the through via hole.

[0019] A multilayer wiring board, wherein the first reinforcing member and the second reinforcing member are connected to each other by the third reinforcing member.

[0020] 11. A multilayer wiring board further comprising a lower wiring layer disposed under the second reinforcing member and a lower insulating layer covering the lower wiring layer in the above 10.

[0021] 12. A multilayer wiring board according to 11 above, further comprising a lower wiring via formed within the lower wiring layer and in contact with the lower wiring layer.

[0022] 13. A multilayer wiring board in the above 1, wherein the thickness of the reinforcing portion is 4 ㎛ to 20 ㎛.

[0023] 14. In the above 1, the wiring laminate is a multilayer wiring board that embeds a passive element formed by the wiring layers, the interlayer connection conductors, or the insulating layers.

[0024] 15. A multilayer wiring board according to the above 14, wherein the passive element includes at least one of a resistor, a capacitor, and an inductor.

[0025]

[0026] According to embodiments of the present invention, a wiring laminate can be laminated on a glass substrate. The glass substrate serves as a support substrate for the wiring laminate, and can suppress overall warpage of the multilayer wiring substrate.

[0027] According to exemplary embodiments, the glass substrate may include a reinforcing member formed on an outer portion. The reinforcing member may apply a compressive force to the outer portion of the glass substrate, thereby reducing or buffering stress due to tensile force of the glass substrate.

[0028] According to exemplary embodiments, a through glass via penetrating the glass substrate can be formed to electrically connect wiring layers included in the wiring laminate to the through glass via. Accordingly, electrical signal loss from the lower surface of the glass substrate to the upper surface of the wiring laminate can be reduced, and high-Q characteristics can be implemented.

[0029] According to exemplary embodiments, the wiring laminate may include passive components embedded therein. Therefore, the high-temperature SMT process for mounting passive components on the outer surface of the substrate can be omitted, thereby further preventing thermal damage and warpage of the substrate. Furthermore, the passive components can be designed utilizing the wiring layers included in the wiring laminate. Therefore, the manufacturing cost of the passive components can be reduced, while facilitating the design of a highly integrated circuit structure.

[0030]

[0031] FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0032] FIG. 2 is a schematic cross-sectional view illustrating a glass substrate according to some exemplary embodiments.

[0033] FIG. 3 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0034] FIG. 4 is a schematic cross-sectional view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0035] FIG. 5 is a schematic cross-sectional view showing one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0036] FIG. 6 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.

[0037] FIG. 7 is a schematic plan view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0038] FIGS. 8A and 8B are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0039]

[0040] Embodiments of the present invention provide a multilayer wiring substrate including a glass substrate and a wiring laminate.

[0041] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification illustrate preferred embodiments of the present invention and, together with the contents of the invention described above, serve to further understand the technical concept of the present invention. Therefore, the present invention should not be interpreted as being limited to the matters described in such drawings.

[0042] The terms “first”, “second”, “third”, “fourth”, “first”, “other”, “top”, “bottom”, etc. used in this application do not limit absolute positions or orders, but are used in a relative sense to distinguish different components or parts.

[0043] FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0044] Referring to FIG. 1, a multilayer wiring board (100) may include a glass substrate (105) and a wiring laminate (107) laminated on the glass substrate (105).

[0045] The glass substrate (105) may be manufactured from a glass product or bare glass that substantially does not contain organic materials. For example, the term "glass substrate" used in the present application may be used to mean a structure in which glass particles or glass fibers are impregnated into an organic layer. In one embodiment, the glass substrate may include tempered glass.

[0046] In some embodiments, the glass substrate (105) may not include any vacancies or etched spaces (e.g., recesses, grooves, cavities, etc.) other than through via holes for forming through glass vias as described below.

[0047] The dielectric constant of the glass substrate (105) may be 1 to 10 at 1 MHz, for example, 1 to 7, 1 to 5, or 1 to 3. The loss tangent (dielectric loss) of the glass substrate (105) may be 0.00005 to 0.001, for example, 0.0005 to 0.001. The coefficient of thermal expansion of the glass substrate (105) may be 1×10 -6 / K to 10 -5 / K, for example, 1×10 -6 / K to 5×10 -6 / K may be.

[0048] The thickness of the glass substrate (105) may be 25 µm to 1,000 µm, 50 µm to 1,000 µm, 100 µm to 1,000 µm, or 500 µm to 1,000 µm. The thickness of the glass substrate (105) may be appropriately adjusted within the above range in consideration of the thickness and number of layers of the wiring laminate (107).

[0049] The glass substrate (105) has a low dielectric loss value and can be applied as a support substrate to a multilayer wiring substrate described later to improve the low loss and high Q characteristics of the wiring substrate. In addition, the glass substrate (105) has a low coefficient of thermal expansion and can effectively suppress warpage occurring during high-temperature operation and build-up processes of the wiring substrate.

[0050] A reinforcing portion (106) may be formed on the surface of the glass substrate (105). According to exemplary embodiments, a first reinforcing portion (106a) and a second reinforcing portion (107b) may be formed on the upper surface and the lower surface, respectively, of the glass substrate (105).

[0051] The glass substrate (105) may have inherent tensile strength. Therefore, cracks may easily occur within the glass substrate (105) due to external impact, and the glass substrate (105) may be easily broken.

[0052] The reinforcing member (106) may have inherent compressive force. Accordingly, by applying compressive force to the upper and lower surfaces of the glass substrate (105), the tensile stress inherent in the glass substrate (105) may be buffered or reduced. Accordingly, a reinforced glass substrate with improved mechanical durability may be provided.

[0053] In some embodiments, the surface portion of the glass substrate (105) may be subjected to physical strengthening treatment to form a strengthened portion (106). According to exemplary embodiments, the surface portion of the glass substrate (105) may be subjected to, for example, 200 o C or higher or 250 o After baking at a high temperature of C or higher, a reinforced portion (106) containing compressive strength can be formed by rapidly cooling.

[0054] The above-mentioned physically strengthened reinforced portion (106) has the same glass material as the portion of the glass substrate (105) excluding the strengthened portion (106), and can maintain compressive strength.

[0055] In some embodiments, the surface portion of the glass substrate (105) may be chemically strengthened to form the strengthened portion (106). According to exemplary embodiments, the glass substrate (105) is immersed in a solution containing a potassium compound, and then heated at a temperature higher than the melting point of the potassium compound (e.g., 300 o C to 450 o C) can be heat treated.

[0056] Accordingly, sodium ions (Na) included in the surface portion of the glass substrate (105) + ) is potassium ion (Ka + ) ions. As potassium ions having a larger radius than sodium ions are substituted, a compressive force is applied to the surface portion of the glass substrate (105) so that it can be strengthened. Accordingly, the strengthened portion (106) may include a glass material containing more potassium ions than the portion of the glass substrate (105) excluding the strengthened portion (106).

[0057] In some embodiments, the compressive force of the physically strengthened or chemically strengthened reinforced portion (106) described above (e.g., the compressive force at the upper surface and / or lower surface of the glass substrate (105)) may be 15 MPa to 50 MPa.

[0058] Within the above compressive force range, the impact resistance of the glass substrate (105) is secured, and the crack stability of the glass substrate (105) can be improved in harsh environments of high or low temperatures. For example, cracks in the glass substrate (105) can be prevented during a process (e.g., forming a through glass via, laminating a wiring laminate, etc.) on the glass substrate (105) or during movement between processes. In addition, warpage or curling of the glass substrate (105) due to excessive increase in compressive force can be prevented.

[0059] In one embodiment, the compressive force of the reinforcing member (106) may be 20 MPa to 50 MPa, 20 MPa to 45 MPa, or 25 MPa to 45 MPa.

[0060] The thickness of the above-described physical strengthening treatment or chemical strengthening treatment-treated reinforcement portion (106) may be 4 µm to 20 µm, 5 µm to 20 µm, 5 µm to 17 µm, or 10 µm to 15 µm. Within the above range, the tensile stress of the glass substrate (105) can be appropriately reduced or absorbed, while preventing an increase in the difference in thermal expansion coefficient due to the reinforcement portion (106). In addition, the above-described compressive force range can be easily secured.

[0061] In one embodiment, the thickness of the physically strengthened reinforcement portion (106) may be 5 μm to 17 μm, or 10 μm to 15 μm. In one embodiment, the thickness of the chemically strengthened reinforcement portion (106) may be 4 μm to 15 μm, or 5 μm to 15 μm, or 5 μm to 13 μm.

[0062] As described above, the glass substrate (105) has a low dielectric loss value and can be applied as a support substrate to a multilayer wiring substrate described later to improve the low loss and high Q characteristics of the wiring substrate. In addition, the glass substrate (105) has a low coefficient of thermal expansion and can effectively suppress warpage occurring during high-temperature operation and build-up process of the wiring substrate.

[0063] Additionally, a reinforcing member (106) may be formed on the surface of the glass substrate (105) to enhance the mechanical durability of the glass substrate (105). Accordingly, the durability of the glass material is increased while preventing warping, thereby providing a reinforced glass substrate with improved physical properties.

[0064] A through glass via (TGV) (110) may be formed inside the glass substrate (105). The through glass via (110) may extend as a single integral structure across the upper and lower surfaces of the glass substrate (105). The upper and lower surfaces of the through glass via (110) may be exposed to the upper and lower surfaces of the glass substrate (105), respectively. The through glass via (TGV) (110) may also penetrate the reinforcement member (106).

[0065] For example, a through via hole penetrating the upper and lower surfaces of the glass substrate (105) can be formed through laser drilling, etc. The through via hole can be filled with a metal material through a plating process (e.g., copper plating) to form a through glass via (110).

[0066] In some embodiments, the maximum diameter of the through via hole (103) may be 25 μm to 300 μm. Within this range, sufficient conductivity can be secured while securing space for forming a filling insulating pattern (115) and preventing an excessive increase in the difference in thermal expansion coefficient due to an increase in the amount of conductive material.

[0067] In one embodiment, the diameter of the through via hole (103) may be 50 μm to 300 μm, or 100 μm to 200 μm.

[0068] The wiring laminate (107) may be an organic substrate including wiring layers. According to exemplary embodiments, the wiring laminate (107) may include insulating layers (120) and wiring layers (130) that are repeatedly laminated from the upper surface of the glass substrate (105). According to exemplary embodiments, the wiring layers (130) and insulating layers (120) may be build-up wiring layers and build-up insulating layers that are alternately and repeatedly laminated.

[0069] For example, the wiring layers (130) may include a first wiring layer (130a), a second wiring layer (130b), a third wiring layer (130c), a fourth wiring layer (130d), and a fifth wiring layer (130e). The insulating layers (120) may include a first insulating layer (120a), a second insulating layer (120b), a third insulating layer (120c), and a fourth insulating layer (120d).

[0070] According to exemplary embodiments, on the upper surface of the glass substrate (105), wiring layers (130) and insulating layers (120) may be alternately and repeatedly laminated in the following order: a first wiring layer (130a), a first insulating layer (120a), a second wiring layer (130b), a second insulating layer (120b), a third wiring layer (130c), a third insulating layer (120c), etc.

[0071] However, the number of wiring layers (130) and insulating layers (120) illustrated in FIG. 1 is only an example provided for convenience of explanation, and the number of layers and circuit design of the wiring laminate (107) are not limited as illustrated in FIG. 1.

[0072] The wiring layers (130) can be formed by forming a conductive layer on the upper surface of the glass substrate (105) (or on the reinforcing portion (106)) or on any one of the insulating layers (120), and then patterning the conductive layer through an etching process. The conductive layer can be formed through a deposition process such as a plating process or a sputtering process.

[0073] In some embodiments, the wiring layers (130) may be formed through a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process.

[0074] The wiring layers (130) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and may include, for example, copper (Cu).

[0075] The insulating layers (120) may each be formed to cover the wiring layer (130). The insulating layers (120) may be formed using a photosensitive resin such as an acrylic resin and / or a thermosetting resin such as an epoxy resin.

[0076] The wiring laminate (107) may further include interlayer connection conductors (140) that connect the wiring layers (130) to each other. The interlayer connection conductors (140) are disposed between wiring layers (130) of different levels and refer to conductors formed within the insulating layer (120).

[0077] In some embodiments, the interlayer interconnect conductor (140) may include interlayer vias that connect wiring layers (130) arranged at different levels.

[0078] In some embodiments, the interlayer interconnect conductor (140) may include a wiring-TGV via (140a) that interconnects the through-glass via (110) and the wiring layer (130) (e.g., the second wiring layer (130b)). The wiring-TGV via (140a) may be in direct contact with the through-glass via (110) and the second wiring layer (130b).

[0079] In some embodiments, the interlayer interconnect conductor (140) may include an interlayer via (140b) that interconnects the upper and lower wiring layers (130) with each other.

[0080] According to embodiments of the present invention, a passive element may be included within the wiring laminate (107). For example, the wiring laminate (107) may be provided as an integrated passive device (IPD) substrate having the passive element built into it.

[0081] According to exemplary embodiments, the passive component may be implemented as an inherent component formed by the arrangement of wiring layers (130) and insulating layers (120) rather than being inserted into the wiring laminate (107) as a separate chip.

[0082] The passive components may include inductors, capacitors, resistors, and the like. In some embodiments, the passive components may include a first passive component (PE1), a second passive component (PE2), and a third passive component (PE3).

[0083] The first passive element (PE1), the second passive element (PE2), and the third passive element (PE3) may each be different types of passive elements. For example, the first passive element (PE1) may include a conductor pattern included in the second wiring layer (130b) and a conductor pattern included in the third wiring layer (130c), and the conductor patterns may face each other with the second insulating layer (120b) interposed therebetween. Accordingly, the first passive element (PE1) may be provided as a capacitor.

[0084] The second passive element (PE2) may include, for example, a line pattern having a relatively large length included in the fourth wiring layer (120d). Accordingly, the second passive element (PE2) may be provided as a resistor.

[0085] The third passive element (PE3) may include a coil in which at least two layers of wiring layers are connected through interlayer connecting conductors (140) (e.g., interlayer vias). Accordingly, the third passive element (PE3) may be provided as an inductor.

[0086] As described above, a passive component embedded in a multilayer wiring board (100) or a wiring laminate (107) can be designed by utilizing the wiring layers (130), insulating layers (120) and / or interlayer connection conductors (140) included in the wiring laminate (107). According to exemplary embodiments, the passive component may not include any other configuration / structure other than the wiring layer (130), insulating layer (120) and / or interlayer connection conductor (140).

[0087] Accordingly, a separate, isolated chip-shaped passive element having a material different from that included in the wiring laminate (107) is not included, and an increase in warpage due to a difference in physical properties, such as a coefficient of thermal expansion, of the chip-shaped passive element can be prevented.

[0088] In addition, the integration density of passive components can be easily controlled by adjusting the line and space of the wiring layers (130). Accordingly, high integration density of passive components can be efficiently implemented, and an RF substrate can be effectively provided.

[0089] As described above, the passive element can be designed to be integrated with the wiring layer (130). Therefore, compared to a case where a separate chip is embedded, signal loss can be reduced and high Q characteristics can be enhanced.

[0090] According to exemplary embodiments, the wiring laminate (107) and the glass substrate (105) may not include a chip receiving space, such as a cavity, recess, or through hole, for inserting / embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), within the chip. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip receiving space, can be prevented.

[0091] Through-glass vias (110) can be classified according to the conductive pattern included in the wiring laminate (107) to which they are connected. In some embodiments, the through-glass vias (110) can include a first through-glass via (110a), a second through-glass via (110b), and a third through-glass via (110c).

[0092] Interlayer connection conductors (140) and wiring layers (130) may be alternately and sequentially laminated on the first through-glass via (110a) to form a common interconnect structure (CI). For example, the common interconnect structure (CI) may provide the shortest distance electrical signal path across the glass substrate (105) and the wiring laminate (107) in the vertical direction or thickness direction of the multilayer wiring board (100).

[0093] The above-described wiring-TGV via (140a) may be laminated or in contact with the upper surface of the first through-glass via (110a). Wiring layers (130) and interlayer vias (140b) may be alternately and repeatedly laminated on the wiring-TGV via (140a) to form a common interconnect structure (CI).

[0094] The common interconnect structure (CI) may be provided as a substantially single pillar. For example, a virtual centerline vertically penetrating the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).

[0095] The second through-glass via (110b) can be connected to a passive element. For example, it can be connected to the first passive element (PE1) through a wiring-TGV via (140a).

[0096] The third through-glass via (110c) may be connected to the wiring layer (130). For example, the third through-glass via (110c) may be electrically connected to the first wiring layer (130a) and the second wiring layer (130b) through a wiring-TGV via (140a) and an interlayer via (140b).

[0097] A lower wiring layer (190) and a lower insulating layer (180) may be laminated on the lower surface of the glass substrate (105) (e.g., the surface of the second reinforcement portion (106b). A lower wiring via (195) may be connected or in contact with the lower wiring layer (190).

[0098] The common interconnect structure (CI) may further include a TGV connecting via (197) that contacts the lower surface of the through glass via (110).

[0099] The wiring laminate (107) may be provided as an upper wiring / insulating structure of a multilayer wiring board (100). The uppermost wiring layer (e.g., the fifth wiring layer (130e)) included in the wiring laminate (107) may include a pad for mounting an electronic component. For example, an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by soldering or wire bonding.

[0100] In some embodiments, the TGV connection via (197) and the lower wiring via (195) may be connected to the motherboard via conductive balls or soldering.

[0101] FIG. 2 is a schematic cross-sectional view illustrating a glass substrate according to some exemplary embodiments.

[0102] Referring to FIG. 2, the reinforcement portion (106) can also be formed on the side wall of the through via hole (103) (the surface portion of the glass substrate (105) exposed by the through via hole (103).

[0103] According to exemplary embodiments, the above-described strengthening treatment may be performed on a glass substrate (105) in which a through via hole (103) is formed to form a third strengthening portion (106c). The first and second strengthening portions (106a, 106b) may be connected to each other by the third strengthening portion (106c).

[0104] The third reinforcement portion (106c) may be formed with a predetermined thickness from the side wall of the through via hole (103). In one embodiment, the thickness of the third reinforcement portion (106c) may be substantially the same as or similar to the thicknesses of each of the first reinforcement portion (106a) and the second reinforcement portion (106b).

[0105] The third reinforcing member (106c) is positioned between the glass substrate (105) and the through glass via (106c), so as to prevent the through glass via (106c) from being separated or damaged by tensile stress applied to the glass substrate (105). In addition, it can also function as a barrier that blocks the stress within the glass substrate (105) from propagating in the horizontal direction.

[0106] In some embodiments, the compressive force (hereinafter referred to as the second compressive force) applied to the third reinforcement member (106c) (the sidewall of the through-via hole (103)) may be less than the compressive force (hereinafter referred to as the first compressive force) applied to the first reinforcement member (106a) or the second reinforcement member (106b) (the upper surface or lower surface of the glass substrate). Accordingly, the stress on the sidewall of the through-via hole (103) can be reduced.

[0107] The difference between the first and second compressive forces may be 3 MPa to 20 MPa. Within the above range, an appropriate compressive force range can be easily secured while simultaneously suppressing cracks and warping of the glass substrate (105).

[0108] In one embodiment, the difference between the first compressive force and the second compressive force in the physically strengthened reinforced portion (106) may be 5 MPa to 20 MPa, for example, 6 MPa to 15 MPa, or 7 MPa to 12 MPa.

[0109] In one embodiment, the difference between the first compressive force and the second compressive force in the chemically strengthened reinforced portion (106) may be 3 MPa to 20 MPa, for example, 5 MPa to 20 MPa, or 5 MPa to 15 MPa.

[0110] As a non-limiting example, the difference between the first compressive force and the second compressive force can be adjusted by controlling the heating rate and / or cooling rate during the strengthening process. For example, increasing the heating rate and / or cooling rate can increase the difference between the first compressive force and the second compressive force.

[0111] Fig. 3 is a schematic cross-sectional view illustrating a multilayer wiring board according to exemplary embodiments. Detailed descriptions of configurations and structures substantially identical or similar to those described with reference to Fig. 1 are omitted.

[0112] Referring to FIG. 3, an organic reinforcement layer (90) may be formed on the surface of a glass substrate (105), and the organic reinforcement layer (90) may be provided as the above-described reinforcement member. The organic reinforcement layer (90) may be formed on the upper surface and the lower surface of the glass substrate (105), respectively. The organic reinforcement layer (90) may include a first organic reinforcement layer (90a) formed on the upper surface of the glass substrate (105) and a second organic reinforcement layer (90b) formed on the lower surface of the glass substrate (105).

[0113] The organic reinforcing layer (90) may include an organic resin such as an acrylic resin, an epoxy resin, a photoresist, etc. In one embodiment, the organic reinforcing layer (90) may not include an inorganic material or a ceramic material such as, for example, silicon oxide, silicon nitride, metal oxide, etc.

[0114] The organic reinforcement layer (90) may inherently have compressive strength. Accordingly, compressive strength may be applied to the upper and lower surfaces of the glass substrate (105), respectively, thereby buffering or reducing the tensile stress inherent in the glass substrate (105). Accordingly, a reinforced glass substrate with improved mechanical durability may be provided.

[0115] In some embodiments, the organic reinforcing layer (90) may have a higher compressive strength than the insulating layer (120).

[0116] According to exemplary embodiments, a composition including the organic resin may be coated on the surface of a glass substrate (105). Thereafter, a preliminary organic reinforcement layer may be formed through photo-curing or thermal curing. The preliminary organic reinforcement layer may be formed, for example, at 200 o C or higher or 250 o After baking at a high temperature of C or higher, an organic reinforcing layer (90) containing compressive strength can be formed by rapidly cooling.

[0117] In some embodiments, the thickness of the organic reinforcement layer (90) may be 0.5 μm to 10 μm, 1 μm to 10 μm, or 5 μm to 10 μm. Within the above range, the tensile stress of the glass substrate (105) can be appropriately reduced or absorbed, while preventing an increase in the thermal expansion coefficient of the organic reinforcement layer (90).

[0118] As described above, a through via hole (103) is formed within the glass substrate (105), and a through glass via (110) can be formed within the through via hole (103).

[0119] An organic reinforcement layer (90) is formed on a glass substrate (105) and a through glass via (110), and a via hole (93) can be formed by partially removing the organic reinforcement layer (90) to expose the upper surface of the through glass via (110). A wiring-TGV via (95) can be formed within the via hole (93) to contact the through glass via (110).

[0120] In some embodiments, as illustrated in FIG. 1, the wiring-TGV via (95) may be provided as a substantially integral conductive member with the through glass via (110).

[0121] The wiring-TGV via (95) may include a first wiring-TGV via (95a) and a second wiring-TGV via (95b) formed within the first organic reinforcement layer (90a) and the second organic reinforcement layer (90b), respectively.

[0122] The wiring laminate (107) described with reference to FIG. 1 can be laminated on the first organic reinforcement layer (90a) and the wiring-TGV via (95).

[0123] The common interconnect structure (CI) may further include a second wiring-TGV via (95b) in contact with the lower surface of the through glass via (110).

[0124] FIG. 4 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 4 illustrates an example implementation of a second passive component (PE2) provided as a resistor.

[0125] Referring to FIG. 4, a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a third insulating layer (120c)). An upper insulating layer (e.g., a fourth insulating layer (120d)) may be in direct contact with the line pattern (132a) and cover the line pattern (132a). Resistance may be adjusted depending on the length of the line pattern (132a), thereby providing a passive element that functions as a resistor.

[0126] A connection electrode (141) may be formed at each end of the line pattern (132a). The connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a). A terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).

[0127] The line pattern (132a) is included as a configuration of one of the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130). The terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (e.g., the uppermost wiring layer (e.g., the fifth wiring layer (130e))) among the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).

[0128] The connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).

[0129] FIG. 5 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 5 illustrates an example implementation of a first passive component (PE1) provided as a capacitor.

[0130] Referring to Fig. 5, the first electrode (131) and the second electrode (133) can be placed facing each other with an insulating layer (120) therebetween. Accordingly, a passive element of a MIM (Metal-Insulator-Metal) capacitor structure can be implemented.

[0131] The first electrode (131) and the second electrode (133) are each included as a component of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0132] As illustrated in FIG. 1, the first electrode (131) and the second electrode (133) may each be connected to an interlayer connection conductor (140) (see the first passive element (PE1)). The interlayer connection conductor (140) connected to the first electrode (131) and the second electrode (133) may be provided as a terminal electrode or an external electrode.

[0133] Figure 6 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments. Figure 6 illustrates one implementation example of a capacitor as a passive component.

[0134] Referring to FIG. 6, one of the wiring layers (130) may be provided as a first terminal electrode (134) (or a first external electrode), and one of the wiring layers (130) may be provided as a second terminal electrode (136) (or a second external electrode). In one embodiment, the first terminal electrode (134) and the second terminal electrode (136) may be included in a wiring layer (130) of the same level. Alternatively, the first terminal electrode (134) and the second terminal electrode (136) may be included in wiring layers (130) of different levels.

[0135] Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.

[0136] One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134). The other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).

[0137] A capacitance can be formed in the insulating layer (120) portion between the first internal electrode (142) and the second internal electrode (144) that are adjacent to each other. Accordingly, a passive element having a multilayer capacitor structure can be implemented.

[0138] The first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0139] FIG. 7 is a schematic plan view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 7 illustrates an example implementation of a third passive component (PE3) provided as an inductor.

[0140] Referring to FIG. 7, a first coil part (138) is placed on a lower insulating layer (not shown) (e.g., a second insulating layer (120b)), and an upper insulating layer (not shown) (e.g., a third insulating layer (120c)) may be in contact with the first coil part (138) and cover the first coil part (138). A second coil part (139) may be placed on the upper insulating layer.

[0141] The first coil section (138) and the second coil section (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having multiple turns can be implemented.

[0142] The first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0143] The above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).

[0144] Terminal electrodes (not shown) may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively. The terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0145] FIGS. 8A and 8B are schematic perspective and cross-sectional views, respectively, illustrating one embodiment of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 8B is a cross-sectional view taken vertically or in the thickness direction along line II' of FIG. 8A.

[0146] Referring to FIGS. 8A and 8B, one of the wiring layers (130) may include a first terminal electrode (135) (or a first external electrode) and lower connection electrodes (135a). The upper wiring layer (130) may include a second terminal electrode (137) (or a second external electrode) and upper connection electrodes (137a) with an insulating layer (120) therebetween relative to the first terminal electrode (135) and lower connection electrodes (135a).

[0147] Coil vias (145) may be distributed within the insulating layer (120). The coil vias (145) are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0148] A first terminal electrode (135) and a second terminal electrode (137) may be connected through coil vias (145) and connection electrodes (135a, 137a) to form a coil-shaped inductor. According to exemplary embodiments, neighboring coil vias (145) in the width direction may be connected to each other by an upper connection electrode (137a), and neighboring coil vias (145) in a diagonal direction with respect to the width direction may be connected to each other by a lower connection electrode (135a). Accordingly, a conductor may be repeated in a zigzag pattern across the lower and upper layers to form a coil.

[0149] The multilayer wiring board (100) described above can be applied as a circuit board for highly integrated electronic devices such as smart phones, PCs, semiconductor packages, etc. A glass substrate (105) and a passive component-embedded wiring laminate can be combined to provide a thin circuit board with low loss, high Q, and high speed.

[0150] Experimental Example 1: Measurement of bending stress according to the formation of a reinforced section.

[0151] Example 1

[0152] A through glass via (110) with a diameter of 50 μm was formed through copper plating within a 1 mm thick glass substrate (105). After forming an acrylic organic reinforcement layer (90) with a thickness of 10 μm on the glass substrate (105), it was baked at 250°C and cooled.

[0153] Example 2

[0154] A 50 μm diameter through-via hole (103) was formed through a 1 mm thick glass substrate (105). Thereafter, the glass substrate (105) was heated to a temperature of 300°C and then rapidly cooled to form a reinforced portion (106). The heating and cooling rates were adjusted so that a 20 μm thick reinforced portion was formed.

[0155] As described above, a through glass via (110) was formed through copper plating within a through via hole (103) of a physically strengthened glass substrate (105).

[0156] Example 3

[0157] A 50 μm diameter through-via hole (103) was formed through a 1 mm thick glass substrate (105). Thereafter, the glass substrate (105) was immersed in a potassium nitrate (KNO3) solution, heat-treated at 400°C, and rapidly cooled with 15°C water. Thereafter, a reinforced portion (106) was formed through washing and drying. The heating and cooling rates were adjusted so that a 20 μm thick reinforced portion was formed.

[0158] As described above, a through glass via (110) was formed through copper plating within a through via hole (103) of a chemically strengthened glass substrate (105).

[0159] Bending stress measurement

[0160] The bending stress of the glass substrates of the examples and comparative examples was measured according to the ASTM C158 standard. Specifically, the bending stress until the through glass via in the glass substrate was removed from the through via hole was measured.

[0161] The measurement results are shown in Table 1 below.

[0162] Thickness of reinforced section (㎛) Bending stress (kgf) Example 11021.3 Example 22030.04 Example 32039.17 Comparative example -9.66

[0163] Referring to Table 1, in examples where a reinforced portion was formed, the bending stress that the glass substrate could withstand increased.

[0164] Experimental Example 2: Reliability Evaluation According to the Compressive Force of the Reinforced Part

[0165] Samples A-1 to A-6

[0166] Samples were manufactured by controlling the heating rate and cooling rate of the physical strengthening treatment of Example 2 to change the thickness of the strengthened parts as shown in Table 2.

[0167] Samples B-1 to B-7

[0168] Samples were manufactured by controlling the heating rate and cooling rate of the chemical strengthening treatment of Example 3 to change the thickness of the strengthened parts as shown in Table 2.

[0169] Compression force measurement

[0170] The compressive force of the reinforcement formed in the samples was measured according to ASTM F218 method using a compressive force measuring device (INSTRON model #5565).

[0171] Crack measurement

[0172] The glass substrates of the examples and comparative examples were stored alternately and repeatedly under conditions of 100°C for 30 minutes and -5°C for 30 minutes, as one cycle. After repeating the above cycle 10 times, the occurrence of cracks was evaluated as follows.

[0173] ○: No cracks

[0174] △: Partial microcracks observed around the through glass via

[0175] X: Cracks clearly observed within the glass body

[0176] Curl measurement

[0177] The glass substrates of the examples and comparative examples were cut to a size of 10 cm × 10 cm and heat-treated at 150°C for 30 minutes. Thereafter, the height at which the cut portion was bent from the floor was measured and evaluated as follows.

[0178] ○: Curl practically does not occur

[0179] △: Curl less than 1mm

[0180] X: Curl larger than 1mm

[0181] The measurement results are shown in Table 2 below.

[0182] Classification Reinforcement Thickness (㎛) Compressive force (MPa) Crack occurrence Curl occurrence Sample A-1413X○Sample A-2515△○Sample A-31029○○Sample A-41543○○Sample A-51750○△Sample A-62058○XSample B-1313X○Sample B-2415△○Sample B-3521○○Sample B-41034○○Sample B-51343○○Sample B-61550○△Sample B-72079○X

[0183] Referring to Table 2, in samples where the compressive strength of the reinforced portion formed by physical / chemical strengthening was controlled in the range of 15 MPa to 50 MPa, cracking of the glass body was prevented and warping or curling was suppressed.

[0184] For example, when the thickness of the physically reinforced portion is in the range of 5 ㎛ to 17 ㎛, an appropriate range of compressive force is easily secured, while simultaneously suppressing the occurrence of cracks and warpage. For example, when the thickness of the chemically reinforced portion is in the range of 4 ㎛ to 15 ㎛, an appropriate range of compressive force is easily secured, while simultaneously suppressing the occurrence of cracks and warpage.

[0185] Experimental Example 3: Reliability Evaluation Based on the Difference in Compressive Force According to the Location of the Reinforcement Section

[0186] Samples C-1 to C-7

[0187] Samples were manufactured by changing the heating rate and cooling rate of the physical strengthening treatment of Example 2 and changing the compressive force size as shown in Table 3.

[0188] Samples D-1 to D-7

[0189] Samples were manufactured by changing the compressive force size as shown in Table 3 by controlling the heating rate and cooling rate of the chemical strengthening treatment of Example 3.

[0190] Compression force measurement

[0191] The compressive force of the reinforced portion formed on the samples was measured according to the ASTM F218 method using a compressive force measuring device (INSTRON model #5565). The compressive force (A) on the glass substrate surface (top or bottom) of the samples and the compressive force (B) on the sidewall of the through via hole (103) were measured, respectively.

[0192] Crack and Curl Evaluation

[0193] Cracks and curls were evaluated using the same method as in Experimental Example 2.

[0194] The measurement results are shown in Table 3 below.

[0195] Classification Compressive force (MPa) Crack occurrence Curl occurrence AB Compressive force difference (AB) Sample C-11394X○ Sample C-215105△○ Sample C-329227○○ Sample C-443358○○ Sample C-5483612○○ Sample C-6504317○△ Sample C-7725022△X Sample D-113112X○ Sample D-221183△○ Sample D-328235○○ Sample D-434259○○ Sample D-5432815○○ Sample D-6503020○△ Sample D-7795524△X

[0196] Referring to Table 3, cracking and warpage were suppressed together when the difference between the compressive force on the glass substrate surface (top or bottom) and the compressive force on the sidewall of the through via hole was in the range of 3 MPa to 20 MPa. For example, in Samples C-7 and D-7, cracking partially occurred even when the surface compressive force increased due to an increase in the compressive force difference.

[0197] For example, when the compressive strength difference of the physically reinforced portion is in the range of 5 MPa to 20 MPa, for example, 6 MPa to 15 MPa, an appropriate compressive strength range is easily secured, while simultaneously suppressing the occurrence of cracks and warpage. For example, when the compressive strength difference of the chemically reinforced portion is in the range of 3 MPa to 20 MPa, for example, 5 MPa to 15 MPa, an appropriate compressive strength range is easily secured, while simultaneously suppressing the occurrence of cracks and warpage.

Claims

1. A glass substrate including a reinforcing portion on the surface; and A multilayer wiring board comprising a wiring laminate including repeatedly laminated wiring layers, insulating layers and interlayer connection conductors, arranged on the above-described reinforcing member.

2. A multilayer wiring board according to claim 1, wherein the reinforcing member has compressive force and has the same glass material as a portion of the glass substrate excluding the reinforcing member.

3. A multilayer wiring board according to claim 2, wherein the reinforcing member has a compressive force of 15 MPa to 50 MPa.

4. A multilayer wiring board according to claim 2, wherein the reinforcing member has compressive force and has a glass material having an increased potassium ion content compared to a portion of the glass substrate excluding the reinforcing member.

5. A multilayer wiring board according to claim 1, further comprising a through glass via (TGV) penetrating the glass substrate.

6. A multilayer wiring board according to claim 5, wherein the through glass via (TGV) penetrates the reinforcement member.

7. In claim 5, the glass substrate includes a through via hole in which the through glass via is formed, A multilayer wiring board, wherein the reinforcing portion is formed on the surface portion of the glass substrate and the sidewall portion of the through via hole.

8. A multilayer wiring board according to claim 7, wherein the compressive force of the reinforcing portion formed on the sidewall of the through via hole is smaller than the compressive force of the reinforcing portion formed on the surface portion.

9. A multilayer wiring board according to claim 8, wherein the difference between the compressive force of the reinforcing portion formed on the surface portion and the compressive force of the reinforcing portion formed on the sidewall portion of the through via hole is 3 MPa to 20 MPa.

10. In claim 7, the reinforcing member includes a first reinforcing member formed on an upper surface portion of the glass substrate, a second reinforcing member formed on a lower surface portion of the glass substrate, and a third reinforcing member formed on a side wall portion of the through via hole. A multilayer wiring board, wherein the first reinforcing member and the second reinforcing member are connected to each other by the third reinforcing member.

11. A multilayer wiring board according to claim 10, further comprising a lower wiring layer disposed under the second reinforcing member and a lower insulating layer covering the lower wiring layer.

12. A multilayer wiring board according to claim 11, further comprising a lower wiring via formed within the lower wiring layer and in contact with the lower wiring layer.

13. A multilayer wiring board according to claim 1, wherein the thickness of the reinforcing portion is 4 ㎛ to 20 ㎛.

14. In claim 1, the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors, or the insulating layers.

15. A multilayer wiring board according to claim 14, wherein the passive component includes at least one of a resistor, a capacitor, and an inductor.

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