A successive approximation register analog to digital converter, a method of analog to digital conversion, mobile user equipment and base station

Abstract

A Successive Approximation Register Analog to digital converter (100), comprises a digital to analog conversion circuit having multiple conversion stages (120-1,..., 120-k) generating a contribution to an output of the digital to analog conversion circuit, the multiple conversion stages being hierarchically ordered, starting with a most significant stage (120-1) and ending with a lest significant stage (120-K). A compara tor circuit is configured to compare an input voltage (110) with the output (120) of the digital to analog conversion circuit, wherein a radix associated with the most significant stage (120-1) is bigger than the radix associated with the least significant stage (120-K).

Description

[0001] A Successive Approximation Register Analog to digital converter, a method of analog to digital conversion, mobile user equipment and base station

[0002] Field

[0003] The present disclosure relates to Successive Approximation Register Analog to digital converters having high accuracy.

[0004] Background

[0005] A Successive Approximation Register (SAR) is a type of analog-to-digital converter (ADC) that works by successively approximating an analog input signal. A SAR ADC uses a binary search algorithm to successively approximate the input analog signal, adjusting the digital output code until an approximation is achieved.

[0006] The idea behind a SAR ADC is to compare the input signal with an internally generated voltage and iteratively adjust an digital output code to minimize the difference between the input signal and the converted digital code, which results in the internally generated voltage. In a simplified step-by-step explanation, a single bit SAR ADC works according to the following principle. The process begins by setting the most significant bit (MSB) of a digital output code to a trial code. The digital output code also serves to steer multiple conversion stages used to generate the internally generated voltage. For example, if the ADC has a 10-bit resolution, 10 conversion stages are present in the event of a single Bit SAR. As a trial code, the MSB is set to 1, resulting in an digital output code of 1,000,000,000. The digital trial code is converted to an analog voltage by a digital-to-analog converter (DAC) serving as a conversion stage. The internally generated voltage provided by the DAC output is then compared with the input analog signal. If the DAC output is greater than the input signal, the corresponding bit is kept at 1; otherwise, it is set to 0. Then, the next bit in the digital output code is considered, and the DAC is adjusted accordingly. The previous steps are repeated for each subsequent bit, proceeding from the MSB to the least significant bit (LSB) until the entire digital code is determined. Once all bits have been de- termined, the digital code represents a binary approximation of the input analog signal. This digital output code establishes the output of the SAR ADC. Based on the same operating principle, Multi Bit SAR ADCs generate multiple Output Bits per Iteration, eventually increasing the conversion speed.

[0007] An SAR converter has some level of intrinsic correction capability for wrong comparator decisions because it is similar to a feedback loop system. For example, if a 0 is erroneously determined in one step instead of a 1, this may be partly mitigated by all following decisions being 1.

[0008] Despite this inherent property, there may still be a demand for a SAR ADC being robust against decision errors.

[0009] Brief description of the Figures

[0010] Some examples of apparatuses and / or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

[0011] Fig. 1 shows an illustration of a example of a SAR ADC;

[0012] Fig. 2 shows a flowchart of a method of analog to digital conversion; and

[0013] Fig. 3 shows a schematic illustration of a mobile user equipment and a base station.

[0014] Detailed Description

[0015] Some examples are now described in more detail with reference to the enclosed figures. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of the features as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be restrictive of further possible examples. Throughout the description of the figures same or similar reference numerals refer to same or similar elements and / or features, which may be identical or implemented in a modified form while providing the same or a similar function. The thickness of lines, layers and / or areas in the figures may also be exaggerated for clarification.

[0016] When two elements A and B are combined using an “or”, this is to be understood as disclosing all possible combinations, i.e. only A, only B as well as A and B, unless expressly defined otherwise in the individual case. As an alternative wording for the same combinations, "at least one of A and B" or "A and / or B" may be used. This applies equivalently to combinations of more than two elements.

[0017] If a singular form, such as “a”, “an” and “the” is used and the use of only a single element is not defined as mandatory either explicitly or implicitly, further examples may also use several elements to implement the same function. If a function is described below as implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity. It is further understood that the terms "include", "including", "comprise" and / or "comprising", when used, describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0018] Fig. 1 is an illustration of an Example of a SAR ADC 100. The SAR ADC compares the input signal 110 with an internally generated voltage and iteratively adjusts a digital output code 120 (also represented by a sequence of bits 130-1 to 130-K) to minimize the difference between the input signal 110 and the internally generated voltage. The internally generated voltage corresponds to the output code 120 and is generated by means of an Digital to Analog Converter (DAC) having multiple conversion stages 120-1 to 120-K, each conversion stage contributing to the internally generated voltage with a certain weight 140-1 to 140-K. The iterative process begins by setting the most significant bit (MSB) 130-1 of the digital output code 120 to a trial code. For example, if the ADC has a 10-bit resolution, corresponding to 10 conver- sion stages in the event of a single Bit SAR, the MSB 130-1 (DI) is set to 1. The digital trial code 1000000000 is converted to the internally generated voltage by a DAC having 10 conversion stages. The DAC output is compared with the input analog signal 110. If the DAC output is greater than the input signal 120, the corresponding bit is kept at 1; otherwise, it is set to 0. Then, the next bit 130-2 of the digital output code 120 is considered, and the DAC is adjusted accordingly. The previous steps are repeated for each subsequent bit, proceeding from the MSB to the LSB until the entire digital code 120 is determined. Once all bits 130-1 to 130-K have been determined, the digital output code 120 represents a binary approximation of the input analog signal 110. This digital output code Di is an output of the SAR ADC and computes to the Sum of the Weights Wi, also be called the weighted sum of the decision cycles:

[0019] In the event of a wrong comparator decision in one of the iterations of the SAR ADC, subsequent iterations may partly compensate for the wrong decision. Nonetheless, there may be a demand for a design being more robust to decision errors.

[0020] A Successive Approximation Register Analog to digital converter 100 according to an example comprises a digital to analog conversion circuit having multiple conversion stages 120-1, ..., 120-K generating a contribution to an output of the digital to analog conversion circuit, the multiple conversion stages 120-1, ..., 120-K being hierarchically ordered, starting with a most significant stage 120-1 and ending with a least significant conversion stage 120-K. A comparator circuit is configured to compare an input voltage 110 with the output of the digital to analog conversion circuit. A radix associated with the most significant conversion stage 120-1 is bigger than the radix associated with the least significant conversion stage. 120-K. For example, a radix is associated to a conversion stage if the radix is computed using a weight factor of the associated conversion stage. For example, the weight factors of two neighboring conversion stages 120-1, and 120-(I+l) of the hierarchically ordered conversion stages 120-1, . . ., 120-K may be used to compute a Radix(I+l) so that both conversion stages 120-1, and 120-(I+ 1 ) are associated with said Radix(I+l). The iterative approximation of the input signal x by a SAR ADC 100 according to an example described having I conversion stages may be described by the following pseudo code in which DAC denotes the output generated from the internal digital to analog conversion circuit. end

[0021] In this Pseudo code, Radix(i) denotes the radix. The radix corresponds to the ratio of weights of two subsequent conversion stages, Radixfi] = W[i-1] / W[i],

[0022] Other than in conventional approaches, the radix associated with the most significant conversion stage is bigger than the radix associated with the least significant conversion stage which can also be interpreted to mean that the ratio of weights W(l) / W(2) of the most significant conversion stage 120-1 and its successor 120-2 is bigger than the ratio of weights W(K-1) / W(K) of the least significant conversion stages 120-(K- 1) and 120-K. Generally speaking, the radix is not fixed among the comparator stages but can vary amongst the conversion stages such that the weight W(l) associated with the most significant conversion stage 120-1 is bigger than the weight W(K) associated with the least significant conversion stage 120-K.

[0023] Having a smaller radix in the least significant conversion stages than in the most significant conversion stages may increase the accuracy of the SAR ADC. This is because in an SAR ADC, comparator noise may have greater impact in later decision cycles (LSB decision bits) since the remaining number of cycles (comparator stages) to compensate for an error are then little. Moreover, the voltages to compare are, on average, smaller towards the later decision cycles, resulting in an increased error probability as compared to earlier decision cycles. A bigger weight serves to mitigate both sources of error. On the one hand, the probability of comparator errors is reduced and, on the other hand, the impact is reduced once an error occurs.

[0024] According to some examples, the radix associated with the conversion stages decreases monotonically from the most significant stage to the least significant stage.

[0025] A function is said to be monotonically decreasing if, as the input values increase, the output values decrease or remain the same. In other words, the function does not increase as its input increases. In other words, the radix or weight according to the examples stays identical or decreases if one moves from one decision cycle to the next decision cycle.

[0026] According to some examples, every conversion stage has associated therewith a weight factor and wherein the weight factor decreases monotonically amongst the hierarchically ordered conversion stages.

[0027] According to some examples, a radix defined by the most significant stage and at least the following conversion stage in the hierarchical order is equal to 2.

[0028] In some examples, the internal DAC works according to the switched capacitance principle, Every conversion stage has associated therewith a capacitance used to generate the internally generated voltage. In other words, a conversion stage comprises at least one capacitor, wherein the capacitance of the conversion stage corresponds to the weight and / or the radix.

[0029] According to some examples, the conversion stages comprise a respective number of unit capacitors, wherein a ratio of the respective number of unit capacitors between at least one pair of a conversion stage and the following conversion stage in the hierarchical order is smaller than 2 to result with a radix being smaller than 2.

[0030] According to some examples, the ratio decreases monotonically within the hierarchically ordered conversion stages. In the event of the single Bit SAR ADC discussed before, a comparator circuit used typically comprises a single comparator. In multi Bit SAR ADCs, multiple Bits are determined in parallel per approximation cycle, resulting in the comparator circuit comprising multiple comparators. For example, in a 2 Bit SAR ADC, a comparator circuit distinguishes between 4 voltage intervals, resulting in the a comparator circuit having 3 comparators.

[0031] There may even be mixed architectures of an SAR ADC, combining a multi-bit / cycle portion for the early conversions and a single single-bit / cycle portion for the last conversions. That is, the MSB conversion stage may comprise a multi Bit comparator circuit while the LSB conversion stage may comprise a single Bit comparator circuit.

[0032] The following pseudo code exemplifies an example based on a 2 Bit SAR ADC. Typically, the Radix(i) changes between subsequent conversion stages and not amongst the comparators of a comparator circuit of a single conversion stage.

[0033] Fig. 2 illustrates a flow chart of a method of analog to digital conversion as it may be performed by the SAR ADC of fig. 1. The method comprises iteratively generating 210 an output of a digital to analog conversion circuit having multiple conversion stages that are hierarchically ordered starting with a most significant stage and ending with a least significant stage, wherein, in every iteration, the next conversion stage within the order is set to contribute to the output, wherein a radix of the most signifi- cant stage is bigger than the radix of the least significant stage. In every iteration, the output of the digital to analog conversion circuit is compared 220 with an input voltage and contribution information is generated 230 for every conversion stage. In the event of a single Bit SAR ADC, the contribution information may be given by a single Bit. In Multi Bit SAR ADCs, however, the contribution information of a single conversion stage may be constituted by multiple Bits.

[0034] Fig. 3 schematically illustrates a user device 1100 in accordance with an aspect and a base station or infrastructure equipment radio head 1200 in accordance with an aspect. Both the user device 1100 and the radio head 1200 may comprise an example of an SAR ADC as described previously referring to figs. 1 and 2, for example in their radio front end modules or in their baseband modules.

[0035] The user device 1100 may be a mobile device in some aspects and includes an application processor 1105, baseband processor 1110 (also referred to as a baseband module), radio front end module (RFEM) 1115, memory 1120, connectivity module 1125, near field communication (NFC) controller 1130, audio driver 1135, camera driver 1140, touch screen 1145, display driver 1150, sensors 1155, removable memory 1160, power management integrated circuit (PMIC) 1165 and smart battery 1170.

[0036] In some aspects, application processor 1105 may include, for example, one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C) or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as secure digital / multi-media card (SD / MMC) or similar, universal serial bus (USB) interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

[0037] In some aspects, baseband module 1110 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged inte- grated circuit soldered to a main circuit board, and / or a multi-chip module containing two or more integrated circuits.

[0038] The base station radio head 1200 may include one or more of application processor 1205, baseband modules 1210, one or more radio front end modules 1215, memory 1220, power management circuitry 1225, power tee circuitry 1230, network controller 1235, network interface connector 1240, satellite navigation receiver module 1245, and user interface 1250.

[0039] In some aspects, application processor 1205 may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD / MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports.

[0040] In some aspects, baseband processor 1210 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

[0041] In some aspects, memory 1220 may include one or more of volatile memory including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM) and / or a three-dimensional crosspoint memory. Memory 1220 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

[0042] In some aspects, power management integrated circuitry 1225 may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (overvoltage) conditions.

[0043] In some aspects, power tee circuitry 1230 may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station radio head 1200 using a single cable.

[0044] In some aspects, network controller 1235 may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

[0045] In some aspects, satellite navigation receiver module 1245 may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and / or BeiDou. The receiver 1245 may provide data to application processor 1205 which may include one or more of position data or time data. Application processor 1205 may use time data to synchronize operations with other radio base stations.

[0046] In some aspects, user interface 1250 may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as light emitting diodes (LEDs) and a display screen.

[0047] In the following, some examples of the proposed concept are presented:

[0048] An example (e.g., example 1) relates to a Successive Approximation Register Analog to digital converter, comprising a digital to analog conversion circuit having multiple conversion stages generating a contribution to an output of the digital to analog conversion circuit, the multiple conversion stages being hierarchically ordered, starting with a most significant stage and ending with a least significant stage, and a comparator circuit configured to compare an input voltage with the output of the digital to analog conversion circuit, wherein a radix associated with the most significant stage is bigger than the radix associated with the least significant stage. Another example (e.g., example 2) relates to a previous example (e.g., example 1) or to any other example, wherein the radix associated with the conversion stages decreases monotonically from the most significant stage to the least significant stage.

[0049] Another example (e.g., example 3) relates to a previous example (e.g., example 1 or 2) or to any other example, wherein a radix of the most significant stage and at least the following conversion stage in the hierarchical order is equal to 2.

[0050] Another example (e.g., example 4) relates to a previous example (e.g., one of examples 1 to 3) or to any other example, wherein the conversion stages comprise at least one capacitor, wherein a capacitance associated to a conversion stage corresponds to the radix.

[0051] Another example (e.g., example 5) relates to a previous example (e.g., one of examples 1 to 4), wherein the conversion stages comprise a respective number of unit capacitors, wherein a ratio of the respective number between at least one pair of a conversion stage and the following conversion stage in the hierarchical order is smaller than 2.

[0052] Another example (e.g., example 6) relates to a previous example (e.g., example 5) or to any other example, further comprising that the ratio decreases monotonically within the hierarchically ordered conversion stages.

[0053] Another example (e.g., example 7), relates to a previous example (e.g., any one of examples 1 to 6) or to any other example, wherein a conversion stage has associated therewith a weight factor and wherein the weight factor decreases monotonically amongst the hierarchically ordered conversion stages.

[0054] Another example (e.g., example 8) relates to a previous example (e.g., example 7) or to any other example, further comprising circuitry for generating an output value configured to evaluate, whether a conversion stage contributes to the input voltage to an extent depending on its weight factor and on associated contribution information indicating a factor of contribution of the associated weight factor.

[0055] Another example (e.g., example 9) relates to a previous example (e.g., example 9) or to any other example, further comprising that the circuitry for generating an output value is further configured to provide an output value by summing up the weight factors that are scaled with their associated contributions.

[0056] An example (e.g., example 10) relates to a method of analog to digital conversion, comprising Iteratively generating an output of a digital to analog conversion circuit having multiple conversion stages that are hierarchically ordered starting with a most significant stage and ending with a least significant stage, wherein, in every iteration, the next conversion stage within the order is set to contribute to the output, wherein a radix associated with the most significant stage is bigger than the radix associated with the least significant stage, in every iteration, comparing the output of the digital to analog conversion circuit with an input voltage, and in every iteration, generating contribution information for every conversion stage.

[0057] Another example (e.g., example 11) relates to a previous example (e.g., example 10) or to any other example, further comprising summing up a digital representation of the contributions of the conversion stages indicated by the contribution information to generate an output of the analog to digital conversion.

[0058] Another example (e.g., example 12) relates to a previous example (e.g., one of the examples 8 or 9) or to any other example, further comprising that the radix associated with the conversion stages decreases monotonically from the most significant stage to the least significant stage.

[0059] An example (e.g., example 13) relates to means for Analog to digital conversion, comprising Means for digital to analog conversion having multiple conversion stages generating a contribution to an output of the means for digital to analog conversion, the multiple conversion stages being hierarchically ordered, starting with a most significant stage and ending with a lest significant stage, wherein a radix associated with the most significant stage is bigger than the radix associated with the least significant stage, and means for comparing an input voltage with the output.

[0060] Another example (e.g., example 14) relates to a previous example (e.g., example 13) or to any other example, further comprising that the conversion stages comprise a respective number of unit capacitors, wherein a ratio of the respective number between at least one pair of a conversion stage and the following conversion stage in the hierarchical order decreases monotonically within the hierarchically ordered conversion stages.

[0061] Another example (e.g., example 15) relates to mobile user equipment comprising a successive Approximation Register Analog to digital converter of any one of examples 1 to 9.

[0062] Another example (e.g., example 16) relates to a base station comprising a successive Approximation Register Analog to digital converter of any one of examples 1 to 9.

[0063] The aspects and features described in relation to a particular one of the previous examples may also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

[0064] Examples may further be or relate to a (computer) program including a program code to execute one or more of the above methods when the program is executed on a computer, processor or other programmable hardware component. Thus, steps, operations or processes of different ones of the methods described above may also be executed by programmed computers, processors or other programmable hardware components. Examples may also cover program storage devices, such as digital data storage media, which are machine-, processor- or computer-readable and encode and / or contain machine-executable, processor-executable or computer-executable programs and instructions. Program storage devices may include or be digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media, for example. Other examples may al- so include computers, processors, control units, (field) programmable logic arrays ((F)PLAs), (field) programmable gate arrays ((F)PGAs), graphics processor units (GPU), application-specific integrated circuits (ASICs), integrated circuits (ICs) or system-on-a-chip (SoCs) systems programmed to execute the steps of the methods described above.

[0065] It is further understood that the disclosure of several steps, processes, operations or functions disclosed in the description or claims shall not be construed to imply that these operations are necessarily dependent on the order described, unless explicitly stated in the individual case or necessary for technical reasons. Therefore, the previous description does not limit the execution of several steps or functions to a certain order. Furthermore, in further examples, a single step, function, process or operation may include and / or be broken up into several sub-steps, -functions, -processes or - operations.

[0066] If some aspects have been described in relation to a device or system, these aspects should also be understood as a description of the corresponding method. For example, a block, device or functional aspect of the device or system may correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in relation to a method shall also be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding device or a corresponding system.

[0067] The following claims are hereby incorporated in the detailed description, wherein each claim may stand on its own as a separate example. It should also be noted that although in the claims a dependent claim refers to a particular combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed, unless it is stated in the individual case that a particular combination is not intended. Furthermore, features of a claim should also be included for any other independent claim, even if that claim is not directly defined as dependent on that other independent claim.

Claims

ClaimsWhat is claimed is:

1. A Successive Approximation Register Analog to digital converter (100), comprising: a digital to analog conversion circuit having multiple conversion stages (120-1, ..., 120-k) generating a contribution to an output of the digital to analog conversion circuit, the multiple conversion stages being hierarchically ordered, starting with a most significant stage (120-1) and ending with a lest significant stage (120-K); and a comparator circuit configured to compare an input voltage (110) with the output (120) of the digital to analog conversion circuit; wherein a radix associated with the most significant stage (120-1) is bigger than the radix associated with the least significant stage (120-K).

2. The Successive Approximation Register Analog to digital converter (100) of claim 1, wherein the radix associated with the conversion stages decreases monotonically from the most significant stage (120-1) to the least significant stage (120-K).

3. The Successive Approximation Register Analog to digital converter (100) of any one of claims 1 or 2, wherein a radix of the most significant stage (120-1) and at least the following conversion stage (120-2) in the hierarchical order is equal to 2.

4. The Successive Approximation Register Analog to digital converter (100) of any one of claims 1 to 3, wherein the conversion stages (120-1, ..., 120-k) comprise at least one capacitor, wherein a capacitance associated to a conversion stage (120-1, . . ., 120-k) corresponds to the radix.

5. The Successive Approximation Register Analog to digital converter (100) of any one of claims 1 to 4, wherein the conversion stages (120-1, 120-k) comprise a respective number of unit capacitors, wherein a ratio of the respective number between at least one pair of a conversion stage and the following conversion stage in the hierarchical order is smaller than 2.

6. The Successive Approximation Register Analog to digital converter (100) of claim 5, wherein the ratio decreases monotonically within the hierarchically ordered conversion stages.

7. The Successive Approximation Register Analog to digital converter (100) of any one of claims 1 to 6, wherein a conversion stage (120-1, ..., 120-k) has associated therewith a weight factor (140-1, ..., 140-K) and wherein the weight factor decreases monotonically amongst the hierarchically ordered conversion stages.

8. The Successive Approximation Register Analog to digital converter (100) of claim 7, further comprising: circuitry for generating an output value configured to evaluate, whether a conversion stage contributes to the input voltage to an extent depending on its weight factor (140-1, ..., 140-K) and on associated contribution information (130-1, ..., 130-K) indicating a factor of contribution of the associated weight factor.

9. The Successive Approximation Register Analog to digital converter (100) of claim 9, wherein the circuitry for generating an output value is further configured to provide an output value (120) by summing up the weight factors (140-1, ..., 140-K) that are scaled with their associated contributions (130-1, ..., 130-K).

10. A method of analog to digital conversion, comprising:Iteratively generating (210) an output of a digital to analog conversion circuit having multiple conversion stages that are hierarchically orderedstarting with a most significant stage and ending with a least significant stage, wherein, in every iteration, the next conversion stage within the order is set to contribute to the output, wherein a radix associated with the most significant stage is bigger than the radix associated with the least significant stage. in every iteration, comparing (220) the output of the digital to analog conversion circuit with an input voltage; and in every iteration, generating (230) contribution information for every conversion stage.

11. The method of claim 10, further comprising: summing up a digital representation of the contributions of the conversion stages indicated by the contribution information to generate an output of the analog to digital conversion.

12. The method of claim 8 or 9, wherein the radix associated with the conversion stages decreases monotonically from the most significant stage to the least significant stage.

13. Means for Analog to digital conversion (100), comprising:Means for digital to analog conversion having multiple conversion stages (120-1, ..., 120-k) generating a contribution to an output of the means for digital to analog conversion, the multiple conversion stages (120-1, ..., 120-k) being hierarchically ordered, starting with a most significant stage (120-1) and ending with a least significant stage (120-K), wherein a radix associated with the most significant stage (120-1) is bigger than the radix associated with the least significant stage (120-K); and means for comparing an input voltage (110) with the output (120).

14. The Means (100) of claim 13, wherein the conversion stages (120-1, ..., 120-k) comprise a respective number of unit capacitors, wherein a ratio of the respective number between at least one pair of a conversion stage and the following conversion stage in the hierarchical order decreases mono-tonically within the hierarchically ordered conversion stages (120-1, 120-k).

15. Mobile user device (1100) comprising a successive Approximation Register Analog to digital converter of any one of claims 1 to 9.

16. A base station (1200) comprising a successive Approximation RegisterAnalog to digital converter of any one of claims 1 to 9.

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