Array substrate, display panel, and display apparatus

Abstract

Provided in the embodiments of the present disclosure are an array substrate, a display panel, and a display apparatus. The array substrate comprises a substrate; a plurality of gate lines, which are located on a side of the substrate and extend in a first direction; a plurality of data lines, which are located on the same side of the substrate as the gate lines and extend in a second direction, the second direction intersecting the first direction; and a plurality of sub-pixels, which are located on the same side of the substrate as the gate lines, at least one of the plurality of sub-pixels comprising: two first sub-pixels successively arranged in the first direction, and a second sub-pixel between the two first sub-pixels, and the brightness of the second sub-pixel being greater than the brightness of the first sub-pixels.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines are located on one side of the substrate and extend along a first direction;

[0008] a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction;

[0009] A plurality of sub-pixels are located on the same side of the substrate as the gate line, and at least one sub-pixel among the plurality of sub-pixels includes: two first sub-pixels arranged in sequence along a first direction, and a second sub-pixel located between the two first sub-pixels; wherein the brightness of the second sub-pixel is greater than the brightness of the first sub-pixel.

[0010] In a possible implementation, the sub-pixel includes: a sub-pixel electrode; the first sub-pixel includes: a first sub-pixel electrode; the second sub-pixel includes: a second sub-pixel electrode; the sub-pixel electrodes include: the first sub-pixel electrode and the second sub-pixel electrode;

[0011] The plurality of second sub-pixel electrodes along the second direction include: a plurality of electrode pattern blocks arranged along the second direction; the orthographic projections of the electrode pattern blocks on the substrate include rhombuses.

[0012] In a possible implementation manner, at least one of the electrode pattern blocks is distributed in the same second sub-pixel electrode.

[0013] In a possible implementation manner, at least one of the electrode pattern blocks is distributed in two adjacent second sub-pixel electrodes.

[0014] In a possible embodiment, the electrode pattern block includes: a first sub-pattern block distributed along the second direction, and a second sub-pattern block; the orthographic projection of the first sub-pattern block on the substrate is a triangle, and the orthographic projection of the second sub-pattern block on the substrate is a triangle;

[0015] An orthographic projection of the second sub-pattern block of a second sub-pixel electrode on the substrate and an orthographic projection of the first sub-pattern block of an adjacent second sub-pixel electrode on the substrate are combined into a rhombus;

[0016] In the same second sub-pixel electrode, the first sub-pattern block and the second sub-pattern block are distributed relative to each other at a vertex angle.

[0017] In a possible embodiment, the electrode pattern block includes: a pattern main portion extending along the second direction, and two pattern branches connected to the pattern main portion; the two pattern branches are respectively located on both sides of the pattern main portion along the first direction;

[0018] A first gap extending along the second direction is defined between the pattern main portion and the pattern branch portion.

[0019] In a possible implementation manner, the two pattern branches are symmetrical with respect to the pattern main portion.

[0020] In a possible implementation manner, the first gaps between two adjacent electrode pattern blocks are not connected.

[0021] In a possible implementation manner, a length of the first gap in the second direction is smaller than a length of the electrode pattern block in the second direction.

[0022] In a possible implementation manner, a width of the first gap in the first direction is substantially equal to a width of the main pattern portion in the first direction.

[0023] In a possible implementation, the sub-pixel electrode has a slit; the sub-pixel electrode includes: a first sub-electrode portion, a second sub-electrode portion, a third sub-electrode portion, and a fourth sub-electrode portion arranged along the second direction;

[0024] The slit extending direction of the first sub-electrode portion is the same as the slit extending direction of the fourth sub-electrode portion; the slit extending direction of the second sub-electrode portion is the same as the slit extending direction of the third sub-electrode portion; the slit extending direction of the first sub-electrode portion is different from the slit extending direction of the second sub-electrode portion;

[0025] An extension direction of a portion of the edge of the electrode pattern block is parallel to an extension direction of the slit; an extension direction of a portion of the edge of the electrode pattern block is perpendicular to the extension direction of the slit.

[0026] In a possible implementation manner, the first sub-pixel electrode is a planar electrode, and the second sub-pixel electrode is a planar electrode.

[0027] In a possible implementation, the orthographic projection of the gate line on the substrate passes through a central area of ​​the orthographic projection of the sub-pixel electrode on the substrate; the first sub-pixel electrode and the second sub-pixel electrode each include: a first electrode portion and a second electrode portion arranged along the second direction; the orthographic projections of the first electrode portion and the second electrode portion on the substrate are respectively located on either side of the orthographic projection of the gate line on the substrate;

[0028] The sub-pixel electrode further includes a first connecting portion; and in the second sub-pixel electrode, the first electrode portion and the second electrode portion are electrically connected via the first connecting portion.

[0029] In a possible implementation manner, the first connection portion includes: a first sub-connection portion and a second sub-connection portion arranged along the second direction;

[0030] A width of the first sub-connection portion in the first direction is greater than a width of the second sub-connection portion in the first direction.

[0031] In a possible implementation manner, the first sub-connection portion is located in an end region of the second connection portion in the second direction, and the first sub-connection portion is formed by the first electrode portion protruding toward one side of the gate line.

[0032] In a possible implementation, the first sub-connection portion is located in a middle area of ​​the second sub-connection portion in the second direction, and the first sub-connection portion is formed by a side of the second sub-connection portion bulging outward along the second direction.

[0033] In a possible implementation, the second sub-connecting portion further includes: a first sub-portion, a second sub-portion, a third sub-portion, a fourth sub-portion, a fifth sub-portion, and a sixth sub-portion; the first sub-portion, the third sub-portion, the fourth sub-portion, and the sixth sub-portion extend along the second direction, and the second sub-portion and the fifth sub-portion extend along the first direction;

[0034] Among them, one end of the first sub-section is electrically connected to the first electrode section, and the other end of the first sub-section is electrically connected to one end of the second sub-section; the other end of the second sub-section is electrically connected to one end of the third sub-section; the other end of the third sub-section is electrically connected to one end of the first sub-connection section; one end of the fourth sub-section is electrically connected to the other end of the first sub-connection section, and the other end of the fourth sub-section is electrically connected to one end of the fifth sub-section; the other end of the fifth sub-section is electrically connected to one end of the sixth sub-section; and the other end of the sixth sub-section is electrically connected to the second electrode section.

[0035] In a possible implementation manner, the orthographic projection of the gate line on the substrate is located at an edge of the orthographic projection of the sub-pixel electrode on the substrate;

[0036] The sub-pixel electrode also includes: a first extension portion; the first extension portion includes: a first sub-extension portion distributed along the second direction, and a second sub-extension portion; the first sub-extension portion is located in the end area of ​​the second sub-extension portion along the second direction, and the width of the first sub-extension portion in the first direction is greater than the width of the second sub-extension portion in the first direction.

[0037] In a possible implementation, the array substrate further includes: a first common trace located on one side of the gate line, and a transfer electrode; an orthographic projection of the transfer electrode on the substrate and an orthographic projection of the first common trace on the substrate have an overlapping area;

[0038] The sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, and a third transistor; the first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode;

[0039] The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode;

[0040] The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode;

[0041] The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; and the second electrode of the third transistor is electrically connected to the switching electrode.

[0042] In a possible implementation, the sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, a third transistor, and a first signal line;

[0043] The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode;

[0044] The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode;

[0045] The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode;

[0046] The control electrode of the third transistor multiplexes with the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor; and the second electrode of the third transistor multiplexes with the first signal line.

[0047] In a possible implementation manner, the orthographic projection of the first signal line on the substrate passes through a central area of ​​the orthographic projection of the electrode pattern block on the substrate.

[0048] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0049] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0051] FIG1B is a schematic diagram of a single film layer of the gate line layer in FIG1A;

[0052] FIG1C is a schematic diagram of a single film layer of the data line layer in FIG1A ;

[0053] FIG1D is a schematic diagram of a single film layer of the active layer in FIG1A;

[0054] FIG1E is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0055] FIG1F is a schematic diagram of a single film layer of the pixel electrode layer in FIG1A ;

[0056] FIG1G is a schematic diagram of the black matrix layer corresponding to FIG1A ;

[0057] FIG1H is a schematic diagram of the light effect corresponding to FIG1A ;

[0058] FIG2A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0059] FIG2B is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0060] FIG2C is a schematic diagram of light effects corresponding to FIG2A ;

[0061] FIG3A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0062] FIG3B is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A ;

[0063] FIG3C is a schematic diagram of light effects corresponding to FIG3A ;

[0064] FIG4A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0065] FIG4B is a schematic diagram of a single film layer of the gate line layer in FIG4A ;

[0066] FIG4C is a schematic diagram of a single film layer of the data line layer in FIG4A ;

[0067] FIG4D is a schematic diagram of a single film layer of the active layer in FIG4A;

[0068] FIG4E is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0069] FIG4F is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0070] FIG4G is a schematic diagram of the black matrix layer corresponding to FIG4A ;

[0071] FIG4H is a schematic diagram of light effects corresponding to FIG4A ;

[0072] FIG5A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0073] FIG5B is a schematic diagram of a single film layer of the data line layer in FIG5A ;

[0074] FIG5C is a schematic diagram showing a comparison of light effects when the first slit is provided and when the first slit is not provided;

[0075] FIG6A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0076] FIG6B is a schematic diagram of a single film layer of the gate line layer in FIG6A;

[0077] FIG6C is a schematic diagram of a single film layer of the data line layer in FIG6A ;

[0078] FIG6D is a schematic diagram of a single film layer of the active layer in FIG6A;

[0079] FIG6E is a schematic diagram of a single film layer of the first insulating layer in FIG6A ;

[0080] FIG6F is a schematic diagram of a single film layer of the pixel electrode layer in FIG6A ;

[0081] FIG7A is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0082] FIG7B is a schematic diagram of a single film layer of the pixel electrode layer in FIG7A ;

[0083] FIG7C is a schematic diagram of light effects corresponding to FIG7A ;

[0084] FIG8A is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0085] FIG8B is a schematic diagram of a single film layer of the pixel electrode layer in FIG8A ;

[0086] FIG9 is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0087] FIG10A is a tenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0088] FIG10B is a schematic diagram of a single film layer of the pixel electrode layer in FIG10A ;

[0089] FIG10C is a schematic diagram of light effects corresponding to FIG10A ;

[0090] FIG11 is an eleventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0091] FIG12 is a twelfth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0092] FIG13 is a thirteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0093] FIG14 is a fourteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0094] FIG15 is a fifteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0095] FIG16 is a sixteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0096] FIG17 is a seventeenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0097] FIG18 is an eighteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0098] FIG19 is a nineteenth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0099] FIG20 is a twentieth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0100] FIG21 is a schematic diagram of sub-pixel distribution of 1P4D;

[0101] FIG22 is an equivalent circuit diagram corresponding to FIG1A ;

[0102] FIG23 is an equivalent circuit diagram corresponding to FIG6A;

[0103] FIG24 is a schematic diagram of various crosstalk images. DETAILED DESCRIPTION

[0104] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0105] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0106] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0107] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0108] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0109] Compared with the UV2A pixel design, ultra-fine optical alignment (SUVA) is an upgraded version of UV2A, as shown in Figure 21, where Figure 21 is a 1P4D (one sub-pixel contains 4 domains) SUVA pixel design. Compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark lines of the pixel, but the transmittance of the SUVA alignment is significantly improved for the 4-domain alignment, while the number of dark lines increases for the 8-domain alignment, and the transmittance improvement is insufficient.

[0110] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in Figures 1A-1H, 2A-2C, 3A-3C, 4A-4H, 5A-5C, 6A-6F, 7A-7C, 8A-8B, 9, 10A-10C, and 11-20, the array substrate includes:

[0111] Substrate 1;

[0112] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0113] A plurality of data lines 3 are located on the same side of the substrate 1 as the gate lines 2 and extend along a second direction Y, which intersects the first direction X;

[0114] Multiple sub-pixels 4 are located on the same side of the substrate 1 as the gate line 2, and at least one sub-pixel 4 among the multiple sub-pixels 4 includes: two first sub-pixels 41 arranged in sequence along the first direction X, and a second sub-pixel 42 located between the two first sub-pixels 41; wherein the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41.

[0115] In the embodiment of the present disclosure, the array substrate includes a plurality of sub-pixels 4, and the sub-pixels 4 include: a first sub-pixel 41, a second sub-pixel 42, and a first sub-pixel 41 distributed in sequence along a first direction X; wherein the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41, that is, the brighter second sub-pixel 42 is located in the middle, and the darker first sub-pixels 41 are arranged on both sides. Due to voltage suppression, longitudinal crosstalk does not occur. At the same time, the sub-pixel 4 has 8 domains, which can greatly reduce the proportion of dark lines, improve transmittance, and at the same time, improve color shift performance.

[0116] In the liquid crystal display panel, various wirings are densely arranged, and there is a large coupling capacitance, which leads to various crosstalk problems. The type of crosstalk is closely related to the row flip / column flip / dot flip of the liquid crystal display panel; as shown in Figure 24, the crosstalk problem includes horizontal crosstalk, vertical crosstalk, etc., among which horizontal crosstalk is related to the coupling capacitance between the data line and the common electrode; and vertical crosstalk, on the one hand, is related to the coupling capacitance between the data line and the pixel electrode, and on the other hand, it is also related to the transistor leakage current Ioff.

[0117] In the conventional 8Domain sub-pixel design, dark pixels are not bright at low grayscales, and only bright pixels are bright. In the disclosed embodiment, by setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4, the distance between the brighter second sub-pixel 42 and the data line can be made farther, and the coupling capacitance Cpd between the sub-pixel electrode and the data line is approximately 0. Therefore, when the image changes at low grayscales, pixels of different grayscales on both sides are unlikely to be affected by the different voltages of the data lines on both sides, so it is difficult for longitudinal crosstalk (i.e., vertical crosstalk) to occur, thereby improving the problem of longitudinal crosstalk. In other words, the setting method of setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4 has good longitudinal crosstalk performance at low grayscales.

[0118] It should be noted that brighter means more backlight is transmitted, and darker means less backlight is transmitted. That is, when different voltages are applied to different areas, the voltage difference formed with the common electrode of the opposite substrate is different. The greater the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the area is. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the area is.

[0119] Specifically, the array substrate may further include a pixel circuit. The brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41 . This can be understood as the brightness of the second sub-pixel 42 being greater than the brightness of the first sub-pixel 41 under the drive of the pixel circuit.

[0120] It should be noted that since the main difference between the structure shown in Figure 2A and the structure shown in Figure 1A lies in the difference in the sub-pixel electrode pattern, the array substrate corresponding to Figure 2A mainly shows the pattern of the sub-pixel electrode layer shown in Figure 2B, and the patterns of the gate line layer, data line layer, active layer, first insulating layer, and black matrix layer corresponding to Figure 2A can be seen in Figures 1B-1G, and are no longer repeated in the embodiments of the present disclosure; the remaining figures are similar.

[0121] In one possible embodiment, as shown in Figure 1F, the sub-pixel 4 includes: a sub-pixel electrode P; the first sub-pixel 41 includes: a first sub-pixel electrode P1; the second sub-pixel 42 includes: a second sub-pixel electrode P2; the sub-pixel electrode P includes: a first sub-pixel electrode P1 and a second sub-pixel electrode P2; the multiple second sub-pixel electrodes P2 along the second direction Y include: a plurality of electrode pattern blocks P0 arranged along the second direction Y; the orthographic projection of the electrode pattern block P0 on the substrate 1 includes a rhombus.

[0122] In one possible embodiment, as shown in FIG1F , the angle formed between one side of the rhombus and the first direction X can be 30° to 60°, specifically, for example, 45°; the angle formed between another side of the rhombus and the first direction X can be 130° to 160°, specifically, for example, 145°. In one possible embodiment, as shown in FIG1F , one diagonal line of the rhombus can be parallel to the first direction X, and the other diagonal line can be parallel to the second direction Y.

[0123] In one possible embodiment, the width of the diamond-shaped electrode pattern block P0 in the first direction X may be one-fifth to four-fifths of the width of the sub-pixel electrode P in the first direction X. In one possible embodiment, the width of the diamond-shaped electrode pattern block P0 in the first direction X may be one-half of the width of the sub-pixel electrode P in the first direction X. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-fifth to four-fifths of the width of the sub-pixel electrode P in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-quarter of the length of the sub-pixel electrode P in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be one-half of the length of the sub-pixel electrode P in the second direction Y. In one possible embodiment, the length of the diamond-shaped electrode pattern block P0 in the second direction Y may be equal to the length of the sub-pixel electrode P in the second direction Y.

[0124] In one possible embodiment, the four corners of the rhombus may all be right angles, as shown in FIG. 1A ; in another possible embodiment, the rhombus may include an obtuse angle, as shown in FIG. 2A-FIG . 2B .

[0125] In one possible embodiment, as shown in FIG1F , the first sub-pixel electrode P1 may have a pattern complementary to that of the second sub-pixel electrode P2. That is, the pattern of the sub-pixel electrode P is such that the pattern of the second sub-pixel electrode P2 is removed, resulting in a pattern of two first sub-pixel electrodes P1. In one possible embodiment, the orthographic projection pattern of the first sub-pixel electrode P1 on the substrate 1 may include multiple triangles, which may be spliced ​​with their corners facing each other, as shown in FIG1A ; or, may include a trapezoid, as shown in FIG2A .

[0126] In one possible embodiment, at least one electrode pattern block P0 is distributed in the same second sub-pixel electrode P2. That is, the area of ​​the electrode pattern block P0 can be relatively small, and one or more electrode pattern blocks P0 can be distributed in a sub-pixel electrode P, as shown in Figures 1A-1H, 2A-2C, 3A-3C, 4A-4H, 5A-5C, 6A-6F, 7A-7C, 8A-8B, 9, 10A-10C, and 11-16. In one possible embodiment, referring to Figure 1A, four electrode pattern blocks P0 can be distributed in a sub-pixel electrode P; in another possible embodiment, referring to Figure 2A, two electrode pattern blocks P0 can be distributed in a sub-pixel electrode P.

[0127] In another possible embodiment, at least one electrode pattern block P0 is distributed in two adjacent second sub-pixel electrodes P2, that is, the area of ​​the electrode pattern block P0 can be larger, and a portion of an electrode pattern block P0 can be distributed in one sub-pixel electrode P, that is, one electrode pattern block P0 can be respectively in multiple sub-pixel electrodes P, as shown in Figures 17-20.

[0128] In a possible embodiment, referring to Figures 17 and 18, the electrode pattern block P0 includes: a first sub-pattern block P01 distributed along the second direction Y, and a second sub-pattern block P02; the orthographic projection of the first sub-pattern block P01 on the substrate 1 is a triangle, and the orthographic projection of the second sub-pattern block P02 on the substrate 1 is a triangle; the orthographic projection of the second sub-pattern block P02 of a second sub-pixel electrode P2 on the substrate 1 is combined with the orthographic projection of the first sub-pattern block P01 of an adjacent second sub-pixel electrode P2 on the substrate 1 to form a rhombus; in the same second sub-pixel electrode P2, the first sub-pattern block P01 and the second sub-pattern block P02 are distributed relative to each other at a vertex angle.

[0129] In one possible embodiment, as shown in FIG. 5B , the electrode pattern block P0 includes a main pattern portion PA extending along the second direction X, and two branch pattern portions PB connected to the main pattern portion PA; the two branch pattern portions PB are located on either side of the main pattern portion PA along the first direction X; and a first gap F1 extending along the second direction is defined between the main pattern portion PA and the branch pattern portions PB. In the disclosed embodiment, the first gap F1 extending along the second direction between the main pattern portion PA and the branch pattern portions PB can narrow the dark lines of the array substrate, thereby improving transmittance.

[0130] Refer to Figure 5C, wherein the left side figure in Figure 5C is a schematic diagram of the light effect corresponding to when there is no first gap F1 between the pattern main part PA and the pattern branch part PB, and the right side figure in Figure 5C is a schematic diagram of the light effect corresponding to when there is a first gap F1 between the pattern main part PA and the pattern branch PB. From the comparison between the two, it can be seen that there is a first gap F1 extending along the second direction between the pattern main part PA and the pattern branch PB, which can make the dark lines of the array substrate narrower, thereby improving the transmittance.

[0131] In one possible embodiment, as shown in FIG5B , the two pattern branches PB are symmetrical about the pattern main portion PA. In one possible embodiment, as shown in FIG5B , the orthographic projection pattern of the pattern branch PB on the substrate 1 is a triangle. Optionally, the orthographic projection pattern of the pattern branch PB on the substrate 1 is a right triangle, with the two pattern branches PB of the right triangle arranged with their hypotenuses facing each other; alternatively, the pattern branch PB of the right triangle is arranged with its hypotenuse facing the first gap F1.

[0132] In one possible embodiment, as shown in FIG5B , the first gaps F1 of two adjacent electrode pattern blocks P0 are not connected. This allows the two pattern branches PB on the left and right sides of the same electrode pattern block P0 to be electrically connected at their upper and lower ends, ensuring that the two pattern branches PB in the same electrode pattern block P0 have good connectivity even when the first gaps F1 are provided.

[0133] In a possible implementation manner, the first gaps F1 of two adjacent electrode pattern blocks P0 may also be connected.

[0134] In one possible embodiment, as shown in FIG5B , the length a1 of the first slit F1 in the second direction Y is less than the length a2 of the electrode pattern block P0 in the second direction Y. In one possible embodiment, the length a1 of the first slit F1 in the second direction Y may be equal to the length a2 of the electrode pattern block P0 in the second direction Y. In one possible embodiment, as shown in FIG5B , the width b1 of the first slit F1 in the first direction X may be approximately equal to the width b2 of the pattern main portion PA in the first direction X.

[0135] In a possible embodiment, as shown in FIG. 1F , the sub-pixel electrode P has a slit S. The sub-pixel electrode P includes a first sub-electrode portion PP1, a second sub-electrode portion PP2, a third sub-electrode portion PP3, and a fourth sub-electrode portion PP4 arranged along the second direction Y.

[0136] The extending direction of the slit S of the first sub-electrode portion PP1 is the same as the extending direction of the slit S of the fourth sub-electrode portion PP4; the extending direction of the slit S of the second sub-electrode portion PP2 is the same as the extending direction of the slit S of the third sub-electrode portion PP3; the extending direction of the slit S of the first sub-electrode portion PP1 is different from the extending direction of the slit S of the second sub-electrode portion PP2;

[0137] The extension direction of some edges of the electrode pattern block P0 is parallel to the extension direction of the slit S; the extension direction of some edges of the electrode pattern block P0 is perpendicular to the extension direction of the slit S. For example, as shown in FIG1F , the extension direction of the upper left and lower right edges of the first electrode pattern block P0 from top to bottom of the leftmost sub-pixel electrode is parallel to the extension direction of the slit S; the extension direction of the upper right and lower left edges of the electrode pattern block P0 is perpendicular to the extension direction of the slit S.

[0138] In a possible embodiment, referring to FIG1F , the angle formed by the extension direction of the slit S in the first sub-electrode portion PP1 and the first direction X may be in the range of 30° to 60°, specifically, for example, 45°; the angle formed by the extension direction of the slit F in the second sub-portion PP2 and the first direction X may be in the range of 130° to 160°, specifically, for example, 145°.

[0139] Specifically, in combination with what is shown in FIG1F , the first sub-electrode portion PP1 may include: a portion of the first sub-pixel electrode P1, and may also include a portion of the second sub-pixel electrode P2; similarly, the second sub-electrode portion PP2 may include: a portion of the first sub-pixel electrode P1, and may also include a portion of the second sub-pixel electrode P2; similarly, the third sub-electrode portion PP3 may include: a portion of the first sub-pixel electrode P1, and may also include a portion of the second sub-pixel electrode P2; similarly, the fourth sub-electrode portion PP4 may include: a portion of the first sub-pixel electrode P1, and may also include a portion of the second sub-pixel electrode P2.

[0140] In one possible implementation, referring to Figures 5A-5C, 6A-6F, 7A-7C, 8A-8B, 9, 10A-10B, and 11-20, the first sub-pixel electrode P1 is a planar electrode, and the second sub-pixel electrode P2 is a planar electrode. In the disclosed embodiment, when the first sub-pixel electrode P1 and the second sub-pixel electrode P2 are planar electrodes, a UV2A alignment scheme can also be employed, thereby improving crosstalk issues associated with the UV2A structure.

[0141] In one possible embodiment, referring to Figures 1A to 1F, the orthographic projection of the gate line 2 on the substrate 1 passes through the central area of ​​the orthographic projection of the sub-pixel electrode P on the substrate 1; the first sub-pixel electrode P1 and the second sub-pixel electrode P2 both include: a first electrode portion PX arranged along the second direction Y, and a second electrode portion PY; the orthographic projections of the first electrode portion PX and the second electrode portion PY on the substrate 1 are respectively located on both sides of the orthographic projection of the gate line 2 on the substrate 1; the sub-pixel electrode P further includes: a first connecting portion L1; in the second sub-pixel electrode P2, the first electrode portion PX and the second electrode portion PY are electrically connected via the first connecting portion L1. In the embodiment of the present disclosure, the second sub-pixel electrode P2 is divided into two upper and lower parts by the gate line 2, with a gap between the two parts to prevent the second sub-pixel electrode P2 from overlapping with the gate line 2. The two parts of the second sub-pixel electrode P2 divided by the gate line 2 are then connected via a third connecting portion L3 to electrically connect the two parts of the second sub-pixel electrode P2 on different sides of the gate line 2.

[0142] Specifically, the first electrode portion PX may include a first sub-electrode portion PP1 and a second sub-electrode portion PP2 ; and the second electrode portion PY may include a third sub-electrode portion PP3 and a fourth sub-electrode portion PP4 .

[0143] In one possible embodiment, as shown in FIG1F , the first connection portion L1 includes a first sub-connection portion L11 and a second sub-connection portion L12 arranged along the second direction Y. The width c1 of the first sub-connection portion L11 in the first direction X is greater than the width c2 of the second sub-connection portion L12 in the first direction X. In this manner, while the first connection portion L1 electrically connects the two portions of the second sub-pixel electrode P2 on different sides of the gate line 2, the wider first sub-connection portion L11 can also be used to electrically connect the second sub-pixel electrode P2 to the transistor of the pixel circuit, thereby enabling the pixel circuit to drive the second sub-pixel electrode P2 to achieve a brighter display.

[0144] In a possible embodiment, as shown in FIG. 1F , the first sub-connection portion L11 is located at an end region of the second connection portion L12 in the second direction Y. The first sub-connection portion L11 is formed by the first electrode portion PX protruding toward the gate line 2 .

[0145] In a possible embodiment, as shown in FIG. 6F , the first sub-connection portion L11 is located in the middle area of ​​the second sub-connection portion L22 in the second direction Y, and the first sub-connection portion L11 is formed by bulging outward along the second direction Y on one side of the second sub-connection portion L12.

[0146] In a possible embodiment, as shown in FIG6F , the second sub-connecting portion L12 further includes: a first sub-portion LX1, a second sub-portion LX2, a third sub-portion LX3, a fourth sub-portion LX4, a fifth sub-portion LX5, and a sixth sub-portion LX6; the first sub-portion LX1, the third sub-portion LX3, the fourth sub-portion LX4, and the sixth sub-portion LX6 extend along the second direction Y, and the second sub-portion LX2 and the fifth sub-portion LX5 extend along the first direction X;

[0147] One end of the first sub-section LX1 is electrically connected to the first electrode section PX, and the other end of the first sub-section LX is electrically connected to one end of the second sub-section LX2; the other end of the second sub-section LX2 is electrically connected to one end of the third sub-section LX3; the other end of the third sub-section LX3 is electrically connected to one end of the first sub-connection section L11; one end of the fourth sub-section LX4 is electrically connected to the other end of the first sub-connection section L11; the other end of the fourth sub-section LX4 is electrically connected to one end of the fifth sub-section LX5; the other end of the fifth sub-section LX5 is electrically connected to one end of the sixth sub-section LX6; and the other end of the sixth sub-section LX is electrically connected to the second electrode section PY. In the disclosed embodiment, the second sub-connection section L12 is a zigzag structure with multiple segments of wiring connected to avoid the third transistor T3 (specifically, it can avoid the location of the active layer in the third transistor T3) and the first signal line 6, so as to provide sufficient space for the first signal line 6 and the third transistor T3, and avoid the generation of coupling capacitance when overlapping with the third transistor T3 and the first signal line 6, which may affect normal display.

[0148] In one possible embodiment, as shown in FIG1F , the subpixel electrode P further includes a second connection portion L3; the two portions of the first subpixel electrode P1 on different sides of the gate line 2 are electrically connected via the second connection portion L3. In one possible embodiment, as shown in FIG1F , the second connection portion L3 extends along the second direction Y.

[0149] In one possible embodiment, as shown in conjunction with Figures 4A-4F , the orthographic projection of the gate line 2 on the substrate 1 is located at the edge of the orthographic projection of the sub-pixel electrode P on the substrate 1; the sub-pixel electrode P further includes: a first extension portion L2; the first extension portion L2 includes: a first sub-extension portion L21 distributed along the second direction Y, and a second sub-extension portion L22; the first sub-extension portion L21 is located at the end region of the second sub-extension portion L22 along the second direction Y, and the width d1 of the first sub-extension portion L21 in the first direction X is greater than the width d2 of the second sub-extension portion L22 in the first direction X. In this way, when the gate line 2 is located at the edge of the sub-pixel electrode P, it can be electrically connected to the transistor of the pixel circuit through the wider first sub-extension portion L21, so that the pixel circuit can drive the second sub-pixel electrode P2 to achieve a brighter display.

[0150] In a possible embodiment, with reference to FIG. 1A to FIG. 1F and FIG. 22 , where FIG. 22 may be an equivalent circuit diagram corresponding to FIG. 1A , the array substrate further includes: a first common trace 51 located on one side of the gate line 2, and a transfer electrode PC; an orthographic projection of the transfer electrode PC on the substrate 1 has an overlapping area with an orthographic projection of the first common trace 51 on the substrate 1;

[0151] The sub-pixel 4 further includes: a pixel circuit; the pixel circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; the first transistor T1 includes: a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes: a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes: a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C;

[0152] The first transistor control electrode T1A is multiplexed with the gate line 2, the first transistor first electrode T1B is multiplexed with the data line 3; the first transistor second electrode T1C is electrically connected to the second sub-pixel electrode P2;

[0153] The control electrode T2A of the second transistor reuses the gate line 2, the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor; the second electrode T2C of the second transistor is electrically connected to the first sub-pixel electrode P1;

[0154] The control electrode T3A of the third transistor reuses the gate line 2 , the first electrode T3B of the third transistor reuses the second electrode T2C of the second transistor; the second electrode T3C of the third transistor is electrically connected to the first common wiring 51 through the switching electrode PC.

[0155] Specifically, the array substrate also includes: a second common wiring 52 located on the other side of the gate line 2, a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode P1 and the common electrode layer of the opposite substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode P2 and the common electrode layer of the opposite substrate, the first capacitor C1 can be formed by the first sub-pixel electrode P1 and the second common wiring 52, and the second capacitor C2 can be formed by the second sub-pixel electrode P2 and the first sub-common wiring 51.

[0156] In the embodiment of the present invention, the first sub-pixel electrode P1 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode P2 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode T3C of the third transistor is electrically connected to the first common wiring 51. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode P2 can be released to the first common wiring 51 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode P1 greater than the brightness of the second sub-pixel electrode P2, thereby achieving different light and dark pixels in the same sub-pixel electrode P, and realizing an 8-domain display effect.

[0157] In one possible embodiment, as shown in Figures 1A-1G , the orthographic projection of the transfer electrode PC on the substrate 1 overlaps with the orthographic projection of the first common trace 51 on the substrate 1 and overlaps with the orthographic projection of the second electrode T3C of the third transistor on the substrate 1. The third via K3 can be a semi-via design, partially exposing the first common trace 51 and partially exposing the second electrode T3C of the third transistor. The transfer electrode PC, at the third via K3, partially contacts the first common trace 51 and partially contacts the second electrode T3C of the third transistor, thereby electrically connecting the first common trace 51 and the second electrode T3C of the third transistor via the transfer electrode PC. Specifically, the semi-via design of the third via K3 can form a stepped structure within the third via K3, which serves to drain the alignment liquid and prevent the appearance of moiré patterns on the image.

[0158] In a possible implementation, as shown in FIG. 1F , the first common traces 51 may be made of the same layer and material as the gate lines 2 . Thus, the first common traces 51 are formed simultaneously with the gate lines 2 , which simplifies the manufacturing process of the array substrate.

[0159] In a possible implementation, as shown in FIG. 1F , the transfer electrode PC may be made of the same layer and material as the sub-pixel electrode P. Thus, the transfer electrode PC is formed at the same time as the sub-pixel electrode P, thereby simplifying the manufacturing process of the array substrate.

[0160] In a possible embodiment, as shown in Figure 1F, the array substrate may further include: a third common routing group extending along the second direction Y, the third common routing group including: two third common routing lines 53, the two third common routing lines 53 of the same third common routing group are projected on the substrate 1, and are located on both sides of the projected data line 3 on the substrate 1.

[0161] In a possible implementation, in combination with FIG. 6A to FIG. 6F and FIG. 23 , where FIG. 23 may be an equivalent circuit diagram corresponding to FIG. 6A , the sub-pixel 4 further includes: a pixel circuit; the pixel circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first signal line 6;

[0162] The first transistor T1 includes: a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes: a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes: a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C;

[0163] The first transistor control electrode T1A is multiplexed with the gate line 2, the first transistor first electrode T1B is multiplexed with the data line 3; the first transistor second electrode T1C is electrically connected to the second sub-pixel electrode P2;

[0164] The control electrode T2A of the second transistor reuses the gate line 2, the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor; the second electrode T2C of the second transistor is electrically connected to the first sub-pixel electrode P1;

[0165] The control electrode T3A of the third transistor multiplexes with the gate line 2 , the first electrode T3B of the third transistor multiplexes with the second electrode T2C of the second transistor; and the second electrode T1C of the third transistor multiplexes with the first signal line 6 .

[0166] Specifically, the array substrate also includes: a first common routing line 51 located on one side of the gate line 2, a second common routing line 52 located on the other side of the gate line 2, a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode P1 and the common electrode layer of the opposing substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode P2 and the common electrode layer of the opposing substrate, the first capacitor C1 can be formed by the first sub-pixel electrode P1 and the second common routing line 52, and the second capacitor C2 can be formed by the second sub-pixel electrode P2 and the first sub-common routing line 51.

[0167] In an embodiment of the present invention, the first sub-pixel electrode P1 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode P2 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode T3C of the third transistor is electrically connected to the first signal line 6. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode P2 can be released to the first signal line 6 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode P1 greater than the brightness of the second sub-pixel electrode P2, thereby achieving different light and dark pixels in the same sub-pixel electrode P, and realizing an 8-domain display effect.

[0168] In one possible embodiment, as shown in Figures 6A to 6F, the orthographic projection of the first signal line 6 on the substrate 1 passes through the central area of ​​the orthographic projection of the electrode pattern block P0 on the substrate 1. In this way, the transmittance of the display panel can be improved by having fewer dark lines.

[0169] In a possible embodiment, with reference to FIG. 1A to FIG. 1H , the array substrate may be provided with, in sequence, a gate line layer as shown in FIG. 1B , a data line layer as shown in FIG. 1C , an active layer as shown in FIG. 1D , a first insulating layer as shown in FIG. 1E , and a sub-pixel electrode layer as shown in FIG. 1F on one side of the substrate 1 ;

[0170] The active layer may include an active pattern 71 corresponding to the transistor;

[0171] The first insulating layer may have a first via hole K1 , a second via hole K2 , and a third via hole K3 ; the first insulating layer may be a first passivation layer or an organic organic layer.

[0172] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0173] Specifically, the counter substrate may include a counter substrate and a common electrode layer located on the side of the counter substrate facing the array substrate. Specifically, the counter substrate may also include a black matrix layer as shown in FIG1G , which may include a black matrix pattern 81 and black matrix openings.

[0174] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0175] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0176] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate and extend along a first direction; a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction; A plurality of sub-pixels are located on the same side of the substrate as the gate line, and at least one sub-pixel among the plurality of sub-pixels includes: two first sub-pixels arranged in sequence along a first direction, and a second sub-pixel located between the two first sub-pixels; wherein the brightness of the second sub-pixel is greater than the brightness of the first sub-pixel.

2. The array substrate according to claim 1, wherein: The sub-pixel includes: a sub-pixel electrode; the first sub-pixel includes: a first sub-pixel electrode; the second sub-pixel includes: a second sub-pixel electrode; the sub-pixel electrodes include: the first sub-pixel electrode and the second sub-pixel electrode; The plurality of second sub-pixel electrodes along the second direction include: a plurality of electrode pattern blocks arranged along the second direction; the orthographic projections of the electrode pattern blocks on the substrate include rhombuses.

3. The array substrate according to claim 2, wherein: At least one of the electrode pattern blocks is distributed in the same second sub-pixel electrode.

4. The array substrate according to claim 3, wherein: At least one of the electrode pattern blocks is distributed between two adjacent second sub-pixel electrodes.

5. The array substrate according to claim 4, wherein: The electrode pattern block includes: a first sub-pattern block distributed along the second direction, and a second sub-pattern block; the orthographic projection of the first sub-pattern block on the substrate is a triangle, and the orthographic projection of the second sub-pattern block on the substrate is a triangle; An orthographic projection of the second sub-pattern block of a second sub-pixel electrode on the substrate and an orthographic projection of the first sub-pattern block of an adjacent second sub-pixel electrode on the substrate are combined into a rhombus; In the same second sub-pixel electrode, the first sub-pattern block and the second sub-pattern block are Relative distribution of vertex angles.

6. The array substrate according to any one of claims 3 to 5, wherein: The electrode pattern block includes: a pattern main portion extending along the second direction, and two pattern branches connected to the pattern main portion; the two pattern branches are respectively located on both sides of the pattern main portion along the first direction; A first gap extending along the second direction is defined between the pattern main portion and the pattern branch portion.

7. The array substrate according to claim 6, wherein: The two pattern branches are symmetrical with respect to the pattern main portion.

8. The array substrate according to claim 6 or 7, wherein: The first gaps between two adjacent electrode pattern blocks are not connected.

9. The array substrate according to any one of claims 6 to 8, wherein: The length of the first gap in the second direction is smaller than the length of the electrode pattern block in the second direction.

10. The array substrate according to any one of claims 6 to 9, wherein: The width of the first slit in the first direction is substantially equal to the width of the main pattern portion in the first direction.

11. The array substrate according to any one of claims 1 to 10, wherein: The sub-pixel electrode has a slit; the sub-pixel electrode includes: a first sub-electrode portion, a second sub-electrode portion, a third sub-electrode portion, and a fourth sub-electrode portion arranged along the second direction; The slit extending direction of the first sub-electrode portion is the same as the slit extending direction of the fourth sub-electrode portion; the slit extending direction of the second sub-electrode portion is the same as the slit extending direction of the third sub-electrode portion; the slit extending direction of the first sub-electrode portion is different from the slit extending direction of the second sub-electrode portion; An extension direction of a portion of the edge of the electrode pattern block is parallel to an extension direction of the slit; an extension direction of a portion of the edge of the electrode pattern block is perpendicular to the extension direction of the slit.

12. The array substrate according to any one of claims 1 to 10, wherein: The first sub-pixel electrode is a planar electrode, and the second sub-pixel electrode is a planar electrode.

13. The array substrate according to any one of claims 2 to 12, wherein: The orthographic projection of the gate line on the substrate passes through the central area of ​​the orthographic projection of the sub-pixel electrode on the substrate; The first sub-pixel electrode and the second sub-pixel electrode each include: a first electrode portion and a second electrode portion arranged along the second direction; the orthographic projections of the first electrode portion and the second electrode portion on the substrate are respectively located on both sides of the orthographic projection of the gate line on the substrate; The sub-pixel electrode further includes a first connecting portion; and in the second sub-pixel electrode, the first electrode portion and the second electrode portion are electrically connected via the first connecting portion.

14. The array substrate according to claim 13, wherein: The first connection portion includes: a first sub-connection portion and a second sub-connection portion arranged along the second direction; A width of the first sub-connection portion in the first direction is greater than a width of the second sub-connection portion in the first direction.

15. The array substrate according to claim 14, wherein: The first sub-connection portion is located in an end region of the second connection portion in the second direction, and the first sub-connection portion is formed by the first electrode portion protruding toward one side of the gate line.

16. The array substrate according to claim 14, wherein: The first sub-connection portion is located in a middle area of ​​the second sub-connection portion in the second direction, and the first sub-connection portion is formed by a side of the second sub-connection portion protruding outward along the second direction.

17. The array substrate according to claim 16, wherein: The second sub-connecting portion further includes: a first sub-portion, a second sub-portion, a third sub-portion, a fourth sub-portion, a fifth sub-portion, and a sixth sub-portion; the first sub-portion, the third sub-portion, the fourth sub-portion, and the sixth sub-portion extend along the second direction, and the second sub-portion and the fifth sub-portion extend along the first direction; Among them, one end of the first sub-section is electrically connected to the first electrode section, and the other end of the first sub-section is electrically connected to one end of the second sub-section; the other end of the second sub-section is electrically connected to one end of the third sub-section; the other end of the third sub-section is electrically connected to one end of the first sub-connection section; one end of the fourth sub-section is electrically connected to the other end of the first sub-connection section, and the other end of the fourth sub-section is electrically connected to one end of the fifth sub-section; the other end of the fifth sub-section is electrically connected to one end of the sixth sub-section; and the other end of the sixth sub-section is electrically connected to the second electrode section.

18. The array substrate according to any one of claims 2 to 12, wherein: The orthographic projection of the gate line on the substrate is located at the edge of the orthographic projection of the sub-pixel electrode on the substrate; The sub-pixel electrode further includes: a first extension portion; the first extension portion includes: A first sub-extension portion and a second sub-extension portion are distributed in two directions; the first sub-extension portion is located in the end area of ​​the second sub-extension portion along the second direction, and the width of the first sub-extension portion in the first direction is greater than the width of the second sub-extension portion in the first direction.

19. The array substrate according to any one of claims 1 to 18, wherein: The array substrate further includes: a first common wiring located on one side of the gate line, and a switching electrode; an orthographic projection of the switching electrode on the substrate and an orthographic projection of the first common wiring on the substrate have an overlapping area; The sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, and a third transistor; the first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode; The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode; The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; and the second electrode of the third transistor is electrically connected to the switching electrode.

20. The array substrate according to any one of claims 1 to 18, wherein: The sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, a third transistor, and a first signal line; The first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode; The control electrode of the second transistor reuses the gate line, and the first electrode of the second transistor reuses the a first electrode of the first transistor; a second electrode of the second transistor being electrically connected to the first sub-pixel electrode; The control electrode of the third transistor multiplexes with the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor; and the second electrode of the third transistor multiplexes with the first signal line.

21. The array substrate according to claim 20, wherein: The orthographic projection of the first signal line on the substrate passes through a central area of ​​the orthographic projection of the electrode pattern block on the substrate.

22. A display panel, wherein: comprising the array substrate according to any one of claims 1 to 21, further comprising an opposite substrate arranged opposite to the array substrate; The opposite substrate includes a common electrode layer.

23. A display device, wherein: Comprising the display panel as claimed in claim 22.

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