Analog-to-digital conversion method and circuit, chip and electronic device

Abstract

Provided in the present application are an analog-to-digital conversion method and circuit, a chip and an electronic device. The analog-to-digital conversion circuit comprises a digital-to-analog conversion capacitor array; a calibration capacitor array, used for calibrating the digital-to-analog conversion capacitor array; and a logic control module, used for selecting, on the basis of a range control signal, the digital-to-analog conversion capacitor array and the calibration capacitor array to sample and / or convert an analog input signal, so as to reduce or amplify the analog input signal according to a proportion corresponding to the range control signal. By reusing the calibration capacitor array, with a smaller circuit area, analog input signals can be reduced or amplified in a larger range.

Description

Analog-to-digital conversion method, circuit, chip, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 2, 2024, with application number 202410006718.5 and invention name “Analog-to-digital conversion method, circuit, chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic circuit technology, and in particular to an analog-to-digital conversion method, circuit, chip, and electronic device. Background Art

[0003] Before the analog signal is converted, both bipolar and unipolar analog input signals are expected to be scaled to the dynamic input range of the analog-to-digital converter (ADC) to effectively process wide input signals.

[0004] In the prior art, a resistor divider is used at the analog input to scale the input signal to the dynamic range of the analog-to-digital converter. This approach requires the analog input source to be able to drive a resistive load. Furthermore, the resistor divider consumes power, which in turn draws power from the analog input source. Furthermore, the analog input range scaling is relatively fixed.

[0005] Therefore, no effective solution has been proposed in the related art regarding how to scale the input signal to the dynamic range of the analog-to-digital converter. Technical Solutions

[0006] In view of the above problems, the embodiments of the present application provide an analog-to-digital conversion method, circuit, chip and electronic device to solve the above technical problems.

[0007] In a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, comprising: a digital-to-analog conversion capacitor array; a calibration capacitor array for calibrating the digital-to-analog conversion capacitor array; and a logic control module for selecting the digital-to-analog conversion capacitor array and the calibration capacitor array based on a range control signal to sample and / or convert an analog input signal, so as to reduce or amplify the analog input signal according to a ratio corresponding to the range control signal.

[0008] In a second aspect, an embodiment of the present application provides a chip comprising the above-mentioned analog-to-digital conversion circuit.

[0009] In a third aspect, an embodiment of the present application provides an electronic device, including a device body and the above-mentioned chip provided in the device body.

[0010] In a fourth aspect, an embodiment of the present application provides an analog-to-digital conversion method, including: selecting a digital-to-analog conversion capacitor array and a calibration capacitor array based on a range control signal to sample and / or convert an analog input signal, so as to reduce or amplify the analog input signal according to a ratio corresponding to the range control signal; wherein, the calibration capacitor array is used to calibrate the digital-to-analog conversion capacitor array.

[0011] The analog-to-digital conversion method, circuit, chip, and electronic device provided in the embodiments of the present application use a calibration capacitor array to sample and / or convert an analog input signal, thereby achieving a larger range of reduction or amplification of the analog input signal with a smaller circuit area.

[0012] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] FIG1 shows a schematic block diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application.

[0015] FIG2 a shows a schematic diagram of a digital-to-analog conversion capacitor array and a calibration capacitor array provided in an embodiment of the present application.

[0016] FIG2 b shows a schematic diagram of an exemplary combination of a digital-to-analog conversion capacitor array and a calibration capacitor array provided in an embodiment of the present application.

[0017] 2c and 2d show equivalent schematic diagrams of an exemplary combination of a digital-to-analog conversion capacitor array and a calibration capacitor array provided in an embodiment of the present application.

[0018] 3a to 3c are schematic diagrams showing a method of selecting a digital-to-analog conversion capacitor array and a calibration capacitor array to amplify an analog input signal according to an embodiment of the present application.

[0019] FIG4 shows a schematic block diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application.

[0020] FIG5 shows a schematic block diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application.

[0021] 6a to 6d are schematic diagrams showing an exemplary combination of a digital-to-analog conversion capacitor array and a calibration capacitor array according to an embodiment of the present application.

[0022] FIG7 shows a flow chart of an analog-to-digital conversion method provided in an embodiment of the present application.

[0023] FIG8 shows a flowchart of another analog-to-digital conversion method provided in an embodiment of the present application.

[0024] Implementation Methods of the Application

[0025] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0026] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0028] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0029] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0030] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0031] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0032] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0033] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0034] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0035] An embodiment of the present application provides an analog-to-digital conversion circuit. The analog-to-digital conversion circuit of the embodiment of the present application can achieve a larger range of reduction or amplification of an analog input signal with a smaller circuit area.

[0036] FIG1 shows a schematic block diagram of an analog-to-digital conversion circuit according to an embodiment of the present application. As shown in FIG1 , the analog-to-digital conversion circuit 100 may include a digital-to-analog conversion capacitor array 101, a calibration capacitor array 102, a logic control module 103, and a comparison unit 104. The logic control module 103 may monitor the output of the comparison unit 104. The calibration capacitor array 102 is used to calibrate the digital-to-analog conversion capacitor array 101.

[0037] In the embodiment of the present application, the logic control module 103 can be configured to select the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 to sample and / or convert the analog input signal based on the range control signal, thereby reducing or amplifying the analog input signal according to the ratio corresponding to the range control signal. For example, the analog input signal can be amplified or reduced to match the dynamic range of the analog-to-digital conversion circuit 100.

[0038] In an embodiment of the present application, the logic control module 103 can also be used to control the calibration capacitor array 102 to perform calibration based on the calibration code. As an embodiment, the amount to be calibrated is the actual value of each capacitor position in the digital-to-analog conversion capacitor array 101. During the calibration phase, the capacitance mismatch value is expressed in the form of an error voltage output by the digital-to-analog conversion capacitor array 101. The calibration capacitor array 102 measures the error voltage value and saves the result as a calibration code. During the working phase, the calibration capacitor array 102 loads the error voltage to the output of the digital-to-analog conversion capacitor array 101 by connecting different capacitors.

[0039] In an embodiment of the present application, the smaller the capacitor for sampling the analog input signal, the greater the reduction ratio; the larger the capacitor for sampling the analog input signal, the greater the amplification ratio; the larger the capacitor for conversion, the greater the reduction ratio. In some examples, the sampling capacitor size can be increased by multiplexing the calibration capacitor array 102 to amplify the analog input signal. In some examples, the conversion capacitor size can be increased by multiplexing the calibration capacitor array 102 to reduce the analog input signal. In some examples, the analog input signal can be reduced by reducing the sampling capacitor size and increasing the conversion capacitor size by multiplexing the calibration capacitor array 102 to increase the reduction ratio of the analog input signal, that is, to reduce the analog input signal. In addition, multiple combinations of sampling capacitor size and conversion capacitor size can provide a variety of reduction or amplification ratios. Multiplexing the calibration capacitor array 102 can achieve more combinations and provide more reduction or amplification ratios.

[0040] In some embodiments, logic control module 103 may, during conversion, select a combination of capacitors in calibration capacitor array 102 and various capacitor bits of digital-to-analog conversion capacitor array 101 based on a range control signal to increase the capacitance of each capacitor bit of digital-to-analog conversion capacitor array 101; and control the combined capacitor bits for conversion. This embodiment can reduce the analog input signal by a ratio corresponding to the range control signal.

[0041] As an embodiment, the logic control module 103 can select capacitors of at least one capacitance position in the calibration capacitor array 102 based on the range control signal to be combined with each capacitance position of the first capacitor array. In this way, the unselected capacitance positions in other calibration capacitor arrays 102 can be used for calibration.

[0042] In some embodiments, the logic control module 103 may further select capacitors in the calibration capacitor array 102 and / or the digital-to-analog conversion capacitor array 101 based on the range control signal during the sampling period to sample the analog input signal. In this embodiment, the capacitor sizes for sampling and the capacitor sizes for conversion are selected based on the range control signal, and the analog input signal can be scaled down according to the ratio corresponding to the range control signal.

[0043] As an example, during a sampling period, one or more capacitors in the digital-to-analog conversion capacitor array 101 can be selected based on a range control signal to sample the analog input signal. The smaller the capacitance of the selected capacitor, the greater the reduction ratio. That is, the smaller the sampled capacitance, the smaller the analog-to-digital input signal. In this example, during a conversion period, the calibration capacitor array 102 can be controlled based on a calibration code for calibration.

[0044] As another example, during sampling, one or more capacitors in the calibration capacitor array 102 can be selected based on the range control signal to sample the analog input signal. The smaller the capacitance of the selected capacitor, the greater the scale-down ratio. That is, the smaller the sampled capacitance, the smaller the analog-to-digital input signal. In this example, during conversion, the calibration capacitor array 102 can be controlled based on the calibration code to perform calibration.

[0045] As another example, during sampling, one or more capacitors of the digital-to-analog conversion capacitor array 101 and one or more capacitors of the calibration capacitor array 102 can be selected based on the range control signal to sample the analog input signal. The smaller the capacitance of the selected capacitor, the greater the reduction ratio. That is, the smaller the sampled capacitance, the smaller the analog-to-digital input signal. In this example, during conversion, the calibration capacitor array 102 can be controlled based on the calibration code to perform calibration.

[0046] In some embodiments, the logic control module 103 may: during a sampling period, select capacitors in the calibration capacitor array 102 and / or the digital-to-analog conversion capacitor array 101 based on a range control signal to sample an analog input signal; during a conversion period, select capacitors in the calibration capacitor array 102 and various capacitor positions in the digital-to-analog conversion capacitor array 101 based on the range control signal to increase the capacitance of each capacitor position in the digital-to-analog conversion capacitor array 101; and control the combined capacitor positions for conversion. In this embodiment, the reduction ratio is determined by both the capacitance of the capacitors being sampled and the capacitance of the capacitors being converted, and the analog input signal can be reduced according to the ratio corresponding to the range control signal.

[0047] As an embodiment, during the conversion period, the logic control module 103 may connect the capacitor corresponding to the capacitance position of the digital-to-analog conversion capacitor array 101 to the reference voltage terminal, and connect the capacitor combined with it in the calibration capacitor array 102 to the reference voltage terminal; if the capacitor corresponding to the capacitance position of the digital-to-analog conversion capacitor array 101 is grounded, the capacitor combined with it in the calibration capacitor array 102 is grounded.

[0048] As an example, the logic control module 103 may select, based on the range control signal, a capacitor of at least one capacitance position in the calibration capacitor array 102 and combine it with each capacitance position of the digital-to-analog conversion capacitor array 101. Exemplarily, each capacitance position in the calibration capacitor array 102 may include multiple capacitors, and the capacitor of at least one capacitance position in the calibration capacitor array 102 may be allocated to each capacitance position of the digital-to-analog conversion capacitor array 101 to adjust the capacitance of each capacitance position of the digital-to-analog conversion capacitor array.

[0049] For example, taking a binary capacitor array as an example, the capacitance sizes of each capacitor bit in the digital-to-analog conversion capacitor array 101 are: 8C, 4C, 2C, 1C. A capacitor bit in the calibration capacitor array 102 includes multiple capacitors, wherein the capacitance sizes of the multiple capacitors at the highest capacitance bit are 4C, 2C, C, and 0.5C. The capacitor at the highest capacitance bit can be combined with each capacitor bit of the digital-to-analog conversion capacitor array 101. After the combination, the capacitance sizes of each capacitor bit of the digital-to-analog conversion capacitor array 101 are: 12C (i.e., 8C+4C), 6C (i.e., 4C+2C), 3C (i.e., 2C+C), and 1.5C (i.e., 1C+0.5C). In this example, the capacitance ratio of each capacitor bit of the digital-to-analog conversion capacitor array 101 is the same before and after the combination.

[0050] In this example, during the conversion phase, if the capacitor corresponding to the highest capacitance position (capacitance of 8C) of the digital-to-analog conversion capacitor array 101 is connected to the reference voltage terminal, and the capacitor with a capacitance of 4C in the highest capacitance position in the calibration capacitor array 102 is connected to the reference voltage terminal, that is, during the conversion phase, the capacitance of the highest capacitance position increases from 8C to 12C; if the capacitor corresponding to the highest capacitance position (capacitance of 8C) of the digital-to-analog conversion capacitor array 101 is grounded, the capacitor with a capacitance of 4C in the highest capacitance position in the calibration capacitor array 102 is grounded. By analogy, if the capacitor corresponding to the second highest position (capacitance of 4C) of the digital-to-analog conversion capacitor array 101 is connected to the reference voltage terminal, and the capacitor with a capacitance of 2C in the highest capacitance position in the calibration capacitor array 102 is connected to the reference voltage terminal, that is, during the conversion stage, the capacitance of the second highest position increases from 4C to 6C; if the capacitor corresponding to the second highest position (capacitance of 4C) of the digital-to-analog conversion capacitor array 101 is grounded, the capacitor with a capacitance of 2C in the highest capacitance position in the calibration capacitor array 102 is grounded.

[0051] In some embodiments, the logic control module 103 may further control unselected capacitor bits in the calibration capacitor array 102 based on the calibration code. For example, the calibration capacitor array 102 includes four calibration capacitor bits, and the highest capacitor bit of the calibration capacitor array 102 is reused to scale the analog input signal. The remaining three calibration capacitor bits of the calibration capacitor array 102 may be used for calibration. For example, if the calibration code is 0010, the remaining three calibration capacitor bits of the calibration capacitor array 102 are controlled based on the last three digits "010" of the calibration code for calibration.

[0052] Referring to Figures 2a, 2b, 2c, and 2d, an example of scaling down an analog input signal is shown. The digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 each include five capacitor positions, each with a capacitance of 8C, 4C, 2C, 1C, and 1C, respectively. In this example, the analog input signal is amplified by reducing the sampling capacitance and increasing the conversion capacitance by reusing the calibration capacitor array 102.

[0053] During the sampling period, the logic control module 103 can select a capacitor position with a capacitance of 1C in the digital-to-analog conversion capacitor array 101 to sample the analog input signal. It should be understood that selecting a capacitor position with a capacitance of 1C is only an example. For example, capacitor positions with capacitances of 2C, 4C, or 8C can also be selected to sample the analog input signal. In this example, the sampling of the analog input signal using a capacitor position with a capacitance of 1C is described. As shown in Figure 2a, one end of the digital-to-analog conversion capacitor array 101 connected to the input end of the comparison unit 104 receives the common-mode voltage Vcm, and the capacitor position with a capacitance of 1C in the digital-to-analog conversion capacitor array 101 receives the analog input signal Vin, so as to sample the analog input signal Vin through this capacitor position, that is, the sampling capacitor has a capacitance of 1C. One end of the calibration capacitor array 102 connected to the input end of the comparison unit 104 can receive the common-mode voltage Vcm, and the other end can be grounded.

[0054] After the sampling is completed, the charge size Q of the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 21 Satisfy: Q 21 =(Vcm-Vin)*1C+(Vcm-0)*(8C+4C+2C+1C+8C+4C +2C+1C+1C)=32C*Vcm-Vin*1C (1)

[0055] Among them, Vin is the analog input voltage and Vcm is the common-mode voltage.

[0056] During the conversion period, the capacitor positions with a capacitance of 8C in the calibration capacitor array 102 can be allocated to the digital-to-analog conversion capacitor array 101. It should be understood that the allocation of the capacitor positions with a capacitance of 8C to the digital-to-analog conversion capacitor array 101 is merely an example. For example, the capacitor positions with a capacitance of 4C in the calibration capacitor array 102 can also be allocated to the digital-to-analog conversion capacitor array 101. As shown in FIG2b, the capacitor positions with a capacitance of 8C in the calibration capacitor array 102 are divided into the following categories according to the capacitance ratio of each capacitor position in the digital-to-analog conversion capacitor array 101: 4C, 2C, 1C, 0.5C, and 0.5C, and are respectively combined with each capacitor position in the digital-to-analog conversion capacitor array 101. As shown in FIG2c, the equivalent capacitance of each capacitor position in the digital-to-analog conversion capacitor array 102 after combination is 12C (i.e., 8C + 4C), 6C (i.e., 4C + 2C), 3C (i.e., 2C + 1C), 1.5C (i.e., 1C + 0.5C), and 1.5C (i.e., 1C + 0.5C).

[0057] During the conversion process, the logic control module 103 controls the combined capacitance bits for conversion, that is, controls the capacitance bits with a capacitance of 8C in the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102. In one embodiment, the remaining capacitance bits of the calibration capacitor array 201 can be controlled based on the calibration code. To facilitate the description of the process of scaling the analog input signal, the following description uses the example of the remaining capacitance bits of the calibration capacitor array 201 being grounded.

[0058] For example, the logic control module 103 may execute SAR logic, such as binary search.

[0059] In the binary search, as shown in FIG2c, the highest capacitance bit (capacitance of 12C) obtained by the combination is connected to the reference voltage terminal (reference voltage Vref), that is, the capacitor corresponding to the highest capacitance bit (capacitance of 8C) of the digital-to-analog conversion capacitor array 101 is connected to the reference voltage terminal, and the capacitor with a capacitance of 4C in the highest capacitance bit of the calibration capacitor array 102 is connected to the reference voltage terminal. At this time, the charge size Q of the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 is 22 Satisfy: Q 22 =(Vx-Vref)*12C+(Vx-0)*(6C+3C+1.5C+1.5C)+(Vx-0) *(4C+2C+1C+1C)=Vx*32C-Vref*12C (2)

[0060] Wherein, Vx is the voltage input from the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 to the comparison unit 104, and Vref is the reference voltage.

[0061] According to the law of charge conservation, Q 21 =Q 22 , therefore: Vx=Vcm-3 / 4*(1 / 24*Vin-1 / 2*Vref) (3)

[0062] In one embodiment, taking the highest capacitance bit as "1" as an example, as shown in FIG2d, the logic control module 103 connects the highest capacitance bit obtained by the combination to the reference voltage terminal. Perform a binary search, as shown in FIG2d, and connect the second highest bit obtained by the combination (capacitance size is 6C) to the reference voltage terminal, that is, connect the capacitor corresponding to the second highest capacitance bit (capacitance size is 4C) of the digital-to-analog conversion capacitor array 101 to the reference voltage terminal, and connect the capacitor with a capacitance of 2C in the highest capacitance bit of the calibration capacitor array 102 to the reference voltage terminal. At this time, the charge size Q of the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 is 23Satisfies: Q23=(Vx-Vref)*18C+(Vx-0)*(3C+1.5C+1.5C)+(Vx-0)*(4C+2C+1C+1C)=Vx*32C-Vref*18C (4)

[0063] According to the law of charge conservation, Q 21 =Q 23 , therefore: Vx=Vcm-3 / 4*(1 / 24*Vin-1 / 2*Vref-1 / 4*Vref) (5)

[0064] And so on, during the conversion:

[0065] Among them, D i is the code value of the i-th capacitance bit of the digital-to-analog conversion capacitor array 101 controlled by the logic control module 103 , the highest capacitance bit i is 3, the second highest capacitance bit i is 2, and so on.

[0066] It can be seen that in the examples shown in FIG. 2 a to FIG. 2 d , the analog input signal is reduced to 1 / 24 of the original value.

[0067] It should be understood that FIG2a to FIG2d are merely examples, and in the present embodiment, the scaling ratio can be adjusted by selecting the size of the capacitor for sampling and / or controlling the size of the capacitor for conversion.

[0068] In some embodiments, the logic control module 103 may, during the sampling period, select capacitors in the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 for sampling based on the range control signal to amplify the analog input signal according to the ratio corresponding to the range control signal; and during the conversion period, control the various capacitor bits of the digital-to-analog conversion capacitor array 101 to perform the conversion. In this embodiment, the larger the capacitor value being sampled, the greater the amplification factor of the analog input signal, and various sampling capacitor values ​​can correspond to various amplification factors. As an embodiment, the logic control module 103 may also control the calibration capacitor array 102 based on the calibration code to perform calibration.

[0069] As an example, when all capacitors in the digital-to-analog conversion capacitor array 101 sample and convert the analog input signal, it can be considered that the analog input signal is not amplified or reduced, that is, the gain is 1. If all capacitors in the digital-to-analog conversion capacitor array 101 sample the analog input signal, and capacitors in the calibration capacitor array 102 are selected to sample the analog input signal, the analog input signal can be amplified, that is, the gain is greater than 1. The amplification ratio is positively correlated with the size of the capacitors being sampled.

[0070] For example, referring to Figures 3a, 3b and 3c, the digital-to-analog conversion capacitor array 101 includes 5 capacitor positions, and the capacitance of each capacitor position is 8C, 4C, 2C, 1C, and 1C respectively. The calibration capacitor array 102 includes 5 capacitor positions, and the capacitance of each capacitor position is 8C, 4C, 2C, 1C, and 1C respectively.

[0071] During the sampling period, the logic control module 103 can select capacitors in the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 to sample the analog input signal Vin. For example, as shown in FIG3a , all capacitors in the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 are selected to sample the analog input signal Vin, that is, all capacitors receive the analog input signal Vin. At this time, the charge Q of the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 is 31 Satisfy: Q 31 =(Vcm-Vin)*(8C+4C+2C+1C+1C+8C+4C+2C+1C+1C) =(Vcm-Vin)*32C (7)

[0072] During the conversion process, the logic control module 103 can control the digital-to-analog conversion capacitor array 101 to perform the conversion. For example, the logic control module 103 can execute SAR logic, such as performing a binary search. In one embodiment, the logic control module 103 can control the calibration capacitor array 102 based on a calibration code during the conversion process. To facilitate illustration of scaling the analog input signal, the following description uses the example of grounding the calibration capacitor array 102 (i.e., not performing calibration).

[0073] In the binary search, as shown in FIG3b , the highest capacitance bit of the D / A conversion capacitor array 101 is connected to the reference voltage, and the remaining bits are grounded. The calibration capacitor array 102 is grounded (i.e., no calibration is performed). At this time, the charge Q of the D / A conversion capacitor array 101 and the calibration capacitor array 102 is 32 Satisfy: Q 32 =(Vx-Vref)*8C+(Vx-0)*(4C+2C+1C+1C+8C+4C+2C+1C+1C) =Vx*32C–Vref*8C (8)

[0074] Wherein, Vx is the voltage outputted from the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 to the comparison unit 504 .

[0075] According to the law of charge conservation, Q62 = Q61. From this, we can know that: Vx = Vcm – 1 / 2 (2*Vin - 1 / 2*Vref) (9)

[0076] In one embodiment, taking the highest capacitance bit as 1 as an example, referring to FIG3c , the highest capacitance bit and the second highest capacitance bit of the digital-to-analog conversion capacitor array 101 are connected to the reference voltage, and the remaining bits are grounded. The calibration capacitor array 102 is grounded (i.e., no calibration is performed). At this time, the charge Q of the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102 is 33 Satisfy: Q 33 =(Vx-Vref)*(8C+4C)+(Vx-0)*(2C+1C+1C+8C+4C+2C+1C+1C) =Vx*32C–Vref*12C (10)

[0077] According to the law of charge conservation, Q 33 =Q 31 From this we can know that: Vx=Vcm–1 / 2(2*Vin-1 / 2*Vref-1 / 4*Vref) (11)

[0078] And so on, during the conversion:

[0079] Among them, D i is the code value of the i-th capacitance bit of the digital-to-analog conversion capacitor array 101 controlled by the logic control module 103 , the highest capacitance bit i is 3, the second highest capacitance bit i is 2, and so on.

[0080] It can be seen that in the examples of FIG. 3 a to FIG. 3 c , the analog input signal is amplified by 2 times.

[0081] It should be understood that Figures 3a to 3c are merely exemplary. In this embodiment, by adjusting the size of the capacitors used to sample the analog input signal in the digital-to-analog conversion capacitor array 101 and the calibration capacitor array 102, the amplification factor of the analog input signal can be adjusted. For example, to achieve a smaller amplification factor, a portion of the capacitor positions in the calibration capacitor array 102 can be selected for sampling, while to achieve a larger amplification factor, more capacitor positions in the calibration capacitor array 102 can be selected for sampling.

[0082] FIG4 shows a schematic block diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application. As shown in FIG4 , the analog-to-digital conversion circuit 400 may include: a digital-to-analog conversion capacitor array 401, a calibration capacitor array 402, a logic control module 403, and a comparison unit 404. As shown in FIG4 , the digital-to-analog conversion capacitor array 401 has an output connected to the input of the comparison unit 404. The calibration capacitor array 402 has an output connected to the input of the comparison unit 404. The logic control module 403 may monitor the output of the comparison unit 404. In this embodiment, the analog input signal can be scaled by the digital-to-analog conversion capacitor array 401 and the calibration capacitor array 402, for example, to scale the analog input signal to within the dynamic range of the analog-to-digital conversion circuit.

[0083] For example, as shown in FIG4 , the digital-to-analog conversion capacitor array 401 may include a positive-end main capacitor array (abbreviated as MAIN CAP) MAIN_CAP_UP and a negative-end main capacitor array MAIN_CAP_DN. The positive-end main capacitor array MAIN_CAP_UP and the negative-end main capacitor array MAIN_CAP_DN each include N capacitor positions. For simplicity, only capacitor positions MAIN_CAP_UPn and MAIN_CAP_DNn are shown in FIG4 . The calibration capacitor array (abbreviated as CAL CAP) 402 may include a positive-end main capacitor array CAL_CAP_UP and a negative-end main capacitor array CAL_CAP_DN. The positive-end main capacitor array CAL_CAP_UP and the negative-end main capacitor array CAL_CAP_DN each include K capacitor positions. Only capacitor positions CAL_CAP_UP1, CAL_CAP_UPk, CAL_CAP_DN1, and CAL_CAP_DNk are shown in FIG4 .

[0084] For example, as shown in FIG4 , the switch network (shown as S in FIG4 ) 1P To S 9P 、S 1N To S 9N ) is used to switch the capacitance bit or capacitor to receive the reference voltage Vref, or the analog-to-digital input signal (Vinp, Vinn), or the ground Gnd.

[0085] As shown in FIG4 , when scaling down an analog input signal, logic control module 403 can, based on a range control signal, select capacitors in calibration capacitor array 402 and combine them with various capacitor bits in digital-to-analog conversion capacitor array 401 during conversion to adjust the capacitance of each capacitor bit in digital-to-analog conversion capacitor array 401, and control the combined capacitor bits for conversion. This allows the analog input signal to be scaled down using multiple calibration capacitor array 402, achieving a larger scaling ratio with a smaller circuit area.

[0086] When reducing the analog input signal, the logic control module 403 can also select the capacitors in the calibration capacitor array 402 and / or the digital-to-analog conversion capacitor array 401 to sample the analog input signal based on the range control signal during the sampling period. At this time, the reduction ratio of the analog input signal is determined by the size of the capacitor that samples the analog input signal and the size of the capacitance of each capacitor position after the combination. The smaller the capacitor that samples the analog input signal, the greater the reduction ratio, that is, the smaller the analog input signal is reduced. The greater the capacitance of each capacitor position after the combination, the greater the reduction ratio, that is, the smaller the analog input signal is reduced.

[0087] As an embodiment, when scaling down the analog input signal, the logic control module 403 may also control the capacitance bits in the calibration capacitor array 402 that are not combined with the digital-to-analog conversion capacitor array 401 based on the calibration code during the conversion period for calibration. For example, the calibration capacitor array 402 includes four calibration capacitance bits, and the highest capacitance bit of the calibration capacitor array 402 is reused to scale down the analog input signal. The remaining three calibration capacitance bits of the calibration capacitor array 402 can be used for calibration. The exemplary calibration code is 0010, and the remaining three calibration capacitance bits of the calibration capacitor array 402 are controlled based on the last three digits "010" of the calibration code for calibration.

[0088] As shown in FIG4 , when amplifying an analog input signal, logic control module 403 can select capacitors in digital-to-analog conversion capacitor array 401 and calibration capacitor array 402 for sampling based on a range control signal during the sampling period to amplify the analog input signal according to the ratio corresponding to the range control signal. During the conversion period, the logic control module 403 controls the individual capacitance bits of digital-to-analog conversion capacitor array 401 for conversion. This allows the calibration capacitor array 402 to be reused to amplify the analog input signal, achieving a higher amplification factor with a smaller circuit area.

[0089] As an implementation, when amplifying the analog input signal, the logic control module 403 may also control the calibration capacitor array 402 based on the calibration code during the conversion period to perform calibration.

[0090] 4 , when the analog input signal is not scaled, the logic control module 403 can connect the analog input signal to the digital-to-analog conversion capacitor array 401 during the sampling period to sample the analog input signal. During the conversion period, the digital-to-analog conversion capacitor array 401 is controlled according to the SAR logic to perform the conversion, and the calibration capacitor array 402 is controlled based on the calibration code. For example, the calibration capacitor array 402 includes four calibration capacitor bits, and the exemplary calibration code is 0010. Then, the third capacitor bit of the calibration capacitor array 402 receives the reference voltage Vref, and the remaining capacitor bits are grounded for calibration.

[0091] FIG5 shows a schematic block diagram of another analog-to-digital conversion circuit provided in an embodiment of the present application. As shown in FIG5 , the analog-to-digital conversion circuit 500 may include: a digital-to-analog conversion capacitor array 501, a calibration capacitor array 502, a logic control module 503, a comparison unit 504, and a resistive digital-to-analog converter (RDAC) 505. The digital-to-analog conversion capacitor array 501 and the RDAC 505 form a hybrid capacitor-resistor digital-to-analog converter. The logic control module 503 may monitor the output of the comparison unit 504.

[0092] For example, as shown in FIG5 , the digital-to-analog conversion capacitor array 501 may include a positive-end main capacitor array (abbreviated as MAIN CAP) MAIN_CAP_UP and a negative-end main capacitor array MAIN_CAP_DN. The positive-end main capacitor array MAIN_CAP_UP and the negative-end main capacitor array MAIN_CAP_DN each include X capacitor positions. For simplicity, only capacitor positions MAIN_CAP_UPx and MAIN_CAP_DNx are shown in FIG5 . The calibration capacitor array (abbreviated as CAL CAP) 502 may include a positive-end main capacitor array CAL_CAP_UP and a negative-end main capacitor array CAL_CAP_DN. The positive-end main capacitor array CAL_CAP_UP and the negative-end main capacitor array CAL_CAP_DN each include Y capacitor positions. Only capacitor positions CAL_CAP_UP1, CAL_CAP_UPy, CAL_CAP_DN1, and CAL_CAP_DNy are shown in FIG5 .

[0093] For example, as shown in FIG5 , the switch network (shown as S in FIG5 ) 1P To S 9P 、S 1N To S 9N ) is used to switch the capacitance bit or capacitor to receive the reference voltage Vref, or the analog-to-digital input signal (Vinp, Vinn), or the ground Gnd.

[0094] In this embodiment, the analog input signal can be scaled by the digital-to-analog conversion capacitor array 501 and the calibration capacitor array 502. For example, the analog input signal can be scaled to within the dynamic range of the analog-to-digital conversion circuit. The logic control module 503 controls the digital-to-analog conversion capacitor array 501 and the calibration capacitor array 502 to scale the analog input signal. For details, refer to the previous description of this specification and are not further elaborated here.

[0095] As shown in Figures 6a, 6b, 6c, and 6d, the main capacitor array and calibration capacitor array in Figures 4 and 5 can adopt a split capacitor structure. For example, as shown in Figures 6a to 6d, each capacitor position can be composed of two split capacitor positions. The following uses the reduction of analog-to-digital input signals as an example to illustrate this.

[0096] During the sampling period, as shown in Figure 6a, the portion of the main capacitor array with a capacitance of 1C is selected for sampling, that is, the capacitor receives the analog input signal Vinp, and the remaining capacitors are grounded. At this time, the charge Q in MAIN_CAP_UP and CAL_CAP_UP 61p Satisfy: Q 61p =(Vcm-Vinp)*1C+(Vcm-0)*(4C+4C+2C+2C+1C+ 1C+1C+4C+4C+2C+2C+1C+1C+1C+1C)=32C*Vcm-Vinp*1C (13)

[0097] During the conversion, as shown in Figure 6b, the capacitance bit CAL_CAP_UP1 in the calibration capacitor array is allocated to MAIN_CAP_UP in the main capacitor array, and the capacitance bit CAL_CAP_DN1 in the calibration capacitor array is allocated to MAIN_CAP_DN in the main capacitor array, with the allocation ratio shown in Figure 6b. The equivalent main capacitor array after allocation can be shown in Figures 6c and 6d.

[0098] Further referring to FIG6b, the highest capacitance bit of the combined main capacitor array is connected to Vref, and the rest are connected to Gnd, wherein the remaining capacitance bits of the calibration capacitor array CAL_CAP are fixedly connected to Gnd (for ease of explanation, the calibration code is not considered). At this time, the charge Q in MAIN_CAP_UP and CAL_CAP_UP is 62p Satisfy: Q 62p =(Vxp-Vref)*(6C+3C+1.5C+1.5C)+(Vxp-0)*(6C+ 3C+1.5C+1.5C)+(Vxp-0)*(2C+2C+1C+1C+1C+1C)=Vxp*32C-Vref*12C (14)

[0099] By Q 61p =Q 62p It can be seen that:

[0100] If the comparison result is too small, refer to Figure 6c, and keep the capacitor connected to Vref unchanged, and then connect the other half 4C with Vref. 63p Satisfy: Q 63p=(Vxp-Vref)*(6C+6C+3C+1.5C+1.5C)+(Vxp-0)* (3C+1.5C+1.5C)+(Vxp-0)*(2C+2C+1C+1C+1C+1C)=Vxp*32C-Vref*18C (16)

[0101] By Q 61p =Q 63p It can be seen that:

[0102] And so on:

[0103] Among them, D i is the code value of the i-th capacitance bit, the highest capacitance bit i is 3, the second highest capacitance bit i is 2, and so on.

[0104] Therefore, by reusing the highest capacitance of the calibration capacitor array during the conversion process, the analog input signal Vinp is scaled down to 1 / 24, allowing for normal conversion. When considering the calibration capacitor array with a calibration offset code value during the conversion process, the derivation process is the same as above, except that the final successive approximation result is not proportional to the multiple because the calibration offset code value is offset.

[0105] Embodiments of the present application also provide an analog-to-digital conversion method, which can be implemented using the analog-to-digital conversion circuit described above. The method includes: selecting a digital-to-analog conversion capacitor array and a calibration capacitor array based on a range control signal to sample and / or convert an analog input signal, thereby reducing or amplifying the analog input signal according to a ratio corresponding to the range control signal.

[0106] In an embodiment of the present application, the smaller the capacitor for sampling the analog input signal, the greater the reduction ratio; the larger the capacitor for sampling the analog input signal, the greater the amplification ratio; the larger the capacitor for conversion, the greater the reduction ratio. In some examples, the sampling capacitor size can be increased by multiplexing the calibration capacitor array to amplify the analog input signal. In some examples, the conversion capacitor size can be increased by multiplexing the calibration capacitor array to reduce the analog input signal. In some examples, the analog input signal can be reduced by reducing the sampling capacitor size and increasing the conversion capacitor size by multiplexing the calibration capacitor array to increase the reduction ratio of the analog input signal, that is, to reduce the analog input signal to a smaller size. In addition, multiple combinations of sampling capacitor size and conversion capacitor size can provide a variety of reduction or amplification ratios, and more combinations can be achieved by multiplexing the calibration capacitor array to provide more reduction or amplification ratios.

[0107] In some implementations, as shown in FIG7 , the analog-to-digital conversion method includes steps S701 and S702 .

[0108] Step S701 : During a sampling period, capacitors in a calibration capacitor array and / or a digital-to-analog conversion capacitor array are selected based on a range control signal to sample an analog input signal.

[0109] As an example, during a sampling period, one or more capacitors in a digital-to-analog conversion capacitor array can be selected based on a range control signal to sample an analog input signal. The smaller the capacitance of the selected capacitor, the greater the reduction ratio. That is, the smaller the sampled capacitance, the smaller the analog-to-digital input signal. In this example, during a conversion period, the calibration capacitor array can be controlled based on a calibration code to perform calibration.

[0110] As another example, during sampling, one or more capacitors in a calibration capacitor array can be selected based on a range control signal to sample the analog input signal, wherein the smaller the capacitance of the selected capacitor, the greater the scale-down ratio, that is, the smaller the sampled capacitance, the smaller the analog-to-digital input signal. In this example, during conversion, the calibration capacitor array can be controlled based on a calibration code to perform calibration.

[0111] As another example, during sampling, one or more capacitors of the digital-to-analog conversion capacitor array 101 and one or more capacitors in the calibration capacitor array can be selected based on the range control signal to sample the analog input signal, wherein the smaller the capacitance of the selected capacitor, the greater the reduction ratio, that is, the smaller the sampled capacitance size, the smaller the analog-to-digital input signal is reduced. In this example, during conversion, the calibration capacitor array can be controlled based on the calibration code to perform calibration.

[0112] Step S702 , during the conversion period, selecting capacitors in the calibration capacitor array and various capacitance bits of the digital-to-analog conversion capacitor array based on the range control signal to increase the capacitance of each capacitance bit of the digital-to-analog conversion capacitor array; and controlling each of the combined capacitance bits for conversion.

[0113] In one embodiment, in step S702, based on the range control signal, a capacitor of at least one capacitance position in the calibration capacitance array is selected and combined with each capacitance position of the first capacitance array. In one embodiment, the capacitance ratio of each capacitance position after the combination is the same as the capacitance ratio of each capacitance position before the combination.

[0114] As an implementation manner, unselected capacitor bits in the calibration capacitor array may be controlled based on the calibration code to perform calibration.

[0115] In some embodiments, as shown in FIG8 , the method includes steps S801 and S802 .

[0116] Step S801 : During a sampling period, capacitors in the digital-to-analog conversion capacitor array and the calibration capacitor array are selected for sampling based on a range control signal to scale the analog input signal according to a ratio corresponding to the range control signal.

[0117] Step S802 , during the conversion period, controlling each capacitor bit of the digital-to-analog conversion capacitor array to perform conversion.

[0118] As an implementation, the calibration capacitor array may also be controlled based on a calibration code.

[0119] The present application also provides a chip including the aforementioned analog-to-digital conversion circuit. A chip, also known as an integrated circuit (IC), may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. This chip can achieve scaling of a wide range of analog input signals with a relatively small circuit area.

[0120] An embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device can achieve a large range of scaling of analog input signals with a smaller circuit area.

[0121] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that, Comprising: A digital-to-analog conversion capacitor array; A calibration capacitor array for calibrating the digital-to-analog conversion capacitor array; A logic control module for selecting the digital-to-analog conversion capacitor array and the calibration capacitor array based on a range control signal to sample and / or convert an analog input signal, so as to reduce or amplify the analog input signal according to the ratio corresponding to the range control signal.

2. The analog-to-digital conversion circuit according to claim 1, wherein The logic control module is configured to: During conversion, Based on the range control signal, select the capacitors in the calibration capacitor array to be combined with each capacitance bit of the digital-to-analog conversion capacitor array to increase the capacitance of each capacitance bit of the digital-to-analog conversion capacitor array; Control each combined capacitance bit to perform conversion.

3. The analog-to-digital conversion circuit according to claim 2, wherein The logic control module is configured to: Based on the range control signal, select the capacitors of at least one capacitance bit in the calibration capacitor array and combine them with each capacitance bit of the first capacitor array.

4. The analog-to-digital conversion circuit according to claim 3, wherein The logic control module is further configured to: Control the unselected capacitance bits in the calibration capacitor array based on a calibration code.

5. The analog-to-digital conversion circuit according to claim 2, wherein The logic control module is further configured to: During sampling, based on the range control signal, select the capacitors in the calibration capacitor array and / or the digital-to-analog conversion capacitor array to sample the analog input signal.

6. The analog-to-digital conversion circuit according to claim 2, wherein, The logic control module is further configured to: During conversion, If the capacitor corresponding to the capacitance bit of the digital-to-analog conversion capacitor array is connected to the reference voltage terminal, connect the capacitor combined with it in the calibration capacitor array to the reference voltage terminal; If the capacitor corresponding to the capacitance bit of the digital-to-analog conversion capacitor array is grounded, ground the capacitor combined with it in the calibration capacitor array.

7. The analog-to-digital conversion circuit according to claim 2, wherein, The capacitance ratio of each combined capacitance bit is the same as the capacitance ratio of each capacitance bit before combination.

8. The analog-to-digital conversion circuit according to claim 1, characterized in that The logic control module is further configured to: During sampling, based on the range control signal, select the capacitors in the digital-to-analog conversion capacitor array and the calibration capacitor array to perform sampling to amplify the analog input signal according to the ratio corresponding to the range control signal; During conversion, control each capacitance bit of the digital-to-analog conversion capacitor array to perform conversion.

9. The analog-to-digital conversion circuit according to any one of claims 1 to 8, characterized in that The logic control module is further configured to: Control the calibration capacitor array based on a calibration code.

10. A chip, characterized in that, Comprising the analog-to-digital conversion circuit according to any one of claims 1 to 9 above.

11. An electronic device, characterized in that, Comprising a device main body and a chip as described in claim 10 above provided on the device main body.

12. An analog-to-digital conversion method, characterized in that, Comprising: Based on a range control signal, select a digital-to-analog conversion capacitor array and a calibration capacitor array to sample and / or convert an analog input signal, so as to reduce or amplify the analog input signal according to the ratio corresponding to the range control signal; Wherein, the calibration capacitor array is used to calibrate the digital-to-analog conversion capacitor array.

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