Display substrate and fabrication method therefor, and display apparatus

Abstract

A display substrate and a fabrication method therefor, and a display apparatus. The display substrate comprises partition structures (10) disposed on a substrate; an anode disposed on the substrate, wherein the orthographic projections of the anode and the partition structures (10) do not overlap on the substrate; a light-emitting layer (7) disposed on the side of the anode away from the substrate, the light-emitting layer (7) being connected to the anode and being interrupted at the partition structures (10); a cathode (3) disposed on the side of the light-emitting layer (7) away from the substrate, the cathode (3) being connected to the light-emitting layer (7) and being interrupted at the partition structures (10); and an auxiliary cathode (20) located on the same film layer as the anode and insulated from the anode, the auxiliary cathode (20) being electrically connected to the cathode (3).

Description

Display substrate, manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 5, 2024, with application number 202410021683.2 and invention name “A display substrate, its preparation method, and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The present application provides a display substrate, characterized by comprising:

[0005] A partition structure is provided on the base;

[0006] an anode, disposed on the substrate, wherein the anode and the orthographic projection of the partition structure on the substrate do not overlap;

[0007] a light-emitting layer, disposed on a side of the anode away from the substrate, the light-emitting layer being connected to the anode and blocked at the partition structure;

[0008] a cathode, disposed on a side of the light-emitting layer away from the substrate, the cathode being connected to the light-emitting layer and being blocked at the partition structure;

[0009] The auxiliary cathode and the anode are located in the same film layer and are insulated from each other. The auxiliary cathode is electrically connected to the cathode.

[0010] In an exemplary embodiment, a connection via is further provided between the auxiliary cathode and the cathode, the cathode is connected to the auxiliary cathode through the connection via, and the connection via does not overlap with the orthographic projections of the anode and the partition structure on the substrate.

[0011] In an exemplary embodiment, a connection avoidance hole is provided in the light emitting layer, and an orthographic projection of the connection avoidance hole on the substrate covers an orthographic projection of the connection via hole on the substrate.

[0012] In an exemplary embodiment, the auxiliary cathode and the anode include the same conductive material.

[0013] In an exemplary embodiment, the auxiliary cathode has a grid shape.

[0014] In an exemplary embodiment, a bump is provided on the auxiliary cathode, the bump protruding from an edge of the auxiliary cathode, and the bump is electrically connected to the cathode.

[0015] In an exemplary embodiment, an orthographic projection of the auxiliary cathode on the substrate is located within an orthographic projection of the cathode on the substrate.

[0016] In an exemplary embodiment, the partition structure includes a first isolation wall arranged on the substrate, the first isolation wall includes a first isolation layer and a second isolation layer arranged on a side of the first isolation layer away from the substrate, at least a portion of the second isolation layer extends out of the side wall of the first isolation layer in a direction parallel to the substrate to form a boss, and the light-emitting layer and the cathode are blocked at the boss.

[0017] In an exemplary embodiment, the partition structure also includes a second isolation wall, an isolation groove is formed between the second isolation wall and the first isolation wall, the second isolation wall includes a third isolation layer and a fourth isolation layer arranged on the side of the third isolation layer away from the substrate, at least a portion of the stacked structure formed by the light-emitting layer and the cathode covers the side walls of the third isolation layer and the fourth isolation layer, and at least a portion of the stacked structure formed by the light-emitting layer and the cathode covers the bottom of the isolation groove.

[0018] In an exemplary embodiment, an organic dielectric layer and an inorganic dielectric layer are further included, wherein the organic dielectric layer is disposed on the substrate, the inorganic dielectric layer is disposed on a side of the organic dielectric layer away from the substrate, the anode is disposed on a side of the inorganic dielectric layer away from the substrate, the first isolation layer is integrally connected to the adjacent organic dielectric layer, the third isolation layer is integrally connected to the adjacent organic dielectric layer, the second isolation layer is integrally connected to the adjacent inorganic dielectric layer, the fourth isolation layer is integrally connected to the adjacent inorganic dielectric layer, and the bottom of the isolation trench is the organic dielectric layer.

[0019] In an exemplary embodiment, a first sub-pixel region, a second sub-pixel region and a third sub-pixel region are included, the first sub-pixel region includes a first anode, a light-emitting layer and a cathode, the second sub-pixel region includes a second anode, a light-emitting layer and a cathode, the third sub-pixel region includes a third anode, a light-emitting layer and a cathode, the first sub-pixel region and the second sub-pixel region are arranged along a second direction to form a sub-pixel column, the third sub-pixel region is located on one side of the sub-pixel column in the first direction, the partition structure is provided on at least one side of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, and the first direction intersects with the second direction.

[0020] In an exemplary embodiment, the auxiliary cathode is disposed around 4 sides of the first sub-pixel region, around 4 sides of the second sub-pixel region, and around 4 sides of the third sub-pixel region.

[0021] In an exemplary embodiment, a connecting via is further included between the auxiliary cathode and the cathode, the cathode is connected to the auxiliary cathode through the connecting via, the connecting vias do not overlap with the orthographic projections of the anode and the partition structure on the substrate, and the connecting vias are located on at least one side of the third sub-pixel area in the second direction.

[0022] In an exemplary embodiment, a first partition structure, a second partition structure, a third partition structure, a fourth partition structure, a fifth partition structure and a sixth partition structure are included, wherein the shape of the first partition structure includes a line extending along the first direction, and the first partition structure is arranged between the first sub-pixel region and the second sub-pixel region; the shape of the second partition structure includes a line extending along the second direction, and the second partition structure is arranged on a side of the first sub-pixel region away from the third sub-pixel region; the shape of the third partition structure includes a line extending along the first direction, and the third partition structure is arranged on a side of the second sub-pixel region away from the first sub-pixel region; the shape of the fourth partition structure includes a line extending along the second direction, and the fourth partition structure is arranged on a side of the second sub-pixel region away from the third sub-pixel region; the shape of the fifth partition structure includes a line extending along the second direction, and the fifth partition structure is arranged between the third sub-pixel region and the first sub-pixel region; the shape of the sixth partition structure includes a line extending along the second direction, and the sixth partition structure is arranged between the third sub-pixel region and the second sub-pixel region.

[0023] In an exemplary embodiment, a pixel definition layer is further included, wherein the pixel definition layer is arranged on the side of the anode away from the substrate, the pixel definition layer is provided with a pixel opening, the pixel opening exposes at least a portion of the anode, the light-emitting layer covers the pixel opening and is connected to the anode, the pixel definition layer is further provided with a connecting via, the cathode is connected to the auxiliary cathode through the connecting via, and the connecting vias do not overlap with the positive projections of the anode and the partition structure on the substrate.

[0024] In an exemplary embodiment, the pixel definition layer is further provided with a partition avoidance hole, and the partition avoidance hole overlaps with an orthographic projection of the partition structure on the substrate.

[0025] The present application also provides a display device, comprising the aforementioned display substrate.

[0026] The present application also provides a method for preparing a display substrate, comprising:

[0027] forming a partition structure on a substrate;

[0028] forming a conductive film on the substrate so that the conductive film forms an anode and an auxiliary cathode that are insulated from each other, wherein the orthographic projections of the anode and the partition structure on the substrate do not overlap, and the orthographic projections of the auxiliary cathode and the partition structure on the substrate do not overlap;

[0029] forming a light-emitting layer on a side of the anode away from the substrate, the light-emitting layer being connected to the anode and blocked at the partition structure;

[0030] A cathode is formed on a side of the light-emitting layer away from the substrate, the cathode is connected to the light-emitting layer, the cathode is blocked at the partition structure, and the cathode is electrically connected to the auxiliary cathode.

[0031] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0032] Summary of the Figures

[0033] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0034] FIG1 is a schematic structural diagram of a display device;

[0035] FIG2 is a schematic diagram of a planar structure of a display area in a display device;

[0036] FIG3 is a schematic diagram of a cross-sectional structure of a display area in a display device;

[0037] FIG4 a is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure;

[0038] FIG4 b is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0039] FIG5 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0040] FIG6 is a schematic diagram of a display substrate after an inorganic dielectric layer and a partition structure are formed according to an embodiment of the present disclosure;

[0041] 7a and 7b are schematic diagrams showing a display substrate after forming a first anode, a second anode, a third anode and an auxiliary cathode according to an embodiment of the present disclosure;

[0042] 8a and 8b are schematic diagrams of a display substrate after forming a pixel definition layer according to an embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram showing a display substrate after a cathode is formed according to an embodiment of the present disclosure.

[0044] Details

[0045] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0046] This application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0047] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0048] Research by the inventors of this application has revealed that a tandem OLED display substrate is a stacked device formed by connecting multiple stacked light-emitting layers together via a connecting layer. This connecting layer generally includes p-type semiconductor material and n-type semiconductor material. The cathode of the tandem OLED display substrate injects electrons, and the anode injects holes. After the electrons and holes are separated by the connecting layer, they can power the light-emitting layer to achieve light emission. In different images, the luminance of the R sub-pixels, G sub-pixels, and B sub-pixels is different, resulting in different currents for illuminating the R sub-pixels, G sub-pixels, and B sub-pixels. Because the tandem OLED display substrate requires a larger cross-voltage drive, when illuminating a sub-pixel with a large current, the current flows to the adjacent sub-pixels, causing the sub-pixels with a small current to be illuminated, causing the sub-pixels at low grayscale to be illuminated, thereby affecting the image quality. The high-brightness tandem OLED display substrate requires a larger cross-voltage, and the larger cross-voltage makes the problem of illuminating low-grayscale sub-pixels more serious. To address the issue of low-grayscale sub-pixels turning on in tandem OLED display substrates, a partition structure can be installed between adjacent sub-pixels in the tandem OLED display substrate. This partition structure isolates the cathodes of adjacent sub-pixels, reducing current crosstalk between them. However, this partition structure increases the cathode sheet resistance, reduces power supply voltage drop and brightness uniformity, and reduces the uniformity of the displayed image.

[0049] The present disclosure provides a display substrate, comprising:

[0050] A partition structure is provided on the base;

[0051] an anode, disposed on the substrate, wherein the anode and the orthographic projection of the partition structure on the substrate do not overlap;

[0052] a light-emitting layer, disposed on a side of the anode away from the substrate, the light-emitting layer being connected to the anode and blocked at the partition structure;

[0053] a cathode, disposed on a side of the light-emitting layer away from the substrate, the cathode being connected to the light-emitting layer and being blocked at the partition structure;

[0054] The auxiliary cathode and the anode are located in the same film layer and are insulated from each other. The auxiliary cathode is electrically connected to the cathode.

[0055] The technical solutions of the embodiments of the present invention are described in detail below through specific examples.

[0056] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij.

[0057] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, and may provide clock signals, scan start signals, and other signals suitable for the specifications of the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of sub-pixel rows, where n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signal, and other signals from the timing controller. For example, the scan signal driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register and can generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of a clock signal, and m can be a natural number. The sub-pixel array may include a plurality of pixel sub-PXij. Each pixel sub-PXij can be connected to a corresponding data signal line and a corresponding scan signal line, and i and j can be natural numbers. The sub-pixel PXij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0058] FIG2 is a schematic diagram of the planar structure of a display area in a display device. As shown in FIG2 , the display area may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the subpixels are respectively connected to scan signal lines and data signal lines. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the display light-emitting devices. The display light-emitting devices in the subpixels are respectively connected to the pixel driving circuits of the subpixels in which they are located. The display light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the subpixels in which they are located.

[0059] In an exemplary embodiment, the first subpixel P1 may be a red subpixel emitting red (R) light, the second subpixel P2 may be a blue subpixel emitting blue (B) light, and the third subpixel P3 may be a green subpixel emitting green (G) light. In an exemplary embodiment, the subpixels may be shaped in any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, or other polygonal shape, and may be arranged in horizontal or vertical parallel arrangement, in an X-shape, a cross, a herringbone shape, a square, a diamond, or a delta shape, etc., which is not limited in this disclosure.

[0060] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited in the present disclosure.

[0061] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , the display device may include: a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the substrate 101. In some possible implementations, the display device may include other film layers, which are not limited in this disclosure.

[0062] In an exemplary embodiment, the substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the substrate 101 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 102 may include a plurality of circuit units. The circuit units may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. The transistor may include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (e.g., traces, etc.) through the connection electrodes.

[0063] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second electrode D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the cathode voltage line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0064] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The cover layer 107 can be made of glass or a flexible plastic colorless polyimide.

[0065] In an exemplary embodiment, the color film structure layer 105 may include a black matrix (BM) and a color filter (CF). The position of the color filter may correspond to the position of the light-emitting device, the black matrix may be located between adjacent color filters, and the color filter is configured to filter the white light emitted by the light-emitting device into red (R) light, green (G) light, and blue (B) light to form red sub-pixels, green sub-pixels, and blue sub-pixels.

[0066] Figure 4a is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure, illustrating the structure of a pixel unit. In an exemplary embodiment, as shown in Figure 4a, the display substrate may include a first sub-pixel region 100, a second sub-pixel region 200, a third sub-pixel region 300, and a non-sub-pixel region 100 in a direction parallel to the display substrate. The first sub-pixel region 100 includes a first sub-pixel disposed on a substrate to emit a first color light, the first sub-pixel including a first anode, a light-emitting layer disposed on a side of the first anode away from the substrate, and a cathode disposed on a side of the light-emitting layer farthest from the substrate; the second sub-pixel region 200 includes a second sub-pixel disposed on a substrate to emit a second color light, the second sub-pixel including a second anode, a light-emitting layer disposed on a side of the second anode away from the substrate, and a cathode disposed on a side of the light-emitting layer farthest from the substrate; the third sub-pixel region 300 includes a third sub-pixel disposed on a substrate to emit a third color light, the third sub-pixel including a third anode, a light-emitting layer disposed on a side of the second anode away from the substrate, and a cathode disposed on a side of the light-emitting layer farthest from the substrate. The non-sub-pixel region 100 is a non-luminous region of the display substrate. The non-sub-pixel region 100 may be located around the first sub-pixel region 100 , around the second sub-pixel region 200 , and around the third sub-pixel region 300 .

[0067] In an exemplary embodiment, the first sub-pixel region 100 , the second sub-pixel region 200 , and the third sub-pixel region 300 may share one cathode 3 and light-emitting layer, that is, the cathode 3 and the light-emitting layer may be a common layer connected together.

[0068] In an exemplary embodiment, the first sub-pixel region 100, the second sub-pixel region 200, and the third sub-pixel region 300 are all rectangular in shape. The first sub-pixel region 100 and the second sub-pixel region 200 may be arranged alternately along the second direction D2 to form a sub-pixel row. The third sub-pixel region 300 is located on one side of the sub-pixel row in the first direction D1. The first sub-pixel region 100, the second sub-pixel region 200, and the third sub-pixel region 300 are arranged in a herringbone shape. The first direction D1 and the second direction D2 are both parallel to the plane of the display substrate, intersecting each other. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0069] In an exemplary embodiment, the display substrate may further include a partition structure 10 disposed on the base. The partition structure 10 is located in the non-sub-pixel region 400 and is disposed on at least one side of the first sub-pixel region 100, the second sub-pixel region 200, and the third sub-pixel region 300. The partition structure 10 is used to isolate the light-emitting layer and the cathode 3 of adjacent sub-pixel regions, thereby preventing current crosstalk between adjacent sub-pixel regions and resolving the issue of sub-pixels with low grayscale being illuminated.

[0070] In example embodiments, the display substrate may include a first partition structure 11 , a second partition structure 12 , a third partition structure 13 , a fourth partition structure 14 , a fifth partition structure 15 , and a sixth partition structure 16 .

[0071] In an exemplary embodiment, the first partition structure 11 is linear and extends along a first direction D1. The first partition structure 11 is located in the non-subpixel region 400. The first partition structure 11 is disposed on one side of the first subpixel region 100 in the second direction D2, and is disposed between the first subpixel region 100 and the second subpixel region 200. The light-emitting layer and the cathode 3 can be blocked at the first partition structure 11 to prevent current crosstalk between the subpixels in the first subpixel region 100 and the subpixels in the second subpixel region 200.

[0072] In an exemplary embodiment, the second partition structure 12 is linear and extends along the second direction D2. The second partition structure 12 is located in the non-sub-pixel region 400. The second partition structure 12 is disposed on a side of the first sub-pixel region 100 opposite the first direction D1, and on a side of the first sub-pixel region 100 away from the third sub-pixel region 300. The light-emitting layer and the cathode 3 can be blocked at the second partition structure 12 to prevent current crosstalk between the sub-pixels in the first sub-pixel region 100 and the sub-pixels in adjacent pixel units.

[0073] In an exemplary embodiment, the third partition structure 13 is linear and extends along the first direction D1. The third partition structure 13 is located in the non-sub-pixel region 400. The third partition structure 13 is disposed on one side of the second sub-pixel region 200 in the second direction D2, and on a side of the second sub-pixel region 200 away from the first sub-pixel region 100. The light-emitting layer and the cathode 3 can be blocked at the third partition structure 13 to prevent current crosstalk between the sub-pixels in the second sub-pixel region 200 and the sub-pixels in adjacent pixel units.

[0074] In an exemplary embodiment, the fourth partition structure 14 is linear and extends along the second direction D2. The fourth partition structure 14 is located in the non-subpixel region 400. The fourth partition structure 14 is disposed on a side of the second subpixel region 200 opposite to the first direction D1, and on a side of the second subpixel region 200 away from the third subpixel region 300. The light-emitting layer and the cathode 3 can be blocked at the fourth partition structure 14 to prevent current crosstalk between the subpixels in the second subpixel region 200 and the subpixels in adjacent pixel units.

[0075] In an exemplary embodiment, the fifth partition structure 15 is linear and extends along the second direction D2. The fifth partition structure 15 is located in the non-subpixel region 400. The fifth partition structure 15 is disposed on a side of the third subpixel region 300 opposite to the first direction D1, and is disposed between the third subpixel region 300 and the first subpixel region 100. The light-emitting layer and the cathode 3 can be blocked at the fifth partition structure 15 to prevent current crosstalk between the subpixels in the third subpixel region 300 and the subpixels in the first subpixel region 100.

[0076] In an exemplary embodiment, the sixth partition structure 16 is linear and extends along the second direction D2. The sixth partition structure 16 is located in the non-subpixel region 400. The sixth partition structure 16 is disposed on a side of the third subpixel region 300 opposite to the first direction D1, and is disposed between the third subpixel region 300 and the second subpixel region 200. The light-emitting layer and the cathode 3 can be blocked at the sixth partition structure 16 to prevent current crosstalk between the subpixels in the third subpixel region 300 and the subpixels in the second subpixel region 200.

[0077] In an exemplary embodiment, the display substrate may further include an auxiliary cathode 20 disposed on the substrate. The auxiliary cathode 20 is located in the non-sub-pixel area 400 and does not overlap with the orthographic projections of the first sub-pixel area 100, the second sub-pixel area 200, and the third sub-pixel area 300 on the substrate. The auxiliary cathode 20 may be located in the same film layer as the anode of the sub-pixel, the auxiliary cathode 20 may not overlap with the orthographic projection of the anode on the substrate, and the auxiliary cathode 20 and the anode are insulated from each other. The auxiliary cathode 20 may overlap with the orthographic projection of the cathode 3 on the substrate. For example, the orthographic projection of the auxiliary cathode 20 on the substrate is located within the orthographic projection of the cathode 3 on the substrate. The auxiliary cathode 20 may be electrically connected to the cathode 3.

[0078] The display substrate of the embodiment of the present disclosure is electrically connected to the cathode 3 via the auxiliary cathode 20 , which reduces the resistance of the cathode 3 , increases the power supply voltage drop, and improves the brightness uniformity and the uniformity of the display image.

[0079] In an exemplary embodiment, the auxiliary cathode 20 can be made of the same conductive material and the same manufacturing process as the anode of the light emitting device, thereby simplifying the manufacturing process and reducing production costs.

[0080] In an exemplary embodiment, the auxiliary cathode 20 and the partition structure 10 do not overlap in their orthographic projections on the substrate, thereby preventing the auxiliary cathode 20 from being blocked at the partition structure 10 and reducing the resistance reduction of the cathode 3 by the auxiliary cathode 20, resulting in a larger resistance of the cathode 3.

[0081] In an exemplary embodiment, the auxiliary cathode 20 has a grid shape and may be disposed around the first sub-pixel region 100 , around the second sub-pixel region 200 , and around the third sub-pixel region 300 .

[0082] In an exemplary embodiment, the display substrate may further include a connection via 30 disposed between the auxiliary cathode 20 and the cathode 3. The connection vias 30 do not overlap with the orthographic projections of the anode and the partition structure 10 on the substrate. The connection via 30 may be located in the non-sub-pixel region 400. The connection via 30 exposes at least a portion of the auxiliary cathode 20. At least a portion of the cathode 3 is connected to the auxiliary cathode 20 through the connection via 30.

[0083] In an exemplary embodiment, the connecting vias 30 overlap with the orthographic projections of the cathode 3 and the auxiliary cathode 20 on the substrate. For example, the orthographic projections of the connecting vias 30 on the substrate are located in the orthographic projections of the cathode 3 and the auxiliary cathode 20 on the substrate.

[0084] In an exemplary embodiment, a shape of an orthographic projection of the connection via 30 on the substrate may include at least one of a circle, an ellipse, a diamond, a rectangle, a pentagon, a hexagon, a heptagon, and an octagon.

[0085] In an exemplary embodiment, the display substrate may further include a first connection via 31 and a second connection via 32. Both the first connection via 31 and the second connection via 32 are disposed on a side of the auxiliary cathode 20 away from the substrate, and both the first connection via 31 and the second connection via 32 expose the auxiliary cathode 20. The first connection via 31 is disposed on a side of the third sub-pixel region 300 opposite the second direction D2. A first bump 211 is disposed on the auxiliary cathode 20. The first bump 211 protrudes from the edge of the auxiliary cathode 20 in the second direction D2, and the first bump 211 protrudes toward the third sub-pixel region 300. The first connection via 31 overlaps with an orthographic projection of the first bump 211 on the substrate. The first connection via 31 exposes at least a portion of the first bump 211, and at least a portion of the cathode 3 is connected to the first bump 211 through the first connection via 31. The second connection via 32 is disposed on a side of the third sub-pixel region 300 in the second direction D2. A second bump 231 is provided on the auxiliary cathode 20. The second bump 231 protrudes from the edge of the auxiliary cathode 20 in the second direction D2 and protrudes toward the third sub-pixel region 300. A second connection via 32 overlaps with the orthographic projection of the second bump 231 on the substrate. The second connection via 32 exposes at least a portion of the second bump 231. At least a portion of the cathode 3 is connected to the second bump 231 through the second connection via 32.

[0086] In an exemplary embodiment, a connection avoidance hole 70 is provided in the light-emitting layer, and the orthographic projection of the connection avoidance hole 70 on the substrate covers the orthographic projection of the connection via 30 on the substrate. When the cathode 3 is connected to the auxiliary cathode 20 through the connection via 30, the light-emitting layer located between the cathode 3 and the auxiliary cathode 20 is separated from the cathode 3 by the connection avoidance hole 70, and the light-emitting layer is insulated from the cathode 3 in the connection via 30 by the insulating material in the connection avoidance hole 70.

[0087] Figure 4b is a schematic diagram of the cross-sectional structure of a display substrate according to an embodiment of the present disclosure, illustrating a cross-sectional view taken along the BB' line in Figure 4a. In an exemplary embodiment, as shown in Figure 4b, the display substrate may include, in a direction perpendicular to the display substrate, a substrate 101, an auxiliary cathode 20 disposed on the substrate 101, a pixel definition layer 6 disposed on a side of the auxiliary cathode 20 away from the substrate 101, a light-emitting layer 7 disposed on a side of the pixel definition layer 6 away from the substrate 101, and a cathode 3 disposed on a side of the light-emitting layer 7 away from the substrate 101.

[0088] In an exemplary embodiment, a connection via 30 is provided in the pixel definition layer 6 . The connection via 30 extends in a direction perpendicular to the substrate 101 . The connection via 30 penetrates the pixel definition layer 6 and exposes at least a portion of the auxiliary cathode 20 .

[0089] In an exemplary embodiment, a connection avoidance hole 70 is provided in the light emitting layer 7 , the connection avoidance hole 70 is connected to the connection via 30 , and the orthographic projection of the connection avoidance hole 70 on the substrate covers the orthographic projection of the connection via 30 on the substrate.

[0090] In an exemplary embodiment, at least a portion of cathode 3 fills connection avoidance hole 70 and connection via 30, covering side walls of connection avoidance hole 70 and connection via 30 and a bottom wall of connection via 30. Cathode 3 is connected to auxiliary cathode 20 through connection avoidance hole 70 and connection via 30.

[0091] FIG5 is a schematic diagram of the cross-sectional structure of a display substrate according to an embodiment of the present disclosure, illustrating a cross-sectional view taken along the A-A' direction in FIG4a. In an exemplary embodiment, as shown in FIG5, the display substrate may include, in a direction perpendicular to the display substrate, a substrate 101, a first connection electrode 1-1 and a second connection electrode 1-2 disposed on the substrate 101, an organic dielectric layer 2 disposed on a side of the first connection electrode 1-1 and the second connection electrode 1-2 away from the substrate 101, an inorganic dielectric layer 4 disposed on a side of the organic dielectric layer 2 away from the substrate 101, a first anode 5-1 and a second anode 5-2 disposed on a side of the inorganic dielectric layer 4 away from the substrate 101, a pixel definition layer 6 disposed on a side of the first anode 5-1 and the second anode 5-2 away from the substrate 101, a light-emitting layer 7 disposed on a side of the pixel definition layer 6 away from the substrate 101, and a cathode 3 disposed on a side of the light-emitting layer 7 away from the substrate 101. The first anode 5-1 and the second anode 5-2 are both electrically connected to the light-emitting layer 7, and the cathode 3 is electrically connected to the light-emitting layer 7. The light-emitting layer 7 emits light when driven by the first anode 5-1 and the cathode 3, and / or emits light when driven by the second anode 5-2 and the cathode 3. The first anode 5-1, the light-emitting layer 7, and the cathode 3 form a light-emitting device of the first sub-pixel, and the second anode 5-2, the light-emitting layer 7, and the cathode 3 form a light-emitting device of the second sub-pixel. The light-emitting layer 7 and the cathode 3 can be a common layer connected together.

[0092] In an exemplary embodiment, the first connection electrode 1-1 can be electrically connected to the pixel driving circuit of the first sub-pixel, and the second connection electrode 1-2 can be electrically connected to the pixel driving circuit of the second sub-pixel. The first connection electrode 1-1 and the second connection electrode 1-2 can be made of the same conductive film and manufactured using the same manufacturing process, thereby simplifying the manufacturing process and reducing production costs.

[0093] In an exemplary embodiment, the organic dielectric layer 2 may be a common layer connected together. A first via hole 2-1 and a second via hole 2-2 are provided in the organic dielectric layer 2. The first via hole 2-1 exposes at least a portion of the first connection electrode 1-1, and the second via hole 2-2 exposes at least a portion of the second connection electrode 1-2.

[0094] In an exemplary embodiment, the inorganic dielectric layer 4 includes a first inorganic dielectric pattern 41 and a second inorganic dielectric pattern 42. The first inorganic dielectric pattern 41 and the second inorganic dielectric pattern 42 can be made of the same inorganic thin film and prepared by the same preparation process, thereby simplifying the preparation process and reducing production costs.

[0095] In an exemplary embodiment, a third via 2-3 is provided in the first inorganic dielectric pattern 41, the orthographic projection of the third via 2-3 on the substrate 101 is located in the orthographic projection of the first via 2-1 on the substrate 101, and at least part of the side wall of the third via 2-3 extends out of the side wall of the first via 2-1 in a direction parallel to the substrate 101.

[0096] In an exemplary embodiment, a fourth via 2-4 is provided in the second inorganic dielectric pattern 42, the orthographic projection of the fourth via 2-4 on the substrate 101 is located in the orthographic projection of the second via 2-2 on the substrate 101, and at least part of the side wall of the fourth via 2-4 extends out of the side wall of the second via 2-2 in a direction parallel to the substrate 101.

[0097] In an exemplary embodiment, the first anode 5-1 and the second anode 5-2 can be made of the same conductive film and produced using the same manufacturing process, thereby simplifying the manufacturing process and reducing production costs. The first anode 5-1 is connected to the first connection electrode 1-1 through the first via 2-1 and the third via 2-3, and the second anode 5-2 is connected to the second connection electrode 1-2 through the second via 2-2 and the fourth via 2-4.

[0098] In an exemplary embodiment, the pixel definition layer 6 may be a common layer connected together. A first pixel opening 6-1 and a second pixel opening 6-2 are provided in the pixel definition layer 6. The first pixel opening 6-1 exposes at least a portion of the first anode 5-1, and at least a portion of the first anode 5-1 can serve as the bottom wall of the first pixel opening 6-1. The second pixel opening 6-2 exposes at least a portion of the second anode 5-2, and at least a portion of the second anode 5-2 can serve as the bottom wall of the second pixel opening 6-2.

[0099] In an exemplary embodiment, the light-emitting layer 7 may be a common layer connected together. The light-emitting layer 7 overlaps with the orthographic projections of the first anode 5-1 and the second anode 5-2 on the substrate 101. For example, the orthographic projection of the first anode 5-1 on the substrate 101 is located in the orthographic projection of the light-emitting layer 7 on the substrate 101, and the orthographic projection of the second anode 5-2 on the substrate 101 is located in the orthographic projection of the light-emitting layer 7 on the substrate 101. At least a portion of the light-emitting layer 7 covers the side walls and bottom walls of the first pixel opening 6-1, and at least a portion of the light-emitting layer 7 is electrically connected to the first anode 5-1 through the first pixel opening 6-1; at least a portion of the light-emitting layer 7 covers the side walls and bottom walls of the second pixel opening 6-2, and at least a portion of the light-emitting layer 7 is electrically connected to the second anode 5-2 through the second pixel opening 6-2.

[0100] In an exemplary embodiment, the cathode 3 may be a common layer connected together. At least a portion of the cathode 3 is electrically connected to the light-emitting layer 7. At least a portion of the cathode 3 overlaps with the orthographic projections of the first anode 5-1 and the second anode 5-2 on the substrate 101. For example, the orthographic projection of the first anode 5-1 on the substrate 101 is located within the orthographic projection of the cathode 3 on the substrate 101, and the orthographic projection of the second anode 5-2 on the substrate 101 is located within the orthographic projection of the cathode 3 on the substrate 101.

[0101] In an exemplary embodiment, the display substrate further includes a partition structure 10 disposed on the base 101 in a direction perpendicular to the display substrate. The partition structure 10 is located between adjacent sub-pixels and blocks the light-emitting layers and cathodes of the adjacent sub-pixels. For example, the partition structure 10 is located between a first sub-pixel and a second sub-pixel, blocking the light-emitting layer and cathode of the first sub-pixel from the light-emitting layer and cathode of the second sub-pixel.

[0102] The embodiment of the present disclosure shows that the substrate blocks the light-emitting layers and cathodes of adjacent sub-pixels through the partition structure 10 to prevent the currents of adjacent sub-pixels from crosstalking with each other.

[0103] In an exemplary embodiment, the partition structure 10 includes a first isolation wall 10-1, a second isolation wall 10-2, and an isolation trench 10-3 located between the first isolation wall 10-1 and the second isolation wall 10-2. The first isolation wall 10-1 is located near the first sub-pixel, and the second isolation wall 10-2 is located near the second sub-pixel.

[0104] In an exemplary embodiment, the first isolation wall 10-1 includes a first isolation layer 111 disposed on the substrate 101 and a second isolation layer 112 disposed on a side of the first isolation layer 111 away from the substrate 101. The first isolation layer 111 can be integrally connected to the adjacent organic dielectric layer 2, using the same organic thin film and fabricated using the same fabrication process, thereby simplifying the fabrication process and reducing production costs. The second isolation layer 112 can be integrally connected to the adjacent first inorganic dielectric pattern 41, using the same inorganic thin film and fabricated using the same fabrication process, thereby simplifying the fabrication process and reducing production costs.

[0105] In an exemplary embodiment, at least a portion of the second isolation layer 112 extends beyond the sidewall of the first isolation layer 111 in a direction parallel to the substrate 101, forming a protrusion 51. The pixel definition layer 6 covers the surface of the second isolation layer 112 facing away from the substrate, exposing at least a portion of the surface and side surfaces of the second isolation layer 112 facing away from the substrate. The light-emitting layer 7 and the cathode 3 are blocked at the protrusion 51.

[0106] In an exemplary embodiment, the second isolation wall 10-2 includes a third isolation layer 113 disposed on the substrate 101 and a fourth isolation layer 114 disposed on a side of the third isolation layer 113 away from the substrate 101. The third isolation layer 113 can be integrally connected to the adjacent organic dielectric layer 2, using the same organic thin film and fabricated using the same fabrication process, thereby simplifying the fabrication process and reducing production costs. The fourth isolation layer 114 can be integrally connected to the adjacent second inorganic dielectric pattern 42, using the same inorganic thin film and fabricated using the same fabrication process, thereby simplifying the fabrication process and reducing production costs.

[0107] In an exemplary embodiment, the side wall of the fourth isolation layer 114 close to the first isolation wall 10-1 and the side wall of the third isolation layer 113 close to the first isolation wall 10-1 form a continuous flat surface, and the stacked structure formed by the pixel definition layer 6, the light-emitting layer 7 and the cathode 3 covers the flat surface formed by the side wall of the fourth isolation layer 114 and the side wall of the third isolation layer 113.

[0108] In an exemplary embodiment, the bottom of the isolation trench 10 - 3 is the organic medium layer 2 , and the stacked structure formed by the light emitting layer 7 and the cathode 3 covers the bottom of the isolation trench 10 - 3 .

[0109] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0110] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0111] (11) Forming an inorganic dielectric layer and a partition structure. In an exemplary embodiment, forming the inorganic dielectric layer and the partition structure may include: first forming an organic dielectric layer on a substrate; then depositing an inorganic insulating film on the organic dielectric layer, and patterning the inorganic insulating film through a patterning process to form an inorganic dielectric layer, wherein the inorganic dielectric layer includes a first inorganic dielectric pattern 41, a second inorganic dielectric pattern 42, and a third inorganic dielectric pattern 43 that are spaced apart from each other, and the first inorganic dielectric pattern 41, the second inorganic dielectric pattern 42, and the third inorganic dielectric pattern 43 all form a partition structure 10 with the organic dielectric layer, as shown in FIG6 .

[0112] In an exemplary embodiment, the shapes of the first inorganic dielectric pattern 41, the second inorganic dielectric pattern 42, and the third inorganic dielectric pattern 43 all include rectangles. The first inorganic dielectric pattern 41 and the second inorganic dielectric pattern 42 are spaced apart along the second direction D2 to form an inorganic dielectric pattern column. The third inorganic dielectric pattern 43 is located on one side of the inorganic dielectric pattern column in the first direction D1.

[0113] In an exemplary embodiment, the partition structure 10 has a linear shape and may be located on at least one side of the first inorganic dielectric pattern 41, the second inorganic dielectric pattern 42, and the third inorganic dielectric pattern 43. For example, the partition structure 10 may be located on one side of the first inorganic dielectric pattern 41 in the second direction D2, and / or on one side of the first inorganic dielectric pattern 41 opposite to the first direction D1, and / or on one side of the second inorganic dielectric pattern 42 in the second direction D2, and / or on one side of the second inorganic dielectric pattern 42 opposite to the first direction D1, and / or on one side of the third inorganic dielectric pattern 43 opposite to the first direction D1 and between the third inorganic dielectric pattern 43 and the first inorganic dielectric pattern 41, and / or on one side of the third inorganic dielectric pattern 43 opposite to the first direction D1 and between the third inorganic dielectric pattern 43 and the second inorganic dielectric pattern 42.

[0114] (12) Forming a first anode, a second anode, a third anode, and an auxiliary cathode. In an exemplary embodiment, forming the first anode, the second anode, the third anode, and the auxiliary cathode may include: depositing a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form the first anode 5-1, the second anode 5-2, the third anode 5-3, and the auxiliary cathode 20, wherein the auxiliary cathode 20 is spaced apart from the first anode 5-1, the second anode 5-2, and the third anode 5-3, as shown in Figures 7a and 7b.

[0115] In an exemplary embodiment, the shapes of the first anode 5-1, the second anode 5-2 and the third anode 5-3 each include a rectangle, and the first anode 5-1 and the second anode 5-2 are spaced apart along the second direction D2 to form an anode column, and the third anode 5-3 is located on one side of the anode column in the first direction D1.

[0116] In an exemplary embodiment, the orthographic projection of the first anode 5-1 on the substrate is located in the orthographic projection of the first inorganic dielectric pattern 41 on the substrate; the orthographic projection of the second anode 5-2 on the substrate is located in the orthographic projection of the second inorganic dielectric pattern 42 on the substrate; and the orthographic projection of the third anode 5-3 on the substrate is located in the orthographic projection of the third inorganic dielectric pattern 43 on the substrate.

[0117] In an exemplary embodiment, the auxiliary cathode 20 has a grid shape and may be disposed around the first sub-pixel region 100 , around the second sub-pixel region 200 , and around the third sub-pixel region 300 .

[0118] In an exemplary embodiment, the auxiliary cathode 20 includes a first side 21, a second side 22, a third side 23, a fourth side 24, a fifth side 25, and a sixth side 26. The first side 21 is linear and extends along a first direction D1. The first side 21 is located on a side of the first sub-pixel region 100 and the third sub-pixel region 300 opposite to the second direction D2. The first end of the first side 21 is connected to the first end of the second side 22, and the second end of the first side 21 is connected to the first end of the fourth side 24. The second side 22 is linear and extends along a second direction D2. The second side 22 is located on a side of the first sub-pixel region 100 and the second sub-pixel region 200 opposite to the first direction D1. The first end of the second side 22 is connected to the first end of the first side 21, and the second end of the second side 22 is connected to the first end of the third side 23. The third side 23 is linear and extends along the first direction D1. It is located on one side of the second sub-pixel region 200 and the third sub-pixel region 300 in the second direction D2. The first end of the third side 23 is connected to the second end of the second side 22, and the second end of the third side 23 is connected to the second end of the fourth side 24. The fourth side 24 is linear and extends along the second direction D2. It is located on one side of the third sub-pixel region 300 in the first direction D1. The first end of the fourth side 24 is connected to the second end of the first side 21, and the second end of the fourth side 24 is connected to the second end of the third side 23. The fifth side 25 is linear and extends along the first direction D1. It is located between the first sub-pixel region 100 and the second sub-pixel region 200. The first end of the fifth side 25 is connected to the middle of the second side 22, and the second end of the fifth side 25 is connected to the middle of the sixth side 26. The sixth side portion 26 is linear in shape and extends along the second direction D2. The sixth side portion 26 is located between the first sub-pixel area 100 and the third sub-pixel area 300 and between the second sub-pixel area 200 and the third sub-pixel area 300. The first end of the sixth side portion 26 is connected to the middle of the first side portion 21, and the second end of the sixth side portion 26 is connected to the middle of the third side portion 23.

[0119] In the exemplary embodiment, a first protrusion 211 is provided on the first side 21 of the auxiliary cathode 20. The first protrusion 211 protrudes from the edge of the first side 21 in the second direction D2, and the first protrusion 211 protrudes toward the direction close to the third anode 5-3. A second protrusion 231 is provided on the third side 23 of the auxiliary cathode 20. The second protrusion 231 protrudes from the edge of the third side 23 in the second direction D2, and the second protrusion 231 protrudes toward the direction close to the third anode 5-3.

[0120] (13) Forming a pixel definition layer. In an exemplary embodiment, forming the pixel definition layer may include: depositing a pixel definition film covering the first anode 5-1, the second anode 5-2, the third anode 5-3, and the auxiliary cathode 20 on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film through a patterning process to form a pixel definition layer 6, as shown in FIG8a and FIG8b.

[0121] In an exemplary embodiment, a first pixel opening 6-1, a second pixel opening 6-2 and a third pixel opening 6-3 are provided in the pixel definition layer 6, the first pixel opening 6-1 exposes at least a portion of the first anode 5-1, and the first anode 5-1 can serve as the bottom wall of the first pixel opening 6-1; the second pixel opening 6-2 exposes at least a portion of the second anode 5-2, and the second anode 5-2 can serve as the bottom wall of the second pixel opening 6-2; the third pixel opening 6-3 exposes at least a portion of the third anode 5-3, and the third anode 5-3 can serve as the bottom wall of the third pixel opening 6-3.

[0122] In an exemplary embodiment, a first connection via 31 and a second connection via 32 are provided in the pixel definition layer 6, the first connection via 31 being located on the side of the third pixel opening 6-3 in the opposite direction of the second direction D2, exposing the first bump of the auxiliary cathode 20; the second connection via 32 being located on the side of the third pixel opening 6-3 in the second direction D2, exposing the second bump of the auxiliary cathode 20.

[0123] In an exemplary embodiment, at least one first partition avoidance hole 61 is provided in the pixel definition layer 6, and the first partition avoidance hole 61 is provided corresponding to the partition structure 10. The first partition avoidance hole 61 overlaps with the orthographic projection of the partition structure 10 on the substrate. The first partition avoidance hole 61 exposes at least part of the partition structure 10, so that the light-emitting layer and cathode formed later can contact the partition structure 10 at the first partition avoidance hole 61 and be blocked at the partition structure 10.

[0124] (14) Forming a light-emitting layer and a cathode. In an exemplary embodiment, forming the light-emitting layer and the cathode may include: on the substrate on which the aforementioned pattern is formed, first depositing a light-emitting layer covering the pixel definition layer 6 on the substrate, the light-emitting layer may be a common layer connected together, the light-emitting layer is connected to the first anode 5-1 through the first pixel opening 6-1, the light-emitting layer is connected to the second anode 5-2 through the second pixel opening 6-2, and the light-emitting layer is connected to the third anode 5-3 through the third pixel opening 6-3; and the light-emitting layer is blocked at the partition structure 10; a first connection avoidance hole and a second connection avoidance hole are provided in the light-emitting layer, the first connection avoidance hole overlaps with the orthographic projection of the first bump 211 of the auxiliary cathode 20 on the substrate, and the second connection avoidance hole overlaps with the orthographic projection of the second bump 231 of the auxiliary cathode 20 on the substrate;

[0125] Subsequently, a second conductive film is deposited on the light-emitting layer, and the second conductive film is patterned by a patterning process to form a cathode 3, as shown in FIG. 9 and FIG. 4 a .

[0126] In an exemplary embodiment, the cathode 3 may be a common layer connected together, the cathode 3 is connected to the light emitting layer, and the cathode 3 is blocked at the partition structure 10 .

[0127] In an exemplary embodiment, the cathode 3 overlaps with the orthographic projections of the first anode 5-1, the second anode 5-2, the third anode 5-3 and the auxiliary cathode 20 on the substrate. For example, the orthographic projection of the first anode 5-1 on the substrate is located in the orthographic projection of the cathode 3 on the substrate, the orthographic projection of the second anode 5-2 on the substrate is located in the orthographic projection of the cathode 3 on the substrate, the orthographic projection of the third anode 5-3 on the substrate is located in the orthographic projection of the cathode 3 on the substrate, and the orthographic projection of the auxiliary cathode 20 on the substrate is located in the orthographic projection of the cathode 3 on the substrate.

[0128] In an exemplary embodiment, the cathode 3 can be connected to the first bump of the auxiliary cathode 20 through the first connection via 31, and the cathode 3 can be connected to the second bump of the auxiliary cathode 20 through the second connection via 32, so that the surface resistance of the cathode 3 can be reduced through the auxiliary cathode 20.

[0129] In an exemplary embodiment, at least one second partition avoidance hole 62 is provided in the cathode 3 . The second partition avoidance hole 62 is provided corresponding to the partition structure 10 . The cathode 3 is blocked at the partition structure 10 to form the second partition avoidance hole 62 .

[0130] The present disclosure also provides a method for preparing a display substrate, comprising:

[0131] forming a partition structure on a substrate;

[0132] forming a conductive film on a substrate so that the conductive film forms an anode and an auxiliary cathode that are insulated from each other, wherein the orthographic projections of the anode and the partition structure on the substrate do not overlap, and the orthographic projections of the auxiliary cathode and the partition structure on the substrate do not overlap;

[0133] forming a light-emitting layer on a side of the anode away from the substrate, the light-emitting layer being connected to the anode and blocked at the partition structure;

[0134] A cathode is formed on a side of the light-emitting layer away from the substrate, the cathode is connected to the light-emitting layer, the cathode is blocked at the partition structure, and the cathode is electrically connected to the auxiliary cathode.

[0135] The present disclosure also provides a display device including the above-mentioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the present disclosure is not limited thereto.

[0136] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A display substrate, characterized in that, Comprising: A partition structure, disposed on a substrate; An anode, disposed on the substrate, and the anode does not overlap with the positive projection of the partition structure on the substrate; A light-emitting layer, disposed on a side of the anode away from the substrate, the light-emitting layer is connected to the anode, and the light-emitting layer is blocked at the partition structure; A cathode, disposed on a side of the light-emitting layer away from the substrate, the cathode is connected to the light-emitting layer, and the cathode is blocked at the partition structure; An auxiliary cathode, located in the same film layer as the anode and insulated from each other, and the auxiliary cathode is electrically connected to the cathode.

2. The display substrate according to claim 1, wherein It further includes connection vias disposed between the auxiliary cathode and the cathode, the cathode is connected to the auxiliary cathode through the connection vias, and the connection vias do not overlap with the positive projections of the anode and the partition structure on the substrate.

3. The display substrate according to claim 2, characterized in that, Connection avoidance holes are provided in the light-emitting layer, and the positive projection of the connection avoidance holes on the substrate covers the positive projection of the connection vias on the substrate.

4. The display substrate according to claim 1, wherein The auxiliary cathode and the anode are made of the same conductive material.

5. The display substrate according to claim 1, wherein The shape of the auxiliary cathode is grid-like.

6. The display substrate according to claim 1, wherein Protrusions are provided on the auxiliary cathode, the protrusions protrude from the edge of the auxiliary cathode, and the protrusions are electrically connected to the cathode.

7. The display substrate according to claim 1, wherein The positive projection of the auxiliary cathode on the substrate is located within the positive projection of the cathode on the substrate.

8. The display substrate according to any one of claims 1 to 7, characterized in that, The partition structure includes a first isolation wall disposed on the substrate, the first isolation wall includes a first isolation layer and a second isolation layer disposed on a side of the first isolation layer away from the substrate, at least a part of the second isolation layer extends along a direction parallel to the substrate out of the side wall of the first isolation layer to form a convex platform, and the light-emitting layer and the cathode are blocked at the convex platform.

9. The display substrate according to claim 8, wherein, The partition structure further includes a second isolation wall, an isolation groove is formed between the second isolation wall and the first isolation wall, the second isolation wall includes a third isolation layer and a fourth isolation layer disposed on a side of the third isolation layer away from the substrate, at least a part of the stacked structure formed by the light-emitting layer and the cathode covers the side walls of the third isolation layer and the fourth isolation layer, and at least a part of the stacked structure formed by the light-emitting layer and the cathode covers the bottom of the isolation groove.

10. The display substrate according to claim 9, wherein It further includes an organic dielectric layer and an inorganic dielectric layer, the organic dielectric layer is disposed on the substrate, the inorganic dielectric layer is disposed on a side of the organic dielectric layer away from the substrate, the anode is disposed on a side of the inorganic dielectric layer away from the substrate, the first isolation layer is integrally connected to the adjacent organic dielectric layer, the third isolation layer is integrally connected to the adjacent organic dielectric layer, the second isolation layer is integrally connected to the adjacent inorganic dielectric layer, the fourth isolation layer is integrally connected to the adjacent inorganic dielectric layer, and the bottom of the isolation groove is the organic dielectric layer.

11. The display substrate according to any one of claims 1 to 7, characterized in that, It includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region includes a first anode, a light-emitting layer, and a cathode. The second sub-pixel region includes a second anode, a light-emitting layer, and a cathode. The third sub-pixel region includes a third anode, a light-emitting layer, and a cathode. The first sub-pixel region and the second sub-pixel region are arranged along a second direction to form a sub-pixel column. The third sub-pixel region is located on one side of the sub-pixel column in a first direction. The partition structure is disposed on at least one side of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region. The first direction intersects the second direction.

12. The display substrate according to claim 11, wherein The auxiliary cathode is disposed around the periphery of the first sub-pixel region, around the periphery of the second sub-pixel region, and around the periphery of the third sub-pixel region.

13. The display substrate according to claim 11, wherein It further includes connection vias disposed between the auxiliary cathode and the cathode. The cathode is connected to the auxiliary cathode through the connection vias. The connection vias do not overlap with the positive projections of the anode and the partition structure on the substrate. The connection vias are located on at least one side of the third sub-pixel region in the second direction.

14. The display substrate according to claim 11, characterized in that, It includes a first partition structure, a second partition structure, a third partition structure, a fourth partition structure, a fifth partition structure, and a sixth partition structure. The shape of the first partition structure includes a line extending along the first direction. The first partition structure is disposed between the first sub-pixel region and the second sub-pixel region. The shape of the second partition structure includes a line extending along the second direction. The second partition structure is disposed on a side of the first sub-pixel region away from the third sub-pixel region. The shape of the third partition structure includes a line extending along the first direction. The third partition structure is disposed on a side of the second sub-pixel region away from the first sub-pixel region. The shape of the fourth partition structure includes a line extending along the second direction. The fourth partition structure is disposed on a side of the second sub-pixel region away from the third sub-pixel region. The shape of the fifth partition structure includes a line extending along the second direction. The fifth partition structure is disposed between the third sub-pixel region and the first sub-pixel region. The shape of the sixth partition structure includes a line extending along the second direction. The sixth partition structure is disposed between the third sub-pixel region and the second sub-pixel region.

15. The display substrate according to any one of claims 1 to 7, characterized in that, It further includes a pixel definition layer. The pixel definition layer is disposed on a side of the anode away from the substrate. The pixel definition layer is provided with pixel openings that expose at least part of the anode. The light-emitting layer covers the pixel openings and is connected to the anode. The pixel definition layer is further provided with connection vias. The cathode is connected to the auxiliary cathode through the connection vias. The connection vias do not overlap with the positive projections of the anode and the partition structure on the substrate.

16. The display substrate according to claim 15, wherein, The pixel definition layer is further provided with partition avoidance holes that overlap with the positive projections of the partition structures on the substrate.

17. A display device, characterized in that, A display substrate as claimed in any one of claims 1 to 16 is included.

18. A method for preparing a display substrate, characterized in that, Comprising: Forming a partition structure on a substrate; Forming a conductive thin film on the substrate, such that the conductive thin film forms an anode and an auxiliary cathode that are insulated from each other, the anode does not overlap with the positive projection of the partition structure on the substrate, and the auxiliary cathode does not overlap with the positive projection of the partition structure on the substrate; Forming a light-emitting layer on a side of the anode away from the substrate, the light-emitting layer is connected to the anode, and the light-emitting layer is blocked at the partition structure; Forming a cathode on a side of the light-emitting layer away from the substrate, the cathode is connected to the light-emitting layer, the cathode is blocked at the partition structure, and the cathode is electrically connected to the auxiliary cathode.

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