Circuit board, and semiconductor package comprising same

Abstract

The circuit board according to an embodiment comprises: a build-up insulating part including a plurality of insulating layers stacked along the vertical direction; via electrodes disposed in via holes provided in the plurality of insulating layers; and wiring layers connected to the via electrodes, wherein at least one of the insulating layers includes an inorganic filler, the insulating layer facing the side surface of a via electrode in a via hole does not expose the inorganic filler, and the horizontal width of the via electrode may be the same along the vertical direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring portion arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring portion connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring portion includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring portion.

[0005] Meanwhile, FIGS. 1A and 1B are drawings showing via electrodes and wiring layers in a circuit board being internally studied. (a) of FIG. 1A may be a via electrode and wiring layer formed by a SAP (Semi Additive Process) or MSAP (Modified Semi Additive Process) process. In addition, (b) of FIG. 1A may be a via electrode and wiring layer formed by an ETS (Embedded Trace Substrate) process.

[0006] Referring to Fig. 1a, a second insulating layer (14) is placed on a first insulating layer (12), and a via electrode (22) penetrating each insulating layer can be formed. The via electrode (22) is formed by forming a via penetrating the inside of the insulating layer and filling it with plating, and the via is formed using a laser drilling method.

[0007] Meanwhile, referring to (a) of Fig. 1a, the via is formed by the laser drilling method in a form in which the horizontal width changes as it goes downward, for example, the horizontal width gradually decreases, and also, an uneven roughness is formed on the inner wall of the via by the laser.

[0008] Accordingly, in the prior art, a voltage drop may occur as the horizontal width of the via electrode changes in the vertical direction, and it is difficult to align the vertical alignment of the via electrodes arranged in each of a plurality of insulating layers, which causes a problem in that the voltage drop increases.

[0009] In addition, in the prior art, there is a problem that the electrical resistance of the via electrode increases due to the occurrence of uneven roughness on the inner wall of the via, thereby reducing the signal transmission speed, and there is a problem that it is difficult to implement a fine pitch due to the size of the pad because the width of the wiring layer or pad must be larger than the minimum width of the via electrode.

[0010] In addition, referring to FIG. 1b, a dimple (P1) having a sunken shape in the center of the wiring layer (20) may be generated due to the shape of the via that becomes narrower as it gets deeper in the via electrode (22). In addition, a second via electrode (23) penetrating the first insulating layer (12) and the second insulating layer (14) may be arranged. The second via electrode (23) may be formed as a skip via. There is a problem that a void (P2) may be formed inside when the via electrode is formed after forming a plating layer on the inner wall of the via penetrating the first insulating layer (12) and the second insulating layer (14). In addition, when forming a via to be connected to the second wiring layer (24), an issue may arise in controlling the depth of the via, or a separation (P3) may occur between the via electrode and the wiring layer due to poor connection between the via electrode (22) and the second wiring layer (24).

[0011] One of the technical challenges of the embodiment is to prevent voltage drops on the circuit board.

[0012] Additionally, one of the technical challenges of the embodiment is to improve the alignment accuracy and alignment of via electrodes and wiring layers.

[0013] Additionally, one of the technical challenges of the embodiment is to increase the number of signal transmission pathways.

[0014] Additionally, one of the technical challenges of the embodiment is to reduce the pitch of the via electrode and wiring layer.

[0015] Additionally, one of the technical challenges of the embodiment is to prevent loss of signal transmission.

[0016] Additionally, one of the technical challenges of the embodiment is to simplify the formation process of the via electrode.

[0017] Additionally, one of the technical challenges of the embodiment is to improve the electrical and structural reliability of the via electrode.

[0018] Additionally, one of the technical challenges of the embodiment is to reduce signal interference of adjacent circuit patterns.

[0019] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0020] A circuit board according to an embodiment comprises a build-up insulating portion including a plurality of insulating layers stacked along a vertical direction; a via electrode disposed within a via hole provided in the plurality of insulating layers; and a wiring layer connected to the via electrode; wherein at least one of the plurality of insulating layers includes an inorganic filler, and the insulating layer facing a side surface of the via electrode within the via hole may not expose the inorganic filler. A horizontal width of the via electrode may be the same along the vertical direction.

[0021] The side surface of the above via electrode may have a uniform surface. In addition, in an embodiment, the width of the upper surface and the width of the lower surface of the above via electrode may be the same.

[0022] Additionally, in an embodiment, the horizontal width of the wiring layer may be the same as the horizontal width of the via electrode.

[0023] Additionally, in the embodiment, the plurality of insulating layers may include a first insulating layer and a second insulating layer disposed on the first insulating layer.

[0024] In addition, in the embodiment, the via electrode includes a first via electrode disposed within the first insulating layer and a second via electrode disposed within the second insulating layer,

[0025] Both side surfaces of the first via electrode and both side surfaces of the second via electrode may be positioned on the same vertical line.

[0026] Additionally, in the embodiment, the via electrode may include a through via electrode penetrating the first insulating layer and the second insulating layer.

[0027] Additionally, in the embodiment, the via electrode includes a third via electrode disposed within the first insulating layer and a fourth via electrode disposed within the second insulating layer.

[0028] The horizontal width of the third via electrode is greater than the horizontal width of the fourth via electrode,

[0029] The central axes of the third via electrode and the fourth via electrode may be the same.

[0030] Additionally, the embodiment may include roughness at the interface where the second insulating layer and the first insulating layer come into contact.

[0031] Additionally, the embodiment may include roughness on the upper surface of the second insulating layer.

[0032]

[0033] In addition, a circuit board according to an embodiment comprises: a build-up insulating portion including a first insulating layer, a second insulating layer, and a third insulating layer stacked along a vertical direction; a plurality of via electrodes respectively disposed within via holes provided in the first insulating layer, the second insulating layer, and the third insulating layer; and

[0034] A plurality of wiring layers each connected to the plurality of via electrodes; wherein at least one of the first insulating layer, the second insulating layer, and the third insulating layer includes an inorganic filler, and the plurality of via electrodes includes a first via electrode disposed in the first insulating layer, a second via electrode disposed in the second insulating layer, and a third via electrode disposed in the third insulating layer, and the horizontal widths of each of the plurality of via electrodes are the same along the vertical direction, and the horizontal width of the first via electrode may be smaller than the horizontal width of the second via electrode and the horizontal width of the third via electrode.

[0035] The horizontal width of the second via electrode may be greater than the horizontal width of the first via electrode, and the horizontal width of the third via electrode may be greater than the horizontal width of the third via electrode.

[0036] The central axes of the first via electrode, the second via electrode, and the third via electrode may be identical to each other.

[0037] The above via electrode may have a cylindrical shape.

[0038] The insulating layer facing the side of the via electrode within the via hole may not expose the inorganic filler.

[0039] The circuit board according to the embodiment has a technical effect of preventing voltage drop of the circuit board.

[0040] For example, referring to FIG. 2a, the embodiment can prevent voltage drop by ensuring that the resistance is constant according to the area of ​​the via electrode as the horizontal width of the via electrode has the same width in the vertical direction.

[0041] In addition, according to an embodiment, the via electrode (120) may include a plurality of via electrodes formed in each insulating layer, for example, a first via electrode (121), a second via electrode (122), and a third via electrode (123), and the horizontal widths of the first via electrode (121), the second via electrode (122), and the third via electrode (123) arranged to vertically overlap each other in different layers are controlled to be the same, thereby adjusting the vertical alignment for the via electrodes arranged in each of the plurality of insulating layers, thereby having the effect of preventing a voltage drop from occurring.

[0042] In addition, the embodiment has a technical effect of improving the alignment accuracy and alignment of via electrodes and wiring layers.

[0043] For example, the embodiment may have the same width on the upper and lower surfaces of the via electrode and the same width as the width of the wiring layer, so that alignment accuracy and alignment can be improved when forming a plurality of via electrodes and wiring layers.

[0044] Additionally, the embodiment has a technical effect that can increase the number of signal transmission pathways.

[0045] For example, the embodiment can form more via electrodes by implementing via electrodes and wiring layers in a fine pattern, thereby increasing the number of signal transmission paths.

[0046] Additionally, the embodiment has a technical effect of reducing the pitch of via electrodes and wiring layers.

[0047] For example, the embodiment can form a via electrode and a wiring layer regardless of the minimum width of the via electrode, thereby forming a fine via electrode or a small via electrode and a wiring layer, thereby reducing the pitch of the via electrode and the wiring layer.

[0048] Additionally, the embodiment has a technical effect that can prevent loss of signal transmission.

[0049] In addition, the embodiment has a technical effect that can simplify the process of forming a via electrode.

[0050] For example, the embodiment can simplify the process of forming a via electrode by forming a via hole through a thinning process of a film layer rather than a laser or drilling process, thereby eliminating the need for a desmear process as smearing does not occur.

[0051] In addition, the embodiment has a technical effect that can improve the electrical and structural reliability of the via electrode.

[0052] For example, referring to FIG. 3a, the side of the via electrode of the embodiment is not roughened, so that signal transmission loss due to roughness can be prevented, and structural reliability can be improved because there is no area where stress is concentrated.

[0053] In addition, the embodiment has a technical effect that can prevent defects such as voids when forming a through via electrode.

[0054] For example, referring to FIG. 2b, the embodiment can prevent defects such as voids inside by forming the through via electrodes uniformly so that the through via electrodes have the same horizontal width along the vertical direction.

[0055] Additionally, the embodiment has a technical effect of reducing signal interference of adjacent circuit patterns.

[0056] For example, in the embodiment, since the via electrode and wiring layer are implemented as a fine pattern, the distance from adjacent circuit patterns increases, so that signal interference can be reduced.

[0057] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0058] Figures 1a and 1b are drawings showing via electrodes and wiring layers in a circuit board being studied internally.

[0059] Fig. 2a is a cross-sectional view of a circuit board (100) according to the first embodiment.

[0060] Fig. 2b is a cross-sectional view of a circuit board (101) according to the second embodiment.

[0061] FIGS. 3A to 4B are drawings showing the first area (A1) of FIG. 2A according to the third to sixth embodiments.

[0062] Figures 5a to 5e are drawings showing a manufacturing process of a circuit board according to an embodiment.

[0063] Figures 6a and 6b are electron microscope drawings showing the upper surface of the insulating layer (116) of Figure 5e.

[0064] Fig. 7a is a cross-sectional view of a circuit board (102) according to the seventh embodiment.

[0065] Figure 7b is a drawing showing the second area (A2) of Figure 7a in detail.

[0066] Fig. 8 is a cross-sectional view of a semiconductor package (103) according to the eighth embodiment.

[0067] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0068] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0069] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0070] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0071] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0072] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0073] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0074] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0075] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0076] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0077] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0078]

[0079] (Example)

[0080] FIG. 2A is a cross-sectional view of a circuit board (100) according to a first embodiment. Referring to FIG. 2A, the circuit board (100) according to the embodiment may include a build-up insulating portion (110), a build-up wiring portion (118), and a protective layer (140, 145). The build-up insulating portion (110), the build-up wiring portion (118), and the protective layer (140, 145) may be referred to as a build-up structure, but is not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0081] The build-up insulation (110) includes a single or multiple laminated insulation layers and provides insulation properties between the build-up wiring sections. The build-up insulation (110) may be referred to as a build-up insulator. The build-up insulation (110) may include, but is not limited to, a first insulation layer (111), a second insulation layer (112), and a third insulation layer (113).

[0082] One of the build-up insulation parts (110) may be a core layer. The second insulation layer (112) located at the center of the build-up insulation part (110) may be a core layer, but is not limited thereto.

[0083] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and enhance its reliability.

[0084] The core layer may include a reinforcing member such as glass fiber extending horizontally and a resin covering the reinforcing member, and the mechanical rigidity may be controlled according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0085] The build-up insulation (110) may include an upper build-up insulation disposed on the upper surface of the core layer and a lower build-up insulation disposed on the lower surface of the core layer. For example, the build-up insulation (110) may include a second insulation layer (112) which is the core layer, a first insulation layer (111) which is the upper build-up insulation disposed on the upper surface of the core layer, and a third insulation layer (113) which is the lower build-up insulation disposed on the lower surface of the core layer.

[0086] The upper build-up insulation part and the lower build-up insulation part each have a function to place a wiring layer or via electrode of the build-up wiring part, secure insulation between circuits, and control impedance or insertion loss due to the circuit, and may include an insulation layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0087] For example, the insulation layer of the build-up insulation (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0088] Also, for example, the insulation layer of the build-up insulation portion (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0089] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0090] Additionally, the insulating layer of the build-up insulation (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0091] Additionally, the insulation layer of the build-up insulation portion (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0092]

[0093] Next, the build-up wiring section (118) of the circuit board (100) includes a wiring layer (130) arranged on the surface of each insulating layer and a via electrode (120) for vertically connecting each wiring layer (130). The wiring layer (130) may have the function of transmitting signals and / or power to semiconductor elements arranged on the circuit board (100) and may have an impedance matching function. The wiring layer (130) may be referred to as a wiring pattern layer, a metal wiring, or a wiring section.

[0094] The via electrode (120) may include a plurality of first via electrodes (121), second via electrodes (122), and third via electrodes (123) formed in through holes penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113), respectively. The via electrode (120) may electrically connect between wiring layers (130) arranged in different layers.

[0095] The via electrode (120) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material. Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the via electrode (120). The metal material forming the via electrode (120) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0096]

[0097] Next, the circuit board (100) according to the embodiment may include a wiring layer (130) electrically connected to a via electrode (120). The wiring layer (130) may include pads and / or traces (or connection patterns) for connecting to the via electrode (120) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads.

[0098] At this time, the pad of the wiring layer (130) may include a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0099]

[0100] The wiring layer (130) may include, but is not limited to, a first wiring layer (131) disposed on a first insulating layer (111) and electrically connected to the upper surface of a first via electrode (121), a second wiring layer (132) disposed on a second insulating layer (112) and electrically connected to the lower surface of the first via electrode (121), a third wiring layer (133) electrically connected to the lower surface of the second via electrode (122), and a fourth wiring layer (134) electrically connected to the lower surface of the third via electrode (123).

[0101] The wiring layer (130) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0102] In addition, any one of the above-described build-up wiring sections (118) may have an ETS (Embedded Trace Substrate) structure. The ETS structure may also be referred to as a buried structure. The ETS structure may be advantageous for miniaturization compared to a build-up wiring section having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0103] In addition, the build-up wiring portion may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring portion may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0104]

[0105] Next, the circuit board (100) according to the embodiment may include a protective layer disposed on the wiring layer of the uppermost or lowermost insulating layer. For example, the protective layer may include a first protective layer (140) disposed on the first insulating layer and a second protective layer (145) disposed under the third insulating layer (113).

[0106] The first protective layer (140) and the second protective layer (145) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer is formed of a material with low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging short circuits between adjacent solders.

[0107] In addition, the first protective layer (140) and the second protective layer (145) include an insulating material, and may include various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. In addition, the first protective layer (140) and the second protective layer (145) may be resist layers, and for example, the first protective layer (140) and the second protective layer (145) may include an epoxy acrylate series resin. In detail, the first protective layer (140) and the second protective layer (145) include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the first protective layer (140) and the second protective layer (145) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0108]

[0109] Meanwhile, in the circuit board (100) according to the embodiment, the side surface of the via electrode (120) may have a vertical slope. The cross-section of the via electrode (120) may have a rectangular shape rather than a trapezoidal shape. In detail, the horizontal width of the via electrode (120) may have the same width in the vertical direction. In addition, the areas of the upper and lower surfaces of the via electrode (120) may be within a uniform range. The widths of the upper and lower surfaces of the via electrode (120) may be the same. Accordingly, the embodiment has a technical effect of preventing voltage drop as the horizontal width of the via electrode (120) is maintained the same.

[0110] In addition, the embodiment enables the miniaturization of via electrodes without having to consider the minimum width of the upper or lower surface, thereby increasing the number of via electrodes and thus having the technical effect of increasing the number of signal transmission paths.

[0111] In addition, the horizontal widths of the first via electrode (121), the second via electrode (122), and the third via electrode (123) may be the same. Both side surfaces of the first via electrode (121) and both side surfaces of the second via electrode may be positioned on the same vertical line. In addition, the side surfaces of the first via electrode (121), the second via electrode (122), and the third via electrode (123) may be vertically overlapped. Accordingly, the embodiment has a technical effect of improving the alignment accuracy or alignment of the vertically overlapped via electrodes as the via electrodes (120) are formed to have a uniform width. In addition, the embodiment has a technical effect of improving the signal transmission speed by enabling the implementation of the shortest path for signal transmission.

[0112]

[0113] Fig. 2b is a cross-sectional view of a circuit board (101) according to a second embodiment. The second embodiment may have different shapes of via electrodes and wiring layers from the first embodiment. Referring to Fig. 2b, the second embodiment may include a fourth via electrode (125) penetrating the build-up insulation portion (110). Meanwhile, the fourth via electrode (125) may be a through via electrode or a skip via electrode penetrating the first insulation layer (111), the second insulation layer (112), and the third insulation layer (113). The horizontal width of the fourth via electrode (125) may be the same along the vertical direction. In addition, the horizontal width of the fourth via electrode (125) may be uniform along the vertical direction. In addition, the width of the upper surface and the width of the lower surface of the fourth via electrode (125) may be the same.

[0114] Accordingly, the second embodiment has a technical effect of reducing the difficulty of the plating process by keeping the width of the via cross-section constant when forming a through via electrode or a skip via electrode, and preventing the problem of voids occurring inside.

[0115]

[0116] Additionally, the second embodiment may include a first wiring layer (131) connected to an upper surface of the fourth via electrode (125) and a second wiring layer (132) connected to a lower surface of the fourth via electrode (125). The first wiring layer (131) and the second wiring layer (132) may be pads connected to an external element or a substrate. In this case, the first wiring layer (131) and the second wiring layer (132) may have a horizontal width that is the same as the horizontal width of the fourth via electrode (125). The side surfaces of the first wiring layer (131) and the second wiring layer (132) may vertically overlap the side surfaces of the fourth via electrode (125).

[0117] Accordingly, the second embodiment has the technical effect of reducing the pad pitch by forming the pad to have the same width as the via electrode and eliminating the need to consider the minimum width of the upper or lower surface of the via electrode. In addition, the second embodiment has the technical effect of improving the alignment accuracy or alignment of the pad and the via electrode.

[0118]

[0119] In addition, although the fourth via electrode (125) is illustrated as an integral via electrode in FIG. 2B, the fourth via electrode (125) may include a form in which multiple via electrodes and multiple wiring layers are connected. The multiple via electrodes and the multiple wiring layers may have a uniform horizontal width along the vertical direction. Accordingly, in the second embodiment, the wiring layer disposed within the build-up insulation portion (110) may also have the same horizontal width as the via electrode, thereby reducing the horizontal width and providing a technical effect of implementing a fine pattern.

[0120]

[0121] FIGS. 3A to 4B are drawings showing the first region (A1) of FIG. 2A according to the third to sixth embodiments. The third embodiment of FIG. 3A and the fourth embodiment of FIG. 3B can be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0122] First, referring to FIG. 3A, an insulating layer (116) may be disposed on a build-up insulating portion (110). The build-up insulating portion (110) may include a plurality of insulating layers, a plurality of via electrodes, and a plurality of wiring layers. In addition, a wiring layer (130) may be disposed on the build-up insulating portion (110). In addition, a via electrode (120) may be disposed on the wiring layer (130). The horizontal width of the wiring layer (130) may be greater than the horizontal width of the via electrode (120).

[0123] In addition, the cross-section of the via electrode (120) may be formed in a rectangular shape. The horizontal width of the via electrode (120) may have the same width in the vertical direction. In addition, the areas of the upper and lower surfaces of the via electrode (120) may be within a uniform range. The widths of the upper and lower surfaces of the via electrode (120) may be the same. Accordingly, the embodiment has a technical effect of preventing voltage drop as the horizontal width of the via electrode (120) is maintained the same.

[0124] In addition, roughness may not be formed on the side surface of the via electrode (120). The side surface of the via electrode (120) may have a smooth shape and a uniform surface. Accordingly, the embodiment has a technical effect in that a portion where stress is concentrated is not created, thereby preventing cracks or peeling of the via electrode (120), thereby improving reliability, and suppressing signal loss.

[0125] In addition, the upper surface of the insulating layer (116) may be positioned lower than the upper surface of the via electrode (120). The upper surface of the insulating layer (116) may have roughness (150) formed during the formation of the via electrode (120). In addition, an additional insulating layer may be laminated on the insulating layer (116). In this case, the adhesive strength between the insulating layers may be improved by the roughness (150) formed on the upper surface of the insulating layer (116).

[0126] In addition, the roughness (150) formed on the insulating layer (116) can be removed through solution treatment, and the detailed process is described in FIGS. 5a to 5d.

[0127]

[0128] Referring to FIG. 3b, a via electrode (120) may be arranged on a wiring layer (130). The via electrode (120) may be formed to have the same horizontal width as the horizontal width of the wiring layer (130). In addition, a side surface of the via electrode (120) may be formed along a vertical direction. The side surface of the wiring layer (130) may vertically overlap with the side surface of the via electrode (120). Accordingly, the fourth embodiment has a technical effect of improving the alignment accuracy or alignment of the wiring layer (130) and the via electrode (120). In addition, since the wiring layer (130) can be formed without considering the minimum width of the via electrode (120), a fine pattern can be implemented, and there is a technical effect of increasing the number of via electrodes (120) and wiring layers (130) in the same area to form a variety of signal transmission routes.

[0129]

[0130] In addition, the fifth embodiment of FIG. 4a and the sixth embodiment of FIG. 4b can form a via electrode and a wiring layer by an ETS (Embedded Trace Substrate) method. Referring to FIG. 4a, a build-up insulation portion (110) can be disposed under an insulating layer (116). A wiring layer (130) can be disposed under an upper surface of the insulating layer (116), and a via electrode (120) can be disposed under the wiring layer (130). The via electrode (120) can penetrate the insulating layer (116). In addition, a lower surface of the via electrode (120) can be positioned lower than a lower surface of the insulating layer (116). In addition, a roughness (150) can be formed on the lower surface of the insulating layer (116) and can be in contact with the build-up insulation portion (110). Accordingly, the adhesive strength of the insulating layer (116) and the build-up insulating portion (110) can be improved.

[0131]

[0132] Next, referring to FIG. 4b, the via electrode (120) can be formed to have the same horizontal width as the wiring layer (130). The side surface of the via electrode (120) can vertically overlap with the side surface of the wiring layer (130). Accordingly, the sixth embodiment has a technical effect that the alignment accuracy or alignment property of the wiring layer (130) and the via electrode (120) can be improved. In addition, since the wiring layer (130) can be formed without considering the minimum width of the via electrode (120), there is a technical effect that a fine pattern can be implemented.

[0133]

[0134] Figures 5a to 5e are drawings illustrating a manufacturing process of a circuit board according to an embodiment. First, referring to Figure 5a, the build-up insulation portion (110) may include multiple insulating layers, multiple via electrodes, and multiple wiring layers. Multiple wiring layers (130) may be formed on the build-up insulation portion (110).

[0135] Next, referring to FIG. 5b, a film layer (117) may be formed on the build-up insulation portion (110). The film layer (117) includes an insulating material and may include a photosensitive material or a photocurable material. The film layer (117) may be, for example, a dry film.

[0136] In addition, a first mask (not shown) may be positioned on the film layer (117). The first mask may be positioned to overlap an area excluding an area where a via electrode is to be formed on the wiring layer (130). Thereafter, the film layer may be cured through an exposure process. In addition, after removing the first mask, a second mask (not shown) may be positioned on an area excluding an area where a via electrode is to be formed, and then a via hole (120H) may be formed through a development process. The via hole (120H) may be formed to have the same horizontal width along the vertical direction. In addition, the cross-sectional area of ​​the via hole (120H) may be uniform along the vertical direction. Therefore, the embodiment forms a via hole through an exposure and development process using a film layer rather than laser processing, so that the via hole (120H) may have a vertical side surface, and there is a technical effect in that roughness is not formed on the inner wall of the via hole (120H). In addition, since the embodiment forms a via hole (120H) by exposure and development rather than laser processing, there is a technical effect that the process can be simplified because a smear is not formed and a desmear process is unnecessary.

[0137] Although FIG. 5b shows that the via hole (120H) has a width smaller than the horizontal width of the wiring layer (130), it can be formed to have the same width as the wiring layer (130) as in FIG. 3b.

[0138]

[0139] Next, referring to FIG. 5c, a via electrode (120) can be formed within a via hole (120H). The via electrode (120) can be formed by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0140] The via electrode (120) may include the same material as the wiring layer (130). For example, the via electrode (120) and the wiring layer (130) may be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).

[0141] The upper surface of the via electrode (120) may be formed to be positioned lower than the upper surface of the film layer (117). The via electrode (120) may be formed such that its side is vertical along the via hole (120H) of FIG. 5B. Since the horizontal width of the via electrode (120) is formed uniformly along the vertical direction, the embodiment has a technical effect of preventing a voltage drop at the via electrode.

[0142] In addition, when the via hole of the via electrode (120) is formed to have the same width as the wiring layer (130) in FIG. 5b, the width of the via electrode (120) can be formed to have the same width as the wiring layer (130). Therefore, since the widths of the via electrode (120) and the wiring layer (130) can be formed to be the same, the embodiment has the technical effect of being able to implement a fine pattern and reducing signal interference when the gap between adjacent via electrodes or wiring layers is formed wide. In addition, since the diameters of the via electrode (120) and the wiring layer (130) can be reduced, the number of fine via electrodes or small via electrodes can be increased, thereby having the technical effect of being able to expand the signal transmission path.

[0143] In addition, roughness may not be formed on the side surface of the via electrode (120). The side surface of the via electrode (120) may have a smooth shape and a uniform surface. Accordingly, the embodiment has a technical effect in that a portion where stress is concentrated is not created, thereby preventing cracks or peeling of the via electrode (120), thereby improving reliability, and suppressing signal loss.

[0144]

[0145] Next, referring to FIG. 5d, after removing the film layer (117) of FIG. 5c, an insulating layer (116) can be formed on the build-up insulating portion (110). In addition, the insulating layer (116) can be a film layer and can be referred to as a build-up film layer. The insulating layer (116) can be formed to cover the via electrode (120) and the wiring layer (130). The upper surface of the insulating layer (116) can be positioned higher than the upper surface of the via electrode (120).

[0146]

[0147] Next, referring to FIG. 5e, a thinning process may be performed on the insulating layer (116). A portion of the upper region of the insulating layer (116) may be removed, and the thinning process may use a plasma process, a solder resist thinning solution, sandblasting (spray processing), etc., but is not limited thereto. Accordingly, the upper surface of the insulating layer (116) may be formed lower than the upper surface of the via electrode (120). In addition, roughness (150) may be formed on the upper surface of the insulating layer (116) by the thinning process.

[0148] Meanwhile, in an embodiment, an additional insulating layer or protective layer may be deposited on the insulating layer (116), and the adhesion to the additionally laminated insulating layer may be improved due to the roughness (150) on the upper surface of the insulating layer (116).

[0149] Additionally, the roughness (150) on the upper surface of the insulating layer (116) can be selectively removed. The roughness (150) can be removed by solution treatment.

[0150]

[0151] FIG. 6A and FIG. 6B are electron microscope drawings showing the upper surface of the insulating layer (116) of FIG. 5E. Referring to FIG. 6A, during the process of thinning the insulating layer (116), roughness (150) may be formed on the upper surface of the insulating layer (116). The roughness (150) may be an inorganic filler distributed within the insulating layer (116).

[0152] Next, referring to FIG. 6b, roughness can be removed from the upper surface of the insulating layer (116) of FIG. 6a through a solution treatment process.

[0153]

[0154] Fig. 7a is a cross-sectional view of a circuit board (102) according to the seventh embodiment. Referring to Fig. 7a, the build-up insulation portion (110) may include a first insulation layer (111), a second insulation layer (112), a third insulation layer (113), and a fourth insulation layer (114). In addition, a plurality of via electrodes (120) may be included in the build-up insulation portion (110). The via electrodes (120) may include a first via electrode (121) disposed in the first insulation layer (111), a second via electrode (122) disposed in the second insulation layer (112), a third via electrode (123) disposed in the third insulation layer (113), and a fourth via electrode (125) disposed in the fourth insulation layer (114).

[0155] The first via electrode (121), the second via electrode (122), the third via electrode (123), and the fourth via electrode (124) may have the same horizontal width in the vertical direction. In addition, the widths of the upper and lower surfaces of the first via electrode (121) may be the same. In addition, the widths of the upper and lower surfaces of the second via electrode (122) may be the same. In addition, the widths of the upper and lower surfaces of the third via electrode (123) may be the same. In addition, the widths of the upper and lower surfaces of the fourth via electrode (124) may be the same.

[0156] Additionally, the central axes of the first via electrode (121) to the fourth via electrode (124) may be the same.

[0157] In addition, a plurality of wiring layers (130) may be included within the build-up insulation portion (110). The plurality of wiring layers (130) may include a first wiring layer (131) connected to the lower surface of the first via electrode (121), a second wiring layer (132) connected to the lower surface of the second via electrode (122), a third wiring layer (133) connected to the lower surface of the third via electrode (123), and a fourth wiring layer (134) connected to the lower surface of the fourth via electrode (124).

[0158] Accordingly, the embodiment has a technical effect of improving vertical alignment accuracy and alignment for via electrodes and wiring layers arranged in each of a plurality of insulating layers by ensuring that the horizontal width within each via electrode is constant, and preventing voltage drop.

[0159] Meanwhile, the horizontal width of the first via electrode (121) and the horizontal widths of the second via electrode (122) to the fourth via electrode (124) may be different. In detail, the horizontal width of the first via electrode (121) may be smaller than the horizontal width of the second via electrode (122). In addition, the horizontal width of the first via electrode (121) may be smaller than the horizontal width of the third via electrode (123). In addition, the horizontal width of the first via electrode (121) may be smaller than the horizontal width of the fourth via electrode (124). In addition, the horizontal widths of the second via electrode (122), the third via electrode (123), and the fourth via electrode (124) may be larger than the horizontal width of the first via electrode (121). The horizontal widths of the second via electrode (122), the third via electrode (123), and the fourth via electrode (124) cannot be less than the horizontal width of the first via electrode (121). In addition, the horizontal widths of the second via electrode (122), the third via electrode (123), and the fourth via electrode (124) can be the same.

[0160] In addition, the horizontal width of the first wiring layer (131) may be greater than the horizontal width of the first via electrode (121). The horizontal width of the first wiring layer (131) may be the same as that of the second via electrode (122). In addition, the seventh embodiment includes a case where the horizontal width of the third via electrode (123) is greater than that of the second via electrode (122), and the horizontal width of the fourth via electrode (124) is greater than that of the third via electrode (123), but the second to fourth via electrodes (122) to (124) may be greater than the horizontal width of the first via electrode (121).

[0161] Accordingly, the seventh embodiment has a technical effect of enabling a fine circuit pattern to be implemented in the outermost layer connected to an external element or substrate, since the first via electrode (121) disposed within the first insulating layer (111) adjacent to the outermost layer of the circuit board (102) has a smaller horizontal width than the via electrode disposed within the second insulating layer (112) to the fourth insulating layer (114). In addition, the seventh embodiment has a technical effect of enabling a signal transmission speed to be improved by forming the via electrodes disposed in insulating layers spaced apart from the outermost layer of the circuit board (102) to have a relatively large horizontal width, thereby reducing resistance.

[0162] Meanwhile, in FIG. 7a, the horizontal width of the first wiring layer (131) is shown to be the same as that of the second via electrode (122), but the seventh embodiment may include a case where the first wiring layer (131) is larger than the horizontal width of the second via electrode (121), as in FIG. 3a or FIG. 4a.

[0163] In addition, the cross-section of the via electrode (120) may be rectangular. The via electrode (120) may include a cylindrical shape. In addition, the diameter of each of the plurality of via electrodes (120) may be the same along the vertical direction. Accordingly, the embodiment has a technical effect of preventing voltage drop as the diameter of each of the via electrodes (120) is formed to be the same according to the height.

[0164] In addition, the upper surface of the first via electrode (121) may be positioned higher than the first insulating layer (111). Roughness may be formed on the upper surface of the first insulating layer (111). In addition, a surface treatment layer (160) may be disposed on the first via electrode (121). The surface treatment layer (160) may cover the upper surface of the first via electrode (121) and may be in contact with the first insulating layer (111). A connection portion may be disposed on the surface treatment layer (160) to be electrically connected to an external element or a substrate.

[0165]

[0166] FIG. 7B is a drawing showing the second region (A2) of FIG. 7A in detail. Referring to FIG. 7B, a first via electrode (121) may be arranged to penetrate a first insulating layer (111). Meanwhile, the first insulating layer (111) may include an inorganic filler (155), and the inorganic filler (155) may not be in contact with a side surface of the first via electrode (121). In detail, the first insulating layer (111) facing the side surface of the first via electrode (121) within the via hole in which the first via electrode (121) is formed may not expose the inorganic filler. Accordingly, the side surface of the first via electrode (121) may have a uniform surface. Accordingly, the embodiment has a technical effect in that structural reliability may be improved because the side surface of the via electrode is uniformly formed, thereby not having a region where stress is concentrated, and signal transmission loss may be prevented.

[0167] In addition, the upper surface of the first via electrode (121) may have a flat shape. In addition, a part of the upper surface of the first via electrode (121) may include a slope. In addition, a surface treatment layer (160) may be disposed on the first via electrode (121). As the surface treatment layer (160) is formed along the upper surface of the first via electrode (121), it may come into contact with the upper surface of the first insulating layer (111). In addition, as the upper surface of the first insulating layer (111) includes roughness (150), the interface where the surface treatment layer (160) comes into contact with the first insulating layer (111) may include roughness. Accordingly, there is a technical effect that the adhesive strength of the surface treatment layer (160), the first via electrode (121), and the first insulating layer (111) may be improved.

[0168]

[0169] Fig. 8 is a cross-sectional view of a semiconductor package (103) according to an eighth embodiment. The eighth embodiment may include the circuit board of the first to seventh embodiments. Referring to Fig. 8, the semiconductor package (103) according to the eighth embodiment may include a chip (200) placed on a circuit board. In detail, a connection portion (190) may be placed on a first wiring layer (131) exposed by a first protective layer (140) on the outermost layer of the circuit board. The connection portion (190) may have a spherical shape. In addition, a cross-section of the connection portion (190) may have a circular shape or a semicircular shape. The connection portion (190) may be a solder ball, but is not limited thereto.

[0170] In addition, the embodiment may further include a bonding portion on the first protective layer (140). The bonding portion is positioned on the upper surface of the first protective layer (140) to perform thermal compression bonding with the semiconductor element, and may be used when the pitch of the first wiring layer (131) becomes fine and it is difficult to implement with conventional solder bonding.

[0171] In addition, a chip (200) or a component may be included on the connection portion (190) of the circuit board. The chip (200) may be a processor chip. For example, the chip (200) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (205) may be included on the bottom surface of the chip (200), and a plurality of terminals (210) may be included.

[0172] The terminal (205) of the chip (200) can be electrically connected to the connection portion (190) of the circuit board.

[0173] Meanwhile, the semiconductor package (103) of the embodiment may include a plurality of chips that are arranged and horizontally spaced apart from each other on a single circuit board. For example, the chip (200) may also include a first chip and a second chip. The first chip and the second chip may be different types of application processor (AP) chips.

[0174] Additionally, the connection portion located at the bottom of the semiconductor package (101) of the embodiment may be for connecting a main board (or motherboard) of an external device.

[0175] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0176] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0177] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0178] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A built-up insulation comprising a plurality of insulating layers laminated along a vertical direction; A via electrode arranged in a via hole provided in the above plurality of insulating layers; and A wiring layer connected to the above via electrode; At least one of the above multiple insulating layers comprises an inorganic filler, The insulating layer facing the side of the via electrode within the via hole does not expose the inorganic filler, The horizontal width of the above via electrode is the same along the vertical direction, circuit board.

2. In paragraph 1, A circuit board wherein the horizontal width of the above wiring layer is the same as the horizontal width of the above via electrode.

3. In paragraph 1, A circuit board, wherein the plurality of insulating layers include a first insulating layer and a second insulating layer disposed on the first insulating layer.

4. In paragraph 3, The above via electrode includes a first via electrode disposed within the first insulating layer and a second via electrode disposed within the second insulating layer, A circuit board, wherein both side surfaces of the first via electrode and both side surfaces of the second via electrode are positioned in the same vertical line.

5. In paragraph 3, A circuit board, wherein the above via electrode includes a through via electrode penetrating the first insulating layer and the second insulating layer.

6. In paragraph 3, A circuit board comprising roughness on an upper surface of the second insulating layer.

7. A build-up insulation member comprising a first insulation layer, a second insulation layer, and a third insulation layer laminated along a vertical direction; A plurality of via electrodes each arranged in a via hole provided in the first insulating layer, the second insulating layer, and the third insulating layer; and It includes a plurality of wiring layers each connected to the plurality of via electrodes; At least one of the first insulating layer, the second insulating layer and the third insulating layer comprises an inorganic filler, The above plurality of via electrodes includes a first via electrode disposed in the first insulating layer, a second via electrode disposed in the second insulating layer, and a third via electrode disposed in the third insulating layer. The horizontal width of each of the above plurality of via electrodes is the same along the vertical direction, A circuit board, wherein the horizontal width of the first via electrode is smaller than the horizontal width of the second via electrode and the horizontal width of the third via electrode.

8. In paragraph 10, A circuit board, wherein the center axes of the first via electrode, the second via electrode, and the third via electrode are identical to each other.

9. In paragraph 10, A circuit board, wherein the insulating layer facing the side of the via electrode within the via hole does not expose the inorganic filler.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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