Memory structure and integration method therefor

Abstract

A memory structure and an integration method therefor, relating to the technical field of semiconductors. The memory structure is located on a semiconductor substrate, and comprises, from bottom to top, a transistor layer, a middle metal interconnection layer, an amplification capacitance layer, and an upper metal interconnection layer, wherein the transistor layer comprises an N-type low-power-consumption bidirectional-conduction device and a P-type low-power-consumption bidirectional-conduction device which are arranged side by side; the middle metal interconnection layer comprises contact holes, SN interconnection line through holes, metal interconnection lines, inter-contact-hole media, and inter-metal-interconnection-line media; the amplification capacitance layer comprises a lower electrode plate layer, a dielectric layer, and an upper electrode plate layer; and the upper metal interconnection layer comprises upper electrode plate through holes, a metal interconnection line, the inter-contact-hole media, and the inter-metal-interconnection-line media. The memory structure is prepared through monolithic integration with a silicon-based CMOS, and has the advantages of no crosstalk, low power consumption and having a read-write speed satisfying circuit requirements, and the integration method for the memory structure has low costs and high technical iterability.

Description

A memory structure and its integration method Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory structure and an integration method thereof. Background Art

[0002] With the continuous advancement of semiconductor technology, device size continues to decrease, circuit performance continues to improve, and chip power density is rapidly increasing. Low power consumption has become a key design trend. Traditional MOSFET devices are limited by the drift-diffusion conduction mechanism, with a subthreshold slope exceeding 60mV / dec, resulting in a trade-off between optimizing the off-state current and the on-state current. Therefore, there is a need to invent a new low-power dual-conductance device and a memory based on this device. Summary of the Invention

[0003] In order to solve the problems in the prior art, the present invention proposes a memory structure and an integration method thereof. The memory structure includes a new low-power dual-conductor device, thereby having lower power consumption than traditional memory while having no read-write crosstalk.

[0004] The technical solutions of the present invention are as follows:

[0005] A memory structure, characterized in that it is located on a semiconductor substrate and includes, from bottom to top, a transistor layer, an intermediate metal interconnect layer, an amplifying capacitor layer, and an upper metal interconnect layer. The transistor layer includes two low-power dual-conducting devices placed side by side, a P-type low-power dual-conducting device on the left and an N-type low-power dual-conducting device on the right. The intermediate metal interconnect layer includes contact holes, SN interconnect line vias, metal interconnect lines, a dielectric between contact holes, and a dielectric between metal interconnect lines. The amplifying capacitor layer includes a lower plate layer, a dielectric layer, and an upper plate layer. The upper metal interconnect layer includes an upper plate via, a metal interconnect line, a dielectric between contact holes, and a dielectric between metal interconnect lines.

[0006] Specifically, the lead electrodes of the two devices in the transistor layer are connected one-to-one with the contact holes in the middle metal interconnect layer. For the P-type low-power dual-conductance device on the left, the lead electrodes are, from left to right, the substrate lead electrode, drain electrode, gate electrode, and source electrode. For the N-type low-power dual-conductance device on the right, the lead electrodes are, from left to right, the drain electrode, gate electrode, source electrode, and substrate lead electrode. The contact holes in the middle metal interconnect layer are several rectangular parallelepipeds, with the center of the contact holes filled with inter-contact hole dielectric. The metal interconnect lines in the middle metal interconnect layer are several rectangular parallelepipeds, with the center of the metal interconnect lines filled with inter-metal interconnect line dielectric. The metal interconnect lines are divided into lower metal interconnect lines and upper metal interconnect lines. The bottom of the contact hole is connected to the lead electrode of the low-power dual-conductance device in the transistor layer, and the top of the contact hole is connected to the lower metal interconnect line. The specific connection relationship is as follows: the substrate lead electrode of the P-type low-power dual-conductance device is connected to the VDD metal interconnect line through a contact hole, the drain electrode of the P-type low-power dual-conductance device is connected to the WBL metal interconnect line through a contact hole, the gate electrode of the P-type low-power dual-conductance device is connected to the WWL metal interconnect line through a contact hole, the source electrode of the P-type low-power dual-conductance device is connected to the SN metal interconnect line through a contact hole, the drain electrode of the N-type low-power dual-conductance device is connected to the RBL metal interconnect line through a contact hole, the gate electrode of the N-type low-power dual-conductance device is connected to the SN metal interconnect line through a contact hole, the source electrode of the N-type low-power dual-conductance device is connected to the VSS metal interconnect line through a contact hole, and the substrate electrode of the N-type low-power dual-conductance device is connected to the VDD metal interconnect line through a contact hole. The two SN metal interconnect lines in the lower metal interconnect line are connected to the upper metal interconnect line through two SN interconnect line vias. The lower plate layer, dielectric layer, and upper plate layer in the amplifying capacitor layer are three rectangular parallelepipeds of equal size, arranged in order from bottom to top. The bottom of the lower plate layer is connected to the upper metal interconnect line of the middle metal interconnect layer, and the top of the upper plate layer is connected to the upper plate via of the upper metal interconnect layer. The upper plate vias are composed of several rectangular parallelepipeds. The areas between the upper plate vias and the outer areas of the amplified capacitor layer are filled with inter-contact dielectric. The upper plate vias are connected to the RWL metal interconnect line, and the outer areas of the RWL metal interconnect line are filled with inter-metal interconnect dielectric.

[0007] Specifically, the materials other than the low-power dual-conductance device in the above memory structure are:

[0008] The material of the upper plate layer and the lower plate layer is a metal or a combination of metals such as titanium nitride, tantalum nitride, tungsten, titanium, and tantalum. The material of the dielectric layer is an oxide dielectric material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide (HZO), and silicon oxide (SiO2). The material of the metal interconnect is a combination of copper, tantalum, and tantalum nitride, or aluminum. The material of the upper plate through hole and the SN interconnect through hole is the same as the material of the metal interconnect. The material of the contact hole is either a combination of tungsten, titanium, titanium nitride, or aluminum. The material of the intermetallic dielectric layer and the dielectric layer between the contact holes is silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a combination of other dielectric materials with a dielectric constant not greater than that of silicon dioxide and silicon nitride.

[0009] The following is a detailed description of the low-power dual-conductor device:

[0010] This low-power dual-conductance device includes six parts: a gate region, a source region, a drain region, a channel region, a substrate region, and a substrate lead-out region. The device can be manufactured based on a semiconductor substrate and is characterized by:

[0011] In terms of spatial location, the device's boundaries are defined by three adjacent shallow trench isolations. The device's gate, source, drain, channel, and substrate regions are all laterally located within the two shallow trench isolations on one side, while the device's substrate lead-out region is located within the two shallow trench isolations on the other side. The source, drain, channel, substrate, and substrate lead-out regions are located on the same semiconductor substrate. The source, drain, and channel regions are located near the surface of the semiconductor substrate, lateral direction in the order of source, channel, and drain regions. The spatial locations of the source and drain regions are interchangeable. The substrate region is located below the source, channel, and drain regions. The gate region is located above the semiconductor substrate.

[0012] Geometrically, the gate region consists of four parts: a gate dielectric layer, a gate conductive layer, a gate metal layer, and a gate isolation layer. These layers are arranged in order from bottom to top, with the gate metal layer serving as the gate electrode. The gate isolation layer consists of a compensation isolation layer and a composite main isolation layer. The compensation isolation layer is located on the gate sidewalls near the source region and on the gate sidewalls near the drain region, while the composite main isolation layer is located on the compensation isolation layer near the drain region. The source region consists of a source metal layer and a source semiconductor layer, with the source metal layer serving as the source electrode. The source metal layer is located vertically at the surface of the semiconductor substrate and at a certain depth within it. The source metal layer is located laterally from the gate sidewalls near the source region to the source region boundary. The source semiconductor layer wraps around the source metal layer and has a certain width. The source semiconductor layer consists of a source extension layer and a source doping layer. The source extension layer completely wraps around the source metal layer, but the wrapping width is relatively narrow. The source doping layer laterally wraps only a portion of the source metal layer near the source region boundary, and the source doping layer vertically wraps around a relatively wide width of the source metal layer. The drain region consists of a drain metal layer and a drain semiconductor layer, with the drain metal layer serving as a drain electrode. The drain metal layer is located vertically on the surface of the semiconductor substrate and at a certain depth within it. Laterally, the drain metal layer is located near the boundary of the composite main isolation layer near the drain region to the boundary of the drain region. The drain semiconductor layer wraps around the drain metal layer and has a certain width. The drain semiconductor layer consists of a drain extension layer and a drain doping layer. The drain extension layer completely wraps the drain metal layer but has a narrower wrapping width. The drain doping layer also completely wraps the drain metal layer but has a wider wrapping width. The channel region is located vertically on the surface of the semiconductor substrate and at a certain depth within it, with a depth consistent with that of the source and drain regions. Laterally, it is located between the source and drain regions and consists of a channel semiconductor layer. The substrate region is located vertically within the semiconductor substrate and below the source, drain, and channel regions. Laterally, it is located between the boundary of the source and drain regions. It consists of a first substrate layer, an upper well layer, and a lower well layer. The first substrate layer is located vertically between the upper boundary of the substrate region and the upper boundary of the upper well layer. The upper boundary of the upper well layer is greater than 200 nm from the surface of the semiconductor substrate. The lower boundary of the upper well layer is located near the bottom of the shallow trench isolation. The upper boundary of the lower well layer coincides with the lower boundary of the upper well layer, and the lower boundary of the lower well layer is the lower boundary of the substrate region. The lower well layer of the substrate region is led out through a substrate lead-out region, which includes an N-type lead-out well, an N-type implant region, and a substrate metal layer. The substrate metal layer serves as a substrate electrode.

[0013] In terms of material composition, the gate dielectric layer can be made of SiO2, a stack of SiO2 and HfO2, or a stack of SiO2 and impurity-doped HfO2. The impurities in the impurity-doped HfO2 can include silicon (Si), lanthanum (La), zirconium (Zr), aluminum (Al), titanium (Ti), nitrogen (N), etc. The gate dielectric layer has a thickness between 1nm and 5nm. The gate conductive layer can be made of impurity-doped polysilicon or a stack of multilayer metals. For N-type devices, the impurities in the polysilicon can be phosphorus or arsenic. The multilayer metal stacks include TiN, TaN, TiAl, Al, etc. For P-type devices, the impurities in the polysilicon can be boron or boron fluoride. The multilayer metal stacks include TiN, TaN, etc. The gate conductive layer has a thickness between 10nm and 500nm. The gate metal layer is made of metal silicides such as nickel silicon, titanium silicon, or cobalt silicon. The compensation isolation layer material can be a stacked material of silicon oxide and silicon nitride or silicon oxynitride, and the thickness of the compensation isolation layer is between 2nm and 20nm. The composite main isolation layer material is a stacked material composed of silicon oxide and silicon nitride or silicon oxynitride, and the thickness of the composite main isolation layer is between 20nm and 70nm. The source metal layer and the drain metal layer material can be metal silicides such as nickel silicon, titanium silicon or cobalt silicon. The source semiconductor layer material is a heavily doped semiconductor material such as heavily doped silicon (Si), heavily doped silicon germanium (SiGe) or heavily doped silicon carbon (SiC), with a peak doping concentration greater than 1E20cm -3 If it is a P-type device, the doping type of the source semiconductor layer is N-type, and the doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. If it is an N-type device, the doping type of the source semiconductor layer is P-type, and the doping impurities can be trivalent elements such as boron or boron fluoride and their compounds. The drain semiconductor layer material is a heavily doped semiconductor material such as heavily doped silicon (Si), heavily doped silicon germanium (SiGe) or heavily doped silicon carbon (SiC), with a peak doping concentration greater than 1E20cm -3 If it is an N-type device, the doping type of the drain semiconductor layer is N-type, and the doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. If it is a P-type device, the doping type of the drain semiconductor layer is P-type, and the doping impurities can be trivalent elements such as boron or boron fluoride and their compounds. The channel semiconductor layer material is lightly doped silicon, and the doping type can be N-type or P-type, with a doping concentration less than 1E16cm -3 If it is N-type doping, the doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. If it is P-type doping, the doping impurities can be trivalent elements such as boron or boron fluoride and their compounds. The first substrate layer is lightly doped silicon, the doping type can be N-type or P-type, and the doping concentration is less than 1E16cm -3If it is N-type doping, the doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. If it is P-type doping, the doping impurities can be trivalent elements such as boron or boron fluoride and their compounds. The upper well layer material is medium-doped silicon, the doping type is P-type, and the peak doping concentration is greater than 5E16cm -3 The doping impurities can be trivalent elements such as boron or boron fluoride and their compounds. The lower well layer material is medium-doped silicon, the doping type is N-type, and the peak doping concentration is greater than 5E16cm -3 The doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. The shallow trench isolation material is an oxide such as silicon oxide. The material of the N-type extraction well and the N-type injection region is medium-doped silicon. The doping impurities can be pentavalent elements such as phosphorus or arsenic and their compounds. The peak doping concentration of the N-type extraction well is greater than 5E16cm -3 , the peak doping concentration of the N-type implantation region is greater than 1E18cm -3 The substrate metal layer material is metal silicide such as nickel silicon, titanium silicon or cobalt silicon.

[0014] The memory structure proposed in the present invention has the advantages of low power consumption, no crosstalk, and read and write speeds that can meet circuit requirements. This is due to the following characteristics of the proposed low-power dual-conductor device:

[0015] 1. The proposed low-power dual-conductor device can achieve bidirectional conduction, making the designed memory structure crosstalk-free.

[0016] Taking an N-type low-power dual-conductance device as an example, when the device is in the on state (i.e., when the channel surface is inverted), a Schottky junction is formed between the source metal layer and the source semiconductor layer, and a PN junction is formed between the channel surface inversion layer and the source semiconductor layer. Therefore, the proposed device has two current paths. The first current path is that carriers enter the channel surface inversion layer from the source metal layer by Schottky thermal emission and Schottky direct tunneling, then enter the drain semiconductor layer by drift diffusion, and then enter the drain metal layer by Schottky thermal emission and Schottky direct tunneling. The second current path is that carriers enter the source semiconductor layer by Schottky thermal emission and Schottky direct tunneling, then enter the channel surface inversion layer by band-to-band tunneling, then enter the drain semiconductor layer by drift diffusion, and finally enter the drain metal layer by Schottky thermal emission and Schottky direct tunneling. When the drain voltage is higher than the source voltage, the source and drain semiconductor layers form a reverse-biased PN junction. The second current path dominates, with current flowing from the drain to the source. When the source voltage is higher than the drain voltage, the source and drain semiconductor layers form a forward-biased PN junction. The first current path dominates, with current flowing from the source to the drain. Because the conduction capabilities of both the first and second current paths are controlled by the device's gate voltage, the proposed low-power dual-conductance device can achieve bidirectional conduction. The same applies to P-type devices.

[0017] 2. It has the advantage of low static power consumption, which makes the designed memory structure have low power consumption advantage

[0018] Taking an N-type low-power dual-conductance device as an example, when the channel surface is in an accumulation state, a PN junction forms between the channel surface accumulation layer and the drain semiconductor layer. If the gate-drain voltage difference of the device is high, causing the PN junction to be reverse-biased and the tunneling window to open, holes will enter the channel surface accumulation layer through band-to-band tunneling from the drain semiconductor layer, thereby increasing the device's off-state current. However, in the device designed by the present invention, the drain metal layer is located laterally from the composite main isolation layer boundary near the drain region to the drain region boundary, and the drain semiconductor layer wraps around the drain metal layer and has a relatively narrow width. This results in the drain semiconductor layer being at a relatively wide distance from the gate boundary near the drain end, approximately equivalent to the width of the composite main isolation layer. Furthermore, the channel surface accumulation layer is primarily located below the gate region, thereby increasing the minimum tunneling width between the channel surface accumulation layer and the drain semiconductor layer. This helps suppress band-to-band tunneling current between the channel surface accumulation layer and the drain semiconductor layer, reducing the device's off-state current, and thus giving the proposed low-power dual-conductance device the advantage of low static power consumption. The same applies to P-type devices.

[0019] In addition, the upper well layer and the lower well layer in the substrate region form a zero-bias or reverse-biased PN junction in the actual circuit, which can suppress leakage between the source semiconductor layer and the drain semiconductor layer of the same doping type between adjacent devices, thereby further reducing static power consumption.

[0020] 3. The conduction current can meet the actual circuit working requirements, so that the read and write speed of the designed memory structure can meet the circuit requirements.

[0021] In the proposed low-power dual-conductor device, the impurities doped in the source semiconductor layer have different solid solubility between the metal and the semiconductor, which causes the position of the impurity peak concentration in the semiconductor to shift to the boundary between the source metal layer and the source semiconductor layer, thereby thinning the tunneling barrier between the inversion layer on the channel surface and the source semiconductor layer and increasing the probability of band-to-band tunneling. It also thins the tunneling barrier between the inversion layer on the channel surface and the source metal layer and increases the probability of direct tunneling. Therefore, the Schottky direct tunneling current in the first current path and the band-to-band tunneling current in the second current path can be increased, ultimately increasing the on-current of the device so that the on-current can meet the actual circuit operation requirements.

[0022] The above memory structure can be prepared by the following integration method.

[0023] A method for integrating the proposed memory structure with a silicon-based CMOS monolithic chip is characterized by comprising the following steps:

[0024] Step 1: Select a high-resistance silicon wafer for device and circuit preparation;

[0025] Step 2: Form shallow trench isolation (STI). The specific method is to define the active area by using photolithography and hard mask, then etch silicon trenches in an anisotropic manner outside the active area. The silicon trenches are then filled with oxide. Rapid thermal annealing (RTA) is then used to make the filled oxide harder. After filling, the surface is planarized by CMP.

[0026] Step 3: Grow a new sacrificial oxide layer on the silicon wafer surface, and then define the nMOSFET device area by photolithography;

[0027] Step 4: Form the P-type doped well of the nMOSFET device by ion implantation, and then remove the resin after implantation;

[0028] Step 5: Define the pMOSFET device area and the substrate lead-out area of ​​the low-power dual-conductor device by photolithography;

[0029] Step 6: Form the N-type doped well of the pMOSFET device and the N-type extraction well of the low-power dual-conductor device by ion implantation, and then remove the resin after implantation;

[0030] Step 7: Define the low-power dual-conductor device area by photolithography;

[0031] Step 8: Form the upper well layer and the lower well layer of the low-power dual-conductor device by ion implantation, and then remove the resin after implantation;

[0032] Step 9: Annealing to remove defects caused by ion implantation and activate ion implanted impurities;

[0033] Step 10: Forming the gate dielectric layer of the CMOS device and the low-power dual-conductor device. The specific method is to deposit dielectric layers of different thicknesses in the core tube and IO tube regions respectively, and pattern them by photolithography, hard mask and etching;

[0034] Step 11: forming a gate conductive layer of the CMOS device and the low-power dual-conductor device by depositing a gate conductive layer material and patterning it by photolithography, hard masking, and etching;

[0035] Step 12: Annealing to improve the reliability of the gate dielectric layer and the conductivity of the gate conductive layer;

[0036] Step 13: forming a compensation isolation layer on the gate sidewall, specifically depositing a re-oxidation layer on the gate sidewall, then depositing an isolation dielectric layer, and then performing anisotropic etching back;

[0037] Step 14: Define the nMOSFET device area, the pMOSFET substrate lead-out area, and the low-power dual-conductor device substrate lead-out area by photolithography;

[0038] Step 15: Forming the NLDD region of the nMOSFET device, the NLDD region of the substrate lead-out region of the pMOSFET device, and the N-type implantation region in the substrate lead-out region of the low-power dual-conductor device by ion implantation, and then removing the resist after implantation;

[0039] Step 16: Define the pMOSFET device area and the nMOSFET substrate lead-out area by photolithography;

[0040] Step 17: Form the PLDD region of the pMOSFET device and the PLDD region of the substrate lead-out region of the nMOSFET device by ion implantation, and then remove the resin after implantation;

[0041] Step 18: Annealing to remove defects caused by ion implantation and activate ion implanted impurities;

[0042] Step 19: forming a composite main isolation layer on the gate sidewall, specifically by depositing a main isolation dielectric layer on the gate sidewall and then performing anisotropic etching back;

[0043] Step 20: defining the nMOSFET device region and the substrate lead-out region of the pMOSFET, the substrate lead-out region of the low-power dual-conductance device, and the N-type doped source doping layer and the N-type doped drain doping layer in the low-power dual-conductance device by photolithography or hard mask;

[0044] Step 21: forming the N+SD region of the nMOSFET, the N+SD region of the substrate lead-out region of the pMOSFET device, the N-type implanted region of the substrate lead-out region of the low-power dual-conducting device, and the N-type doped source doping layer and the N-type doped drain doping layer in the low-power dual-conducting device by ion implantation or epitaxy, and then stripping the resist or removing the hard mask;

[0045] Step 22: defining the pMOSFET device region, the substrate lead-out region of the nMOSFET device, and the P-type doped source doping layer and the P-type doped drain doping layer in the low-power dual-conducting device by photolithography or hard mask;

[0046] Step 23: Form the P+SD region of the pMOSFET, the P+SD region of the nMOSFET device substrate lead-out region, and the P-type doped source doping layer and the P-type doped drain doping layer in the low-power dual-conductivity device by ion implantation or epitaxy, and then remove the resist or hard mask;

[0047] Step 24: Annealing to remove defects caused by ion implantation and activate ion implanted impurities;

[0048] Step 25: Use a hard mask to define the source region of the low-power dual-conductor device;

[0049] Step 26: Remove the composite main isolation layer at the source end of the low-power dual-conductor device by etching, and retain the compensation isolation layer;

[0050] Step 27: Remove the hard mask and define the N-type doped source extension layer and the N-type doped drain extension layer in the low-power dual-conductor device by photolithography;

[0051] Step 28: Forming an N-type doped source extension layer and an N-type doped drain extension layer in the low-power dual-conductor device by ion implantation, and then removing the resist after implantation;

[0052] Step 29: Defining a P-type doped source extension layer and a P-type doped drain extension layer in the low-power dual-conductor device by photolithography;

[0053] Step 30: forming a P-type doped source extension layer and a P-type doped drain extension layer in the low-power dual-conductivity device by ion implantation, and performing resist removal after implantation;

[0054] Step 31: Annealing to remove defects caused by ion implantation and activate ion implanted impurities;

[0055] Step 32: Forming self-aligned metal silicide, wherein the self-aligned silicide in the source region and the self-aligned silicide in the drain region of the low-power dual-conducting device form the source metal layer and the drain metal layer of the low-power dual-conducting device, the self-aligned silicide in the gate region of the low-power dual-conducting device forms the gate electrode of the low-power dual-conducting device, and the self-aligned metal silicide in the substrate lead-out region of the low-power dual-conducting device forms the substrate electrode of the low-power dual-conducting device. The specific method is to remove the oxide on the device surface and then form metal silicide on the silicon and polysilicon surfaces by depositing metal, annealing, etching excess metal and metal silicide, etc.

[0056] Step 33: forming a dielectric layer between the contact holes, specifically by growing the dielectric layer between the contact holes by chemical vapor deposition (CVD) and planarizing the surface by chemical mechanical polishing;

[0057] Step 34: defining a contact hole region outside the gate contact hole by photolithography, and forming the contact hole region outside the gate contact hole by reactive ion etching (RIE) and wet etching;

[0058] Step 35: Filling the contact hole material and planarizing the surface by chemical mechanical polishing to form contact holes other than the gate contact hole;

[0059] Step 36: Define the gate contact hole region by photolithography, and form the gate contact hole region by reactive ion etching (RIE) and wet etching;

[0060] Step 37: Fill the contact hole material and smooth the surface by chemical mechanical polishing to form a gate contact hole;

[0061] Step 38: forming an intermetallic dielectric layer by growing the intermetallic dielectric layer using a chemical vapor deposition (CVD) method and planarizing the surface using a chemical mechanical polishing method;

[0062] Step 39: Defining the metal interconnection area by photolithography, and forming the metal interconnection area by reactive ion etching (RIE) and wet etching;

[0063] Step 40: Filling the metal interconnection material and smoothing the surface by chemical mechanical polishing to form the metal interconnection;

[0064] Step 41: forming a dielectric layer between the contact holes, specifically by growing the dielectric layer between the contact holes by chemical vapor deposition (CVD) and planarizing the surface by chemical mechanical polishing;

[0065] Step 42: defining the SN interconnection line through-hole region by photolithography, and forming the SN interconnection line through-hole region by reactive ion etching (RIE) and wet etching;

[0066] Step 43: Filling the SN interconnection line through-hole material and planarizing the surface by chemical mechanical polishing to form the SN interconnection line through-hole;

[0067] Step 44: forming an intermetallic dielectric layer by growing the intermetallic dielectric layer using a chemical vapor deposition (CVD) method and planarizing the surface thereof by a chemical mechanical polishing method;

[0068] Step 45: Defining the metal interconnection area by photolithography, and forming the metal interconnection area by reactive ion etching (RIE) and wet etching;

[0069] Step 46: Filling the metal interconnection material and smoothing the surface by chemical mechanical polishing to form the metal interconnection;

[0070] Step 47: depositing lower electrode layer material, dielectric layer material, and upper electrode layer material;

[0071] Step 48: Patterning the capacitor by photolithography and reactive ion etching (RIE);

[0072] Step 49: forming a dielectric layer between the contact holes, specifically by growing the dielectric layer between the contact holes by chemical vapor deposition (CVD) and planarizing the surface by chemical mechanical polishing;

[0073] Step 50: defining the upper plate through-hole region by photolithography, and forming the upper plate through-hole region by reactive ion etching (RIE);

[0074] Step 51: Fill the upper plate through-hole material and smooth the surface by chemical mechanical polishing to form the upper plate through-hole;

[0075] Step 52: forming an intermetallic dielectric layer by growing the intermetallic dielectric layer using a chemical vapor deposition (CVD) method and planarizing the surface using a chemical mechanical polishing method;

[0076] Step 53: Defining the metal interconnection area by photolithography, and forming the metal interconnection area by reactive ion etching (RIE) and wet etching;

[0077] Step 54: Filling the metal interconnection material and smoothing the surface by chemical mechanical polishing to form metal interconnection lines;

[0078] Step 55: Annealing.

[0079] Further, specifically:

[0080] The doping type of the wafer in step 1 can be boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm;

[0081] The thickness of STI in step 2 should be between 200nm and 1000nm;

[0082] In step 3, the thickness of the sacrificial oxide layer is between 1 nm and 2 nm;

[0083] The ion implantation conditions in steps 4 and 6 are the well implantation conditions in mature CMOS processes. The impurities of the P-type doped wells may be boron or boron fluoride, and the impurities of the N-type doped wells may be phosphorus or arsenic.

[0084] The impurities implanted by ion implantation in step 8 are of two types: N-type and P-type. The N-type impurities can be phosphorus or arsenic. The implantation energy is between 100keV and 500keV, and the implantation dose is 2E12cm -2 to 5E13cm -2 The P-type impurity can be boron or boron fluoride, with an injection energy of 40keV to 300keV and an injection dose of 2E12cm -2 to 5E13cm -2 between;

[0085] The annealing conditions in step 9 are the annealing conditions for doped wells in mature CMOS processes;

[0086] The gate dielectric layer material in step 10 can be SiO2, a stacked material composed of SiO2 and HfO2, or a stacked material composed of SiO2 and impurity-doped HfO2. The impurities in the impurity-doped HfO2 can be silicon (Si), lanthanum (La), zirconium (Zr), aluminum (Al), titanium (Ti), nitrogen (N), etc. The thickness of the gate dielectric layer material is between 1nm and 5nm. The hard mask is used to define the core tube and IO tube device areas. The hard mask material can be a stacked material of silicon nitride or silicon oxynitride and silicon oxide.

[0087] The gate conductive layer material in step 11 can be an impurity-doped polysilicon material, or a stacked material composed of multiple metal layers. For N-type devices, the dopant impurities in the polysilicon can be phosphorus or arsenic, and the multilayer metal stacked materials include TiN, TaN, TiAl, Al, etc. For P-type devices, the dopant impurities in the polysilicon can be boron or boron fluoride, and the multilayer metal stacked materials include TiN, TaN, etc. The thickness of the gate conductive layer material is between 10 nm and 500 nm, and the hard mask material can be silicon nitride or a stacked material of silicon oxynitride and silicon oxide;

[0088] The annealing conditions in step 12 are the annealing conditions for the gate dielectric layer and the gate conductive layer in a mature CMOS process;

[0089] The isolation layer material in step 13 may be silicon nitride or silicon oxynitride, and the thickness of the compensation isolation layer is between 2 nm and 20 nm;

[0090] The ion implantation conditions in step 15 and step 17 are the NLDD and PLDD implantation conditions in a mature CMOS process. The impurities in the PLDD may be boron, boron fluoride, germanium, carbon, etc., and the impurities in the N-type doped well may be phosphorus, arsenic, germanium, carbon, etc.

[0091] The annealing conditions in step 18 are the annealing conditions for NLDD and PLDD in mature CMOS processes;

[0092] The main isolation dielectric layer in step 19 is made of a laminated material composed of silicon oxide and silicon nitride or silicon oxynitride, and the thickness of the main isolation dielectric layer is between 20 nm and 70 nm.

[0093] The hard mask material in step 20 and step 22 may be silicon nitride or a stacked material of silicon oxynitride and silicon oxide;

[0094] The ion implantation conditions in step 21 are N+ SD implantation conditions in mature CMOS processes. The implanted impurities may be phosphorus, arsenic, germanium, etc., and the epitaxial material may be phosphorus-doped silicon or phosphorus-doped silicon carbide (SiC).

[0095] The ion implantation conditions in step 23 are the P+SD implantation conditions in mature CMOS processes. The implanted impurities may be boron, boron fluoride, germanium, etc., and the epitaxial material may be boron-doped silicon or boron-doped silicon germanium (SiGe).

[0096] The annealing conditions in step 24 are the annealing conditions for N+ SD and P+ SD in mature CMOS processes;

[0097] The hard mask material in step 25 may be silicon nitride or a stacked material of silicon oxynitride and silicon oxide;

[0098] The purpose of step 26 is to form the source metal layer and the drain metal layer in a self-aligned manner in the proposed device in combination with step 32;

[0099] The ion implantation impurities in step 28 can be phosphorus or arsenic, with an implantation energy between 1keV and 30keV and an implantation dose of 1E15cm -2 to 1E16cm -2 between;

[0100] The ion implantation impurity in step 30 may be boron or boron fluoride, with an implantation energy between 1 keV and 30 keV and an implantation dose of 1E15 cm-2 to 1E16cm -2 between;

[0101] The annealing method in step 31 is laser annealing, the annealing temperature is between 1000° C. and 2000° C., and the annealing time is between 0.1 ms and 1000 s;

[0102] The metal deposited in step 32 may be titanium, nickel, cobalt, or other metal that can react with silicon or polysilicon to form metal silicide;

[0103] The method of filling the metal interconnection line material, contact hole material, SN interconnection line through-hole material and upper electrode through-hole material in steps 35 to 54 is one of magnetron sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD) or electroplating, or a combination thereof;

[0104] The thickness of the dielectric layer material between the contact holes in step 33, step 41 and step 49 is between 80 nm and 250 nm;

[0105] The thickness of the intermetallic dielectric layer material in steps 38, 44 and 52 is between 120 nm and 500 nm;

[0106] In step 47, the method for depositing the lower electrode layer material and the upper electrode layer material is one of magnetron sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD), and the method for depositing the dielectric layer material is atomic layer deposition (ALD);

[0107] The annealing method in step 55 can be one of rapid thermal annealing (RTA), furnace annealing, laser annealing or spike annealing, or a combination of several annealing methods.

[0108] The specific technical effects of the integration method proposed in the present invention are as follows:

[0109] 1. The integration method proposed in the present invention can be used to integrate the proposed memory and silicon-based CMOS devices into a single chip on the existing silicon-based CMOS logic process platform, with low cost.

[0110] The memory structure and integration method proposed in the present invention can be manufactured using the existing silicon-based CMOS logic process platform without introducing additional thermal budget, without changing the corresponding process of the CMOS device, and without affecting the performance of the CMOS device. Therefore, the memory structure and integration method proposed in the present invention can be introduced into the existing silicon-based CMOS logic process platform at a relatively low cost.

[0111] 2. The integration method proposed in this invention is applicable to multiple existing integrated circuit process nodes and has technical iterativeness

[0112] The memory structure and integration method proposed in the present invention include a low-power dual-conductor device that can be changed according to different process nodes and can be a planar device structure, a fin-gate device structure, a nanosheet device structure, a nanowire device structure, or other device structures, and has technical iterativeness. BRIEF DESCRIPTION OF THE DRAWINGS

[0113] FIG1 is a schematic diagram showing a display effect obtained by monolithically integrating a memory structure based on a tunneling field effect transistor (TFET) and a silicon-based CMOS device according to a specific embodiment of the present invention.

[0114] FIG2 to FIG49 are schematic diagrams showing a memory structure based on a tunneling field effect transistor (TFET) and its integration method according to a specific embodiment of the present invention, and the steps for monolithically integrating the proposed memory structure with a CMOS device, wherein:

[0115] FIG2 is a diagram after shallow trench isolation (STI) is formed;

[0116] FIG3 is a diagram showing the growth of a new sacrificial oxide layer and the photolithography definition of the nMOSFET device area;

[0117] FIG4 is a diagram showing a P-type CMOS well formed by ion implantation;

[0118] FIG5 is a diagram after photolithographic definition of the pMOSFET device region and the TFET device substrate lead-out region;

[0119] FIG6 is a diagram showing an N-type CMOS well formed by ion implantation;

[0120] FIG7 is a diagram showing the TFET device region after photolithography definition;

[0121] FIG8 is a diagram showing an upper isolation well and a lower isolation well formed by ion implantation in a TFET device;

[0122] FIG9 is a diagram showing the gate dielectric layer of a CMOS device and a TFET device after formation;

[0123] FIG10 is a diagram showing the gate conductive layer after forming a CMOS device and a TFET device;

[0124] FIG11 is a diagram showing a CMOS device and a TFET device after forming a compensation isolation layer on the gate sidewalls;

[0125] FIG12 is a diagram after photolithographically defining the nMOSFET device region, the pMOSFET substrate lead-out region, and the TFET device substrate lead-out region;

[0126] 13 is a diagram showing an N-type implanted region formed by ion implantation into the NLDD region of an nMOSFET device, the substrate lead-out NLDD region of a pMOSFET, and the substrate lead-out region of a TFET device;

[0127] FIG14 is a diagram showing the pMOSFET device region and the nMOSFET substrate lead-out region defined by photolithography;

[0128] FIG15 is a diagram showing the PLDD region of the pMOSFET device formed by ion implantation and the substrate-extracted PLDD region of the nMOSFET;

[0129] FIG16 is a diagram showing a composite main isolation layer formed on the gate sidewalls of a CMOS device and a TFET device;

[0130] FIG17 is a diagram after photolithography defines the nMOSFET device region, the TFET device substrate lead-out region, and the N-type doped source doping layer and the N-type doped drain doping layer in the TFET device;

[0131] 18 is a diagram after ion implantation to form the N+ SD region of the nMOSFET, the N-type implant region of the TFET device substrate lead-out region, and the N-type doped source doping layer and the N-type doped drain doping layer in the TFET device;

[0132] FIG19 is a diagram after photolithography defines the pMOSFET device region and the P-type doped source doping layer and the P-type doped drain doping layer in the TFET device;

[0133] FIG20 is a diagram after ion implantation to form the P+ SD region of the pMOSFET and the P-type doped source doping layer and the P-type doped drain doping layer in the TFET device;

[0134] FIG21 is a diagram showing a hard mask defining the source region of a TFET device;

[0135] FIG22 is a diagram after etching away the composite main isolation layer at the source end of the TFET device;

[0136] FIG23 is a diagram after photolithographically defining an N-type doped source extension layer and an N-type doped drain extension layer in a TFET device;

[0137] FIG24 is a diagram showing an N-type doped source extension layer and an N-type doped drain extension layer formed in a TFET device by ion implantation;

[0138] FIG25 is a diagram after photolithographic definition of a P-type doped source extension layer and a P-type doped drain extension layer in a TFET device;

[0139] FIG26 is a diagram after ion implantation to form a P-type doped source extension layer and a P-type doped drain extension layer in a TFET device;

[0140] FIG27 is a diagram after forming a self-aligned metal silicide;

[0141] FIG28 is a diagram after forming a dielectric layer between contact holes;

[0142] FIG29 is a diagram showing the areas of contact holes for source electrodes, drain electrodes, and substrate electrodes defined by photolithography for CMOS and TFET devices;

[0143] FIG30 is a diagram showing the formation of source electrodes, drain electrodes and substrate electrode contact holes for CMOS devices and TFET devices;

[0144] FIG31 is a diagram showing the gate electrode contact hole regions of CMOS devices and TFET devices after photolithography and etching;

[0145] FIG32 is a diagram after forming gate electrode contact holes for CMOS devices and TFET devices;

[0146] FIG33 is a diagram after forming an intermetallic dielectric layer;

[0147] FIG34 is a diagram showing the metal interconnection area defined by photolithography and etching;

[0148] FIG35 is a diagram after metal interconnection lines are formed;

[0149] FIG36 is a diagram after forming a dielectric layer between contact holes;

[0150] FIG37 is a diagram showing the SN interconnection line through-hole area defined by photolithography;

[0151] FIG38 is a diagram after forming SN interconnection line through holes;

[0152] FIG39 is a diagram after forming an intermetallic dielectric layer;

[0153] FIG40 is a diagram after photolithography and etching to define SN metal interconnection lines;

[0154] FIG41 is a diagram after forming SN metal interconnection lines;

[0155] FIG42 is a diagram showing the formation of a lower electrode layer, a dielectric layer, and an upper electrode layer;

[0156] FIG43 is a diagram after photolithography and etching to define a ferroelectric capacitor;

[0157] FIG44 is a diagram after forming a dielectric layer between contact holes;

[0158] FIG45 is a diagram after photolithography and etching to define the upper plate through-hole area;

[0159] FIG46 is a diagram after forming the upper plate through hole;

[0160] FIG47 is a diagram after forming an intermetallic dielectric layer;

[0161] FIG48 is a diagram illustrating the photolithography and etching process for defining the RWL metal interconnection line region;

[0162] FIG. 49 is a diagram showing the area where RWL metal interconnects are formed.

[0163] In the picture:

[0164] 1 - High-resistance silicon substrate 2 - N-type isolation well

[0165] 3 - P-type isolation well 4 - N-type CMOS well

[0166] 5 - Shallow Trench Isolation 6 - Gate Dielectric Layer

[0167] 7 - Gate conductive layer of P-type device 8 - Gate conductive layer of N-type device

[0168] 9 - Compensating isolation layer 10 - Composite main isolation layer

[0169] 11 - N+ SD area 12 - P+ SD area

[0170] 13 - N+ expansion area 14 - P+ expansion area

[0171] 15 - Self-aligned silicide 16 - Dielectric layer between contact holes

[0172] 17 — Contact hole 18 — Intermetallic dielectric layer

[0173] 19 - VDD metal interconnection line 20 - WBL metal interconnection line

[0174] 21 - VSS metal interconnection line 22 - RBL metal interconnection line

[0175] 23 - SN metal interconnect 24 - WWL metal interconnect

[0176] 25 — SN interconnection line through hole 26 — bottom plate layer

[0177] 27 - Dielectric layer 28 - Top plate layer

[0178] 29 - Upper plate through hole 30 - RWL metal interconnect

[0179] 31 —— P-type CMOS well 32 —— VSS metal interconnect

[0180] 33 —— P-type LDD region 34 —— N-type LDD region

[0181] 35 - Photoresist 36 - Sacrificial oxide layer DETAILED DESCRIPTION

[0182] The present invention is further illustrated below by way of examples. It should be noted that the purpose of disclosing the examples is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the examples, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

[0183] Figure 1 is a schematic diagram of the memory structure proposed in the present invention integrated with a silicon-based CMOS monolithic chip, wherein a tunneling field-effect transistor (TFET) is used as its low-power dual-conductance device. The memory structure is located on a semiconductor substrate 1 and comprises, from bottom to top, a transistor layer, an intermediate metal interconnect layer, an amplifying capacitor layer, and an upper metal interconnect layer. The transistor layer consists of two TFET devices placed side by side: a P-type TFET device on the left and an N-type TFET device on the right. The intermediate metal interconnect layer consists of contact holes 17, SN interconnect line vias 25, metal interconnect lines 19-24, inter-contact hole dielectric 16, and inter-metal interconnect line dielectric 18. The amplifying capacitor layer consists of a lower plate layer 26, a dielectric layer 27, and an upper plate layer 28. The upper metal interconnect layer consists of an upper plate via 29, a metal interconnect line 30, an inter-contact hole dielectric 16, and an inter-metal interconnect line dielectric 18. Specifically, the lead electrodes of the two devices in the transistor layer are connected one-to-one with the contact holes 17 of the middle metal interconnect layer. The lead electrodes of the P-type TFET device on the left are, from left to right, the substrate lead electrode, the drain electrode, the gate electrode, and the source electrode. The lead electrodes of the N-type TFET device on the right are, from left to right, the drain electrode, the gate electrode, the source electrode, and the substrate lead electrode. The gate electrode of the P-type TFET device is connected to the WWL metal interconnect line 24, the drain electrode of the P-type TFET device is connected to the WBL metal interconnect line 20, the source electrode of the P-type TFET device is connected to the SN metal interconnect line 23, the gate electrode of the N-type TFET device is connected to the SN metal interconnect line 23, the source electrode of the N-type TFET device is connected to the VSS metal interconnect line 21, the drain electrode of the N-type TFET device is connected to the RBL metal interconnect line 22, and the substrate electrodes of both the P-type TFET device and the N-type TFET device are connected to the VDD metal interconnect line 19. The bottom of the lower plate layer 26 in the amplifying capacitor layer is connected to the SN metal interconnection line 23 of the middle metal interconnection layer, and the top of the upper plate layer 28 is connected to the upper plate via 29 of the upper metal interconnection layer. The upper plate via 29 is connected to the RWL metal interconnection line 30.

[0184] The N-type and P-type TFET devices consist of six parts: a gate region, a source region, a drain region, a channel region, a substrate region, and a substrate lead-out region. The TFET device on the left is a P-type planar structure device, and the TFET device on the right is an N-type planar structure device. The device is fabricated on a high-resistance silicon substrate 1, and the device boundary is defined by a shallow trench isolation 5. Specifically, the gate dielectric layer 6, the gate conductive layer 7 of the P-type device, the gate conductive layer 8 of the N-type device, the compensation isolation layer 9, and the composite main isolation layer 10 constitute the gate region. The N+ extension region 13 serves as an N-type doped extension layer of the TFET device, the P+ extension region 14 serves as a P-type doped extension layer of the TFET device, the N+ SD region 11 serves as an N-type doped doping layer of the TFET device, and the P+ SD region 12 serves as a P-type doped doping layer of the TFET device. The N-type doped extension layer and the N-type doped layer form the source semiconductor layer in the source region of the P-type TFET device and the drain semiconductor layer in the drain region of the N-type TFET device. The P-type doped extension layer and the P-type doped layer form the drain semiconductor layer in the drain region of the P-type TFET device and the source semiconductor layer in the source region of the N-type TFET device. The N-type LDD region 34 and the N+ SD region 11 form the N-type implant region in the substrate lead-out region of the TFET device, and the N-type CMOS well 4 forms the N-type lead-out well in the substrate lead-out region of the TFET device. The self-aligned silicide 15 in the substrate lead-out region forms the substrate metal layer, serving as the substrate electrode. The self-aligned silicide 15 in the gate region forms the gate metal layer, serving as the gate electrode. The self-aligned silicide 15 in the source and drain regions form the source metal layer and the drain metal layer, serving as the source and drain electrodes, respectively. These are surrounded by the N-type doped extension layer 13 or the P-type doped extension layer 14. The channel region is located between the source and drain regions. The first substrate layer is located below the source, channel, and drain regions, and above the upper well layer consisting of the P-type isolation well 3. Below the upper well layer is the lower well layer consisting of the N-type isolation well 2. The area below the lower well layer represents the semiconductor region below the device.

[0185] The memory shown in FIG1 can be manufactured by a method proposed by the present invention that is compatible with CMOS technology. The specific method is shown in FIG2 to FIG49 . The steps are as follows:

[0186] First, a boron-doped P-type high-resistance silicon wafer was selected for device and circuit fabrication, with a resistivity of 9 Ohm-cm.

[0187] Secondly, shallow trench isolation (STI) is done by depositing 15nm of silicon oxide and 15nm of silicon nitride. The active area is then defined using photolithography. The silicon oxide and silicon nitride are etched to form a hard mask. Silicon trenches are then anisotropically etched outside the active area. The trenches are then filled with oxide, which is then hardened using rapid thermal annealing (RTA). After filling, the surface is planarized using CMP. As shown in Figure 2, 2 is a 300nm STI and 1 is a lightly doped P-type substrate.

[0188] Next, as shown in FIG3 , a new sacrificial oxide layer 36 of 2 nm is grown on the surface of the silicon wafer, and then the nMOSFET device area is defined by photolithography;

[0189] Next, as shown in FIG4 , boron is implanted by ion implantation to form the P-type doped well of the nMOSFET. A total of three ion implantations are performed, with the conditions being 90 keV, 1E13 cm -2 、200keV5E13cm -2 、10keV1E13cm -2 , after ion implantation, the resin is removed;

[0190] Next, as shown in FIG5 , the pMOSFET device region and the substrate lead-out region of the TFET device are defined by photolithography;

[0191] Next, as shown in FIG6 , phosphorus is implanted by ion implantation to form the N-type doped well of the pMOSFET and the N-type extraction well of the TFET device. A total of three ion implantations are performed, with the conditions of 30keV5E12cm -2 、220keV5E12cm -2 、380keV5E13cm -2 , after ion implantation, the resin is removed;

[0192] Next, as shown in FIG7 , the TFET device region is defined by photolithography;

[0193] Next, as shown in FIG8 , phosphorus is implanted by ion implantation to form the lower well layer of the proposed device. The implantation energy is 340 keV and the implantation dose is 1e13 cm -2 Then, boron is implanted by ion implantation to form the upper well layer of the proposed device. The implantation energy is 60 keV and the implantation dose is 1e13 cm -2 , remove the glue after injection;

[0194] Next, rapid thermal annealing (RTA) was performed to remove defects caused by the ion implantation and activate the implanted impurities. The annealing temperature was 1100°C, the annealing time was 15 seconds, and the annealing atmosphere was nitrogen.

[0195] Next, as shown in FIG9 , the gate dielectric layer of the CMOS device and the TFET device is formed. Here, the gate dielectric layer thickness is selected from the gate dielectric layer thickness of the core tube, which is 2 nm. Silicon dioxide is deposited to a thickness of 2 nm and then patterned by photolithography and etching.

[0196] Next, as shown in FIG10 , the gate conductive layer of the CMOS device and the TFET device is formed by depositing 100 nm of polysilicon, patterning it by photolithography and etching, defining the P-type MOSFET device and P-type TFET device regions by photolithography, and then implanting boron by ion implantation at a rate of 4 keV 3E15 cm -2 After the injection, the resin is removed and the N-type MOSFET device and N-type TFET device are defined by photolithography. Then phosphorus is implanted by ion implantation. The implantation conditions are 4keV3E15cm -2 , remove glue after injection;

[0197] Next, rapid thermal annealing (RTA) is performed to improve the reliability of the gate dielectric layer and the conductivity of the gate conductive layer. The annealing temperature is 100°C, the annealing time is 10 seconds, and the annealing atmosphere is oxygen.

[0198] Next, as shown in FIG11 , a compensation isolation layer is formed on the gate sidewall. Specifically, a 2 nm reoxidation layer is deposited on the gate sidewall, followed by an 8 nm silicon nitride deposition, and then anisotropic etching is performed.

[0199] Next, as shown in FIG12 , the nMOSFET device region, the substrate lead-out region of the pMOSFET, and the substrate lead-out region of the TFET device are defined by photolithography;

[0200] Next, as shown in FIG13 , arsenic is implanted by ion implantation to form the NLDD region of the nMOSFET device, the NLDD region of the substrate lead-out region of the pMOSFET device, and the N-type implantation region of the substrate lead-out region of the TFET device. The implantation conditions are 2.5keV 1.3E15cm -2 , remove the glue after injection;

[0201] Next, as shown in FIG14 , the pMOSFET device region and the nMOSFET substrate lead-out region are defined by photolithography;

[0202] Next, as shown in FIG15 , boron fluoride is implanted by ion implantation to form the PLDD region of the pMOSFET device and the PLDD region of the substrate lead-out region of the nMOSFET device. The implantation conditions are 2.5keV1.3E15cm -2 , remove the glue after injection;

[0203] Next, spike annealing is performed to remove defects caused by ion implantation and activate the implanted impurities. The annealing temperature is 950°C.

[0204] Next, as shown in FIG16 , a composite main isolation layer is formed on the gate sidewalls of the CMOS device and the TFET device. Specifically, 9 nm of silicon oxide and 42 nm of silicon nitride are deposited on the gate sidewalls, and then anisotropically etched back.

[0205] Next, as shown in FIG17 , the nMOSFET device region, the pMOSFET substrate lead region, the TFET device substrate lead region, and the N-type doped layer in the TFET device are defined by photolithography;

[0206] Next, as shown in FIG18 , phosphorus and arsenic are implanted by ion implantation to form the N+ SD region of the nMOSFET, the N+ SD region of the substrate lead-out region of the pMOSFET device, the N-type implantation region of the substrate lead-out region of the TFET device, and the N-type doped layer in the TFET device. The phosphorus implantation condition is 5keV2E14cm -2 The injection conditions of arsenic are 25keV2E14cm -2 , after ion implantation, the resin is removed;

[0207] Next, as shown in FIG19 , the pMOSFET device region, the substrate lead region of the nMOSFET device, and the P-type doped drain doping layer in the TFET device are defined by photolithography;

[0208] Next, as shown in FIG20 , boron fluoride is implanted by ion implantation to form the P+ SD region of the pMOSFET, the P+ SD region of the substrate lead-out region of the nMOSFET device, and the P-type doped layer in the TFET device. The implantation conditions are 6keV2.5E15cm -2 , after ion implantation, the resin is removed;

[0209] Next, rapid thermal annealing (RTA) is performed to remove defects caused by ion implantation and activate the implanted impurities. The annealing temperature is 500°C and the annealing time is 7 seconds.

[0210] Next, as shown in FIG21 , the source region of the TFET device is defined by a hard mask, specifically by depositing 15 nm of silicon oxide and 15 nm of silicon nitride, and then patterning them by photolithography and etching.

[0211] Next, as shown in FIG22 , the composite main isolation layer at the source end of the TFET device is removed by etching, leaving the compensation isolation layer;

[0212] Next, as shown in FIG23 , the hard mask is removed and the N-type doped extension layer of the TFET device is defined by photolithography;

[0213] Next, as shown in FIG24 , arsenic is implanted by ion implantation to form an N-type doped extension layer of the TFET device. The implantation conditions are 4keV5E15cm -2 , remove glue after injection;

[0214] Next, as shown in FIG25 , a P-type doped extension layer of the TFET device is defined by photolithography;

[0215] Next, as shown in FIG26 , boron fluoride is implanted by ion implantation to form a P-type doped extension layer of the TFET device. The implantation conditions are 1.5keV5E15cm -2 , remove glue after injection;

[0216] Next, laser annealing is performed to remove defects caused by ion implantation and activate the implanted impurities. The annealing temperature is 1170°C and the single annealing time is 0.8 milliseconds.

[0217] Next, as shown in FIG27 , a self-aligned metal silicide is formed by removing the oxide on the surface of the device active area, then depositing 30 nm of nickel, performing a rapid thermal annealing at 300° C. to remove the nickel that has not reacted with silicon, and then performing a rapid thermal annealing at 550° C.

[0218] Next, as shown in FIG28 , a dielectric layer is formed between the contact holes by growing 30 nm thick silicon nitride (Si 3 N 4 ) and 150 nm thick SiO 2 using chemical vapor deposition (CVD) and planarizing the surface by chemical mechanical polishing.

[0219] Next, as shown in FIG29 , a contact hole region outside the gate contact hole is defined by photolithography, and SiO2 is etched by reactive ion etching (RIE). The remaining SiO2 and etching products are then rinsed with buffered hydrofluoric acid. The exposed Si3N4 is then removed by hot phosphoric acid etching. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form a contact hole region outside the gate contact hole.

[0220] Next, as shown in FIG30 , titanium (Ti) and titanium nitride (TiN) are grown by magnetron sputtering, and then filled with tungsten (W) by chemical vapor deposition (CVD). The surface is then planarized by chemical mechanical polishing to form contact holes other than the gate contact hole.

[0221] Next, as shown in FIG31 , the gate contact hole region is defined by photolithography, and SiO2 is etched by reactive ion etching (RIE). The remaining SiO2 and etching products are then rinsed with buffered hydrofluoric acid. The exposed Si3N4 is then removed by hot phosphoric acid etching. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form the gate contact hole region.

[0222] Next, as shown in FIG32 , titanium (Ti) and titanium nitride (TiN) are grown by magnetron sputtering, and then filled with tungsten (W) by chemical vapor deposition (CVD). The surface is then planarized by chemical mechanical polishing to form a gate contact hole.

[0223] Next, as shown in FIG33 , an intermetallic dielectric layer is formed by growing 30 nm thick silicon nitride (Si 3 N 4 ) and 200 nm thick SiO 2 by chemical vapor deposition (CVD), and then planarizing the surface by chemical mechanical polishing.

[0224] Next, as shown in FIG34 , the metal interconnect area is defined by photolithography, and the SiO2 is etched using reactive ion etching (RIE). The remaining SiO2 and etching products are then rinsed with buffered hydrofluoric acid. Hot phosphoric acid etching is then used to remove the exposed Si3N4. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form the metal interconnect area.

[0225] Next, as shown in FIG35 , metal tantalum (Ta) and tantalum nitride (TaN) are grown by magnetron sputtering, and then filled with metal copper (Cu) by electroplating. The surface is then planarized by chemical mechanical polishing to form metal interconnects.

[0226] Next, as shown in FIG36 , a dielectric layer is formed between the contact holes by growing 30 nm thick silicon nitride (Si 3 N 4 ) and 150 nm thick SiO 2 by chemical vapor deposition (CVD), and then planarizing the surface by chemical mechanical polishing.

[0227] Next, as shown in FIG37 , the SN interconnection line via region is defined by photolithography, and SiO2 is etched by reactive ion etching (RIE). The residual SiO2 and etching products are then rinsed with buffered hydrofluoric acid. Hot phosphoric acid etching is then used to remove the exposed Si3N4. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form the SN interconnection line via region.

[0228] Next, as shown in FIG38 , metal tantalum (Ta) and tantalum nitride (TaN) are grown by magnetron sputtering, and then filled with metal copper (Cu) by electroplating. The surface is then planarized by chemical mechanical polishing to form SN interconnection vias 25.

[0229] Next, as shown in FIG39 , an intermetallic dielectric layer is formed by growing 30 nm thick silicon nitride (Si 3 N 4 ) and 200 nm thick SiO 2 by chemical vapor deposition (CVD), and then planarizing the surface by chemical mechanical polishing.

[0230] Next, as shown in FIG40 , the metal interconnect area is defined by photolithography, and the SiO2 is etched using reactive ion etching (RIE). The remaining SiO2 and etching products are then rinsed with buffered hydrofluoric acid. Hot phosphoric acid etching is then used to remove the exposed Si3N4. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form the metal interconnect area.

[0231] Next, as shown in FIG41 , metal tantalum (Ta) and tantalum nitride (TaN) are grown by magnetron sputtering, and then filled with metal copper (Cu) by electroplating. The surface is then planarized by chemical mechanical polishing to form SN metal interconnects 23.

[0232] Next, as shown in FIG42, a 25 nm titanium nitride (TiN) layer is grown as the lower electrode layer material by magnetron sputtering, and a 10 nm hafnium zirconium oxide (HfZO) layer is grown by atomic layer deposition (ALD). 0.5 Zr 0.5 O2) as the dielectric layer material, and then grow 25nm titanium nitride (TiN) as the top electrode layer material by magnetron sputtering;

[0233] Next, as shown in FIG43 , the capacitor is patterned by photolithography and reactive ion etching (RIE);

[0234] Next, as shown in FIG44 , a dielectric layer is formed between the contact holes by growing 30 nm thick silicon nitride (Si 3 N 4 ) and 150 nm thick SiO 2 by chemical vapor deposition (CVD), and then planarizing the surface by chemical mechanical polishing.

[0235] Next, as shown in FIG45 , the upper plate through-hole region is defined by photolithography, and the upper plate through-hole region is formed by reactive ion etching (RIE);

[0236] Next, as shown in FIG46 , metal tantalum (Ta) and tantalum nitride (TaN) are grown by magnetron sputtering, and then filled with metal copper (Cu) by electroplating. The surface is then flattened by chemical mechanical polishing to form a top plate through-hole.

[0237] Next, as shown in FIG47 , a specific method is to grow 30 nm thick silicon nitride (Si 3 N 4 ) and 200 nm thick SiO 2 by chemical vapor deposition (CVD), and then planarize the surface by chemical mechanical polishing.

[0238] Next, as shown in FIG48 , the metal interconnect area is defined by photolithography, and the SiO2 is etched using reactive ion etching (RIE). The remaining SiO2 and etching products are then rinsed with buffered hydrofluoric acid. Hot phosphoric acid etching is then used to remove the exposed Si3N4. The metal oxide produced during the etching process is then rinsed with buffered hydrofluoric acid to form the metal interconnect area.

[0239] Next, as shown in FIG49 , metal tantalum (Ta) and tantalum nitride (TaN) are grown by magnetron sputtering, and then filled with metal copper (Cu) by electroplating. The surface is then planarized by chemical mechanical polishing to form RWL metal interconnects 30.

[0240] Next, the dielectric layer 27 is crystallized by rapid thermal annealing (RTA) at 500°C for 30 seconds, and then alloyed by furnace annealing at 400°C for 30 minutes.

[0241] In summary, the memory shown in FIG1 and its integration with CMOS devices are prepared.

[0242] Although the present invention has been disclosed above with reference to preferred embodiments, this is not intended to limit the present invention. Any person skilled in the art can, without departing from the scope of the present invention, utilize the methods and technical content disclosed above to make many possible changes and modifications to the present invention, or modify the present invention into equivalent embodiments with equivalent variations. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A memory structure, characterized in that, Located on a semiconductor substrate, from bottom to top, it includes a transistor layer, an intermediate metal interconnect layer, an amplifying capacitor layer, and an upper metal interconnect layer. Among them, the transistor layer includes two low-power double-gate devices placed side by side, one is a P-type low-power double-gate device, and the other is an N-type low-power double-gate device. The intermediate metal interconnect layer includes contact holes, SN interconnect via holes, metal interconnect lines, dielectric between contact holes, and dielectric between metal interconnect lines. The amplifying capacitor layer includes a lower plate layer, a dielectric layer, and an upper plate layer. The upper metal interconnect layer includes upper plate via holes, RWL metal interconnect lines, dielectric between contact holes, and dielectric between metal interconnect lines; The contact holes of the intermediate metal interconnect layer are several cuboids, and the dielectric between contact holes fills the space between the contact holes. The metal interconnect lines of the intermediate metal interconnect layer are several cuboids, and the dielectric between metal interconnect lines fills the space between the metal interconnect lines. The metal interconnect lines are divided into two parts: lower metal interconnect lines and upper metal interconnect lines. The lower metal interconnect lines include VDD metal interconnect lines, VSS metal interconnect lines, SN metal interconnect lines, WWL metal interconnect lines, WBL metal interconnect lines, and RBL metal interconnect lines. The upper metal interconnect lines include SN metal interconnect lines. Two of the SN metal interconnect lines in the lower metal interconnect lines are connected to the upper SN metal interconnect line through two SN interconnect via holes respectively. The bottom of the contact holes of the intermediate metal interconnect layer is connected to the lead electrodes of the low-power double-gate devices in the transistor layer, and the top of the contact holes is connected to the lower metal interconnect lines; The lead electrodes of the P / N-type low-power double-gate devices in the transistor layer respectively include substrate lead electrodes, drain electrodes, gate electrodes, and source electrodes. Their lead electrodes are connected to the contact holes of the intermediate metal interconnect layer in one-to-one correspondence. The substrate lead electrode of the P-type low-power double-gate device is connected to the VDD metal interconnect line through a contact hole. The drain electrode of the P-type low-power double-gate device is connected to the WBL metal interconnect line through a contact hole. The gate electrode of the P-type low-power double-gate device is connected to the WWL metal interconnect line through a contact hole. The source electrode of the P-type low-power double-gate device is connected to the SN metal interconnect line through a contact hole. The drain electrode of the N-type low-power double-gate device is connected to the RBL metal interconnect line through a contact hole. The gate electrode of the N-type low-power double-gate device is connected to the SN metal interconnect line through a contact hole. The source electrode of the N-type low-power double-gate device is connected to the VSS metal interconnect line through a contact hole. The substrate electrode of the N-type low-power double-gate device is connected to the VDD metal interconnect line through a contact hole; The lower plate layer, dielectric layer, and upper plate layer in the amplifying capacitor layer are three cuboids of the same size, arranged in sequence from bottom to top. The bottom of the lower plate layer is connected to the upper metal interconnect lines of the intermediate metal interconnect layer. The top of the upper plate layer is connected to the upper plate via holes of the upper metal interconnect layer. The upper plate via holes are composed of several cuboids. The space between the upper plate via holes and the outer region of the amplifying capacitor layer are all filled with dielectric between contact holes. The top of the upper plate via holes is connected to the RWL metal interconnect lines, and the outer side of the RWL metal interconnect lines is filled with dielectric between metal interconnect lines; The P / N type low-power double-gate device includes six parts: a gate region, a source region, a drain region, a channel region, a substrate region, and a substrate lead-out region. The boundaries of the device are defined by three adjacent shallow trench isolations. The gate region, source region, drain region, channel region, and substrate region of the device are all located laterally within two shallow trench isolations on one side, and the substrate lead-out region of the device is located within two shallow trench isolations on the other side; the source region, drain region, channel region, substrate region, and substrate lead-out region are located on the same semiconductor substrate. The source region, drain region, and channel region are located in the part of the semiconductor substrate close to the surface. Along the lateral direction, they are the source region, channel region, and drain region in sequence, or the drain region, channel region, and source region in sequence; the substrate region is located below the source region, channel region, and drain region; the gate region is located above the semiconductor substrate; The gate region is composed of four parts: a gate dielectric layer, a gate conductive layer, a gate metal layer, and a gate isolation layer. The gate dielectric layer, the gate conductive layer, and the gate metal layer are arranged in sequence from bottom to top. The gate metal layer serves as a gate electrode. The gate isolation layer is composed of a compensation isolation layer and a composite main isolation layer. The compensation isolation layer is located on the gate sidewalls near the source region and on the gate sidewalls near the drain region. The composite main isolation layer is located on the compensation isolation layer near the drain region. The source region is composed of two parts: a source metal layer and a source semiconductor layer. The source metal layer serves as a source electrode. The source metal layer is longitudinally located on the surface of the semiconductor substrate and at a certain depth inside it. The source metal layer is laterally located from near the gate sidewall of the source region to the boundary of the source region. The source semiconductor layer wraps around the source metal layer and has a certain width. The source semiconductor layer is composed of two parts: a source extension layer and a source doping layer. The source extension layer completely wraps the source metal layer but has a narrow wrapping width. The source doping layer only wraps a part of the source metal layer near the boundary of the source region laterally and wraps a relatively wide width of the source metal layer longitudinally. The drain region is composed of two parts: a drain metal layer and a drain semiconductor layer. The drain metal layer serves as a drain electrode. The drain metal layer is longitudinally located on the surface of the semiconductor substrate and at a certain depth inside it. The drain metal layer is laterally located from near the boundary of the composite main isolation layer of the drain region to the boundary of the drain region. The drain semiconductor layer wraps around the drain metal layer and has a certain width. The drain semiconductor layer is composed of two parts: a drain extension layer and a drain doping layer. The drain extension layer completely wraps the drain metal layer but has a narrow wrapping width. The drain doping layer also completely wraps the drain metal layer but has a wide wrapping width. The channel region is longitudinally located on the surface of the semiconductor substrate and at a certain depth inside it, with the same depth as the source region and the drain region. Laterally, it is located between the source region and the drain region and is composed of a channel semiconductor layer. The substrate region is longitudinally located inside the semiconductor substrate and below the source region, the drain region, and the channel region. Laterally, it is located between the boundary of the source region and the boundary of the drain region and is composed of three parts: a first substrate layer, an upper well layer, and a lower well layer. The first substrate layer is longitudinally located between the upper boundary of the substrate region and the upper boundary of the upper well layer. The lower boundary of the upper well layer is near the bottom of the shallow trench isolation. The upper boundary of the lower well layer coincides with the lower boundary of the upper well layer. The lower boundary of the lower well layer is the lower boundary of the substrate region. The lower well layer of the substrate region is led out through a substrate lead-out region, which is jointly composed of an N-type lead-out well, an N-type implantation region, and a substrate metal layer. The substrate metal layer serves as a substrate electrode.

2. The memory structure according to claim 1, wherein The upper boundary of the upper well layer in the substrate region is more than 200 nm away from the surface of the semiconductor substrate.

3. The memory structure according to claim 1, characterized in that, The materials of the upper plate layer and the lower plate layer in the amplification capacitor layer are one metal or a combination of metals among titanium nitride, tantalum nitride, tungsten, titanium, and tantalum, and the dielectric layer material is hafnium oxide HfO2, zirconium oxide ZrO2, hafnium zirconium oxide HZO, or silicon dioxide SiO2.

4. A memory structure according to claim 1, characterized in that, The materials of the metal interconnection line, the upper plate via material, and the SN interconnection via are the same, which are a combination of copper, tantalum, and tantalum nitride, or aluminum.

5. A memory structure as claimed in claim 1, wherein, The material of the contact hole is a combination of tungsten, titanium, titanium nitride, or aluminum.

6. A memory structure as claimed in claim 1, wherein The material of the inter-metal dielectric layer is the same as that of the inter-contact-hole dielectric layer, which is silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or a combination of other dielectric materials with a dielectric constant not greater than that of silicon dioxide and silicon nitride.

7. A memory structure according to claim 1, characterized in that, The material of the gate dielectric layer is SiO2, or a stacked material composed of SiO2 and HfO2, or a stacked material composed of SiO2 and impurity-doped HfO2. Among them, the impurities in the impurity-doped HfO2 are silicon Si, lanthanum La, zirconium Zr, aluminum Al, titanium Ti, or nitrogen N; the thickness of the gate dielectric layer is between 1 nm and 5 nm.

8. A memory structure as claimed in claim 1, characterized in that, The material of the gate conductive layer is impurity-doped polycrystalline silicon material or a stacked material composed of multiple layers of metals. For N-type devices, the doping impurities in the polycrystalline silicon are phosphorus or arsenic, and the multi-layer metal stacked material is TiN, TaN, TiAl, Al. For P-type devices, the doping impurities in the polycrystalline silicon are boron or boron fluoride, and the multi-layer metal stacked material is TiN, TaN; the thickness of the gate conductive layer is between 10 nm and 500 nm.

9. A memory structure as claimed in claim 1, wherein, The material of the gate metal layer is a metal silicide: nickel silicide, titanium silicide, or cobalt silicide.

10. A memory structure as described in claim 1, characterized in that, The material of the compensation isolation layer is a stacked material of silicon dioxide and silicon nitride or silicon oxynitride; the thickness of the compensation isolation layer is between 2 nm and 20 nm.

11. A memory structure as claimed in claim 1, wherein, The material of the composite main isolation layer is a stacked material composed of silicon dioxide and silicon nitride or silicon oxynitride; the thickness of the composite main isolation layer is between 20 nm and 70 nm.

12. A memory structure according to claim 1, characterized in that, The material of the source metal layer is the same as that of the drain metal layer, which is a metal silicide: nickel silicide, titanium silicide, or cobalt silicide.

13. A memory structure according to claim 1, characterized in that, The material of the source semiconductor layer is heavily doped silicon (Si), heavily doped silicon-germanium (SiGe), or heavily doped silicon-carbon (SiC), and its peak doping concentration is greater than 1E20 cm -3 . If it is a P-type device, the doping type of the source semiconductor layer is N-type, and the doping impurities are pentavalent elements phosphorus or arsenic and their compounds. If it is an N-type device, the doping type of the source semiconductor layer is P-type, and the doping impurities are trivalent elements boron or boron fluoride and their compounds.

14. A memory structure according to claim 1, characterized in that, The material of the drain semiconductor layer is heavily doped silicon (Si), heavily doped silicon-germanium (SiGe), or heavily doped silicon-carbon (SiC), and its peak doping concentration is greater than 1E20 cm -3 . If it is an N-type device, the doping type of the drain semiconductor layer is N-type, and the doping impurity is a pentavalent element such as phosphorus or arsenic and their compounds. If it is a P-type device, the doping type of the drain semiconductor layer is P-type, and the doping impurity is a trivalent element such as boron or boron fluoride and their compounds.

15. A memory structure as claimed in claim 1, wherein, The material of the channel semiconductor layer is lightly doped silicon, and the doping type is N-type or P-type, with a doping concentration less than 1E16 cm -3 . If it is N-type doping, the doping impurity is a pentavalent element such as phosphorus or arsenic and their compounds. If it is P-type doping, the doping impurity is a trivalent element such as boron or boron fluoride and their compounds.

16. A memory structure as claimed in claim 1, wherein The material of the first layer of liner is lightly doped silicon, and the doping type is N-type or P-type, with a doping concentration less than 1E16 cm -3 . If it is N-type doping, the doping impurity is a pentavalent element such as phosphorus or arsenic and its compounds. If it is P-type doping, the doping impurity is a trivalent element such as boron or boron fluoride and its compounds.

17. A memory structure as claimed in claim 1, wherein, The material of the upper well layer is moderately doped silicon, with a P-type doping type and a peak doping concentration greater than 5E16 cm -3 , and the doping impurities are trivalent elements boron or boron fluoride and their compounds.

18. A memory structure according to claim 1, characterized in that The material of the lower well layer is medium-doped silicon, the doping type is N-type, and the peak doping concentration is greater than 5E16 cm -3 , and the doping impurities are pentavalent elements phosphorus or arsenic and their compounds.

19. A memory structure according to claim 1, characterized in that, The material of the shallow trench isolation is silicon dioxide.

20. A memory structure according to claim 1, characterized in that, The materials of the N-type extraction well and the N-type implantation region in the substrate extraction region are moderately doped silicon, and the doping impurities are pentavalent elements phosphorus or arsenic and their compounds. The peak doping concentration of the N-type extraction well is greater than 5E16 cm -3 , and the peak doping concentration of the N-type implantation region is greater than 1E18 cm -3 ; The material of the substrate metal layer is nickel silicide, titanium silicide or cobalt silicide.

21. An integration method for monolithically integrating the memory structure as described in claim 1 with silicon-based CMOS, characterized in that, The specific method is as follows: Step 1: Select a wafer corresponding to high-resistance silicon for device and circuit fabrication; Step 2: Form a shallow trench isolation (STI). The specific method is to define the active area by lithography and hard mask, then anisotropically etch the silicon trench outside the active area, then fill the silicon trench with oxide, and then use rapid thermal annealing (RTA) to make the filled oxide harder. After filling, perform surface planarization by chemical mechanical polishing (CMP); Step 3: Grow a new sacrificial oxide layer on the silicon wafer surface, and then define the nMOSFET device area by lithography; Step 4: Form the P-type doped well of the nMOSFET device by ion implantation, and remove the photoresist after implantation; Step 5: Define the pMOSFET device area and the substrate lead-out area of the low-power double-guide device by lithography; Step 6: Form the N-type doped well of the pMOSFET device and the N-type lead-out well of the low-power double-guide device by ion implantation, and remove the photoresist after implantation; Step 7: Define the low-power double-guide device area by lithography; Step 8: Form the upper well layer and the lower well layer of the low-power double-guide device by ion implantation, and remove the photoresist after implantation; Step 9: Anneal to remove the defects caused by ion implantation and activate the impurities implanted by ions. Step 10: Form the gate dielectric layers of the CMOS device and the low-power double-gate device. Specifically, dielectric layers with different thicknesses are deposited in the core transistor and I / O transistor regions respectively, and are patterned by means of photolithography, hard mask and etching; Step 11: Form the gate conductive layers of the CMOS device and the low-power double-gate device. Specifically, gate conductive layer materials are deposited and are patterned by means of photolithography, hard mask and etching; Step 12: Anneal to improve the reliability of the gate dielectric layer and enhance the conductivity of the gate conductive layer; Step 13: Form a compensation isolation layer on the gate sidewalls. Specifically, a re-oxidation layer is deposited on the gate sidewalls, then an isolation dielectric layer is deposited, and then anisotropic etch-back is performed; Step 14: Define the nMOSFET device region, the substrate lead-out region of the pMOSFET, and the substrate lead-out region of the low-power double-gate device by means of photolithography; Step 15: Form the NLDD regions of the nMOSFET device, the NLDD regions of the substrate lead-out regions of the pMOSFET device, and the N-type implantation regions in the substrate lead-out regions of the low-power double-gate device by means of ion implantation. After implantation, the photoresist is removed; Step 16: Define the pMOSFET device region and the substrate lead-out region of the nMOSFET by means of photolithography; Step 17: Form the PLDD regions of the pMOSFET device and the PLDD regions of the substrate lead-out regions of the nMOSFET device by means of ion implantation. After implantation, the photoresist is removed; Step 18: Anneal to remove the defects caused by ion implantation and activate the implanted impurities; Step 19: Form a composite main isolation layer on the gate sidewalls. Specifically, a main isolation dielectric layer is deposited on the gate sidewalls, and then anisotropic etch-back is performed; Step 20: Define the nMOSFET device region, the substrate lead-out regions of the pMOSFET, the substrate lead-out regions of the low-power double-gate device, the N-type doped source doping layer, and the N-type doped drain doping layer in the low-power double-gate device by means of photolithography or hard mask; Step 21: Form the N+ SD regions of the nMOSFET, the N+ SD regions of the substrate lead-out regions of the pMOSFET device, the N-type implantation regions in the substrate lead-out regions of the low-power double-gate device, the N-type doped source doping layer, and the N-type doped drain doping layer in the low-power double-gate device by means of ion implantation or epitaxy. After that, the photoresist is removed or the hard mask is removed; Step 22: Define the pMOSFET device region, the substrate lead-out region of the nMOSFET device, and the P-type doped source doping layer and the P-type doped drain doping layer in the low-power double-gate device by means of photolithography or hard mask; Step 23: Form the P+ SD regions of the pMOSFET, the P+ SD regions of the substrate lead-out regions of the nMOSFET device, and the P-type doped source doping layer and the P-type doped drain doping layer in the low-power double-gate device by means of ion implantation or epitaxy. After that, the photoresist is removed or the hard mask is removed; Step 24: Anneal to remove the defects caused by ion implantation and activate the implanted impurities; Step 25: Define the source region of the low-power double-gate device by means of hard mask; Step 26: Remove the composite main isolation layer at the source end of the low-power double-guide device by etching, and retain the compensation isolation layer; Step 27: Remove the hard mask, and define the N-type doped source extension layer and N-type doped drain extension layer in the low-power double-guide device by photolithography; Step 28: Form the N-type doped source extension layer and N-type doped drain extension layer in the low-power double-guide device by ion implantation, and remove the photoresist after implantation; Step 29: Define the P-type doped source extension layer and P-type doped drain extension layer in the low-power double-guide device by photolithography; Step 30: Form the P-type doped source extension layer and P-type doped drain extension layer in the low-power double-guide device by ion implantation, and remove the photoresist after implantation; Step 31: Anneal to remove the defects caused by ion implantation and activate the implanted impurities; Step 32: Form self-aligned silicides. Among them, the self-aligned silicides in the source region and drain region of the low-power double-guide device form the source metal layer and drain metal layer of the low-power double-guide device, the self-aligned silicides in the gate region of the low-power double-guide device form the gate electrode of the low-power double-guide device, and the self-aligned silicides in the substrate lead-out region of the low-power double-guide device form the substrate electrode of the low-power double-guide device. The specific method is to remove the oxide on the device surface, and then form silicides on the silicon and polysilicon surfaces by depositing metal, annealing, and etching the excess metal and silicides; Step 33: Form the inter-contact hole dielectric layer. The specific method is to grow the inter-contact hole dielectric layer by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 34: Define the contact hole region other than the gate contact hole by photolithography, and form the contact hole region other than the gate contact hole by reactive ion etching (RIE) and wet etching; Step 35: Fill the contact hole material and planarize the surface by chemical mechanical polishing to form the contact holes other than the gate contact hole; Step 36: Define the gate contact hole region by photolithography, and form the gate contact hole region by reactive ion etching (RIE) and wet etching; Step 37: Fill the contact hole material and planarize the surface by chemical mechanical polishing to form the gate contact hole; Step 38: Form the inter-metal dielectric layer. The specific method is to grow the inter-metal dielectric layer by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 39: Define the metal interconnect region by photolithography, and form the metal interconnect region by reactive ion etching (RIE) and wet etching; Step 40: Fill the metal interconnect material and planarize the surface by chemical mechanical polishing to form the metal interconnect; Step 41: Form the inter-contact hole dielectric layer. The specific method is to grow the inter-contact hole dielectric layer by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 42: Define the SN interconnect via region by photolithography, and form the SN interconnect via region by reactive ion etching (RIE) and wet etching; Step 43: Fill the via material for the SN interconnect line and planarize the surface by chemical mechanical polishing to form the SN interconnect line via hole; Step 44: Form the intermetal dielectric layer. Specifically, grow the intermetal dielectric layer by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 45: Define the metal interconnect line region by photolithography and form the metal interconnect line region by reactive ion etching (RIE) and wet etching; Step 46: Fill the metal interconnect line material and planarize the surface by chemical mechanical polishing to form the metal interconnect line; Step 47: Deposit the lower electrode layer material, dielectric layer material, and upper electrode layer material; Step 48: Pattern the capacitor by photolithography and reactive ion etching (RIE); Step 49: Form the dielectric layer between contact holes. Specifically, grow the dielectric layer between contact holes by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 50: Define the upper electrode via hole region by photolithography and form the upper electrode via hole region by reactive ion etching (RIE); Step 51: Fill the upper electrode via hole material and planarize the surface by chemical mechanical polishing to form the upper electrode via hole; Step 52: Form the intermetal dielectric layer. Specifically, grow the intermetal dielectric layer by chemical vapor deposition (CVD) and planarize the surface by chemical mechanical polishing; Step 53: Define the metal interconnect line region by photolithography and form the metal interconnect line region by reactive ion etching (RIE) and wet etching; Step 54: Fill the metal interconnect line material and planarize the surface by chemical mechanical polishing to form the metal interconnect line; Step 55: Anneal.

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