Time synchronization method and device, and storage medium

Abstract

The present application discloses a time synchronization method and device, and a storage medium. The method comprises: by using an inner domain time as a reference, determining a first time stamp at which an outer domain synchronization message in a synchronization message enters an inner domain ingress of a TSN bridge; by using the inner domain time and an outer domain time as references respectively, determining a second time stamp and a third time stamp at which the outer domain synchronization message enters a preset centralized processing engine in the TSN bridge; and on the basis of the first time stamp, the second time stamp, and the third time stamp, determining a time deviation between the TSN bridge and an outer domain master clock in a master clock, and, on the basis of the time deviation, controlling the TSN bridge to synchronize with the outer domain master clock.

Description

Time synchronization method, device and storage medium

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202410041683.9 filed on January 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a time synchronization method, device, and storage medium. Background Art

[0004] Currently, the synchronization of the fifth generation communication system (5GS) requires the synchronization of the terminal (UE), 5G base station (gNB), and 5G core network (UPF) with the internal system clock of the fifth generation communication (5G). Specifically, it is divided into two cross-segments: wired and wireless synchronization: (1) time synchronization between the 5G base station (gNB), 5G core network (UPF) and the fifth generation communication (5G) master clock GM, which is usually performed using the standard IEEE1588 or IEEE802.1AS mechanism; (2) time synchronization between the terminal (UE) and the fifth generation communication (5G) master clock GM; however, in most scenarios, when the external domain passes through the fifth generation communication (5G) network, deterministic transmission is still required, and deterministic forwarding is achieved by the Qbv TAS mechanism in IEEE802.1AS; and the premise for achieving Qbv is that the TSN bridge needs to be synchronized with the external domain master clock GM. Since there are at least two domains superimposed in the TSN bridge, the model complexity is increased by more than 1 times, making it difficult to achieve synchronization between the TSN bridge and the external domain master clock. Therefore, how to simply and effectively synchronize the TSN bridge with the external domain master clock has become an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The main purpose of this application is to provide a time synchronization method, device and storage medium, aiming to solve the technical problem of how to simply and effectively achieve synchronization between the TSN bridge and the external domain master clock.

[0007] To achieve the above object, the present application provides a time synchronization method, which includes the following steps:

[0008] When a TSN bridge in a communication system receives a synchronization message sent by a master clock, it determines the inner domain time and outer domain time corresponding to the TSN bridge;

[0009] Determine, with reference to the inner domain time, a first timestamp of the outer domain synchronization message in the synchronization message entering the inner domain entrance of the TSN bridge;

[0010] Determine a second timestamp and a third timestamp of the outer domain synchronization message entering a preset centralized processing engine in the TSN bridge, respectively, using the inner domain time and the outer domain time as references;

[0011] Determine a time deviation between the TSN bridge and an external domain master clock in the master clock according to the first timestamp, the second timestamp, and the third timestamp, and control the TSN bridge to synchronize with the external domain master clock according to the time deviation.

[0012] In one embodiment, the TSN bridge is a system-side TSN bridge. When the TSN bridge in the communication system receives a synchronization message sent by a master clock, the step of determining the inner domain time and the outer domain time corresponding to the TSN bridge specifically includes:

[0013] When the system-side TSN bridge in the communication system receives a synchronization message sent by the master clock, determining an initial inner domain frequency offset corresponding to the system-side TSN bridge, and determining an initial inner domain clock period according to the initial inner domain frequency offset;

[0014] Determine the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock cycle;

[0015] An initial outer domain clock period is determined according to the initial outer domain frequency offset corresponding to the system-side TSN bridge, and an outer domain time corresponding to the system-side TSN bridge is determined according to the initial outer domain clock period.

[0016] In one embodiment, when the system-side TSN bridge in the communication system receives a synchronization message sent by a master clock, the step of determining the initial inner domain frequency offset corresponding to the system-side TSN bridge specifically includes:

[0017] When the system-side TSN bridge in the communication system receives an inner domain synchronization message sent by an inner domain master clock in a master clock, determining first time sampling information of the inner domain master clock sending the inner domain synchronization message;

[0018] Determine second time sampling information of the system-side TSN bridge receiving the inner domain synchronization message;

[0019] When the system-side TSN bridge receives an adjacent inner-domain synchronization message corresponding to the inner-domain synchronization message and sent by the inner-domain master clock, determining third time sampling information at which the inner-domain master clock sends the adjacent inner-domain synchronization message;

[0020] Determining fourth time sampling information of the system-side TSN bridge receiving the adjacent inner domain synchronization message;

[0021] An initial inner domain frequency offset corresponding to the system-side TSN bridge is determined according to the first time sampling information, the second time sampling information, the third time sampling information, and the fourth time sampling information.

[0022] In one embodiment, the step of determining the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period specifically includes:

[0023] Determining an initial inner domain time of a first iteration according to the initial inner domain clock period;

[0024] Using the initial inner domain time as a reference, returning to the step of determining the initial inner domain frequency offset corresponding to the system-side TSN bridge to obtain a new inner domain frequency offset and a new inner domain time;

[0025] When the new inner domain frequency offset converges to a preset value, the corresponding new inner domain time is used as the inner domain time corresponding to the system-side TSN bridge.

[0026] In one embodiment, after the step of determining the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period, the method further includes:

[0027] Determine the target inner domain clock period corresponding to the system-side TSN bridge according to the inner domain time;

[0028] The system-side TSN bridge is controlled to synchronize with the inner domain master clock in the master clock according to the target inner domain clock period.

[0029] In one embodiment, before the step of determining an initial outer domain clock period according to the initial outer domain frequency offset corresponding to the system-side TSN bridge, and determining the outer domain time corresponding to the system-side TSN bridge according to the initial outer domain clock period, the step further includes:

[0030] When the system-side TSN bridge in the communication system receives an outer-domain synchronization message sent by an outer-domain master clock in the master clock, determining fifth time sampling information of the outer-domain master clock sending the outer-domain synchronization message;

[0031] Determine, with reference to the inner domain time, sixth time sampling information of when the system-side TSN bridge receives the outer domain synchronization message;

[0032] When the system-side TSN bridge receives an adjacent outer domain synchronization message corresponding to the outer domain synchronization message sent by the outer domain master clock, determining seventh time sampling information of the adjacent inner domain synchronization message sent by the outer domain master clock;

[0033] Determining, with the inner domain time as a reference, eighth time sampling information of when the system-side TSN bridge receives the adjacent inner domain synchronization message;

[0034] An initial outer domain frequency offset corresponding to the system-side TSN bridge is determined according to the fifth time sampling information, the sixth time sampling information, the seventh time sampling information, and the eighth time sampling information.

[0035] In one embodiment, the step of determining the time offset between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp, and the third timestamp specifically includes:

[0036] Determine the inner domain residence time between the inner domain entry of the system-side TSN bridge and the preset centralized processing engine according to the first timestamp, the second timestamp, and the outer domain frequency offset;

[0037] Obtaining the source timestamp and correction domain field carried by the outer domain synchronization message;

[0038] The time offset between the system-side TSN bridge and the outer-domain master clock in the master clock is determined according to the third timestamp, the source timestamp, the correction domain field, and the inner-domain residence time.

[0039] In one embodiment, after the step of determining the time offset between the TSN bridge and an external domain master clock in the master clock according to the first timestamp, the second timestamp, and the third timestamp, and controlling the synchronization of the TSN bridge and the external domain master clock according to the time offset, the step further includes:

[0040] When a terminal-side TSN bridge in a communication system receives an outer domain synchronization message forwarded by the system-side TSN bridge, determining a terminal inner domain time and a terminal outer domain time corresponding to the terminal-side TSN bridge;

[0041] Determine, using the terminal inner domain time and the terminal outer domain time as references respectively, a fourth timestamp and a fifth timestamp when the outer domain synchronization message enters the terminal preset centralized processing engine in the terminal-side TSN bridge;

[0042] Determine the terminal time deviation between the terminal-side TSN bridge and the external domain master clock according to the first timestamp, the fourth timestamp, and the fifth timestamp, and control the terminal-side TSN bridge to synchronize with the external domain master clock according to the terminal time deviation.

[0043] In addition, to achieve the above-mentioned purpose, the present application also proposes a time synchronization device, which includes: a memory, a processor, and a time synchronization program stored on the memory and executable on the processor, wherein the time synchronization program is configured to implement the steps of the time synchronization method described above.

[0044] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, on which a time synchronization program is stored. When the time synchronization program is executed by a processor, the steps of the time synchronization method described above are implemented.

[0045] The present application determines the inner domain time and outer domain time corresponding to the TSN bridge when the TSN bridge in the communication system receives the synchronization message sent by the master clock, and then determines the first timestamp of the outer domain synchronization message in the synchronization message entering the inner domain entrance of the TSN bridge with the inner domain time as a reference, and then determines the second timestamp and third timestamp of the outer domain synchronization message entering the preset centralized processing engine in the TSN bridge with the inner domain time and the outer domain time as a reference respectively, and then determines the time deviation between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp and the third timestamp, and controls the synchronization of the TSN bridge and the outer domain master clock according to the time deviation. This application determines the time deviation between the TSN bridge and the outer domain master clock in the master clock based on the first timestamp, the second timestamp and the third timestamp, and can compensate for the residence time of the outer domain synchronization message entering the inner domain entrance of the TSN bridge to the preset centralized processing engine, and obtain the time deviation of the TSN bridge relative to the outer domain master clock, thereby simply and effectively realizing the synchronization of the TSN bridge and the outer domain master clock based on the time deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a schematic diagram of the structure of a time synchronization device in a hardware operating environment according to an embodiment of the present application;

[0047] FIG2 is a flow chart of a first embodiment of a time synchronization method of the present application;

[0048] FIG3 is a flow chart of a second embodiment of the time synchronization method of the present application;

[0049] FIG4 is a flow chart of a third embodiment of the time synchronization method of the present application;

[0050] 5 and 6 are a schematic diagram of a network configuration and a schematic diagram of corresponding message timestamp processing according to an embodiment of a time synchronization method of the present application;

[0051] FIG7 is another networking diagram of an embodiment of the time synchronization method of the present application;

[0052] FIG8 is another networking diagram of an embodiment of the time synchronization method of the present application;

[0053] FIG9 is a schematic diagram of a circuit device according to an embodiment of the time synchronization method of the present application.

[0054] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0056] Refer to Figure 1, which is a schematic diagram of the time synchronization device structure of the hardware operating environment involved in the embodiment of the present application.

[0057] As shown in Figure 1, the time synchronization device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may include a standard wired interface and a wireless interface (such as a wireless fidelity (Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk storage. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0058] Those skilled in the art will appreciate that the structure shown in FIG1 does not limit the time synchronization device and may include more or fewer components than shown, or a combination of certain components, or a different arrangement of components.

[0059] As shown in FIG. 1 , the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a time synchronization program.

[0060] In the time synchronization device shown in Figure 1, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the time synchronization device of the present application can be set in the time synchronization device, and the time synchronization device calls the time synchronization program stored in the memory 1005 through the processor 1001, and executes the time synchronization method provided by the embodiment of the present application.

[0061] Based on the above-mentioned time synchronization device, an embodiment of the present application provides a time synchronization method. Referring to FIG. 2 , FIG. 2 is a flow chart of a first embodiment of the time synchronization method of the present application.

[0062] In this embodiment, the time synchronization method includes the following steps:

[0063] Step S10: When a TSN bridge in the communication system receives a synchronization message sent by a master clock, it determines the inner domain time and outer domain time corresponding to the TSN bridge.

[0064] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a computer, or an electronic device or time synchronization device capable of implementing the above functions. The following uses the time synchronization device as an example to illustrate this embodiment and the following embodiments.

[0065] It can be understood that the communication system in this embodiment can be a fifth-generation communication system. The communication system can include terminals, 5G base stations, and 5G core networks. At the boundary of the virtual bridge, it can include two interface converters, namely the system-side TSN bridge (NW-TT) and the terminal-side TSN bridge (DS-TT). The TSN bridge in this embodiment can be the above-mentioned system-side TSN bridge or the terminal-side TSN bridge.

[0066] In a specific implementation, a TSN bridge may include an inner domain and an outer domain. The master clock may include an inner domain master clock and an outer domain master clock. The inner domain master clock may be a Global Positioning System (GPS), and the outer domain master clock may be a Time Sensitive Network (TSN) domain. Accordingly, synchronization messages may also include inner domain synchronization messages and outer domain synchronization messages. Inner domain synchronization messages are synchronization messages sent from the inner domain to UEs, gNBs, UPFs, etc., while outer domain synchronization messages are synchronization messages sent from the outer domain to TSN bridges, etc. The inner domain time may be the time when an inner domain synchronization message sent by the inner domain is received, and the outer domain time may be the time when an outer domain synchronization message sent by the outer domain is received.

[0067] Step S20: Using the inner domain time as a reference, determine a first timestamp of the outer domain synchronization message in the synchronization message entering the inner domain entry of the TSN bridge.

[0068] It should be understood that the first timestamp can be the moment when the outer domain synchronization message sent by the outer domain enters the inner domain entrance of the TSN bridge with reference to the inner domain time. The first timestamp is obtained under the inner domain time.

[0069] Step S30: using the inner domain time and the outer domain time as references respectively, determining a second timestamp and a third timestamp when the outer domain synchronization message enters the preset centralized processing engine in the TSN bridge.

[0070] It is understood that the preset centralized processing engine refers to a centralized processing engine pre-set in the TSN bridge, which can be the internal time reference plane of the TSN bridge. The second timestamp refers to the time when the outer domain synchronization message sent by the outer domain enters the entry of the preset centralized processing engine, with the inner domain time as the reference. The third timestamp refers to the time when the outer domain synchronization message sent by the outer domain enters the entry of the preset centralized processing engine, with the outer domain time as the reference.

[0071] Step S40: Determine the time deviation between the TSN bridge and the external domain master clock in the master clock according to the first timestamp, the second timestamp, and the third timestamp, and control the TSN bridge to synchronize with the external domain master clock according to the time deviation.

[0072] It should be understood that time deviation refers to the absolute value deviation between the local time counter of the TSN bridge and the external domain master clock. For example, the current local time of the TSN bridge is 1 second after 9:00 on October 11, 2023, and the master clock is 2 seconds after 9:00 on October 11, 2023. The time deviation between the two is 1 second, which can be determined based on the first timestamp, the second timestamp, and the third timestamp. The TSN bridge is controlled to synchronize with the external domain master clock based on the time deviation. For example, if the time deviation of the TSN bridge relative to the external domain master clock is -1 second, the time obtained by the external domain time counter in the TSN bridge is added by 1 second to synchronize the TSN bridge with the external domain master clock. This counter is used to represent the local external domain time of the TSN bridge.

[0073] This embodiment determines the inner domain time and outer domain time corresponding to the TSN bridge when the TSN bridge in the communication system receives the synchronization message sent by the master clock, and then determines the first timestamp of the outer domain synchronization message in the synchronization message entering the inner domain entrance of the TSN bridge with reference to the inner domain time, and then determines the second timestamp and third timestamp of the outer domain synchronization message entering the preset centralized processing engine in the TSN bridge with reference to the inner domain time and the outer domain time respectively, and then determines the time deviation between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp and the third timestamp, and controls the synchronization of the TSN bridge and the outer domain master clock according to the time deviation. This embodiment determines the time deviation between the TSN bridge and the outer domain master clock based on the first timestamp, the second timestamp and the third timestamp, and can compensate for the residence time of the outer domain synchronization message entering the inner domain entrance of the TSN bridge to the preset centralized processing engine, and obtain the time deviation of the TSN bridge relative to the outer domain master clock, thereby simply and effectively realizing the synchronization of the TSN bridge and the outer domain master clock based on the time deviation.

[0074] Refer to FIG3 , which is a flow chart of a second embodiment of the time synchronization method of the present application.

[0075] Based on the above first embodiment, in this embodiment, step S10 includes:

[0076] Step S101: When the system-side TSN bridge in the communication system receives a synchronization message sent by a master clock, it determines an initial inner domain frequency offset corresponding to the system-side TSN bridge, and determines an initial inner domain clock period according to the initial inner domain frequency offset.

[0077] It can be understood that the TSN bridge in this embodiment can be a system-side TSN bridge (NW-TT), the initial inner domain frequency deviation refers to the frequency deviation of the local physical clock in the system-side TSN bridge relative to the inner domain master clock, and the initial inner domain clock period refers to the period of the local physical clock in the system-side TSN bridge.

[0078] Furthermore, in order to accurately determine the initial inner domain frequency deviation corresponding to the TSN bridge, in this embodiment, when the system-side TSN bridge in the communication system receives the synchronization message sent by the master clock, the step of determining the initial inner domain frequency deviation corresponding to the system-side TSN bridge specifically includes: when the system-side TSN bridge in the communication system receives the inner domain synchronization message sent by the inner domain master clock in the master clock, determining the first time sampling information of the inner domain master clock sending the inner domain synchronization message; determining the time sampling information of the system-side TSN bridge receiving the inner domain synchronization message second time sampling information of the inner domain synchronization message; when the system-side TSN bridge receives the adjacent inner domain synchronization message corresponding to the inner domain synchronization message sent by the inner domain master clock, determine the third time sampling information of the adjacent inner domain synchronization message sent by the inner domain master clock; determine the fourth time sampling information of the system-side TSN bridge receiving the adjacent inner domain synchronization message; determine the initial inner domain frequency deviation corresponding to the system-side TSN bridge according to the first time sampling information, the second time sampling information, the third time sampling information and the fourth time sampling information.

[0079] It should be understood that the first time sampling information refers to the time when the inner domain synchronization message is sent by the inner domain master clock, and the second time sampling information refers to the time when the TSN bridge receives the inner domain synchronization message. The adjacent inner domain synchronization message refers to the adjacent message of the inner domain synchronization message when the TSN bridge receives the second time sampling information. The third time sampling information refers to the time when the inner domain master clock sends the adjacent inner domain synchronization message, and the fourth time sampling information refers to the time when the TSN bridge receives the adjacent inner domain synchronization message.

[0080] It is understandable that the initial inner domain frequency offset can be obtained based on the first time sampling information, the second time sampling information, the third time sampling information, and the fourth time sampling information. The initial inner domain frequency offset refers to the inner domain frequency offset at the first iteration. Specifically, Wherein, RRin(1) represents the initial inner domain frequency offset, T1(0) represents the first time sampling information, T2(0) represents the second time sampling information, T1(1) represents the third time sampling information, and T2(1) represents the fourth time sampling information.

[0081] In a specific implementation, the initial inner domain clock period can be determined based on the initial inner domain frequency deviation. Specifically, Ptt(0)=8ns, Ptt(1)=RRin(1)*Ptt(0) can be set first, where Ptt(1) represents the initial inner domain clock period, and RRin(1) represents the initial inner domain frequency deviation.

[0082] Step S102: Determine the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period.

[0083] Furthermore, in order to accurately determine the inner domain time corresponding to the system-side TSN bridge, in this embodiment, step S102 includes: determining the initial inner domain time of the first iteration based on the initial inner domain clock period; using the initial inner domain time as a reference, returning to the step of determining the initial inner domain frequency deviation corresponding to the system-side TSN bridge to obtain a new inner domain frequency deviation and a new inner domain time; when the new inner domain frequency deviation converges to a preset value, the corresponding new inner domain time is used as the inner domain time corresponding to the system-side TSN bridge.

[0084] It should be understood that the initial inner domain time refers to the inner domain time at the first iteration. Specifically, TSin(1) = TSin(0) + Ptt(1), TSin(1) represents the initial inner domain time, TSin(0) represents the previous inner domain time, which can be set in advance, and Ptt(1) represents the initial inner domain clock period.

[0085] It is understandable that after obtaining the initial inner domain time, the steps of determining the inner domain frequency offset, inner domain period, and inner domain time can be repeated with the initial inner domain time as a reference, that is, Ptt(i)=RRin(i)*Ptt(i-1), TSin(i)=TSin(i-1)+Ptt(i), where i represents the number of iterations. The above formula can be used to obtain the new inner domain frequency deviation, new inner domain period, and new inner domain time under each iteration number. The above steps are repeated until the new inner domain frequency deviation converges to a preset value, which can be 1. At this time, the inner domain period approaches the real period, and the corresponding new inner domain time can be used as the inner domain time corresponding to the TSN bridge on the system side.

[0086] In the specific implementation, a time closed-loop tracking model of the inner domain can be established. Specifically, the frequency deviation of the local physical clock in the inner domain of the TSN bridge relative to the inner domain master clock GM is established through a specific mechanism to establish a frequency proportional relationship. For example, for GPS, the frequency proportional relationship can be established based on two 1pps pulses; for 1588 and 1as, the frequency proportional relationship can be established based on two synchronization or pdelay messages; for the fifth generation communication (5G) air interface frame, the frequency proportional relationship can be established based on RRC or SIB9 messages; the mechanism includes the time interval information reflecting the sending side and the time interval information of the local reception. Based on this, a closed-loop feedback system is formed, with the initial RRin(0) = 1 and Ptt(0) being the theoretical clock cycle; the time TSin increases by the step size Ptt in each clock cycle; when the local physical clock is faster than the master clock GM, the step size of TSin is faster than the master clock GM, the interval between T2(i) and T2(i-1) is larger than expected, and the calculated RRin is <1, thereby adjusting the step size of the inner domain time TSin to make it run slower. After several iterations, RRin finally converges to 1, and Ptt approaches the real clock cycle; vice versa; when the local physical clock is slower than the master clock GM, the interval between T2(i) and T2(i-1) is smaller than expected, and the calculated RRin is >1, thereby adjusting the step size of the local time TSin to make it run faster; the calculated RRin value can be properly filtered to make the convergence faster and more stable.

[0087] Furthermore, in this embodiment, in order to achieve synchronization between the system-side TSN bridge and the inner domain master clock, after step S102, it also includes: determining the target inner domain clock period corresponding to the system-side TSN bridge according to the inner domain time; and controlling the system-side TSN bridge to synchronize with the inner domain master clock in the master clock according to the target inner domain clock period.

[0088] It can be understood that the target inner domain clock period refers to the inner domain clock period corresponding to the above-mentioned inner domain time. The target inner domain clock period is used as the clock period of the inner domain of the system side TSN bridge, and according to the IEEE1588V2 protocol, the inner domain of the system side TSN bridge can be synchronized with the inner domain master clock.

[0089] Step S103: determining an initial outer domain clock period according to the initial outer domain frequency offset corresponding to the system-side TSN bridge, and determining the outer domain time corresponding to the system-side TSN bridge according to the initial outer domain clock period.

[0090] Further, in this embodiment, before step S103, it also includes: when the system-side TSN bridge in the communication system receives the outer domain synchronization message sent by the outer domain master clock in the master clock, determining the fifth time sampling information of the outer domain synchronization message sent by the outer domain master clock; using the inner domain time as a reference, determining the sixth time sampling information of the outer domain synchronization message received by the system-side TSN bridge; when the system-side TSN bridge receives the adjacent outer domain synchronization message corresponding to the outer domain synchronization message sent by the outer domain master clock, determining the seventh time sampling information of the adjacent inner domain synchronization message sent by the outer domain master clock; using the inner domain time as a reference, determining the eighth time sampling information of the adjacent inner domain synchronization message received by the system-side TSN bridge; and determining the initial outer domain frequency offset corresponding to the system-side TSN bridge according to the fifth time sampling information, the sixth time sampling information, the seventh time sampling information, and the eighth time sampling information.

[0091] It should be understood that the fifth time sampling information refers to the time of the outer domain synchronization message sent by the outer domain master clock, and the sixth time sampling information refers to the time when the TSN bridge receives the outer domain synchronization message with reference to the inner domain time Tsin. The adjacent outer domain synchronization message refers to the adjacent message of the outer domain synchronization message when the TSN bridge receives the sixth time sampling information. The seventh time sampling information refers to the time of the adjacent outer domain synchronization message sent by the outer domain master clock, and the eighth time sampling information refers to the time when the TSN bridge receives the adjacent outer domain synchronization message with reference to the inner domain time Tsin.

[0092] It is understandable that the initial outer domain frequency offset can be obtained based on the fifth time sampling information, the sixth time sampling information, the seventh time sampling information, and the eighth time sampling information. The initial outer domain frequency offset refers to the outer domain frequency offset at the first iteration. Specifically, In the formula, RRo(1) represents the initial outer domain frequency offset, To3(0) represents the fifth time sampling information, To4(0) represents the sixth time sampling information, To3(1) represents the seventh time sampling information, and To4(1) represents the eighth time sampling information.

[0093] In a specific implementation, the initial outer domain clock period can be determined based on the initial outer domain frequency offset. Specifically, Ptto(0) = 8ns, Ptto(1) = RRo(1) * Ptto(0), where Ptto(1) represents the initial outer domain clock period and RRo(1) represents the initial outer domain frequency offset. TSo(1) = TSo(0) + Ptto(1), where TSo(1) represents the initial outer domain time and TSo(0) represents the previous outer domain time, which can be pre-set. Ptto(1) represents the initial outer domain clock period.

[0094] It should be understood that after obtaining the initial outer domain time, the steps of determining the outer domain frequency offset, outer domain period, and outer domain time can be repeated with the initial outer domain time as a reference. For details, please refer to the method for determining the inner domain time corresponding to the system-side TSN bridge. Specifically, RRo(n) represents the outer domain frequency offset at the nth iteration, To3(h) represents the time of the outer domain synchronization message sent by the outer domain master clock at the nth iteration, and To4(n) represents the time of receiving the outer domain synchronization message sent by the outer domain master clock at the nth iteration with reference to the above inner domain time.

[0095] It is understood that the outer-domain clock period can be determined based on the outer-domain frequency deviation. Specifically, Ptto(n) = RRo(n) * Ptto(n-1), where Ptto(n) represents the outer-domain clock period at the nth iteration. TSo(n) = TSo(n-1) + Ptto(n), where TSo(n) represents the outer-domain time at the nth iteration. After continuous iterations, if the outer-domain frequency deviation approaches 1, the outer-domain time at that iteration can be used as the outer-domain time corresponding to the system-side TSN bridge.

[0096] In its implementation, this embodiment establishes a time tracking model that superimposes the inner and outer domains. A specific mechanism is used to establish a frequency proportional relationship between the inner domain of the TSN bridge and the outer domain frequency offset of the outer domain master clock. For example, the outer domain frequency proportional relationship is established based on the T3 and T4 values ​​of two pdelay messages, according to IEEE802.1AS. The calculated outer domain time can be appropriately filtered to achieve faster and more stable convergence.

[0097] Furthermore, in order to accurately determine the time deviation between the system-side TSN bridge and the outer domain master clock, in this embodiment, the step of determining the time deviation between the TSN bridge and the outer domain master clock in the master clock based on the first timestamp, the second timestamp and the third timestamp specifically includes: determining the inner domain residence time between the inner domain entry of the system-side TSN bridge and the preset centralized processing engine based on the first timestamp, the second timestamp and the outer domain frequency deviation; obtaining the source timestamp and correction domain field carried by the outer domain synchronization message; determining the time deviation between the system-side TSN bridge and the outer domain master clock in the master clock based on the third timestamp, the source timestamp, the correction domain field and the inner domain residence time.

[0098] It can be understood that the inner domain residence time refers to the residence time of the outer domain synchronization message sent by the outer domain master clock in the inner domain of the system side TSN bridge, which can be specifically determined based on the first timestamp, the second timestamp and the outer domain frequency deviation, that is, the inner domain residence time = (Tsi1-Tsi)*RRo, Tsi represents the first timestamp, Tsi1 represents the second timestamp, and RRo represents the outer domain frequency deviation.

[0099] It should be understood that the source timestamp and correction domain field are information carried in the outer domain synchronization message. The time deviation between the system-side TSN bridge and the outer domain master clock in the master clock is offset = t2-CF-t1-(Tsi1-Tsi)*RRo, t2 represents the third timestamp, CF represents the correction domain field, t1 represents the source timestamp, and (Tsi1-Tsi)*RRo represents the inner domain residence time.

[0100] This embodiment determines the initial inner domain frequency offset corresponding to the system-side TSN bridge when the system-side TSN bridge in the communication system receives a synchronization message sent by the master clock, and determines the initial inner domain clock period based on the initial inner domain frequency offset. Then, the inner domain time corresponding to the system-side TSN bridge is determined based on the initial inner domain clock period. Then, the initial outer domain clock period is determined based on the initial outer domain frequency offset corresponding to the system-side TSN bridge, and the outer domain time corresponding to the system-side TSN bridge is determined based on the initial outer domain clock period. This embodiment determines the initial inner domain clock period based on the initial inner domain frequency offset, and then determines the inner domain time corresponding to the system-side TSN bridge based on the initial inner domain clock period. This embodiment can correct the inner domain time based on the inner domain clock period, and correct the outer domain time based on the outer domain clock period.

[0101] Refer to FIG4 , which is a flowchart of a third embodiment of the time synchronization method of the present application.

[0102] Based on the above second embodiment, in this embodiment, after step S40, the method further includes:

[0103] Step S50: When the terminal-side TSN bridge in the communication system receives the outer domain synchronization message forwarded by the system-side TSN bridge, the terminal inner domain time and the terminal outer domain time corresponding to the terminal-side TSN bridge are determined.

[0104] It should be understood that, with reference to Figure 5, Figures 5 and 6 are a networking diagram and a corresponding message timestamp processing diagram of an embodiment of the time synchronization method of the present application. As shown in Figure 5, the inner layer is the fifth generation communication system (5GS), the master clock GM is the global positioning system (GPS), the terminal (UE) and the 5G base station (gNB) are time synchronized through GPS, the 5G core network (UPF) and the 5G base station are time synchronized through IEEE1588V2, and the outer domain master clock is a time-sensitive network TSN domain, which passes through the inner 5GS domain from the 5G core network (UPF) direction. The outer domain synchronization message sent by the outer domain master clock (TSN GM) passes through the system side TSN bridge (NW-TT) and can be forwarded to the terminal side TSN bridge (DS-TT).

[0105] In a specific implementation, the method for determining the terminal inner domain time and the terminal outer domain time corresponding to the terminal-side TSN bridge can refer to the method for determining the inner domain time and the outer domain time corresponding to the system-side TSN bridge. Specifically, on the terminal-side TSN bridge (DS-TT) of the terminal (UE), the frequency relationship between the terminal (UE) and the master clock GM is established through two 1pps sending t1 intervals and receiving t2 intervals of the GPS; Where T1(s)-T1(s-1) is fixed to 1s. Using a similar method, we obtain Ptt and the inner domain time function of DS-TT: TSin1(i)=TSin1(i-1)+Ptt1. After several iterations, Ptt approaches the true period of the physical clock, and the time is synchronized with GPS.

[0106] On the other hand, DS-TT also forwards the synchronization message of the outer domain to the centralized processing engine 2 on DS-TT; after receiving the synchronization message of the outer domain, the centralized processing engine 2 extracts the frequency offset information RRo1 in the message, uses RRo1*Ptt1 as the time step of the outer domain, and obtains the outer domain time function TSo1(m)=TSo1(m-1)+RRo1*Ptt1.

[0107] It can be understood that, as shown in Figure 6, the outer domain TSN GM sends an outer domain synchronization message (Sync message) through the NW-TT to the DS-TT, and the UPF and the outer domain TSN GM pass through the t3 interval (reflecting the outer domain TSN GM frequency) and t4 interval (with the converged inner domain time TSin as a reference, reflecting the frequency of the inner domain 5G master clock GM) of the two pdelay_resp messages. The outer domain synchronization message records the Tsi timestamp (first timestamp) with the inner domain time TSin as a reference at the inner domain entrance of the NW-TT, and carries Tsi and RRo (outer domain frequency offset) into the message and forwards it to the centralized processing engine 1 (preset centralized processing engine); at the entrance of the centralized processing engine 1, the Tsi1 timestamp (second timestamp) is recorded with the inner domain time TSin as a reference, and at the same time, t2 (third timestamp) is recorded with the outer domain TSo as a reference; the near-end entrance to the centralized processing is corrected according to (Tsi1-Tsi)*RRo. The residence time of engine 1; then, according to the t1 (source timestamp) and correction domain CF field (correction domain field) in the 802.1AS protocol synchronization message of the time-sensitive network TSN master clock GM, the time deviation between the local outer domain and the master clock GM can be calculated as offset = t2-CF-t1-(Tsi1-Tsi)*RRo, and the outer domain time of the 5G core network (UPF) is calibrated to TSo(i) = TSo(i-1)+RRo*Ptt+offset, so that it is synchronized with the time-sensitive network TSN master clock GM.

[0108] Step S60: using the terminal inner domain time and the terminal outer domain time as references respectively, determining a sixth timestamp and a seventh timestamp when the outer domain synchronization message enters the terminal preset centralized processing engine in the terminal-side TSN bridge.

[0109] It should be understood that the centralized processing engine 2 (the terminal preset centralized processing engine) records the Tsi2 timestamp (the fourth timestamp) with reference to the terminal inner domain time TSin1, and at the same time, records t2 (the fifth timestamp) with reference to the outer domain time TSo1; and corrects the residence time from the near-end entrance to the remote centralized processing engine 2 according to (Tsi2-Tsi)*RRo.

[0110] Step S70: Determine the terminal time deviation between the terminal side TSN bridge and the external domain master clock according to the first timestamp, the fourth timestamp, and the fifth timestamp, and control the terminal side TSN bridge to synchronize with the external domain master clock according to the terminal time deviation.

[0111] It can be understood that a similar method is used to calculate the terminal time deviation between the outer domain time on DS-TT and TSN GM, offset = t2-CF-t1-(tsi2-tsi)*RRo, and adjust the outer domain time TSo of the terminal-side TSN bridge (DS-TT) to synchronize with the time-sensitive network TSN master clock GM.

[0112] In a specific implementation, refer to FIG7 , which is another networking diagram of an embodiment of the time synchronization method of the present application. As shown in FIG7 , the inner layer is the fifth generation communication system (5GS), the 5G core network (UPF) synchronizes time with the 5G base station through IEEE1588, and the terminal (UE) synchronizes time with the 5G base station through the air interface; the outer domain is a time-sensitive network TSN domain; compared with FIG5 , the difference is that the terminal (UE) synchronizes time with the 5G base station through the air interface; according to 3GPP R17, time can be transmitted through SIB or RRC messages, and the granularity of the reference clock information is increased to 10ns. By comparing the sending and receiving time intervals of the two messages and performing certain filtering processing, a frequency offset relationship is established to obtain RRin and the true Ptt.

[0113] In addition, referring to FIG8 , FIG8 is another networking diagram of an embodiment of the time synchronization method of the present application. As shown in FIG8 , the inner layer is a third-party transmission network, which performs time synchronization through 802.1AS; the outer domain is three independent time-sensitive network TSN domains (it can also be multiple outer domains); compared with FIG5 and FIG7 , the outer domain in FIG8 is three independent time-sensitive network TSN domains; on the inner domain, similar to FIG5 , one inner time TSin, frequency deviation RRin and real period Ptt are maintained; on the proximal bridge side NW_TT of the outer domain, the TSo time function and Frequency offset RRo; The three outer domains each establish a frequency offset relationship with the corresponding GM through an independent pdelay_resp mechanism; Each domain uses TSin as a reference and records t4. The other processes are similar to the previous embodiment; The frequency offsets RRo_1, RRo_2, and RRo_3 of the three domains can be obtained respectively; On the other hand, at the NW_TT entrance, the Tsi timestamps of each outer domain entering NW_TT are latched with the inner domain time TSin, and are carried into each synchronization message respectively; The message is then forwarded to the centralized processing engine; At the centralized processing engine entrance, the inner domain time TSin is used as a reference , respectively latch the timestamps tsi1_1, tsi1_2, and tsi1_3 of each outer domain synchronization message entering the centralized processing engine entrance; at the same time, latch the entrance timestamps t2_1, t2_2, and t2_3 respectively with each outer domain time TSo; according to tsi1_n-tsi_n, the internal residence time of the nth outer domain from the phy entrance to the centralized processing engine is obtained, and the residence time under the outer domain can be corrected by RRo_n as (tsi1_n-tsi_n)*RRo_n; where n=1, 2, 3; according to the residence time, t2_n, t1_n, and cf_n, the The time deviation of the nth outer domain relative to the master clock GM is: offset_n = t2_n - CF_n - t1_n - (Tsi1_n - Tsi_n) * RRo_n. Except for TSo, which requires n sets of circuits to be maintained separately, all other calculations can be processed serially according to the message pipeline to maximize resource savings. On the far_TT side of the outer domain remote bridge, the processing flow is basically similar, except that tsi and RRo are carried in the synchronization message from the near-end bridge. The internal residence time is reflected in the delay from the near-end bridge phy entrance to the far-end bridge centralized processing engine entrance.

[0114] Further, referring to FIG9 , FIG9 is a schematic diagram of a circuit device of an embodiment of the time synchronization method of the present application. As shown in FIG9 , (1) the circuit device includes multiple outer domain ports and one inner domain port; wherein the outer domain port is used for the interaction of outer domain messages passing through the inner domain; the inner domain port is used to realize the synchronization message interaction between the inner domain and the inner GM; (2) an entry timestamp recording unit, for each port, records the entry timestamp of the synchronization message according to the inner domain TSin time at the entry; (3) a message forwarding unit, forwards the synchronization messages of all ports to the centralized processing engine unit; (4) a centralized processing engine unit, For the internal time reference plane mentioned above, for all synchronization messages, the entry timestamp is recorded according to the inner domain TSin time; at the same time, the t2 timestamp is recorded according to the respective outer domain TSo time; in particular, for the inner domain synchronization message, its TSo = TSin; (5), the frequency deviation calculation unit, according to the calculation method mentioned above, calculates the frequency deviation RR relative to each GM packet by packet in a pipeline manner; the frequency deviation is calculated as RRin for the inner message and RRo for the outer domain message; and the frequency deviation information is transmitted to the time deviation calculation unit Element and multi-domain time generation unit; (6), time offset calculation unit, according to the calculation method mentioned above, calculates the internal residence time of each domain packet by packet in a pipeline manner; in particular, for the inner domain, the residence time is (tsi1-tsi), and no frequency offset correction is required; and then calculates the time offset offset of each domain relative to GM; (7), multi-domain time generation unit, according to the calculation method mentioned above, it iterates multiple times to obtain the real cycle step; the real cycle step is Ptt calculated by the inner domain, and RRo*Ptt is calculated for the outer domain message based on the inner domain Ptt and the outer domain RRo; then according to the time function generation method mentioned above, according to the cycle step information, the TS time counter of each domain is generated; according to the time offset information, the time is calibrated to synchronize it with GM; except for the multi-domain time generation unit and the port, which need to be instantiated according to the number of outer domains, all other circuits can be shared, which can greatly save circuit area. At the same time, the inner domain and the outer domain are unified and compatible, and the scalability is greatly enhanced.

[0115] This embodiment determines the terminal inner domain time and terminal outer domain time corresponding to the terminal side TSN bridge when the terminal side TSN bridge in the communication system receives the outer domain synchronization message forwarded by the system side TSN bridge, and then determines the fourth timestamp and fifth timestamp of the terminal preset centralized processing engine when the outer domain synchronization message enters the terminal side TSN bridge with reference to the terminal inner domain time and the terminal outer domain time respectively, and then determines the terminal time deviation between the terminal side TSN bridge and the outer domain master clock according to the first timestamp, the fourth timestamp and the fifth timestamp, and controls the terminal side TSN bridge to synchronize with the outer domain master clock according to the terminal time deviation. This embodiment determines the terminal time deviation between the terminal side TSN bridge and the outer domain master clock based on the first timestamp, the fourth timestamp and the fifth timestamp, and can compensate for the residence time of the outer domain synchronization message entering the inner domain entrance of the terminal side TSN bridge to the terminal preset centralized processing engine, and obtain the terminal time deviation of the terminal side TSN bridge relative to the outer domain master clock, thereby simply and effectively realizing the synchronization of the terminal side TSN bridge and the outer domain master clock based on the terminal time deviation.

[0116] In addition, an embodiment of the present application further proposes a storage medium, on which a time synchronization program is stored. When the time synchronization program is executed by a processor, the steps of the time synchronization method described above are implemented.

[0117] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0118] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as read-only memory / random access memory, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0120] The above are merely optional embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A time synchronization method, wherein, The time synchronization method includes the following steps: When the TSN bridge in the communication system receives the synchronization message sent by the master clock, determine the inner domain time and the outer domain time corresponding to the TSN bridge; Taking the inner domain time as a reference, determine the first timestamp when the outer domain synchronization message in the synchronization message enters the inner domain entrance of the TSN bridge; Taking the inner domain time and the outer domain time as references respectively, determine the second timestamp and the third timestamp when the outer domain synchronization message enters the preset centralized processing engine in the TSN bridge; Determine the time deviation between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp, and the third timestamp, and control the TSN bridge to synchronize with the outer domain master clock according to the time deviation.

2. The time synchronization method according to claim 1, wherein, The TSN bridge is a system-side TSN bridge. The step of determining the inner domain time and the outer domain time corresponding to the TSN bridge when the TSN bridge in the communication system receives the synchronization message sent by the master clock specifically includes: When the system-side TSN bridge in the communication system receives the synchronization message sent by the master clock, determine the initial inner domain frequency offset corresponding to the system-side TSN bridge, and determine the initial inner domain clock period according to the initial inner domain frequency offset; Determine the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period; Determine the initial outer domain clock period according to the initial outer domain frequency offset corresponding to the system-side TSN bridge, and determine the outer domain time corresponding to the system-side TSN bridge according to the initial outer domain clock period.

3. The time synchronization method according to claim 2, wherein, The step of determining the initial inner domain frequency offset corresponding to the system-side TSN bridge when the system-side TSN bridge in the communication system receives the synchronization message sent by the master clock specifically includes: When the system-side TSN bridge in the communication system receives the inner domain synchronization message sent by the inner domain master clock in the master clock, determine the first time sampling information when the inner domain master clock sends the inner domain synchronization message; Determine the second time sampling information when the system-side TSN bridge receives the inner domain synchronization message; When the system-side TSN bridge receives the adjacent inner domain synchronization message corresponding to the inner domain synchronization message sent by the inner domain master clock, determine the third time sampling information when the inner domain master clock sends the adjacent inner domain synchronization message; Determine the fourth time sampling information when the system-side TSN bridge receives the adjacent inner domain synchronization message; Determine the initial inner domain frequency offset corresponding to the system-side TSN bridge according to the first time sampling information, the second time sampling information, the third time sampling information, and the fourth time sampling information.

4. The time synchronization method according to claim 2, wherein, The step of determining the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period specifically includes: Determine the initial inner domain time of the first iteration according to the initial inner domain clock period; Taking the initial inner domain time as a reference, return the step of determining the initial inner domain frequency offset corresponding to the system-side TSN bridge, and obtain a new inner domain frequency offset and a new inner domain time; When the new inner domain frequency offset converges to a preset value, use the corresponding new inner domain time as the inner domain time corresponding to the system-side TSN bridge.

5. The time synchronization method according to claim 2, wherein, After the step of determining the inner domain time corresponding to the system-side TSN bridge according to the initial inner domain clock period, it further includes: Determine the target inner domain clock period corresponding to the system-side TSN bridge according to the inner domain time; Control the system-side TSN bridge to synchronize with the inner domain master clock in the master clock according to the target inner domain clock period.

6. The time synchronization method according to claim 2, wherein, Before the step of determining the initial outer domain clock period according to the initial outer domain frequency offset corresponding to the system-side TSN bridge and determining the outer domain time corresponding to the system-side TSN bridge according to the initial outer domain clock period, it further includes: When the system-side TSN bridge in the communication system receives the outer domain synchronization message sent by the outer domain master clock in the master clock, determine the fifth time sampling information of the outer domain master clock sending the outer domain synchronization message; Taking the inner domain time as a reference, determine the sixth time sampling information of the system-side TSN bridge receiving the outer domain synchronization message; When the system-side TSN bridge receives the adjacent outer domain synchronization message corresponding to the outer domain synchronization message sent by the outer domain master clock, determine the seventh time sampling information of the outer domain master clock sending the adjacent inner domain synchronization message; Taking the inner domain time as a reference, determine the eighth time sampling information of the system-side TSN bridge receiving the adjacent inner domain synchronization message; Determine the initial outer domain frequency offset corresponding to the system-side TSN bridge according to the fifth time sampling information, the sixth time sampling information, the seventh time sampling information and the eighth time sampling information.

7. The time synchronization method according to claim 2, wherein, The step of determining the time deviation between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp and the third timestamp specifically includes: Determine the inner domain residence time between the inner domain entrance of the system-side TSN bridge and the preset centralized processing engine according to the first timestamp, the second timestamp and the outer domain frequency offset; Obtain the source timestamp and the correction domain field carried in the outer domain synchronization message; Determine the time deviation between the system-side TSN bridge and the outer domain master clock in the master clock according to the third timestamp, the source timestamp, the correction domain field and the inner domain residence time.

8. The time synchronization method according to any one of claims 2 to 7, wherein, After the step of determining the time deviation between the TSN bridge and the outer domain master clock in the master clock according to the first timestamp, the second timestamp and the third timestamp and controlling the TSN bridge to synchronize with the outer domain master clock according to the time deviation, it further includes: When the TSN bridge on the terminal side in the communication system receives the outer domain synchronization message forwarded by the TSN bridge on the system side, it determines the terminal inner domain time and the terminal outer domain time corresponding to the TSN bridge on the terminal side; With the terminal inner domain time and the terminal outer domain time as references respectively, it determines the fourth timestamp and the fifth timestamp when the outer domain synchronization message enters the terminal preset centralized processing engine in the TSN bridge on the terminal side; It determines the terminal time deviation between the TSN bridge on the terminal side and the outer domain master clock according to the first timestamp, the fourth timestamp and the fifth timestamp, and controls the TSN bridge on the terminal side to synchronize with the outer domain master clock according to the terminal time deviation.

9. A time synchronization device, wherein, The device includes: a memory, a processor, and a time synchronization program stored on the memory and executable on the processor, and the time synchronization program is configured to implement the steps of the time synchronization method as described in any one of claims 1 to 8.

10. A storage medium, wherein, A time synchronization program is stored on the storage medium, and when the time synchronization program is executed by a processor, it implements the steps of the time synchronization method as described in any one of claims 1 to 8.

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