Digital to analogue converter

Abstract

A capacitive DAC with a capacitor array including a plurality of capacitors. Wherein a plate of at least one capacitor of the array is selectively connectable to a reference voltage via an electrical path. The electrical path having a switching arrangement, which includes a first switching element and a second switching element. Wherein the first switching element is operable between a first switching state, in which the electrical path is conductive, and a second switching state in which the electrical path is non-conductive. Wherein the second switching element is capacitive and is operable between a first switching state, in which the second switching element holds a charge, and a second switching state. Wherein when the second switching element is operated from the first switching state to the second switching state, it injects its stored charge onto the electrical path.

Description

[0001] Digital to Analogue Converter Technical Field

[0002] This disclosure relates to digital to analogue converters (DACs). In particular, this disclosure may relate to capacitive DACs for successive approximation register analogue to digital converters (SAR ADCs), including time interleaved SAR ADCs made up of several sub-ADCs operating in sequence.

[0003] Background

[0004] In digital to analogue conversion using capacitive DACs, it is generally important to provide one or more stable reference voltages. These reference voltages are used in the digital to analogue conversion process to provide a voltage to a capacitor plate in a capacitor array when a corresponding bit of a digital input is set.

[0005] By way of example, a digital input of ‘100T to a four-bit capacitive DAC may be converted to an analogue output by setting one plate of a first capacitor in the array to a high voltage (e.g. Vref), setting one plate of a second capacitor in the array to a low voltage (e.g. 0 V), setting one plate of a third capacitor in the array to the low voltage, and setting one plate of a fourth capacitor in the array to the high voltage. Usually the capacitive DAC starts from an initial (or reset) state and the output of the DAC is then relative to that initial state due to the charge redistribution.

[0006] In many common DAC designs, the capacitance of the first capacitor in the array may be twice the capacitance of the second capacitor in the array such that the charge stored on the first capacitor when it is connected to a high reference voltage is twice the charge stored on the second capacitor in the array when it is connected to the same high reference voltage. Thus, using the same approach for the third and fourth capacitors in the array, the combined output of the capacitors may be proportional to the binary digital input. In other DAC designs the capacitances of the first and second capacitors may be the same, but the high voltage provided to the second capacitor plate may be twice the high voltage provided to the first capacitor plate. It will be apparent that a combination of these approaches may be used.

[0007] Regardless of the approach used, it is important that the reference voltage(s) provided to the DAC are accurate and stable, such that the analogue output is an accurate and consistent representation of the digital input. However, when a reference voltage connects to a capacitor in the array (e.g. by operation of a switch), charge may be absorbed by either the capacitor or the reference voltage source (depending on whether the capacitor is charging or discharging). This movement of charge may result in a temporary variation of the voltage provided by the reference voltage source. To minimise this problem, the reference voltage sources are typically designed to be very responsive, i.e. to have a very fast response to any deviations so as to recover to the intended voltage rapidly (ideally before it is needed as a reference again). However, providing such fast response often involves high power consumption. For high speed capacitive DACs with a lot of switching, it becomes important to avoid or reduce fluctuations in the reference voltage, especially given that the time interval between successive uses of the reference voltage may be very small. Ideally, the reference voltage recovers substantially within this time interval.

[0008] In certain applications, this may be more problematic than in other applications. For example, the DAC output of a capacitive DAC that is used as part of a SAR ADC is used as an intermediate value in the SAR conversion process. If the reference voltage changes from one comparison to the next then the accuracy of the SAR ADC is affected.

[0009] Additional problems can occur, for example, in a time-interleaved SAR ADC in which several ADC sub-stages operate in parallel. If a common reference voltage is used for all of the sub-stages then it is likely that two sub-stages will draw from the voltage reference at substantially the same time (in the sense that the reference voltage cannot recover in between). This results in one sub-ADC influencing the conversion of another, resulting in ADC cross-talk.

[0010] Summary

[0011] According to a first aspect, the present invention provides a capacitive digital to analogue converter (DAC), comprising a capacitor array; wherein the capacitor array comprises a plurality of capacitors; wherein a first plate of at least one capacitor of the capacitor array is selectively connectable to a first reference voltage via a first electrical path; wherein the first electrical path comprises a first switching arrangement; wherein the first switching arrangement comprises a first switching element and a second switching element; wherein the first switching element is operable between a first switching state in which the first electrical path is conductive and a second switching state in which the first electrical path is non-conductive; wherein the second switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the second switching element holds a charge; wherein the second switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the first electrical path.

[0012] By having a second switching element arranged to inject its stored charge onto the first electrical path (and equally able to absorb charge from the first electrical path by switching from the second switching state to the first switching state), a capacitive DAC according to the present invention may provide charge compensation, e.g. so as to reduce the influence on the first reference voltage when the first switching element changes state.

[0013] By way of example, when the first plate of the capacitor is connected to the first reference voltage, charge may be drawn from, or injected into, a first reference voltage source. The amount of charge transfer depends on two sources, the first being the array capacitor of the DAC and the second being the first switching element. If no compensation for this is provided, the charge transfer may result in a small (but undesirable) variation of the first reference voltage. However, with the charge compensation provided by the second switching element, at least some of the charge transfer takes place with the second switching element rather than the reference voltage source. Thus, variation of the first reference voltage may be reduced. In particular, because the second switching element is associated only with the particular array capacitor that is being switched, its charge compensation can be timed to coincide with the charge transfer required by the array capacitor and / or the first switching element. Further, as the second switching element is specific to one array capacitor, its frequency of use may be much lower than the frequency with which the reference voltage is needed. This may be the case for example if the reference voltage is also used by other capacitors in the array and / or by other DACs. The second switching element can be reset (e.g. recharged) at a suitably chosen time when it is less likely to have an adverse impact on the voltage reference. In some embodiments, a switching path of the second switching element is arranged in parallel with the first electrical path. The switching path of a switching element is the electrical path that is made to be conductive or non-conductive depending on the switching state of the second switching element. For example, in a MOSFET, the switching path is the path between source and drain. This means that the second switching element does not affect the conductive state of the first electrical path. The second switching element may thus be considered as a dummy switching element.

[0014] The first switching element may be any type of switching element operable to selectively connect the at least one capacitor of the capacitor array to the first reference voltage. However, in some embodiments, the first switching element is capacitive. Various switching elements with non-negligible parasitic capacitance, such as field effect transistors (FETs) are well suited for use in integrated circuits. However, a capacitive first switching element may absorb / inject charge from / to the first electrical path, adding to the charge transfer required by an associated charging / discharging of the array capacitor. In addition, as the capacitor sizes of DAC arrays becomes ever smaller (making for smaller, cheaper and / or faster DACs), the relative importance of the charge absorbed / injected by the capacitive switching element increases.

[0015] In some embodiments, in one of the first switching state and the second switching state, the first switching element holds a charge, and when the first switching element is operated to the other of the first switching state and the second switching state it injects its stored charge onto the first electrical path. It should be noted that the first switching element may hold charge merely due to its design, i.e. its charge holding property is an unintended consequence of its design, (usually referred to as parasitic capacitance).

[0016] It is possible that absorbing / injecting charge may provide some charge compensation (e.g. if the first switching element is arranged to inject charge when the capacitor charges or if the first switching element is arranged to absorb charge when the capacitor discharges).

[0017] It is also possible that the first switching element may exacerbate the need for charge compensation by the second switching element (e.g. if the first switching element is arranged to inject charge when the capacitor discharges or if the first switching element is arranged to absorb charge when the capacitor charges). In various embodiments, the second switching element may compensate for at least some of the charge injected / absorbed by the at least one capacitor of the capacitor array. It may also compensate for charge transfer due to the switching of the first switching element. However, in some examples, both the first and second switching elements may be arranged to absorb charge at the same time and / or inject charge at the same time. For instance, the first and second switching elements in combination may be arranged to provide charge compensation for at least some of the charge injected to / absorbed by the at least one capacitor of the capacitor array.

[0018] In some embodiments, the first switching element and the second switching element are controlled in opposition such that one injects charge while the other absorbs charge. Thus, the second switching element may be arranged to compensate for at least some of the charge injected / absorbed by the first switching element. This may be particularly useful where the first switching element absorbs charge when the at least one capacitor of the capacitor array absorbs charge, and likewise where the first switching element injects charge when the at least one capacitor of the capacitor array injects charge.

[0019] In some embodiments, the second switching element is arranged to absorb and / or inject the same amount of charge as the first switching element, thus fully compensating for the switching event that connects the array capacitor and leaving the voltage reference only to provide the required charge adjustment to the array capacitor.

[0020] In some embodiments, the second switching element is arranged to absorb and / or inject more charge than the first switching element. Thus, the second switching element may compensate for the charge absorbed / injected by the first switching element and also at least some of the charge absorbed / injected by the at least one array capacitor when the first plate of the capacitor is connected to the first reference voltage.

[0021] It will be appreciated that the amount of charge absorbed or injected will depend on the capacitance of the element as well as the voltage change.

[0022] In some embodiments, the first switching element is a field effect transistor (FET), optionally a MOSFET.

[0023] In some embodiments, the second switching element is a field effect transistor (FET), optionally a MOSFET. In some embodiments the first switching element and the second switching elements may be different types of switching element. Even where both the first switching element and the second switching element are capacitive switching elements, e.g. FETs, it is possible that the first switching element may be dissimilar to the second switching element. For example, the first switching element could be an n-type FET and the second switching element may a p-type FET or vice-versa. In some embodiments, the first switching element and the second switching element are the same type of switching element. This may be convenient for designing (e.g. sizing) the second switching element to compensate appropriately for the first switching element. In addition, or alternatively, it may be convenient to control the first and second switching elements, e.g. such that they operate in opposition, if they are both of the same type.

[0024] In some embodiments, the first switching element and the second switching element are both capacitive and have approximately equal capacitances. When controlled by similar voltages the two switching elements will then compensate for one another.

[0025] In some embodiments, the first switching element and the second switching element are both capacitive and the second switching element has a greater capacitance than the first switching element. For example, the second switching element may have a greater capacitance than the first switching element so as to compensate for at least some charge absorbed / injected by the capacitor in addition to the charge absorbed / injected by the first switching element.

[0026] The first reference voltage could be, for example, a high reference voltage e.g. which represents the maximum analogue output of the DAC. However, in other embodiments the first reference voltage could be a low reference voltage, e.g. ground, or an intermediate reference voltage between a high reference voltage and a low reference voltage.

[0027] In some embodiments, the first plate of the at least one capacitor of the capacitor array is selectively connectable to a second reference voltage via a second electrical path.

[0028] In embodiments where the first reference voltage is a high reference voltage, the second reference voltage may be a low reference voltage. Thus, the capacitor may be selectively connected to either the first input voltage or the second input voltage so as to set the voltage of the first plate of the capacitor to a high or low voltage in accordance with a digital input bit signal. In some embodiments, the second electrical path comprises a second switching arrangement; wherein the second switching arrangement comprises a third switching element and a fourth switching element; wherein the third switching element is operable between a first switching state in which the second electrical path is conductive and a second switching state in which the second electrical path is non-conductive; wherein the fourth switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the fourth switching element holds a charge; wherein the fourth switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the second electrical path.

[0029] Thus, certain embodiments of the capacitive DAC may provide charge compensation when the first plate of the capacitor is connected to the first reference voltage and may also provide charge compensation when the first plate of the capacitor is connected to the second reference voltage.

[0030] It will be readily understood that optional features of the first switching arrangement discussed above may equally be applied to the second switching arrangement. By way of example, the second switching arrangement may be similar to the first switching arrangement, although they may not be identical.

[0031] In some embodiments, the second reference voltage is a low reference voltage. For instance, the second reference voltage may be lower than the first reference voltage. The second reference voltage may be ground.

[0032] In some embodiments, the first switching element and the second switching element are p-type elements; and the third switching element and the fourth switching element are n-type elements. Thus, the same input signal may be used in certain embodiments to control the first and third switching elements to operate as an inverter, thus connecting the capacitor plate to either the first voltage reference or the second voltage reference (but never both).

[0033] In some embodiments, the first switching element and the second switching element are n-type elements; and the third switching element and the fourth switching element are p-type elements.

[0034] It may be preferable to use a p-type first switching element to connect to a high reference voltage. Similarly, it may be preferable to use an n-type switching element to connect to a low reference voltage. Thus, in embodiments where the first reference voltage is a high reference voltage and the second reference voltage is a low reference voltage, a p-type first switching element may be used and an n- type third switching element may be used. The opposite may be true in embodiments where the first reference voltage is a low reference voltage and the second reference voltage is a high reference voltage.

[0035] In some embodiments the first plate of the at least one capacitor of the capacitor array is selectively connectable to a third reference voltage via a third electrical path. The third reference voltage could be, for example, a high reference voltage, e.g. corresponding to a digital input of one, a low reference voltage, e.g. corresponding to a digital input of zero, or an intermediate reference voltage between a high reference voltage and a low reference voltage.

[0036] In some embodiments, the third electrical path comprises a third switching arrangement; wherein the third switching arrangement comprises a fifth switching element and a sixth switching element; wherein the fifth switching element is operable between a first switching state in which the third electrical path is conductive and a second switching state in which the third electrical path is non-conductive; wherein the sixth switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the sixth switching element holds a charge; and wherein the sixth switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the third electrical path.

[0037] Thus, certain embodiments of the capacitive DAC may provide charge compensation when the first plate of the capacitor is connected to the first reference voltage and may also provide charge compensation when the first plate of the capacitor is connected to the third reference voltage. This may be in addition to providing charge compensation when the first plate of the capacitor is connected to the second reference voltage, although it is also possible that charge compensation is only required for the first and third voltages (for example, if the second reference voltage is ground which may be more resilient to voltage variations). It will be readily understood that optional features of the first switching arrangement may be applied to the third switching arrangement. By way of example, the third switching arrangement may be similar to the first switching arrangement, although they may not be identical.

[0038] In some embodiments, the third reference voltage is an intermediate voltage. This intermediate voltage may be lower than a high reference voltage, if present, and / or higher than a low reference voltage, if present. In some embodiments, the DAC is arranged to charge the at least one capacitor to the third, intermediate, reference voltage and then subsequently connect the at least one capacitor to either the first reference voltage or the second reference voltage according to an input signal. The input signal may be a digital input. For example, a digital input of one may correspond with connecting the corresponding array capacitor to a high voltage, whereas a digital input of zero may correspond with connecting the corresponding array capacitor to a low voltage (or vice-versa, e.g. if the input bits are in an inverted form). It will be appreciated that the digital input to the DAC may be in the form of a plurality of input bits, e.g. the most significant bit (MSB), MSB-1 , MSB-2, ... , LSB (least significant bit).

[0039] By selectively providing an intermediate reference voltage to the first plate of the at least one capacitor, e.g. before connecting the first plate to either a high voltage or a low voltage, the charge absorbed / injected by the first plate when it is connected to the high voltage or the low voltage is reduced. In turn, this reduces any variation of the high voltage or the low voltage as provided by the corresponding reference voltage sources.

[0040] The DAC may be arranged to provide the intermediate voltage to the first plate of the capacitor before and / or after providing the first or second reference voltage. For example, between conversions of the DAC, the first plate of the capacitor may be connected to the intermediate voltage ready for the next conversion.

[0041] As the capacitor may need to be returned to the intermediate voltage from either a high voltage or a low voltage, choosing either p-type or n-type switching elements for the third electrical path will be optimal in only one charging direction. To mitigate this, in some embodiments the first plate of the at least one capacitor of the capacitor array is selectively connectable to the third reference voltage via a fourth electrical path; wherein the fourth electrical path comprises a fourth switching arrangement; wherein the fourth switching arrangement comprises a seventh switching element and an eighth switching element; wherein the seventh switching element is operable between a first switching state in which the fourth electrical path is conductive and a second switching state in which the fourth electrical path is non-conductive; wherein the eighth switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the eighth switching element holds a charge; and wherein the eighth switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the fourth electrical path.

[0042] As the third and fourth electrical paths each provide a connection to the third reference voltage, together they provide a lower impedance connection. However, in some embodiments one of the third and fourth switching arrangements may use n-type switching elements and the other may use p-type elements. At least one of the third and fourth electrical paths will then be optimal for resetting the capacitor to the third reference voltage, regardless of whether this is from a higher voltage or a lower voltage.

[0043] It will be appreciated that a capacitive DAC generally comprises multiple array capacitors (one for each bit in the digital input). The charge compensation arrangement may be applied to all array capacitors (i.e. one charge compensation switching arrangement for each array capacitor (and optionally multiple such switching arrangements where each capacitor connects to multiple reference voltages). However, it may not be necessary to implement the charge compensation for all capacitors. Particularly where the capacitors in the array scale from a large capacitor for the MSB to a small capacitor for the LSB, the largest problems typically occur with the larger capacitors. Therefore, it may be sufficient to compensate only for the largest expected charge transfer. However, in many embodiments the charge compensation arrangements discussed above may be applied to more than one capacitor in the array.

[0044] As noted above, some embodiments may use different reference voltages for different array capacitors so as to reduce the size of at least some of the larger capacitors. Thus, in some embodiments, different capacitors within the capacitor array (to which the above charge compensation arrangements are applied) are connectable to different first reference voltages (and, if present, optionally also second and / or third reference voltages).

[0045] In some embodiments, two or more capacitors within the array may have different first reference voltages, but may share the same second reference voltage (e.g. the second reference voltage for both capacitors may be ground); and / or the capacitors may share the same third reference voltage (e.g. a common intermediate reference voltage which lies between all of the second reference voltages and all of the first reference voltages).

[0046] Having different reference voltages for different capacitors in the array provides an alternative means of scaling the array elements other than scaling the sizes of the capacitors. While this requires provision of more reference voltages, it allows smaller capacitors to be used and is thus useful in certain implementations. It will be appreciated that combinations of reference voltage and capacitor size may be used. Thus, the array may have more than one first reference voltage (and / or more than one second reference voltage and / or more than one third reference voltage). It may, but need not, have one first (and / or second and / or third) reference voltage for each array capacitor.

[0047] By way of example, a first plate of a second capacitor of the at least two capacitors of the capacitor array may be selectively connectable to one or more reference voltages via a respective one or more electrical paths; wherein one or more of the one or more electrical paths may comprise a respective switching arrangement; wherein one or more of the respective switching arrangements may comprise a first switching element and a second switching element; wherein the first switching element is operable between a first switching state in which the respective electrical path is conductive and a second switching state in which the respective electrical path is non-conductive; wherein the second switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the second switching element holds a charge; wherein the second switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the respective electrical path. In such embodiments, the one or more reference voltages to which the first plate of the second capacitor is able to be selectively connected may be the same one or more reference voltages to which the first plate of the first capacitor is selectively connected, or they may be different reference voltages.

[0048] In some embodiments, more than one capacitor of the plurality of capacitors of the capacitor array has a first plate selectively connectable to the first reference voltage via a respective first electrical path and a respective first switching arrangement. When more than one capacitor is connectable to the same reference voltage, it will be appreciated that the possibility of voltage variation increases, e.g. if two or more capacitors draw from the reference at the same time or very close in time. In such arrangements the charge compensation on each capacitor helps to alleviate the problem.

[0049] In some embodiments, the more than one capacitor (for which charge compensation arrangements are provided) includes at least the two capacitors in the array that are arranged to hold the largest charge. It will be appreciated that this may be the capacitors for the MSB and MSB-1 bits. Alternatively, for example, in examples wherein the DAC comprises a split capacitor array, a first capacitor of the more than one capacitors may represent the most significant bit of the DAC and a second capacitor of the more than one capacitors may represent another bit approximately half-way (or more generally part-way) between the most significant bit and the least significant bit of the DAC.

[0050] The first reference voltage can be provided by any suitable stable reference voltage supply. However, in some embodiments the first reference voltage is provided by a first reference voltage supply; wherein the first reference voltage supply comprises a multi-stage amplifier with a dominant output pole. Using a multistage amplifier for a reference voltage supply is fairly common practice as it provides a voltage buffer with low output impedance driven by a highly stable voltage reference circuit such as a bandgap voltage reference circuit. However, the multi-stage amplifier of such circuits is normally arranged so that the output pole is not dominant. Instead, the amplifier is designed such that a pole associated with an earlier stage of the amplifier is dominant. The dominant pole stage is typically slower to respond. As discussed above, fast response speed is generally a key concern for voltage reference supplies for capacitive DACs. However, according to the arrangements described here, the first reference voltage supply is unusually designed with a dominant output pole. Given the charge compensation that may be provided by the capacitive switching elements discussed above (e.g. by the first switching arrangement), the strain on the reference voltage supply is reduced such that a slower response of the multi-stage amplifier can be tolerated. Having a dominant output pole means that the amplifier can be designed to have a reduced power consumption. In design scenarios such as capacitive DACs with a well- defined capacitive load, normal practice for a two stage amplifier design would be to ensure stability by making the input stage pole dominant. This can be done for example by introducing a Miller capacitance across the output stage that slows down the first stage, making it dominant. It will be appreciated that there are other ways of achieving first stage pole dominance. By contrast, the amplifier here is designed to have a dominant output pole which in turn means that the input stage should be designed to be fast enough to ensure amplifier stability.

[0051] In some embodiments, the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the reference voltage. The reservoir capacitor can hold a significant charge such that its voltage is relatively stable with small variations of charge. As the charge compensation arrangements discussed above reduce the charge drawn by / provided to the array capacitor, the influence that these charge movements have on the voltage of the reservoir capacitor is sufficiently small that it can be adequately compensated by the slower amplifier (i.e. one with a dominant output pole). Thus, the charge compensation arrangements allow for a lower power amplifier to be used for the reference voltage supply. The reservoir capacitor acts to decouple the multi-stage amplifier from the array capacitor(s). In addition to its decoupling effect on the capacitor array, the reservoir capacitor also influences the multi-stage amplifier. In particular, a large reservoir capacitor pulls the output pole to be more dominant, as desired. This can be exploited to reduce the power consumption of the amplifier as explained above. In particular, it is the reservoir capacitor together with the biasing of the amplifier stages that makes the output pole dominant.

[0052] In particular, as the reservoir capacitor makes the output stage dominant and stability is then ensured via design of the first stage to be fast enough, there is no need for a Miller capacitance. Nor is there any need for feed forward stabilisation techniques. Thus the amplifier design is simpler and has lower power consumption. Accordingly, in some embodiments, the multi-stage amplifier has no Miller capacitor and / or no feed forward stabilisation. According to a second aspect, the invention provides a differential capacitive DAC comprising a positive DAC and a negative DAC, wherein each of the positive DAC and negative DAC are capacitive DACs according to any of the embodiments of the first aspect of the invention, and wherein both the positive DAC and the negative DAC are driven by parts of the same input. For example the positive DAC and the negative DAC may be driven by a differential input, i.e. by the positive and negative parts of the same input. Minor differences in control logic may be needed, e.g. due to signal inversion.

[0053] The inputs to the positive DAC and the negative DAC may be inverted such that the two DACs can use the same reference voltages. Alternatively, the negative DAC may receive the same input (non-inverted) but instead uses reference voltage(s) that are the negative equivalent of the respective reference voltage(s) of the positive DAC. If a positive DAC and a negative DAC share a reference voltage supply, then the load on that supply increases and the charge compensation becomes more beneficial.

[0054] A differential capacitive DAC may ensure that any voltage fluctuations experienced by both the positive DAC and the negative DAC, e.g. resulting from electromagnetic interference, are cancelled out when the outputs of the DACs are differenced.

[0055] According to a third aspect, the invention provides a successive approximation register analogue to digital converter comprising a capacitive DAC according to any of the embodiments of the first or second aspects of the invention.

[0056] According to a fourth aspect, the invention provides a time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC according to the third aspect of the invention; and wherein at least one reference voltage is shared by a plurality of sub-ADCs.

[0057] In some embodiments, each of the plurality of sub-ADCs has a local reference capacitor to provide a local reference voltage; and each sub-ADC recharges its local reference capacitor from a global reference voltage supply once per conversion. The global reference voltage may be the previously mentioned first reference voltage. Recharging the local reference capacitor from the global reference voltage supply ensures that there is no cross-talk between sub-ADCs as each sub-ADC can complete a conversion process without being connected to any component common to the other sub-ADCs. In addition, as the sub-ADCs only connect to the global reference voltage once per conversion and the sub-ADCs are typically used sequentially, the local reference capacitors will generally recharge from the global reference voltage supply in sequence and thus will spread the load on the reference supply in time so that the global reference voltage supply can remain relatively stable.

[0058] In various embodiments, there may be two or more global reference voltages, e.g. corresponding to two or more of the previously mentioned first reference voltage, second reference voltage and third reference voltage. In such embodiments, each of the plurality of sub-ADCs may have a respective local reference capacitor for each of the global reference voltages.

[0059] In some embodiments, the global reference voltage comprises a multi-stage amplifier with a dominant output pole. As the load from the sub-ADCs is spread out in time, such an amplifier provides an adequate responsiveness while consuming less power for the reasons discussed above.

[0060] In some embodiments, the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the global reference voltage. As discussed above, the reservoir capacitor may be sized so as to ensure that the output pole of the multi-stage amplifier is dominant.

[0061] According to a fifth aspect, the invention provides a capacitive DAC having at least one reference voltage supply for charging and / or discharging a switched capacitor array; wherein the reference voltage supply comprises a multi-stage amplifier with a dominant output pole.

[0062] As discussed above, having a multi-stage amplifier with a dominant output pole may be more power efficient than a multi-stage amplifier with a non-dominant output stage. However, this is counter-intuitive for capacitive DACs as the dominant output pole makes the amplifier relatively slow to react to changes whereas capacitive DACs operate very fast. However, in certain applications and / or in combination with other mechanisms to alleviate the effects of charging the capacitive array, a multi-stage amplifier with a dominant output pole may be suitable. In particular, in combination with a charge compensation on at least some parts of the capacitive array, such an amplifier is suitable and may be designed to advantageously have lower power. In some embodiments, the multi-stage amplifier is a voltage buffer amplifier. The voltage buffer amplifier typically buffers a high output impedance reference voltage circuit such as a band gap circuit.

[0063] In some embodiments, the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the reference voltage. Such a reservoir capacitor may be arranged to store charge and / or may be arranged to decouple the multistage amplifier from the capacitive array of the DAC. The reservoir capacitor has the dual purpose of making the output pole of the amplifier dominant (in combination with the amplifier biasing) and also providing a large charge reservoir to stabilise the voltage supplied to the array capacitors. Thus, the reservoir capacitor itself compensates for the slowing effect that it has on the amplifier, while reducing the power consumption of the amplifier.

[0064] In some embodiments, the reservoir capacitor is sized to ensure that the amplifier output pole is dominant.

[0065] In some embodiments, the multi-stage amplifier has no Miller capacitor and / or no feed forward stabilisation.

[0066] According to a sixth aspect, the invention provides a successive approximation register analogue to digital converter comprising a capacitive DAC according to any of the embodiments of the fifth aspect.

[0067] According to a seventh aspect, the invention provides a time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC according to any of the embodiments of the sixth aspect; wherein the reference voltage supply is a global reference voltage supply shared between all the sub-ADCs; wherein each sub-ADC comprises a local reservoir capacitor; and wherein each sub-ADC is arranged to recharge its local reservoir capacitor from the global reference voltage supply once per conversion.

[0068] According to an eighth aspect, the invention provides a method of operating a capacitive digital to analogue converter (DAC), comprising a capacitor array; wherein the capacitor array comprises a plurality of capacitors; the method comprising: selectively connecting a first plate of at least one capacitor of the capacitor array to a first reference voltage via a first electrical path by operating a first switching element of a switching arrangement from a second switching state in which the first electrical path is non-conductive to a first switching state in which the first electrical path is conductive; and operating a second switching element of the switching arrangement from a first switching state in which the second switching element holds a charge to a second switching state such that the second switching element injects its stored charge onto the first electrical path.

[0069] It will be appreciated that a DAC having the features of any of the embodiments of the first aspect of the invention may be arranged to perform this method. Thus, optional features of the first aspect of the invention may be equally applicable to the eighth aspect.

[0070] According to a ninth aspect, the invention provides method of operating a differential capacitive DAC, comprising a positive DAC and a negative DAC, wherein each of the positive DAC and negative DAC are operated according to the method of any of the embodiments of the eighth aspect of the invention, and wherein both the positive DAC and the negative DAC are driven by parts of the same input. For example, the positive DAC and negative DAC may be driven by a positive part and a negative part of a differential input signal.

[0071] It will be appreciated that a differential capacitive DAC having the features of any of the embodiments of the second aspect of the invention may be arranged to perform this method. Thus, optional features of the second aspect of the invention may be equally applicable to the ninth aspect.

[0072] According to a tenth aspect, the invention provides a method of operating a successive approximation register analogue to digital converter comprising a capacitive DAC, wherein the capacitive DAC is operated according to the method as of any of the embodiments of the ninth aspect of the invention.

[0073] It will be appreciated that a successive approximation register analogue to digital converter having the features of any of the embodiments of the third aspect of the invention may be arranged to perform this method. Thus, optional features of the third aspect of the invention may be equally applicable to the tenth aspect.

[0074] According to an eleventh aspect, the invention provides a method of operating a time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC operated according to the method of any of the embodiments of the tenth aspect of the invention; and wherein at least one reference voltage is shared by a plurality of sub-ADCs.

[0075] It will be appreciated that a time interleaved ADC having the features of any of the embodiments of the fourth aspect of the invention may be arranged to perform this method. Thus, optional features of the fourth aspect of the invention may be equally applicable to the eleventh aspect.

[0076] According to a twelfth aspect, the invention provides a method of operating a time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC comprising a capacitive DAC having a switched capacitor array; the time interleaved ADC comprising at least one global reference voltage supply for charging and / or discharging each switched capacitor array; wherein the global reference voltage supply comprises a multi-stage amplifier with a dominant output pole; wherein each sub-ADC comprises a local reservoir capacitor; the method comprising: recharging each local reservoir capacitor from the global reference voltage once per conversion.

[0077] It will be appreciated that a time interleaved ADC having the features of any of the embodiments of the seventh aspect of the invention may be arranged to perform this method. Thus, optional features of the seventh aspect of the invention may be equally applicable to the twelfth aspect.

[0078] Brief Description of Drawings

[0079] One or more non-limiting examples will now be described, by way of example only, and with reference to the accompanying figures in which:

[0080] Figure 1 shows a successive approximation register analogue to digital converter (SAR ADC) including a differential capacitive digital to analogue converter (DAC) including a positive capacitive DAC and a negative capacitive DAC;

[0081] Figure 2 shows a capacitive DAC which may be either the positive or negative half of the differential DAC of Figure 1, the DAC includes a switching arrangement for selectively connecting a first capacitor in a capacitor array to one or more reference voltages;

[0082] Figure 3 shows a switching arrangement for the capacitive DAC of Figure 2;

[0083] Figure 4 shows the control logic for the switching relay of Figure 3; Figure 5 shows a variation of the switching relay of Figure 3;

[0084] Figure 6 shows a voltage source to provide a reference voltage for the negative capacitive DAC of Figure 2;

[0085] Figure 7 shows a time interleaved ADC comprising several ADC sub-stages, each of which may be similar to the ADC sub-stage shown in Figure 1 ; and

[0086] Figure 8 shows a voltage source to provide a reference voltage for a capacitive DAC.

[0087] Detailed Description

[0088] Figure 1 shows a successive approximation register analogue to digital converter (SAR ADC) 100. The SAR ADC 100 includes a capacitive digital to analogue converter (DAC) 106, a comparator 109 and a controller 110.

[0089] The SAR ADC 100 is arranged to receive a positive input voltage 104 and a negative input voltage 105 of the same magnitude, but the opposite polarity.

[0090] The capacitive DAC 106 in this example is a differential CDAC and includes a positive DAC and a negative DAC. The positive DAC is arranged to produce a positive output voltage VDAC+ 107, and the negative DAC is arranged to produce a negative output voltage VDAC- 108 of the same magnitude, but the opposite polarity.

[0091] The capacitive DAC 106 receives a first reference voltage 101 , a second reference voltage 102 and a third reference voltage 103. The first reference voltage 101 is a high reference voltage, the second reference voltage 102 is a low reference voltage and the third reference voltage 103 is an intermediate reference voltage, between the high reference voltage and the low reference voltage. In use, the capacitive DAC 106 uses the first 101 and second 102 reference voltages as the upper and lower limits of its analogue output. The intermediate reference voltage 103 is used for efficiency as will be explained later, with reference to Figure 2.

[0092] In use, the SAR ADC 100 deducts the output of the positive DAC from the positive input voltage 104 to provide a positive difference signal 107.

[0093] Similarly, the SAR ADC 100 deducts the output of the negative DAC from the negative input voltage 105 to provide a negative difference signal 108.

[0094] In use, the comparator 109 compares the positive difference signal 107 with the negative difference signal 108. If the result of the comparison is positive, this indicates a magnitude of input voltage 104, 105 greater than the magnitude of the DAC 106 output, while a negative result indicates a smaller magnitude of input voltage 104, 105 than the magnitude of the DAC 106 output. This differential approach provides an arrangement that is robust to systematic or common mode errors on the input voltage 104, 105 and / or the DAC 106 outputs VDAC+ 107, VDAC- 108, e.g. as a result of electromagnetic interference, capacitive coupling, supply variation, substrate noise, etc.

[0095] In use, the controller iteratively sets the digital input 111 to the DAC 106 based on the output of the comparator 109 so as to set the magnitude of the positive and negative outputs of the DAC 106, and thus the positive and negative difference signals 107, 108. The SAR ADC 100 attempts to set the DAC 106 outputs so as to cancel the input voltage 104, 105 (and thus make the difference signals 107, 108 as small as possible). The digital input 111 also forms the basis of the SAR ADC output.

[0096] The SAR ADC 100 shown in Figure 1 may be one ADC sub-stage of a time- interleaved ADC, e.g. as shown in Fig. 7. A time-interleaved ADC gains processing speed at the expense of area by directing input samples to different ADC substages in turn, the sub-stages operating in parallel to produce digitised outputs of the samples which may be output by the ADC sub-stages in the same order as they were sampled.

[0097] In this example, the first 101 , second 102 and third 103 reference voltages are shared by all of the SAR ADC sub-stages. Due to this sharing of reference voltages, it is particularly important to ensure stability of the reference voltage sources to minimise risk of cross-talk.

[0098] Figure 2 shows a capacitive DAC 200 which may form one half (either positive or negative) of the capacitive DAC 106 of Figure 1. The DAC 200 includes a capacitor array 201. The capacitor array has several capacitors CO to C8 and CS. The first capacitor 202 (CO) in this example corresponds to the most significant bit of a digital input, e.g. the digital input 111 of Figure 1 or an inverted version of this digital input 111.

[0099] The output 108 (VDAC in Figure 2, corresponding to VDAC+ or VDAC- of Figure 1) of the DAC 200 is the voltage on the top plates of the capacitors in the capacitor array 201 (in this example, it is the voltage on the top plates of CO to C4 to the left of the split capacitor 204). This voltage is determined by the voltages applied to the bottom plates of the capacitors and the sizes of the capacitors. In this example, because the DAC 200 is part of the SAR ADC 100, a sampler 207 is arranged to sample the input voltage (positive input 104 or negative input 105) of the SAR ADC 100 onto the top plate of each of the capacitors in the capacitor array 201. The DAC 200 then modifies this voltage based on its digital input. In the specific case of the SAR ADC 100, the DAC 200 is used to try to cancel the input voltage 104, 105 as closely as possible. The positive DAC and the negative DAC that form the differential DAC 100 of Figure 1 work in the same manner.

[0100] The DAC 200 includes a set of switches for each of the capacitors in the capacitor array 201. For instance, the set of switches 203 for the first capacitor 202 and the set of switches 206 for the second capacitor 205 are labelled in Figure 2 (the other sets of switches can be seen, but are not labelled).

[0101] The set of switches 203 is able to connect the bottom plate of the first capacitor 202 to one of the first reference voltage 101 , the second reference voltage 102 or the third reference voltage 103.

[0102] If the most significant bit of the digital input is one, the set of switches 203 connects the bottom plate of the first capacitor 202 to the first reference voltage 101. If the most significant bit of the digital input is zero, the set of switches 203 connects the bottom plate of the first capacitor to the second reference voltage 102.

[0103] When the set of switches 203 connects the bottom plate of the first capacitor 202 to one of the reference voltages 101 , 102, 103, charge moves between the reference voltage source and the capacitor plate. The movement of charge to or from the reference voltage source may result in variation of the reference voltage 101 , 102, 103. The more charge that is transferred, the greater the effect on the reference voltage 101 , 102, 103. This problem can be exacerbated when the reference voltages 101 , 102, 103 supply several (or indeed all) capacitors in the array 201 , which is the case in this example.

[0104] In order to reduce the movement of charge to / from the first and second reference voltage sources in a single switching operation, the bottom plate of the first capacitor 202, and the other capacitors in the array 201, is connected to the third, intermediate, reference voltage 103 between cycles of the DAC 200. This means that when the bottom capacitor plate is connected to the first reference voltage 101, less, e.g. half as much, charge is required to increase the voltage to the reference voltage 101. The same is true for movement of charge to / from the low reference voltage source when the bottom capacitor plate is connected to the low reference voltage 102.

[0105] Thus, providing a third, intermediate, reference voltage 103 to the bottom plates of the capacitors in the array 201 between cycles of the DAC 200 may reduce variation of the first 101 and second 102 reference voltages.

[0106] A second capacitor 205 corresponds to the next most significant bit of the digital input to the DAC 200. The capacitance of the second capacitor 205 is typically around half the capacitance, i.e. half the size, of the first capacitor 202 such that only half the charge is required to reach the same first reference voltage 101. It will be appreciated that the capacitors in the array need not be sized with ratios of two, but may be sized with ratios less than two (which may be referred to as a sub-radix 2 array). For example, it is advantageous in some implementations to undersize capacitors so that they have a size ratio of 1.8 or 1.85 which alleviates problems that can arise due to process variations in smaller implementations, although it requires an extra process at the digital side to reconstruct the signal. In particular, the capacitors can be sized for thermal noise rather than for device mismatch which results in small devices (less area required).

[0107] As previously mentioned, the second capacitor has a corresponding set of switches 206, which is similar to the set of switches 203 of the first capacitor 202.

[0108] In this example, the DAC 200 is a nine-bit DAC, which has an array 201 of nine capacitors (CO to C8). If each capacitor in the array 201 stored half the charge as the previous capacitor in the array 201, the first capacitor 202 (CO) in the array 201 would have to store two-hundred and fifty-six times the charge of the ninth capacitor (C8) in the array 201. This could be achieved, for example, by using a first capacitor (CO) that is two-hundred and fifty-six times as large as than the ninth capacitor (C8); or by using a reference voltage for the first capacitor (CO) that is two-hundred and fifty-six times as large as than the ninth capacitor (C8) (or an appropriate combination of size and reference voltage to achieve the same effect).

[0109] In this example, the DAC 200 uses a split capacitor arrangement which includes a split capacitor 204 to reduce the charge drawn by the size of the larger capacitors in the array 201. The split capacitor 204 is appropriately sized to reduce the charge contribution of the sixth, seventh, eighth and ninth capacitors in the array 201 to the output 107 by a factor of 16. As a result, the fifth capacitor (C4) may be sized similarly to the ninth capacitor (C8), the fourth capacitor (C3) may be sized similarly to the eight capacitor (C7) and so on. Thus, the largest capacitor in the array (CO) 201 only draws sixteen times the charge of the smallest capacitors (C4 and C8) when connected to the reference voltages 101, 102, 103. This reduction in capacitor sizes reduces variation of the reference voltages 101 , 102, 103 associated with the movement of charge to / from the reference voltage sources. It will be apparent that more than one split capacitor could be used as necessary.

[0110] Figure 3 shows the set of switches 203 of the first capacitor 202 of the DAC 200 of Figure 2 (or equivalently any other set of switches for other capacitors in that figure). The set of switches 203 includes a first switching arrangement 310, a second switching arrangement 320 and a third switching arrangement 330.

[0111] The first switching arrangement 310 selectively connects the bottom plate of the first capacitor 202 (connected at the node labelled VOIIT) to the first reference voltage 101.

[0112] The first switching arrangement includes a first switching element 311 and a second switching element 312. The first switching element 311 is arranged between the first reference voltage 101 and the bottom plate of the first capacitor 202 via a first electrical path 313. Therefore, when the first switching element is conductive, the first reference voltage is provided to the bottom plate of the first capacitor 202.

[0113] When the bottom plate of the first capacitor 202 is connected to the first reference voltage, charge moves between the first reference voltage source and the capacitor plate.

[0114] In this example, the first switching element 311 is a MOSFET. As the MOSFET is a capacitive device, when the first switching element 311 changes state, charge is either absorbed by the MOSFET or injected from the MOSFET onto the first electrical path 313.

[0115] In this example, the second switching element 312 is a MOSFET which also either absorbs or injects charge to the first electrical path 313 when it changes switching state.

[0116] The second switching element 312 is arranged to change switching state at the same time as the first switching element 311 changes switching state. Thus, when the first reference voltage 101 is connected to the bottom plate of the first capacitor 202, the second switching element 312 provides charge to the first electrical path 313 to compensate for the charge otherwise moved from the first reference voltage source to the first switching element 311 and / or to the bottom plate of the first capacitor 202. In this example, the first switching element 311 and the second switching element 312 are both p-type MOSFETs, and thus for the second switching element 312 to compensate for the charge that the first switching element 311 absorbs / injects it must conduct when the first switching element 311 does not conduct and vice-versa. The second switching element is therefore arranged as a dummy switch with its drain and source connected so that it is always-conductive. Thus, operation of this dummy switch does not affect the conductivity of the first electrical path 313. Instead, the function of the dummy switch is to provide charge compensation.

[0117] The second switching arrangement 320 is similar to the first switching arrangement 310 and is arranged to selectively connect the bottom plate of the first capacitor 202 to the second reference voltage 102 via a second electrical path 323. However, the first switching element 321 and the second switching element 322 of the second switching arrangement 320 are both n-type MOSFETs in this example. In a similar manner, the second switching element 322 of the second switching arrangement 320 is a dummy switch that does not affect the conductivity of the second electrical path 323 but only provides charge compensation for the first switching element 321 and / or the first capacitor 202.

[0118] The third switching arrangement 330 in this example includes a first switching element 331 , a second switching element 332, a third switching element 333 and a fourth switching element 334.

[0119] The first switching element 331 and the second switching element 332 of the third switching arrangement 330 are similar to the first switching element 321 and the second switching element 322 of the second switching arrangement 320, and operate in a similar manner to selectively connect the bottom plate of the first capacitor 202 to the third reference voltage 103 via a third electrical path 335.

[0120] The third switching element 333 and the fourth switching element 334 of the third switching arrangement 330 are similar to the first switching element 311 and the second switching element 312 of the first switching arrangement 310, and operate in a similar manner to selectively connect the bottom plate of the first capacitor 202 to the third reference voltage 103 via a fourth electrical path 336.

[0121] The first 331 and second 332 switching elements of the third switching arrangement 330 operate in tandem with the third 333 and fourth 334 switching elements of the third switching arrangement 330 such that both pairs of switching element connect the bottom plate of the output capacitor 202 to the third reference voltage 103 at the same time.

[0122] In this example, the third switching arrangement 330 has a p-type pair of switching elements 333, 334 and an n-type pair of switching elements 331 , 332 to ensure that the switch impedance is sufficiently low when connecting the third reference voltage 103 to the bottom plate of the capacitor 202 regardless of whether it was previously connected to a the first reference voltage 101 or the second reference voltage 102. Providing an electrical path 336 which uses p-type MOSFETs 333, 334 and another electrical path 335 which uses n-type MOSFETs 331 , 332 ensures that charging / discharging is efficient regardless of whether the voltage of the bottom plate of the capacitor 202 is being adjusted from VHI 101 or VLO 102 to VCM 103.

[0123] On the other hand, only p-type MOSFETs 311 , 312 are used on the first electrical path 313 as VHI 101 will always be equal to or higher than the bottom plate of the capacitor 202. Similarly, the bottom plate of the capacitor 202 will always be equal to or higher than LO 102, and so only n-type MOSFETs 321 , 322 are used on the second electrical path 323.

[0124] In this example, the charge contribution of the third switching element 333 when it is switched to a state where it conducts is substantially equal and opposite to the charge contribution of the first switching element 331 when it is switched to a state where it conducts. Thus, the charge contribution to the electrical paths 335, 336 of the first and third switching elements 331, 333 may effectively cancel out. As a result, the second and fourth switching elements 332, 334 only need to compensate for any difference between the charge contributions of the first and third switching elements 331 , 333 and to compensate for the movement of charge between the capacitor 202 and the third reference voltage 103.

[0125] Figure 4 shows the switch control logic of the switching elements shown in Figure 3. Note that Figure 4 includes two pairs of columns, one headed “POS” and defining operation for switching elements on the positive half of the differential DAC106, the other headed “NEG” and defining operation for switching elements on the negative half of the differential DAC 106. The value input ‘VAL’ is the bit value of the digital input to be converted to analogue. Note that this is inverted for the positive and negative DACs. The enable input ‘EN’ is held ‘0’ until it is desired to perform a switching operation and it is changed to T when it is time to switch the corresponding capacitor to either the first or second reference voltages 101, 102. Thus, when the enable input ‘EN’ is ‘O’, the value input ‘VAL’ does not affect operation of the positive or negative half of the DAC 106.

[0126] As can be seen from Figure 4, when enable is set to ‘0’ and value is set to ‘O’, the bottom plate of the first capacitor 202 is connected to the third reference voltage 103 and is disconnected from the first reference voltage 101 and the second reference voltage 102. Specifically, CTL3 is T which puts the first switching element 311 of the first switching arrangement 310 in a non-conducting state, thereby disconnecting the first reference voltage 101 via the first electrical path 313. CTL2 is ‘0’ which puts the first switching element 321 of the second switching arrangement 320 in a non-conducting state, thereby disconnecting the second reference voltage 102 by making the second electrical path 323 non-conductive. CTL1 is ‘0’ and CTLo is T so that both the first switching element 331 and third switching element 333 of the third switching arrangement 330 are in a conducting state, thereby connecting the third reference voltage 103 via both the third electrical path 335 and the fourth electrical path 336.

[0127] When enable is set to ‘0’ and value is set to T, the same situation applies (all switching states are the same), i.e. the bottom plate of the first capacitor 202 is connected to the third reference voltage 103. Thus, the bottom plate of the first capacitor 202 remains connected to the third reference voltage 103 while the enable input is ‘O’, regardless of the state of the value input.

[0128] For a switching arrangement on a negative half of a DAC 106, the fifth and sixth columns of Table 1 in Fig. 4 apply (as well as the seventh and eighth columns which are common to both the positive half of the DAC and the negative half of the DAC). When enable is set to T and value is set to ‘O’, CTL3 remains unchanged, but CTL2, CTL1 and CTLo all change state. Thus, the first switching element 321 of the second switching arrangement 320 becomes conductive and the bottom plate of the first capacitor 202 is connected to the second reference voltage 102. At the same time, the first switching element 331 and third switching element 333 of the third switching arrangement 330 become non-conductive, electrically separating the bottom plate of the first capacitor 202 from the third reference voltage 103 by making the third electrical path 335 and the fourth electrical path 336 non- conductive. Importantly, as the control signals for the first switching element 321 and the second switching element 322 of the second switching arrangement 320 receive opposite control signals both before and after switching, i.e. both switches transition state and they transition in opposite ways, i.e. one switches on while the other switches off. Therefore, one switch deposits charge onto the second electrical path 323 while the other removes charge from the second electrical path 323. The dummy switch 322 (second switching element) therefore compensates for the charge effect of the first switching element 321 so that the first switching element 321 does not significantly influence the voltage of the reference voltage as it transitions to connect the capacitor 202 to the second voltage reference 102. If the two switching elements 321, 322 are identical then their charge contribution will be identical (and opposite) such that they almost exactly cancel each other out. However, if desired, the dummy switch (second switching element) 322 can be designed with a larger capacitance so that it additionally compensates for the charge transfer with the capacitor 202. For example, when the capacitor 202 switches from the third (intermediate) reference voltage 103 to the second (low) reference voltage 102, it will transfer positive charge to the second reference voltage supply. If the second switching element 322 is large enough then its switching action can absorb some of that charge, thereby limiting the charge supplied to the second voltage reference supply.

[0129] When enable is set to T and value is set to T, the bottom plate of the first capacitor 202 is connected to the first reference voltage 101. A similar process occurs except that this time the switching state of the first switching element 321 of the second switching arrangement 320 remains unchanged, while the first switching element 311 of the first switching arrangement 310 changes state. The dummy switch (second switching element) 312 of the first switching arrangement 310 also changes state, in the opposite way to the first switching element 311. Therefore, as positive charge flows onto the bottom plate of the capacitor 102 to charge it to the first reference voltage 101, at least some of that charge absorbed due to the switching process of the first switching element 311 is supplied from the dummy element 312. If these two switching elements 311 , 312 are identical then the dummy switching element can fully compensate for the first switching element. If the dummy switching element 312 is large enough then it can also supply charge onto the first electrical path 313 that can flow onto the capacitor 202, reducing the charge draw from the first voltage reference source.

[0130] In both of the above processes, the capacitor 202 is disconnected from the third (intermediate) voltage reference 103. Although these switching processes disconnect the capacitor 202, the first and third switching elements 331, 333 still involve charge transfer as they change state. However, as each is paired with a dummy switch (second switching element 332 and fourth switching element 334) which changes switching state in an opposite manner, each switching transition is charge compensated so as to reduce the charge draw on the third voltage reference supply.

[0131] Figure 5 shows a variation 203’ of the set of switches 203 of Figure 3. The third switching arrangement 330’ of this variation 203’ does not have a fourth switching element corresponding to the fourth switching element 334 of the third switching arrangement 330 of Figure 3. As previously discussed, the first switching element 331 and the third switching element 333 provide a substantially equal and opposite charge contribution, and thus cancel each other out. Thus, a fourth switching element is not necessary to provide compensation for the third switching element 333. In this example, the single dummy switch 332 compensates for the movement of charge between the capacitor 202 and the third reference voltage 103, as well as any minor discrepancies between the charge contributions of the first and third switching elements 331 , 333 when they are switched.

[0132] In the same manner, the third switching element 333 of the third switching arrangement 330 is also not essential, and in some embodiments it too can be omitted.

[0133] Thus, it will be understood that the whole parallel connection to the third voltage reference 103 (i.e. the fourth electrical path 336) is not strictly necessary as a single connection (third electrical path 335) is sufficient. While the additional pathway is good for optimal charging / discharging to the intermediate voltage, VCM (one PMOS path and one NMOS path), it does add area to the circuit which can be saved if desired. It will be appreciated that this set of switches is present for each capacitor in the array and that in some use cases, many such capacitor arrays may be present (e.g. in the case of a time-interleaved ADC with several sub-ADCs, each with its own capacitor array). Therefore, the area saving can mount up quickly to be worthwhile. It will also be appreciated that the second switching element 332 may be omitted instead of the fourth switching element 334, and also that the third electrical path 335 may be omitted rather than the fourth electrical path 336.

[0134] Figure 6 shows a first reference voltage source 600 for providing the first reference voltage 101.

[0135] As previously mentioned, the first reference voltage 101 may be used by several SAR ADCs, such as the one shown in Figure 1. This may be the case, for example, in a time-interleaved SAR ADC comprising a plurality of sub-ADCs operating in parallel. It is convenient to provide a single common voltage reference for all the sub-ADCs if possible.

[0136] A highly accurate first reference voltage 101 in this example is provided by a band gap circuit 601, although there are numerous known techniques for generating voltages to a high degree of accuracy. This type of voltage source typically has a high output impedance and is therefore not suitable for supplying a load. Thus, a multi-stage buffer amplifier 602 is provided after the voltage source 601 to isolate the input to the multi-stage amplifier 602 from the output.

[0137] The multi-stage amplifier 602 has a pole associated with each amplification stage. The multi-stage amplifier 602 is designed such that its output pole, i.e. the pole of the last amplification stage, is dominant. This is contrary to the normal design principles for an ADC reference driver. In normal practice, there are two options for ADC reference driver design. The first is to have a fast response over a wide bandwidth and the other is to use a decoupling capacitor to handle fast transients. In the first case, stability is achieved by ensuring that the input stage has a dominant pole, but ensuring minimal output capacitance. In the second case, with the large decoupling capacitor the normal way to ensure amplifier stability is also to make the input pole dominant. In both cases, a larger decoupling capacitor pushes the amplifier towards less stability because the output pole slows down the output stage. Multi-stage amplifiers with dominant output poles generally respond slower to load and thus are more susceptible to variation of the output voltage. However, in certain applications this may be acceptable and it may be acceptable to have a multi-stage amplifier with a dominant output pole in a capacitive DAC where the charge draw is limited or spread out in time or is otherwise mitigated, e.g. by charge compensation using one or more of the techniques discussed in relation to Figures 1 to 5.

[0138] In this example, the output pole of the multi-stage amplifier 602 is made to be the dominant pole by providing a large reservoir capacitor 603 at the output of the multi-stage amplifier 602. This reservoir capacitor 603 is able to store a large reservoir of charge, which is also beneficial for maintaining a stable reference voltage 101. Thus, the reservoir capacitor 603 has a dual purpose. One purpose is to make the amplifier output pole dominant. The other purpose is to provide resilience against load from the capacitive DACs. As the reservoir capacitor 603 mitigates the load on the amplifier 602, it becomes viable to have an amplifier with a dominant output pole which can more slowly recharge the reservoir capacitor over time. An amplifier 602 with a dominant output pole may be made to be more power efficient than one with a non-dominant output pole for the reasons mentioned above.

[0139] As illustrated in Fig. 6, in some embodiments, each SAR ADC sub-stage, (which may for example have the form of the SAR ADC 100 shown in Figure 1) has a sampler 604 and a local reference capacitor 605 to provide a local first reference voltage source 101 to the respective SAR ADC sub-stage (and more specifically to its capacitive DAC). Once the local reference capacitor 605 has been charged to the reference voltage from the global buffer, the sampling switch 604 is opened so as to prevent cross-talk with other sub-ADCs. As the ADC sub-stage do not connect to the reservoir capacitor 603 at the same time, the load on multi-stage amplifier 602 is spread out in time, allowing it to be slower to replenish the charge stored on the reservoir capacitor 603 and thus permitting the lower power arrangement with a dominant output pole. Each sub-ADC only replenishes its local reference capacitor 605 once per ADC conversion. In this example, the charge of the local reference capacitor 605 is replenished between cycles of the respective SAR ADC sub-stage.

[0140] In this example, the second reference voltage 102 is provided by ground. Therefore, there is no need in this example to have a similar reference voltage source to the one shown in Figure 6 for the second reference voltage 102.

[0141] In other examples, there is a reference voltage source corresponding to the first reference voltage source 600 for providing the second reference voltage 102. A further reference voltage source corresponding to the first reference voltage source 600 may also be provided for the third voltage reference if required.

[0142] While Fig. 6 shows the design of a reference voltage source for a time- interleaved ADC with several sub-ADCs, the same principles can be applied for a single ADC. In such embodiments, there is no need for the local reference capacitor 605 and the sampling switch 604. Instead, the amplifier output and reservoir capacitor 603 can directly provide a reference voltage source to a capacitive DAC (which may in some embodiments be part of a SAR ADC).

[0143] Figure 7 shows a time interleaved ADC 700 comprising several ADC substages 701, 702, 703, 704. Each SAR ADC sub-stage 701, 702, 703, 704 is equivalent to the SAR ADC 100 shown in Figure 1.

[0144] A sampling arrangement 705, which in this example is a set of switches, samples an input voltage VIN 706 to each of the ADC sub-stages 701, 702, 703, 704 in turn. Thus, each ADC sub-stage 701, 702, 703, 704 is able to perform ADC conversion on a different sample of the input voltage VIN 706 in parallel to enable a higher overall sampling and conversion speed of the input voltage VIN 706. A first reference voltage VHI 707, a second reference voltage LO 708, and a third reference voltage CM 709 are provided to each of the ADC sub-stages. These reference voltages 707, 708, 709 are equivalent to the reference voltages 101, 102, 103 shown in Figure 1.

[0145] Figure 8 shows a voltage source 800 to provide a reference voltage for a capacitive DAC. The voltage source 800 may be similar to, e.g. substantially the same as, the voltage source 600 shown in Figure 6. For instance, the voltage source 800 includes a multi-stage amplifier 802 and a reservoir capacitor 803 which are the equivalent of their counterparts in Figure 6. The multi-stage amplifier provides a buffer between a voltage VREF 801, e.g. from a band-gap circuit or the like, so as to provide a buffered reference voltage REFBUF 804 at its output. This buffered reference voltage REFBUF 804 is stored on the reservoir capacitor 803, which is sized so as to ensure that the output pole of the multi-stage amplifier 802 is dominant and also to store a large reservoir of charge so as to be more robust to movement of charge to / from the capacitor 803.

[0146] However, unlike the voltage source shown in Figure 6, the voltage source 800 of Figure 8 is used by a single DAC circuit (or a single ADC circuit, such as the one shown in Figure 1), and not by several ADC sub-stages of a time interleaved ADC. Thus, the voltage source 800 of Figure 8 does not have a sampler, such as the sampler 604 shown in Figure 6, and the voltage source 800 of Figure 8 does not have a local reference capacitor, corresponding to the local reference capacitor 605 of Figure 6. Instead, the reservoir capacitor 803 is effectively used as a local reference capacitor for the single DAC circuit that is connected to it.

[0147] In certain applications, it may be acceptable for more than one DAC circuit (or more than one ADC sub-stage) to be connected directly to the reservoir capacitor 803 of the voltage source 800 of Figure 8. However, as previously discussed, it may be preferable to introduce the samplers 604 and local reference capacitors 605 of the voltage source 600 of Figure 6 to avoid cross-talk between ADC sub-stages.

[0148] It will be appreciated by those skilled in the art that this disclosure has been illustrated by describing one or more specific examples thereof, but is not limited to these examples; many variations and modifications are possible, within the scope of the accompanying claims.

Claims

Claims1. A capacitive digital to analogue converter (DAC), comprising a capacitor array; wherein the capacitor array comprises a plurality of capacitors; wherein a first plate of at least one capacitor of the capacitor array is selectively connectable to a first reference voltage via a first electrical path; wherein the first electrical path comprises a first switching arrangement; wherein the first switching arrangement comprises a first switching element and a second switching element; wherein the first switching element is operable between a first switching state in which the first electrical path is conductive and a second switching state in which the first electrical path is non-conductive; wherein the second switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the second switching element holds a charge; wherein the second switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the first electrical path.

2. A capacitive DAC as claimed in claim 1 , wherein a switching path of the second switching element is arranged in parallel with the first electrical path.

3. A capacitive DAC as claimed in claim 1 or 2, wherein the first switching element is capacitive, wherein in one of the first switching state and the second switching state, the first switching element holds a charge, and wherein when the first switching element is operated to the other of the first switching state and the second switching state it injects its stored charge onto the first electrical path.

4. A capacitive DAC as claimed in claim 3, wherein the first switching element and the second switching element are controlled in opposition such that one injects charge while the other absorbs charge.

5. A capacitive DAC as claimed in claim 3 or 4 wherein the second switching element is arranged to absorb and / or inject the same amount of charge as the first switching element.

6. A capacitive DAC as claimed in claim 3 or 4 wherein the second switching element is arranged to absorb and / or inject more charge than the first switching element.

7. A capacitive DAC as claimed in any preceding claim, wherein the first switching element is a field effect transistor.

8. A capacitive DAC as claimed in any preceding claim, wherein the second switching element is a field effect transistor.

9. A capacitive DAC as claimed in any preceding claim, wherein the first switching element and the second switching element are the same type of switching element.

10. A capacitive DAC as claimed in any preceding claim, wherein the first switching element and the second switching element are both capacitive and have approximately equal capacitances.

11. A capacitive DAC as claimed in any preceding claim, wherein the first switching element and the second switching element are both capacitive and wherein the second switching element has a greater capacitance than the first switching element.

12. A capacitive DAC as claimed in any preceding claim, wherein the first reference voltage is a high reference voltage.

13. A capacitive DAC as claimed in any preceding claim, wherein the first plate of the at least one capacitor of the capacitor array is selectively connectable to a second reference voltage via a second electrical path; wherein the second electrical path comprises a second switching arrangement;wherein the second switching arrangement comprises a third switching element and a fourth switching element; wherein the third switching element is operable between a first switching state in which the second electrical path is conductive and a second switching state in which the second electrical path is non-conductive; wherein the fourth switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the fourth switching element holds a charge; wherein the fourth switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the second electrical path.

14. A capacitive DAC as claimed in claim 13, wherein the second reference voltage is a low reference voltage.

15. A capacitive DAC as claimed in claim 13 or 14, wherein the first switching element and the second switching element are p-type elements; and wherein the third switching element and the fourth switching element are n-type elements.

16. A capacitive DAC as claimed in any preceding claim, wherein the first plate of the at least one capacitor of the capacitor array is selectively connectable to a third reference voltage via a third electrical path; wherein the third electrical path comprises a third switching arrangement; wherein the third switching arrangement comprises a fifth switching element and a sixth switching element; wherein the fifth switching element is operable between a first switching state in which the third electrical path is conductive and a second switching state in which the third electrical path is non-conductive; wherein the sixth switching element is capacitive and is operable between a first switching state and a second switching state; wherein in the first switching state the sixth switching element holds a charge; andwherein the sixth switching element is arranged such that when it is operated from the first switching state to the second switching state it injects its stored charge onto the third electrical path.

17. A capacitive DAC as claimed in claim 16, wherein the third reference voltage is an intermediate voltage.

18. A capacitive DAC as claimed in claim 17 and claim 13, wherein the DAC is arranged to charge the at least one capacitor to the intermediate voltage and then subsequently connect the at least one capacitor to either the first reference voltage or the second reference voltage according to an input signal.

19. A capacitive DAC as claimed in any preceding claim, wherein the at least one capacitor comprises more than one capacitor.

20. A capacitive DAC as claimed in claim 19, wherein different capacitors of the more than one capacitor are connectable to different first reference voltages.

21. A capacitive DAC as claimed in claim 19 or 20, wherein each capacitor of the more than one capacitor has a first plate selectively connectable to the first reference voltage via a respective first electrical path and a respective first switching arrangement.

22. A capacitive DAC as claimed in claim 21 , wherein the more than one capacitor includes at least the two capacitors in the array that are arranged to hold the largest charge.

23. A capacitive DAC as claimed in any preceding claim, wherein the first reference voltage is provided by a first reference voltage supply; wherein the first reference voltage supply comprises a multi-stage amplifier with a dominant output pole.

24. A capacitive DAC as claimed in claim 23, wherein the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the reference voltage.

25. A differential capacitive DAC comprising a positive DAC and a negative DAC, wherein each of the positive DAC and negative DAC are as claimed in any preceding claim, and wherein both the positive DAC and the negative DAC are driven by the same input.

26. A successive approximation register analogue to digital converter comprising a capacitive DAC as claimed in any preceding claim.

27. A time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC as claimed in claim 26; and wherein at least one reference voltage is shared by a plurality of sub-ADCs.

28. A time interleaved ADC as claimed in claim 27, wherein each of the plurality of sub-ADCs has a local reference capacitor to provide a local reference voltage; and wherein each sub-ADC recharges its local reference capacitor from a global reference voltage supply once per conversion.

29. A time interleaved ADC as claimed in claim 28, wherein the global reference voltage comprises a multi-stage amplifier with a dominant output pole.

30. A time interleaved ADC as claimed in claim 29, wherein the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the global reference voltage.

31. A capacitive DAC having at least one reference voltage supply for charging and / or discharging a switched capacitor array; wherein the reference voltage supply comprises a multi-stage amplifier with a dominant output pole.

32. A capacitive DAC as claimed in claim 31 , wherein the multi-stage amplifier is a voltage buffer amplifier.

33. A capacitive DAC as claimed in claim 31 or 32, wherein the multi-stage amplifier has a reservoir capacitor connected to its output to buffer the reference voltage.

34. A capacitive DAC as claimed in claim 33, wherein the reservoir capacitor is sized to ensure that the amplifier output pole is dominant.

35. A successive approximation register analogue to digital converter comprising a capacitive DAC as claimed in any of claims 31 to 34.

36. A time interleaved ADC comprising a plurality of sub-ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC as claimed in claim 35; wherein the reference voltage supply is a global reference voltage supply shared between all the sub-ADCs; wherein each sub-ADC comprises a local reservoir capacitor; and wherein each sub-ADC is arranged to recharge its local reservoir capacitor from the global reference voltage supply once per conversion.

37. A method of operating a capacitive digital to analogue converter (DAC), comprising a capacitor array; wherein the capacitor array comprises a plurality of capacitors; the method comprising: selectively connecting a first plate of at least one capacitor of the capacitor array to a first reference voltage via a first electrical path by operating a first switching element of a switching arrangement from a second switching state in which the first electrical path is non-conductive to a first switching state in which the first electrical path is conductive; and operating a second switching element of the switching arrangement from a first switching state in which the second switching element holds a charge to a second switching state such that the second switching element injects its stored charge onto the first electrical path.

38. A method of operating a differential capacitive DAC, comprising a positive DAC and a negative DAC, wherein each of the positive DAC and negative DAC are operated according to the method as claimed in claim 37, and wherein both the positive DAC and the negative DAC are driven by the same input.

39. A method of operating a successive approximation register analogue to digital converter comprising a capacitive DAC, wherein the capacitive DAC is operated according to the method as claimed in claim 37 or claim 38.

40. A method of operating a time interleaved ADC comprising a plurality of subADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC operated according to the method as claimed in claim 39; and wherein at least one reference voltage is shared by a plurality of sub-ADCs.

41. A method of operating a time interleaved ADC comprising a plurality of sub- ADCs which process samples in sequence; wherein each sub-ADC is a successive approximation register ADC comprising a capacitive DAC having a switched capacitor array; the time interleaved ADC comprising at least one global reference voltage supply for charging and / or discharging each switched capacitor array; wherein the global reference voltage supply comprises a multi-stage amplifier with a dominant output pole; wherein each sub-ADC comprises a local reservoir capacitor; the method comprising: recharging each local reservoir capacitor from the global reference voltage once per conversion.

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