Methods and devices for determining physical representations of logical operators of a quantum error correcting code

Abstract

Methods for determining physical representations of logical operators of QEC codes involve obtaining a description of a logical operator associated with a predetermined QEC code. The QEC code is configured for encoding logical qubits on physical qubits. The logical operator corresponds to an operation to be performed on at least one of the logical qubits. A first physical representation of the logical operator acts on at least one of the physical qubits. A set of diagonal Clifford stabilizer generators is obtained. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator. A second physical representation of the logical operator is determined, using a closest vector problem, CVP, algorithm. The CVP algorithm is performed on the first physical representation. The second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

Description

METHODS AND DEVICES FOR DETERMINING PHYSICAL REPRESENTATIONS OF LOGICAL OPERATORS OF A QUANTUM ERROR CORRECTING CODEField

[0001] This disclosure generally relates to methods and devices for determining physical representations of logical operators of a quantum error correcting (QEC) code. The disclosure further relates to methods and devices for determining a physical implementation of a quantum circuit.Background

[0002] Quantum computing allows processing of information based on quantum effects such as superpositions, (de-)coherence or entanglement of quantum states. Quantum circuits are designed for carrying out the necessary steps of a quantum algorithm. Logical quantum circuits can be implemented as physical quantum circuits (or physical circuits). Logical quantum circuits comprise a plurality of logical gates (or operators). An important set of gates, the so-called Clifford gates are used in the implementation of many quantum algorithms, and with the addition of the “T” unitary gate, form a universal gate set.

[0003] In quantum information, errors can originate from decoherence effects and other quantum noise sources. To reduce the effects of noise, QEC codes have been developed which help in detecting and correcting errors in the quantum information.

[0004] For a given QEC code, a logical (encoded) Clifford gate is implemented by a quantum circuit comprising physical (unencoded) Clifford gates. For a given logical Clifford gate, there are several quantum circuits implementing the logical Clifford gate. It is thus of great importance that for a given QEC code, one identifies a quantum circuit with low error-spreading properties. Yet, there are no known general methods for efficiently searching the space of physical implementations for a given logical operator.

[0005] Some studies restrict to codes on very low numbers of physical qubits, e.g., the 7-qubit Steane code. Other studies relate to families of so-called “topological codes”. Codes from this family have strong geometrical properties which facilitates searching for logical operator implementations. However, these geometric properties also greatly restrict the number of possible logical qubits. For each encoded qubit thatthe code protects, there is a very high overhead of physical qubit resources required, which makes practical applications more involved.

[0006] Therefore, it is desirable to find improved ways to efficiently search the space of physical implementations for a given logical operator in a general setting, i.e., for any QEC code.Summary

[0007] The present disclosure has several aspects, including methods and devices for determining physical representations of logical operators of a QEC code, and including methods and devices for determining a physical implementation of a quantum circuit.

[0008] A first aspect of the disclosure provides a method for determining physical representations of logical operators of a QEC code. A description of a logical operator associated with a predetermined QEC code is obtained. The QEC code is configured for encoding logical qubits on physical qubits. The logical operator corresponds to an operation to be performed on at least one of the logical qubits. A first physical representation of the logical operator is obtained. The physical representation of the logical operator implements the logical operator on at least one of the physical qubits. A set of diagonal Clifford stabilizer generators is obtained. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator. A second physical representation of the logical operator is determined, using a closest vector problem (CVP) algorithm. The CVP algorithm is performed on the first physical representation. The second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

[0009] The invention can be applied when searching for improved physical representations of logical operators. In particular, the second physical representation of the logical operator will generally have better error-spreading properties than the first physical representation of the logical operator. As will be explained in this specification, lattice (basis) reduction and CVP algorithms can be used when determining improved physical representations of logical operators, using a specific description of the logical operators.

[0010] A QEC code is defined by specifying a codespace of the QEC code. Herein, a codespace is a vector subspace of a Hilbert space which is spanned by so-calledcodewords of the QEC code. A codeword is a state which encodes some data. A codeword corresponds to a logical state of the QEC code.

[0011] In general, a quantum mechanical operation on one or more qubits is described by a unitary operator. Important unitary operators are determined by the Pauli group. The single-qubit Pauli groupis the group of Pauli operators that can each act on the qubit. There are 16 Pauli operators. Up to a complex phase, there are 3 distinct non-trivial operators, the Pauli X, Y, and Z operators. The single-qubit Pauli group is formed by all products of the Pauli X, Y, and Z operators. The n-qubit Pauli group ?nis formed by all length n tensor products of elements of the single-qubit Pauli group J , where n is an integer greater than 1 . The Pauli group is a non-Abelian group, i.e., group elements in general do not commute. The elements of the n-qubit Pauli group are denoted as Pauli operators.

[0012] A QEC code is in general a mapping of k qubits onto n qubits, where n > k. The k qubits are elements of a Hilbert space of dimension 2k. The n qubits are elements of a Hilbert space of dimension 2n. Herein, the k qubits are the “logical qubits” or “encoded qubits” that are to be protected from error, e.g., a threshold amount of error. The n qubits are the “physical qubits” implementing the logical qubits. The additional n - k qubits allow the k logical qubits to be stored in a redundant fashion so that the encoded information is less susceptible to noise or other disturbances.

[0013] A QEC code with block size n, encoded qubits k, and distance d is denoted as an “ [[n, k, d]] QEC code,” where the distance d is the minimum support of a logical operator in the code. The distance d sets a bound on the number of errors the QEC code can detect and correct. For example, if there are fewer than errors, aperfect decoder can identify and correct these errors without changing the intended quantum state. On the other hand, if there are more than errors, a perfectdecoder may be unable to correct all the errors.

[0014] The QEC code can be provided by the user. In particular, the QEC code can be a stabilizer code C. A stabilizer code is a QEC code defined by a set of mutually commuting Hermitian Pauli operators C that does not contain the negative of the identity operator, -I.

[0015] The commuting Hermitian Pauli operators that define the associated stabilizer code C are denoted as “Pauli stabilizers”, S. This collection forms a subgroup of thefull Pauli group. In particular, the composition of two Pauli stabilizers produces another Pauli stabilizer. Each Pauli stabilizer is an n qubit gate. In the case of a Calderbank-Shor-Steane (CSS) stabilizer code (CSS code), the group S of Pauli stabilizers is determined by binary matrices Cxand Cz:S = {XUZV: u G RowSpan(Cx), v G RowSpan(Cz)}.

[0016] For more general codes, the group S of Pauli stabilizers is determined by a single matrix H comprising n - k rows, each of length 2n:S = {XUZV: (u|v) G RowSpan(H)}.

[0017] More specifically, the codewords c G C of the stabilizer code are the n qubit states (i.e. vectors in the Hilbert spaceof dimension 2n) that are unchanged when any Pauli stabilizer is applied. The codewords are therefore the fixed points of the Pauli stabilizers.

[0018] The Pauli stabilizers can be used to detect unwanted errors. For a given codeword, a detectable error will transform the codeword to a different vector in the Hilbert spaceof dimension 2nthat is no longer a fixed point of the Pauli stabilizers. By determining which Pauli stabilizers still fix the vector, the error can be identified and corrected.

[0019] In the following, the term “logical Lie group” denotes the set of unitary operators that preserve the codespace of the QEC code, i.e., unitary operators onwhich map C -> C. In other words, elements of the logical Lie group £ can change the state of a qubit within the codespace without taking it out of the codespace:£ : = {g E TL(n) : gC = C}.

[0020] In quantum error correction, logical operators in the logical Lie group can be used to manipulate logical qubits without disturbing the encoded information. In general, operators in the logical Lie group £ will map codewords around the subspace C non-trivially.

[0021] In the following, the term “stabilizer Lie group” denotes the set of unitary operators that preserve each codeword in the codespace of the QEC code. In other words, each element of the stabilizing Lie group leaves every codeword in the codespace invariant. This means that if \ip) is a codeword in the codespace, then for every operator U in the stabilizer Lie group S, the following holds:U ) = I -

[0022] The stabilizer Lie group is a subgroup of the logical Lie group £■.S Q L.

[0023] The Pauli stabilizers are example elements of the stabilizer Lie group. The Pauli stabilizers S of a stabilizer code are given by the intersection of the stabilizer Lie group and the n-qubits Pauli group ?n.-S = S P'n.

[0024] Operators in the the stabilizer Lie group can be used to detect errors.

[0025] In the following, the term “Clifford group” denotes the group of so-called Clifford operators which are unitary operators that preserve the Pauli group under conjugation. This means that the n-qubit Clifford groupis the set of all operators that map Pauli operators in the n-qubit Pauli group SPnto other Pauli operators in the n-qubit Pauli group SPnunder conjugation. The n-qubit Clifford groupis said to “normalize” the n-qubit Pauli group SPn. The fact that the Clifford operators map Pauli operators to other Pauli operators under conjugation makes the Clifford operators easier to to describe. Up to a phase, a Clifford operator g can be described by the images of the 2n Pauli operators Xtand Zy- under conjugation by g. / Clifford operator can therefore be described by a 2n x (2n + 1) matrix (with one column tracking signs) which is much more efficient than a general unitary operator which can only be fully described by a 2nx 2nmatrix.

[0026] For example, conjugating the Pauli X operator by the Hadamard gate H gives the Pauli Z operator:HX = Z.

[0027] Similar relation hold for the other Pauli Y,Z operators. The Hadamard gate H is an example of a Clifford operator.

[0028] The Clifford group is generated by the Hadamard gate H , the phase gate S, and the CNOT gate. Herein, a list of gates or operators is said to “generate” a larger collection of gates or operators, if every element of the larger collection can be composed as products of elements from the list of gates. These compositions may be arbitrarily long and may contain repetitions.

[0029] Every element of the Clifford group is uniquely specified (up to a phase) by specifying where the Clifford operator maps a generating set of the Pauli group under conjugation. Advantageously, the Clifford group can be efficiently simulated classically and allows for fault-tolerant gate constructions.

[0030] The Hadamard gate H , the phase gate S, and the CNOT gate generate other Clifford group elements such as the Controlled-Z gate (denoted as CZ gate) and the SWAP gates.

[0031] In the following, the term “error spread” denotes a metric which can be used in characterizing physical representatives of a logical operator. Single qubit Pauli errors (denoted as “Pauli noise”) can propagate through the circuit implementing the logical operator. The error spread describes the worst-case scenario for this error propagation. The error spread describes the maximal error weight of an error that may be caused by the propagation. Herein, the term “error weight” denotes the number of non-identity components of an n-qubit Pauli operator. Each non-identity component indicates an unwanted error on that particular qubit.

[0032] Another commonly used metric for characterising the physical representative of a logical operator is the transversality.

[0033] Yet another commonly used metric for characterising the physical representative of a logical operator is the “average error spread” which denotes the average weight of an error resulting from Pauli noise propagating through the circuit implementing the logical operator. The average is taken over all possible Pauli inputs.

[0034] In the following, the term “stabilizing Clifford group G” denotes the intersection of the stabilizer Lie group and the n-qubit Clifford groupG = A C-£n.

[0035] Not all elements of the Clifford group commute with each other, hence the order of these gates in a physical circuit matter. Once a logical Clifford operator of a particular code has been identified, a corresponding physical circuit that realizes the action of the logical Clifford operator on the encoded qubits must be synthesized. In practice, there are several physical circuits (i.e., physical implementations) of a logical Clifford operator. In some QEC codes, the physical representations of a logical Clifford operator may include a representation comprised exclusively of transversal gates. Herein, transversal gates are desirable because they are automatically fault- tolerant. If an error occurs on one physical qubit, there is no action that can propagate it onto a different physical qubit in the same QEC code block because no two qubits in the same block ever interact. In such cases, it may be desirable to synthesize that specific implementation. Yet, in general, most physical implementations of a logical Clifford operator are not transversal, and therefore have the potential to spread errors in a non-fault tolerant manner. It is desirable to synthesize a physical implementation with low error spread.

[0036] For a given logical Clifford operator, the space of physical implementations of the logical Clifford operator can be searched, minimizing parameters that contribute to fault-tolerance. Potential parameters are the gate count, the circuit depth, and the error spread. This is typically a difficult problem. For example, circuits A and B are given, representing two logical operators X and Y, respectively. Specifically, X is a non-trivial logical operator and Y is a stabilising operator for the code, i.e., Y fixes all encoded states and consequently, the composite operator X Y implements the same logical operator as X. A circuit forX Y is obtained by the appended circuits A+B. However, because the gates present in A+B do not commute in general, careful analysis is needed to decide if any simplifications, or gate cancellations can be made in the circuit A+B.

[0037] Clifford operators (Clifford gates) are desirable for implementing a logical operator of a QEC code. However, not all elements of the Clifford group commutewith each other. This places a limitation on the gate simplification by reordering. Accordingly, it is advantageous to refer to diagonal operators in the Clifford group.

[0038] In the following, the term “diagonal Clifford group” refers to diagonal operators in the Clifford group. A unitary operator g G TZ(n) is called diagonal if the computational basis,{lOJ Zo1is a basis of eigenvectors for g. Equivalently, the matrix representation for g is diagonal with respect to the computational basis.

[0039] The diagonal Clifford group is a subgroup of the Clifford group in which all elements commute. This is because elements of the diagonal Clifford group are diagonal matrices, and diagonal matrices always commute. The diagonal Clifford group is generated by S and CZ gates. More explicitly, the group Dnof diagonal n- qubit Clifford operators is generated by:where Sj acts on the j-th qubit as shown and as an identity operator on all other qubits, and where CZj kacts on theidentity operator on all other qubits. Under the diagonal Clifford group framework, a circuit with a reduced number of CZ gates have low error spread.

[0040] In the following, the term “logical diagonal Clifford operators” relates to the intersection between the logical Lie group and the diagonal Clifford group. This intersection is itself also a group.

[0041] In the following, the term “stabilizing diagonal Clifford operators” relates to the intersection of the stabilizer Lie group and the diagonal Clifford group. This intersection is itself also a group.

[0042] In the following, the term “diagonal Clifford stabilizer generators” relates to a subset of the stabilizing diagonal Clifford operators that generates the full group of stabilizing diagonal Clifford operators. This list of generators is independent, i.e. , it is not possible to choose a smaller sub-collection of diagonal Clifford stabilizer generators and still generate the full group of stabilizing diagonal Clifford operators. In general, the choice of diagonal Clifford stabilizer generators is not unique. For a fixed QEC code, any chosen list of diagonal Clifford stabilizer generators will be of the same fixed size.

[0043] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a quantum computing system is configured to implement a QEC protocol. The implementation of the QEC code on the quantum computing system is done using the predetermined QEC code and the second physical representation of the logical operator. The quantum computing system can be used to implement a quantum algorithm, using the QEC code.

[0044] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the logical operator is a logical diagonal Clifford operator. Herein, logical diagonal Clifford operators are in the intersection of the logical Lie group and the diagonal Clifford group, as defined above. The commutative property of the diagonal Clifford group allows a reformulation of the problem of searching the space of quantum circuits that implement the logical diagonal Clifford operator in terms of a lattice problem which can be solved by means of a lattice theory algorithm, for example a closest vector problem (CVP) algorithm.

[0045] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the CVP algorithm is used to determine the physical representation of the logical operator such that the number of controlled-Z gates (CZ- gates) of the second physical representation of the logical operator is smaller than or equal to the number of CZ-gates of the first physical representation of the logical operator. Accordingly, a physical representation of the logical operator (in particular, a logical diagonal Clifford operator) can be found such that the circuit of the physical representation has reduced error spreading properties.

[0046] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the CVP algorithm is configured to minimize the number of controlled-Z gates in order to determine the second physical representation of the logical operator. The CVP algorithm helps in finding a binary representation of the physical representation of the logical operator such that the number of CZ-gates of the circuit corresponding to the physical representation of the logical operator is minimized. This physical representation of the logical operator is provided as the second physical representation of the logical operator.

[0047] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the CVP algorithm is configured to minimize a Hamming weight of a binary string representation of the first physical representation of the logical operator, using the diagonal Clifford stabilizer generators, in order to obtain the second physical representation of the logical operator. A measure of the spread of a physical representation of a logical diagonal Clifford operator is given by the Hamming weight of its binary image. Minimizing the number of CZ gates in the circuit is equivalent to minimizing the Hamming weight of the binary representation.

[0048] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the CVP algorithm is a binary lattice algorithm. That is, the underlying field is the binary field and not the field of real numbers.

[0049] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the binary lattice algorithm is a binary adaptation of a Lenstra-Lenstra-Lovasz (LLL) algorithm. Other binary lattice algorithms are also possible. For example, according to an embodiment, the binary lattice algorithm is a binary adaptation of a Blockwise Korkine-Zolotarev (BKZ)-algorithm or an (extreme) pruning enumeration algorithm.

[0050] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a binary string representation of the first physical representation of the logical operator is determined. Further, a binary string representation of each of the diagonal Clifford stabilizer generators is determined. The CVP algorithm is applied, being an algorithm for solving a closest vector problem (CVP), using the binary string representation of the first physical representation of the logical operator and the binary string representations of the diagonal Clifford stabilizer generators. The second physical representation of the logical operator is determined based on a solution of the CVP.

[0051] In an embodiment of the method for determining physical representations of logical operators of a QEC code, determining the binary string representation of the first physical representation of the logical operator and determining the binary string representation of the diagonal Clifford stabilizer generators comprises a step of determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators. A flattening operation is applied to the symmetric matrix representations of the first physical representation of the logical operator and to the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators. The symmetric matrix representation essentially corresponds to the upper right block of a matrix known as a "Clifford tableau".

[0052] In an embodiment of the method for determining physical representations of logical operators of a QEC code, determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators comprises a step of mapping phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to diagonal matrix elements of the symmetric matrix representations. Controlled-Z gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators are mapped to off-diagonal matrix elements of the symmetric matrix representations. In this way, each physical representation of the logical operator can be represented as a symmetric matrix.

[0053] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the flattening operation is applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

[0054] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a pre-processing step of making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators is included. The CVP algorithm is applied using the transformed binary string representations of the diagonal Clifford stabilizer generators. The preprocessing steps helps in finding solutions to the CVP.

[0055] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the pre-processing step is implemented using alattice basis reduction algorithm, such as LLL. The lattice basis reduction algorithm can be used to generate a new basis that has desirable properties, for example, shorter vectors which are closer to orthogonal vectors. After the pre-processing, a CVP algorithm can be applied, i.e. , the CVP is solved. The CVP algorithm can be a pruned enumeration or Size Reduce algorithm (a binary adaptation of Babai's nearest plane algorithm).

[0056] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the QEC code is a stabilizer code defined by a set of Pauli stabilizers, as defined above. Stabilizer codes are very important and widespread examples of QEC codes.

[0057] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the second physical representation of the logical operator is stored in a database. The information regarding the second physical representation of the logical operator can then be retrieved during circuit design.

[0058] In an embodiment of the method for determining physical representations of logical operators of a QEC code, for each logical operator of a plurality of logical operators a respective second physical representation of the logical operator is determined. The second physical representations for each logical operator can be stored in the database.

[0059] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a candidate QEC code is received. For each logical operator of the candidate QEC code, a respective second physical representation is determined as described above. The candidate QEC code is assessed based on at least one error spread property of the second physical representations of the logical operators. This helps during circuit design because QEC codes can be classified according to the error spread properties. For example, the error spread property can be the number of CZ-gates.

[0060] In an embodiment of the method for determining physical representations of logical operators of a QEC code, the candidate QEC code is discarded if the at least one error spread property of the second physical representations is outside a predefined range. For example, the candidate QEC code is discarded if the number of CZ-gates of the second physical representations is above a predefined value.

[0061] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a physical quantum system is operated, e.g., aquantum computer. The physical quantum system implements a plurality of physical operators operating on a plurality of physical qubits. At least one physical operator of the plurality of physical operators is implemented according to the second physical representation of the logical operator.

[0062] In an embodiment of the method for determining physical representations of logical operators of a QEC code, a quantum operation is performed with the physical quantum system.

[0063] A second aspect of the disclosure provides a computer-implemented method. The method comprises receiving a candidate QEC code. The method further comprises, for each logical operator of the candidate QEC code, determining a respective physical representation based on a solution to a closest vector problem. The candidate QEC code is assessed based on at least one error spread property of the second physical representations of the logical operators. This helps during circuit design because QEC codes can be classified according to the error spread properties. For example, the error spread property can be the number of CZ-gates.

[0064] In an embodiment, the candidate QEC code is discarded if the at least one error spread property of the second physical representations is outside a predefined range. For example, the candidate QEC code is discarded if the number of CZ-gates of the second physical representations is above a predefined value.

[0065] A third aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to the first aspect or the second aspect.

[0066] A fourth aspect of the disclosure provides a non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to the first aspect.

[0067] A fifth aspect of the disclosure provides a device for determining physical representations of logical operators of a QEC code, comprising an interface configured to obtain a description of a logical operator associated with a predetermined QEC code. The QEC code is configured for encoding logical qubits on physical qubits. The logical operator corresponds to an operation to be performed on at least one of the logical qubits. The interface is further configured to obtain a first physical representation of the logical operator, wherein the physical representation of the logical operator acts on at least one of the physical qubits (i.e., the physical representation of the logical operator implements the logical operator on the at leastone of the physical qubits). Further, the interface obtains a set of diagonal Clifford stabilizer generators, wherein each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator. A processor is configured to determine a second physical representation of the logical operator, using a closest vector problem (CVP) algorithm. The CVP algorithm is performed on the first physical representation. The second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

[0068] A sixth aspect of the disclosure provides a computer-implemented method for determining a physical implementation of a quantum circuit. For a plurality of logical operators associated with a QEC code, a respective physical representation of the logical operator is determined, using a closest vector problem (CVP) algorithm, wherein the CVP algorithm is used to minimize a number of controlled-Z gates of the physical representations of the logical operator. The physical implementation of the quantum circuit is determined. The logical operators appearing in the quantum circuit are implemented as physical operators based on the determined physical representations of the logical operators.

[0069] In an embodiment of the method for determining a physical implementation of a quantum circuit, the physical representations of the logical operators are stored in a database. The logical operators appearing in the quantum circuit are implemented by retrieving the physical representations of the logical operators from the database.

[0070] In an embodiment of the method for determining a physical implementation of a quantum circuit, a quantum computing system is configured to implement a QEC protocol, using the determined physical implementation of the quantum circuit. The QEC code can be provided by a user.

[0071] In an embodiment of the method for determining a physical implementation of a quantum circuit, the logical operators are logical diagonal Clifford operators. Logical diagonal Clifford operators are diagonal unitary operators which are elements of the Clifford group and stabilize the codespace of the QEC code.

[0072] In an embodiment of the method for determining a physical implementation of a quantum circuit, for each logical operator, the CVP algorithm is configured to minimize a Hamming weight of a binary string representation of a first physical representation of said logical operator, using a set of diagonal Clifford stabilizer generators, in order to obtain a second physical representation of the logical operator.

[0073] In an embodiment of the method for determining a physical implementation of a quantum circuit, the CVP algorithm is a binary lattice algorithm.

[0074] In an embodiment of the method for determining a physical implementation of a quantum circuit, the binary lattice algorithm is a binary adaptation of an LLL algorithm. Other algorithms are possible, as mentioned above.

[0075] In an embodiment of the method for determining a physical implementation of a quantum circuit, for each logical operator, a binary string representation of a first physical representation of said logical operator is determined. A binary string representation of a plurality of diagonal Clifford stabilizer generators is determined. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator. The CVP algorithm is applied. The CVP algorithm is an algorithm for solving the CVP on a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators. The second physical representation of the logical operator is determined based on a solution of the CVP obtained using the CVP algorithm.

[0076] In an embodiment of the method for determining a physical implementation of a quantum circuit, determining the binary string representation of the first physical representation of the logical operator and determining the binary string representation of the diagonal Clifford stabilizer generators comprises a step of determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators. A flattening operation is applied to the symmetric matrix representations of the first physical representation of the logical operator and to the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators.

[0077] In an embodiment of the method for determining a physical implementation of a quantum circuit, determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators comprises mapping phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to diagonal matrix elements of the symmetric matrix representations. Controlled-Z gates (CZ gates) of the first physical representation of the logical operator and the diagonal Clifford stabilizergenerators are mapped to off-diagonal matrix elements of the symmetric matrix representations.

[0078] In an embodiment of the method for determining a physical implementation of a quantum circuit, the flattening operation is applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

[0079] In an embodiment of the method for determining a physical implementation of a quantum circuit, a pre-processing step of making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators is included, e.g., using lattice reduction algorithms. The lattice reduction algorithm is applied to the transformed binary string representations of the diagonal Clifford stabilizer generators.

[0080] In an embodiment of the method for determining a physical implementation of a quantum circuit, the QEC code is a stabilizer code defined by a set of Pauli stabilizers, as defined above.

[0081] In an embodiment of the method for determining a physical implementation of a quantum circuit, a physical quantum system is operated, wherein the physical quantum system implements a plurality of physical operators operating on a plurality of physical qubits. At least one physical operator of the plurality of physical operators is implemented according to the determined physical representation of the logical operator.

[0082] A seventh aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to the fifth aspect.

[0083] An eighth aspect of the disclosure provides a non-transitory, computer- readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to the fifth aspect.

[0084] A ninth aspect of the disclosure provides a device for determining a physical implementation of a quantum circuit. The device comprises a processor configured to determine, for a plurality of logical operators associated with a QEC code, a respective physical representation of the logical operator, using a lattice theory algorithm (e.g., CVP algorithm), wherein the lattice theory algorithm is used to minimize a number of controlled-Z gates of the physical representations of the logical operator. The processor is further configured to determine the physicalimplementation of the quantum circuit, wherein the logical operators appearing in the quantum circuit are implemented as physical operators based on the determined physical representations of the logical operators.

[0085] Another aspect of the disclosure provides a device for performing any of methods described herein.

[0086] The disclosure relates to all combinations of the above features, even if these are recited in different aspects or different claims.Brief description of the drawings

[0087] In the following, further aspects and exemplary embodiments will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the described exemplary embodiments and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.

[0088] Fig. 1 schematically shows a block diagram illustrating a system according to an embodiment of the disclosure;

[0089] Fig. 2 shows a flow diagram illustrating a method for determining physical representations of logical operators of a QEC code according to an embodiment of the disclosure;

[0090] Fig. 3 shows a flow diagram illustrating a method for assessing QEC codes according to an embodiment of the disclosure; and

[0091] Fig. 4 shows a flow diagram illustrating a method for determining a physical implementation of a quantum circuit according to an embodiment of the disclosure.Detailed description

[0092] Fig. 1 schematically shows a block diagram illustrating a system 100 which can be used for determining physical representations of logical operators of a QEC code, for assessing QEC codes, and for determining physical implementations of quantum circuits.

[0093] The system 100 comprises a representation determining device 200. The representation determining device 200 comprises a processor 203 (i.e. , a computing device). The processor 203 can be a logic processing unit and can comprise a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller (pC), anintegrated circuit (IC), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a program logic unit (PLU), a network processor (NP) or a combination thereof.

[0094] The representation determining device 200 further comprises a memory 204 which can comprise at least one of a magnetic hard disk, an optical disc (e.g., compact disc, digital video disc, Blu-ray disc), a solid state disc (SSD), a magnetooptical memory or a hard disc drive (HDD). For example, the memory 204 can comprise a volatile semiconductor or solid state memory, e.g., a random access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM). The memory 204 can comprise a non-volatile semiconductor or solid state memory, e.g., a read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), or the like.

[0095] The memory 204 stores processor-executable instructions and / or processor- readable data associated with the operation of the representation determining device 200. The processor-executable instructions and / or processor-readable data can comprise an operating system, peripheral drivers, server instructions, application instructions, calibration instructions, or communication channel instructions.

[0096] The representation determining device 200 further comprises a user interface 205, having at least one of a display, a keyboard, a touch screen, a mouse, buttons, a microphone, loudspeakers and the like. A user may provide or receive information regarding the operation of the system 100 via the user interface 205.

[0097] All of the components of the representation determining device 200 described above can be controlled and / or can communicate over at least one bus 201 . The processor 203 may be configured to control the other above-described components 202, 204, 205 of the representation determining device 200.

[0098] The processor 203 can receive a description of a QEC code. For example, a user can provide a description of a QEC code via the user interface 205. The QEC code is configured for encoding k logical qubits on n physical qubits.

[0099] In particular, the QEC code can be a stabilizer code which can be defined by a set of mutually commuting Hermitian Pauli operators S. The stabilizer code may be defined by providing a check matrix. Herein, the check matrix may have been brought into the standard form. The check matrix allows to deduce the definition of Pauli Z operators and Pauli X operators.

[0100] The processor 203 can further receive a description of a logical operator associated with the QEC code. The logical operator corresponds to an operation tobe performed on at least one of the k logical qubits. The logical operator can in particular be a logical diagonal Clifford operator which is to be implemented on the k logical qubits.

[0101] The processor 203 further receives (a description of) a first physical representation of the logical operator, e.g., from a user via the user interface 205.

[0102] The physical representation of the logical operator acts on at least one of the n physical qubits. The first physical representation of the logical operator can be given in the form of a circuit on n physical qubits which contains a plurality of S and CZ gates. The first physical representation of the logical operator implements the logical operator.

[0103] The processor 203 further receives a set of diagonal Clifford stabilizer generators, e.g., via the user via user interface 205. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator. The diagonal Clifford stabilizer generators are operators that transform one logical diagonal Clifford operator into another. The diagonal Clifford stabilizer generators describe the space of diagonal Clifford representatives that fix each codeword of the code, elementwise.

[0104] The set of diagonal Clifford stabilizer generators determines the search space, i.e., the space that determines the potential physical representations of the logical operator. In some embodiments, only a subset of A diagonal Clifford stabilizer generators is selected, where there is a total of B > A diagonal Clifford stabilizer generators. The space of possible circuits is of dimension 2A. Restricting the search space might be advantageous in order to reduce the computational costs. In other embodiments, the entire search space is used, i.e., all diagonal Clifford stabilizer generators. This ensures that the best possible physical representation of the logical operator is included in the search space.

[0105] As mentioned, both the first physical representation of the logical operator and the set of diagonal Clifford stabilizer generators may have been received from a user via the user interface 205.

[0106] In other embodiments, the processor 203 may synthesize the first physical representation of the logical operator.

[0107] The processor 203 can carry out a search in order to determine a second physical representation (e.g., a second diagonal Clifford representative) of the logical operator. The processor 203 conducts a search of the space of diagonal Cliffordrepresentatives, using the first physical representation (e.g., an initial diagonal Clifford representative) and the set of diagonal Clifford stabilizer generators. The second physical representation of the logical operator has low error-spreading properties.

[0108] Both the first physical representation of the logical operator and the second physical representation of the logical operator comprise a plurality of S gates and / or CZ gates. The processor 203 uses a lattice theory algorithm (e.g., CVP algorithm) to determine the second physical representation of the logical operator. The lattice theory algorithm minimizes the number of CZ gates. This implies that the error spreading properties of the identified second physical representation of the logical operator is less than that of the first physical representation of the logical operator.

[0109] The processor 203 may then store information for identifying the second physical representation of the logical operator in the memory 204.

[0110] The processor 203 may generate a respective second physical representation for each logical operator corresponding to the QEC code. For example, given a code with k logical qubits there are approximately k2logical diagonal Clifford operators. For each logical diagonal Clifford operator, a second physical representation is generated, based on a first physical representation of the logical diagonal Clifford operator and further based on the set of diagonal Clifford stabilizer generators. Based on the second physical representation, it is possible to compute with encoded data.

[0111] A description of the second physical representation of each logical operator can be stored, e.g., in memory 204 and / or in an external database, e.g., on an external server. This description may comprise a list of physical gates that can be applied.

[0112] In the following, a more detailed description of how to use the lattice theory algorithm is given.

[0113] A lattice L with a basis {v of linearly independent vectors vlt...,vkG F" is defined as:

[0114] For a binary lattice, the vectors are in F” instead. Similarly, the coefficients atare in F2.

[0115] In standard lattice theory algorithms for solving the CVP in real spaces, the Euclidean norm is used to measure distances. The Euclidean norm is defined as the square root of the inner product of a vector with itself. In binary spaces, the Hamming norm can be used. The Hamming norm (or Hamming weight) refers to the count of non-zero elements in a vector. The Hamming distance (or Hamming metric) is defined for two vectors of equal length and is given by the number of positions at which the corresponding values are different.

[0116] An algorithmic reduction theory for binary codes has been suggested, comprising F2-analogues of the LLL algorithm and related algorithms, by replacing the usual notion of orthogonality with one of disjoint support. An exemplary algorithm which can be used in the present disclosure is described in Debris-Alazard, et al, “An Algorithmic Reduction Theory for Binary Codes: LLL and more”, https: / / eprint.iacr.org / 2020 / 869, which is hereby incorporated by reference in its entirety.

[0117] The processor 203 determines a binary string representation of the first physical representation of the logical operator, and further determines a binary string representation for each of the diagonal Clifford stabilizer generators. The mapping to binary string representations places the focus on operators that are prone to error propagation, i.e. , the CZ gates. The binary representation makes it possible to use lattice theory methods, which are otherwise typically not applicable in the context of quantum operators.

[0118] The binary string representation can be deduced from the phase-polynomial representation of diagonal operators. The phase gates S and CZ gates which generate the diagonal Clifford operators can be mapped as follows:

[0119] These basis polynomials are elements of Z4[xf]. Equivalently, a representation in terms of symmetric matrices in Mn(Z4) can be given as follows:where Ei:Jhas (i,;)-th entry equal to 1 and zeros elsewhere.

[0120] For example,

[0121] A flattening operation can now be applied to the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators. The flattening operation is applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

[0122] More explicitly, a flattening function f can be defined on the diagonal Clifford generators as follows:Sf0CZij >-> et-i . .-g-CZn-O+y-i where e;denotes the / -th standard basis vector.

[0123] For example, on 4 qubits: f{Z1S3• CZ1;2• CZ1;4• CZ24) = (1,0, 1,0, 1,0).

[0124] For a diagonal operator g G D in matrix form M, one can show that the spread of g is equal to the maximal column (or row) weight, excluding diagonal elements Mi:i, plus one. It can further be shown that the average 1 -spread is minimized by determining the physical representation of the logical operator which has the minimal number of CZ gates. Herein, the average 1 -spread for g G t / (n) is defined as:

[0125] Moreover, minimizing the number of CZ gates of a chosen diagonal Clifford operator is equivalent to minimizing the Hamming weight of its image under the flattening function f.

[0126] The processor 203 applies a closest vector problem (CVP) algorithm for solving the CVP on a lattice. As will be appreciated, the input parameters for the CVP are a lattice basis and a predefined target vector. Solving the CVP corresponds to finding a lattice point in the lattice that is closest to the predefined target vector. Herein, the binary string representation of the first physical representation of the logical operator is the target vector and the binary string representations of the diagonal Clifford stabilizer generators define the basis of the lattice. Specifically, if the diagonal Clifford stabilizer generators are denoted as gi tthe images under the flattening function f gi) are the basis vectors of the lattice.

[0127] For a chosen logical diagonal Clifford operator g, the image under the flattening function is t = f(g In other words, t is the binary string representation. The binary string representation t will be the target of a CVP. Finding g' G gS that minimises the number of CZ gates corresponds to solving the CVP for the binary lattice L with target t. In particular, ifis the closest lattice point to the target t, then g' = g ■ Hs contains the minimal number of CZ gates, and consequently, has the best average 1 -spread.

[0128] Prior to applying the CVP algorithm, the processor 203 may pre-process the binary string representations of the diagonal Clifford stabilizer generators, using lattice basis reduction methods. The lattice basis reduction method can be a Lenstra- Lenstra-Lovasz (LLL) algorithm, for example. By pre-processing, the binary string representations can be made as “orthogonal” as possible (in the sense of binary strings), i.e. , an optimal basis can be established. Pre-processing the binary string representations in this manner can improve the solution of the CVP as most CVP algorithms have a greater probability of returning an optimal solution when using pre- processed binary strings.

[0129] The processor 203 determines the second physical representation of the logical operator based on a solution of the CVP obtained using the CVP algorithm.

[0130] The solution can be a binary string representation that describes an improved physical representation of the logical operator (e.g., a diagonal Clifford logical operator). That is, the number of CZ gates of the second physical representation of the logical operator is generally smaller than the number of CZ gates of the first physical representation of the logical operator.

[0131] In some rare cases, the first physical representation of the logical operator may already be the best possible representation. In this case, the second physical representation of the logical operator can be identical to the first physical representation of the logical operator.

[0132] Furthermore, the CVP algorithms also do not guarantee that the best physical representation is actually found without an exponential overhead in terms of time and computational complexity. However, the CVP algorithms return an approximate best solution in polynomial time.

[0133] The system 100 further comprises a physical quantum system 400, i.e., a physical device or machine which can be used to implement algorithms (e.g., a quantum computer). The physical quantum system 400 comprises physical qubits 401 and physical components that implement the physical gates 402 operating on the qubits. For example, the quantum system 400 may comprise a semiconductor body with luminescent defects as described in US 2022 / 0366290 A1 and / or US 2022 / 0327416 A1 , which are hereby incorporated by reference in their entirety.

[0134] The physical quantum system 400 may be used for any practical application in quantum sensing, quantum computing or quantum communication.

[0135] Quantum computing comprises any processing of information based on quantum effects, such as superpositions of states of quantum systems and (de-)coherence or entanglement of quantum systems. The physical quantum system 400 may have physical qubits 401 that can be entangled with each other or with physical qubits of other physical quantum systems.

[0136] Quantum communication comprises the transmission of classical information or of quantum states between different devices, e.g., between the physical quantum system 400 and another physical quantum system based on quantum effects as described above.

[0137] Quantum sensing comprises measurements which utilize quantum effects such as entanglement, interference or quantum state squeezing.

[0138] The system 100 comprises a control device 300 which can control the physical quantum system 400 to implement a specific quantum algorithm. For example, the algorithm can be obtained by a user, e.g., via the user interface 205 of the representation determining device 200 or via a separate user interface of the control device 300.

[0139] Whenever the algorithm requires a particular logical diagonal gate (i.e., logical operator), the control device 300 accesses the description of the best possible physical representations. That is, the control device 300 retrieves a description of the second physical representation from the memory 204 and implements the logical operator using the physical gates 402, based on the description of the second physical representation.

[0140] The control device 300 may also control a cooling device 500 and an actuator device 600 which can influence the physical quantum system 400.

[0141] The actuator system 600 can comprise a plurality of actuators. For example, the actuator system 600 can comprise an electromagnet to apply a time-invariant electric field, a time-varying electric field or a pulsed electric field to the physical quantum system 400.

[0142] The cooling device 500 may maintain the physical quantum system 400 at a predefined cryogenic temperature, e.g., in a range from about 1 mK to 77 K, or more particularly in a range from about 1 .5 K to 4 K. The physical quantum system 400 may also be kept at constant air pressure, e.g., a stable vacuum.

[0143] The system 100 further comprises a code assessing device 700 which receives a candidate QEC code, e.g., via the user interface 205 or a user interface of the code assessing device 700. The code assessing device 700 sends a request to the representation determining device 200 for searching physical representations. The representation determining device 200 will then determine a second physical representation for all logical operators or at least a subset of the logical operators corresponding to the candidate QEC code. In particular, the representation determining device 200 may determine a second physical representation for all logical diagonal Clifford operators corresponding to the QEC code.

[0144] The code assessing device 700 will then determine at least one error spread property of the second physical representations of the logical operators, e.g., a maximum number of CZ gates. The code assessing device 700 will assess the candidate QEC code based on the error spread property. For example, if the errorspread property of the second physical representations is below a predetermined threshold, the candidate QEC code is accepted and the user is informed that the candidate QEC code can be implemented with a sufficiently good error spread. In contrast, if the error spread property of the second physical representations is above the predetermined threshold, the candidate QEC code is discarded and the user is informed that the candidate QEC code cannot be implemented with a sufficiently good error spread.

[0145] The code assessing device 700 can therefore be used as part of the code discovery process. Even if a candidate QEC code has good n, k, and d parameters, it may turn out not to be good in practice unless the logical diagonal Clifford operators can be implemented in a low spread fashion. Therefore, if a second physical representation with low spread does not exist and cannot be found, the algorithm might not be implemented.

[0146] Whereas the memory 204 is illustrated as part of the representation determining device 200, there can also be a separate memory or a memory which is part of the control device 300 for storing the descriptions of the second physical representations of the logical operators.

[0147] Likewise, the user interface 205 is illustrated as part of the representation determining device 200, but there can also be a separate user interface or a user interface which is part of the control device 300 or the code assessing device 700.

[0148] Fig. 2 shows a flow diagram illustrating a method for determining physical representations of logical operators of a QEC code. The method can for example be performed with the system 100 of Fig. 1 .

[0149] In step S11 , a description of logical operators associated with a predetermined QEC code is obtained. The QEC code is configured for encoding logical qubits on physical qubits. The QEC code can be a stabilizer code defined by a set of Pauli stabilizers, as defined above. In some embodiments, the description is received from a user external to the system 100. In other embodiments, the system 100 may generate the code.

[0150] Each logical operator corresponds to an operation to be performed on at least one of the logical qubits. In particular, the logical operator can be a logical diagonal Clifford operator as defined above.

[0151] In step S12, a first physical representation of each logical operator is obtained. In some embodiments, the first physical representation is received from a userexternal to the system 100. In other embodiments, the system 100 may generate the first physical representation. The physical representation of the respective logical operator acts on at least one of the physical qubits. Further, a set of diagonal Clifford stabilizer generators is obtained. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator.

[0152] In step S13, for each logical operator, a binary string representation of the first physical representation of the logical operator is determined. Further, binary string representations of the diagonal Clifford stabilizer generators is determined. As an example, symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators can be obtained. In order to determine the symmetric matrix representation, phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators can be mapped to diagonal matrix elements of the symmetric matrix representations. Controlled-Z gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators are mapped to off-diagonal matrix elements of the symmetric matrix representations.

[0153] A flattening operation is applied to the symmetric matrix representations of the first physical representation of the logical operator and to the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators. The flattening operation can be applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

[0154] Step S14 is a pre-processing step of making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators.The pre-processing step comprises applying a lattice reduction algorithm to a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators. The lattice reduction algorithm can be a Lenstra-Lenstra-Lovasz (LLL) algorithm, for example. The lattice reduction algorithm can be used to generate a “new” basis that has desirable properties, for example, shorter vectors which are closer to orthogonal vectors.

[0155] In step S15, a CVP algorithm is applied to solve the CVP. In some embodiments, the CVP algorithm is a pruned enumeration or Size Reduce algorithm. The CVP algorithm minimizes the Hamming weight of a binary string representation of the first physical representation of the logical operator, using the diagonal Clifford stabilizer generators. More specifically, the CVP algorithm is performed on the binary string representation of the first physical representation of the logical operator, with respect to the lattice generated by the binary string representations of the diagonal Clifford stabilizer generators.

[0156] In step S16, a second physical representation of the logical operator is determined based on a solution of the CVP. The second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

[0157] As explained above, the CVP algorithm is configured to minimize the number of controlled-Z gates in order to determine the second physical representation of the logical operator. That is, the number of controlled-Z gates of the second physical representation of the logical operator is smaller than or equal to the number of controlled-Z gates of the first physical representation of the logical operator. In some embodiments, the number of controlled-Z gates of the second physical representation of the logical operator is smaller than the number of controlled-Z gates of the first physical representation of the logical operator, although it is in principle not guaranteed that a global minimum is found.

[0158] In an optional step S17, the second physical representation of each of the logical operators is stored in a database.

[0159] In an optional step S18, a physical quantum system (e.g., a quantum computing system) is configured to implement a QEC protocol, using the predetermined QEC code and the second physical representation of the logical operator. The physical quantum system implements a plurality of physical operators operating on a plurality of physical qubits. At least one physical operator of the plurality of physical operators is implemented according to the second physical representation of the logical operator. A quantum operation can be performed with the physical quantum system.

[0160] Although the method has been described for obtaining second physical representations for each logical operator, it is also possible to determine only second physical representations for some of the logical operators, i.e., only a subset of the logical operators.

[0161] Fig. 3 shows a flow diagram illustrating a method for assessing QEC codes.

[0162] In a step S21 , a candidate QEC code is received.

[0163] In a step S22, for each logical operator of the candidate QEC code, a respective second physical representation is determined. Each respective second physical representation may be determined based on a solution to a closest vector problem. The solution to the closest vector problem may be determined using a CVP algorithm, e.g., using the method described in the context of Fig. 2.

[0164] In a step S23, the candidate QEC code is assessed based on at least one error spread property of the second physical representations of the logical operators. To do so, it is determined, whether at least one error spread property (ESP) of the second physical representations is within a predefined range.

[0165] In step S24, the candidate QEC code is discarded if the at least one error spread property of the second physical representations is outside the predefined range.

[0166] Otherwise, in step S25, the QEC code is accepted.

[0167] Fig. 4 shows a flow diagram illustrating a method for determining a physical implementation of a quantum circuit.

[0168] In step S31 , a plurality of logical operators associated with a QEC code are obtained. The logical operators can be logical diagonal Clifford operators. The QEC code can be a stabilizer code defined by a set of Pauli stabilizers.

[0169] In step S32, binary string representations of given first physical representations of each logical operator and binary string representations of the set of diagonal Clifford stabilizer generators are obtained. Each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator.

[0170] For example, symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators can be computed by mapping phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to diagonal matrix elements of the symmetric matrix representations. Controlled-Z gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators are mapped to off-diagonal matrix elements of the symmetric matrix representations. A flattening operation is applied to the symmetric matrix representations of the first physical representation of the logical operator and to thediagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators. The flattening operation can be applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

[0171] Step S33 is a pre-processing step of making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators, e.g., using a lattice reduction algorithm such as LLL.

[0172] In step S34, a CVP algorithm (e.g., pruned enumeration or Size Reduce algorithm) is applied to solve the CVP for a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators. More specifically, the CVP algorithm is applied to determine a closest lattice point in a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators, relative to the binary string representation of the first physical representation of the logical operator.

[0173] In step S35, for each logical operator, a respective physical representation of the logical operator is determined based on the solution of the CVP from step S34. The CVP algorithm minimizes a number of controlled-Z gates of the physical representations of the logical operator. The CVP algorithm minimizes a Hamming weight of the binary string representation of the first physical representation of said logical operator, using the set of diagonal Clifford stabilizer generators. A second physical representation of the logical operator is determined based on a solution of the CVP. As will be appreciated, the coefficients ai twhich are obtained from the solution of the CVP, are used when determining the second physical representation of the logical operator based on the expression g' = g • Hfl Saspreviously discussed.

[0174] In step S36, the second physical representations of the logical operators are stored in a database.

[0175] In step S37, the physical implementation of the quantum circuit is determined. The logical operators appearing in the quantum circuit are implemented as physical operators by retrieving the physical representations of the logical operators from the database.

[0176] In an optional step S38, a physical quantum system (e.g., a quantum computing system) is configured to implement a QEC protocol, using the determined physical implementation of the quantum circuit. The physical quantum system is operable to implement a plurality of physical operators operating on a plurality of physical qubits. At least one physical operator of the plurality of physical operators is implemented according to the determined physical representation of the logical operator.

[0177] The devices, apparatuses and systems described in the present disclosure may comprise electronic components and circuits known to those skilled in the art. Therefore, details of the circuitry and its components have not be explained in any greater extent than that considered necessary for the understanding and appreciation of the underlying concepts of the present disclosure.

[0178] Where reference is made to a component, such as a device, component, software module or the like, the reference to that component is intended to include as equivalents any component being functionally equivalent, i.e. , performing the same function, even though the component is not necessarily structurally equivalent to the component that performs in the exemplary embodiments.

[0179] In the above description, embodiments have been described with reference to specific details, e.g., parts of a method, components, materials, and the like. A person skilled in the art will understand that embodiments may be implemented without one or more of these specific details.

[0180] All of the US patents, US patent application publications, US patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification, or referred to on any application data sheet, are incorporated by reference in their entireties for all purposes herein.

[0181] A person skilled in the art may understand that certain method steps may be described or depicted in a particular order of occurrence while such specificity with respect to sequence is not actually required.

[0182] Phrases like “an embodiment” and “another embodiment” are used in the sense that particular features described in connection with the embodiment are included in at least one embodiment. Those phrases do not necessarily all refer to the same embodiment. Terms such as "first", "second", “third”, and so on, are used to distinguish between the elements described by these terms. These terms do not necessarily imply any temporal or other prioritization of such elements.

[0183] As used herein, the singular forms "a," "one," and "the " are also intended to encompass the plural forms unless the context indicates otherwise. In addition, it is understood that the expressions "includes" and / or "including" when used in this specification relates to the presence of features, numbers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more features, numbers, steps, operations, elements and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0184] Terms such as “horizontal”, “vertical”, “upper”, “lower”, “above”, “below”, “forward” and “backward” refer to particular orientations of components and / or events in time and / or space. The skilled person understands that may therefore depend on the specific orientation and may change if the components and / or events are oriented differently.

[0185] In this specification, the present disclosure has been described with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure is not limited to the described exemplary embodiments described and may be modified in various different ways.Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.

[0186] As used herein, the terms "about," "approximately," or "substantially" refer to a value, amount, or property that is close to the specified value, amount, or property. The value, amount, or property is such that a desired function or result is still achieved. According to an example, an amount may be less than 10%, 5%, 1%, or 0.1% of the specified amount, respectively.

[0187] Even if the disclosure has been described and illustrated with reference to illustrative embodiments, various modifications may be made without departing from the scope of the present disclosure as defined in the claims. Such modifications may comprise replacement of features, components and / or method steps with equivalent features, components and / or method steps; mixing of features, components and / or method steps from different embodiments; and / or omitting or combining features, components and / or method steps from described embodiments. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A computer-implemented method for determining physical representations of logical operators of a quantum error correcting, QEC, code, wherein the method comprises: obtaining a description of a logical operator associated with a predetermined QEC code, wherein the QEC code is configured for encoding logical qubits on physical qubits, and wherein the logical operator corresponds to an operation to be performed on at least one of the logical qubits; obtaining a first physical representation of the logical operator, wherein the physical representation of the logical operator, when performed on at least one of the physical qubits, implements the logical operator, and obtaining a set of diagonal Clifford stabilizer generators, wherein each diagonal Clifford stabilizer generator is for transforming the first physical representation of the logical operator into another physical representation of the same logical operator; and determining a second physical representation of the logical operator, using a closest vector problem, CVP, algorithm, wherein the CVP algorithm is performed on the first physical representation, and wherein the second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

2. The method according to claim 1 , further comprising: configuring a quantum computing system to implement a QEC protocol, using the predetermined QEC code and the second physical representation of the logical operator.

3. The method according to claim 1 or 2, wherein the logical operator is a logical diagonal Clifford operator, wherein logical diagonal Clifford operators are diagonal unitary operators which are elements of the Clifford group and stabilize all elements of a codespace of the QEC code elementwise.

4. The method according to any one of claims 1 to 3, wherein the CVP algorithm is used to determine the physical representation of the logical operator such that the number of controlled-Z gates of the second physical representation of the logical operator is smaller than or equal to the number of controlled-Z gates of the first physical representation of the logical operator.

5. The method according to any one of claims 1 to 3, wherein the CVP algorithm is configured to minimize the number of controlled-Z gates in determining the second physical representation of the logical operator.

6. The method according to any one of claims 1 to 5, wherein the CVP algorithm is configured to minimize a Hamming weight of a binary string representation of the first physical representation of the logical operator, using the diagonal Clifford stabilizer generators, in order to obtain the second physical representation of the logical operator.

7. The method according to claim 1 , wherein the CVP algorithm is a binary lattice algorithm.

8. The method according to claim 7, wherein the binary lattice algorithm is a binary adaptation of an LLL algorithm.

9. The method according to any one of claims 1 to 5 further comprising: determining a binary string representation of the first physical representation of the logical operator, and determining binary stringrepresentations of the diagonal Clifford stabilizer generators; applying the CVP algorithm to determine a closest lattice point in a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators, relative to the binary string representation of the first physical representation of the logical operator; and determining the second physical representation of the logical operator based on the determined closest lattice point.

10. The method according to claim 9, wherein determining the binary string representation of the first physical representation of the logical operator and determining the binary string representations of the diagonal Clifford stabilizer generators comprises: determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators; and applying a flattening operation to the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representations of the diagonal Clifford stabilizer generators.

11. The method according to claim 10, wherein determining the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators comprises: mapping phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to diagonal matrix elements of the symmetric matrix representations; andmapping controlled-Z gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to off- diagonal matrix elements of the symmetric matrix representations.

12. The method according to claim 10, wherein the flattening operation is applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

13. The method according to any one of claims 9 to 12, further comprising making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators to obtain transformed binary string representations of the diagonal Clifford stabilizer generators, wherein the CVP algorithm is applied to determine the closest lattice point in the lattice generated by the transformed binary string representations of the diagonal Clifford stabilizer generators.

14. The method according to any one of claims 1 to 13, wherein the QEC code is a stabilizer code defined by a set of Pauli stabilizers.

15. The method according to claim 1 , wherein the second physical representation of the logical operator is stored in a database.

16. The method according to claim 1 , wherein for each logical operator of a plurality of logical operators a respective second physical representation of the logical operator is determined.

17. The method according to claim 1 , comprising the further step of operating a physical quantum system, wherein the physical quantum system implements a plurality of physical operators operating on a plurality of physical qubits, wherein at least one physical operator of theplurality of physical operators is implemented according to the second physical representation of the logical operator.

18. The method according to claim 17, further comprising: performing a quantum operation with the physical quantum system.

19. A computer-implemented method comprising: receiving a candidate QEC code; determining, for each logical operator of the candidate QEC code, a respective physical representation based on a solution to a closest vector problem; and assessing the candidate QEC code based on at least one error spread property of the physical representations of the logical operators.

20. The method according to claim 19, wherein the candidate QEC code is discarded if the at least one error spread property of the second physical representations is outside a predefined range.

21. A computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to any one of claims 1 to 20.

22. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to any one of claims 1 to 20.

23. A device configured to perform the method according to any one of claims 1 to 20.

24. A device for determining physical representations of logical operators of a quantum error correcting, QEC, code, comprising a processor configured to: obtain a description of a logical operator associated with a predetermined QEC code, wherein the QEC code is configured for encoding logical qubits on physical qubits, and wherein the logical operator corresponds to an operation to be performed on at least one of the logical qubits; obtain a first physical representation of the logical operator, wherein the physical representation of the logical operator, when performed on at least one of the physical qubits, implements the logical operator; obtain a set of diagonal Clifford stabilizer generators, wherein each diagonal Clifford stabilizer generator is for transforming the first physical representation of the logical operator into another physical representation of the same logical operator; and determine a second physical representation of the logical operator, using a closest vector problem, CVP, algorithm, wherein the CVP algorithm is performed on the first physical representation, and wherein the second physical representation of the logical operator comprises a plurality of phase gates and / or controlled-Z gate.

25. The device according to claim 24, wherein the processor is configured to implement a QEC protocol, using the QEC code and the second physical implementation of the logical operator.

26. The device according to claim 24 or 25, wherein the processor is configured determine the second physical implementation of the logical operator by minimizing a Hamming weight of a binary stringrepresentation of the first physical implementation of the logical operator.

27. A computer-implemented method for determining a physical implementation of a quantum circuit, comprising the steps: determining, for a plurality of logical operators associated with a quantum error correcting, QEC, code, a respective physical representation of the logical operator, using a closest vector problem, CVP, algorithm, wherein the CVP algorithm is used to minimize a number of controlled-Z gates of the physical representations of the logical operator; and determining the physical implementation of the quantum circuit, wherein the logical operators appearing in the quantum circuit are implemented as physical operators based on the determined physical representations of the logical operators.

28. The method according to claim 27, wherein the physical representations of the logical operators are stored in a database, and wherein the logical operators appearing in the quantum circuit are implemented by retrieving the physical representations of the logical operators from the database.

29. The method according to claim 27, further comprising: configuring a quantum computing system to implement a QEC protocol, using the determined physical implementation of the quantum circuit.

30. The method according to claim 27, wherein the logical operators are logical diagonal Clifford operators, wherein logical diagonal Clifford operators are diagonal unitary operators which are elements of the Clifford group and stabilize all elements of a codespace of the QECcode elementwise.

31. The method according to claim 27, wherein, for each logical operator, the CVP algorithm is configured to minimize a Hamming weight of a binary string representation of a first physical representation of said logical operator, using a set of diagonal Clifford stabilizer generators, in order to obtain a second physical representation of the logical operator.

32. The method according to claim 27, wherein the CVP algorithm is a binary lattice algorithm.

33. The method according to claim 32, wherein the binary lattice algorithm is a binary adaptation of an LLL algorithm.

34. The method according to claim 27, further comprising, for each logical operator: determining a binary string representation of a first physical representation of said logical operator, and determining a binary string representation of a plurality of diagonal Clifford stabilizer generators, wherein each diagonal Clifford stabilizer generator transforms the first physical representation of the logical operator into another physical representation of the same logical operator; applying the CVP algorithm to determine a closest lattice point in a lattice generated by the binary string representations of the diagonal Clifford stabilizer generators, relative to the binary string representation of the first physical representation of said logical operator; and determining the second physical representation of the logical operator based on the determined closest lattice point.

35. The method according to claim 34, wherein determining the binary string representation of the first physical representation of the logical operator and determining the binary string representation of the diagonal Clifford stabilizer generators comprises: determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators; and applying a flattening operation to the symmetric matrix representations of the first physical representation of the logical operator and to the diagonal Clifford stabilizer generators in order to obtain the binary string representation of the first physical representation of the logical operator and the binary string representation of the diagonal Clifford stabilizer generators.

36. The method according to claim 35, wherein determining symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators comprises: mapping phase gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to diagonal matrix elements of the symmetric matrix representations; and mapping controlled-Z gates of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators to off- diagonal matrix elements of the symmetric matrix representations.

37. The method according to claim 35, wherein the flattening operation is applied to a strictly upper triangular portion of the symmetric matrix representations of the first physical representation of the logical operator and the diagonal Clifford stabilizer generators.

38. The method according to claim 35, further comprising a pre-processing step of making a basis transformation on the binary string representations of the diagonal Clifford stabilizer generators, wherein the CVP algorithm is applied to determine the closest lattice point in the lattice generated by the transformed binary string representations of the diagonal Clifford stabilizer generators.

39. The method according to claim 27, wherein the QEC code is a stabilizer code defined by a set of Pauli stabilizers.

40. The method according to claim 27, comprising the further step of operating a physical quantum system, wherein the physical quantum system implements a plurality of physical operators operating on a plurality of physical qubits, wherein at least one physical operator of the plurality of physical operators is implemented according to the determined physical representation of the logical operator.

41. A computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to any one of claims 27 to 40.

42. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to any one of claims 27 to 40.

43. A device configured to perform the method according to any one of claims 27 to 40.

44. A device for determining a physical implementation of a quantum circuit, comprising a processor configured to: determine, for a plurality of logical operators associated with a quantum error correcting, QEC, code, a respective physical representation of thelogical operator, using a closest vector problem, CVP, algorithm, wherein the CVP algorithm is used to minimize a number of controlled-Z gates of the physical representations of the logical operator; and determine the physical implementation of the quantum circuit, wherein the logical operators appearing in the quantum circuit are implemented as physical operators based on the determined physical representations of the logical operators.

45. The device according to claim 44, wherein the processor is configured to configure a quantum computing system to implement a QEC protocol, using the determined physical implementation of the quantum circuit.

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