Formal verification method for realizing optimized multiplier by cooperation of sca and sat

Abstract

Disclosed in the present invention is a formal verification method for realizing an optimized multiplier by cooperation of SCA and SAT. The formal verification method comprises: a reverse engineering algorithm systematically recovers an adder tree from an optimized multiplier; 2) a constraint satisfaction algorithm uses only an adder to complete generation of a reference multiplier by means of a constraint condition; and 3) a verification method based on SCA and SAT combines the complementary advantages of SCA and SAT. In the verification framework, the present invention introduces a reference multiplier generator for generating a correct reference multiplier which has both a structure similar to the optimized multiplier and a clear adder boundary. The clear adder boundary makes it possible to use SCA-based verification to prove the correctness of the multiplier. By using the structural similarity of the reference multiplier and the optimized multiplier, the reference multiplier is then used as a known correct model and used for SAT-based verification of the optimized multiplier.

Description

Formal Verification Method for Optimized Multipliers Using SCA-SAT Synergy Technical Field

[0001] The present invention relates to a method for formally verifying an integer multiplier, and in particular to a formal verification method for realizing an optimized multiplier through the automatic generation of a reference multiplier and the synergistic effect of SCA-SAT. Background Art

[0002] Integer multipliers are a key component in computer science and electrical engineering. They play an important role in various hardware devices, including but not limited to AI chips, CPUs, and GPUs. These devices play a vital role in many aspects of our daily lives, including data processing, graphics rendering, and artificial intelligence computing. Therefore, ensuring the correctness of these devices is of paramount importance.

[0003] However, due to the complexity of design and implementation, integer multipliers can exhibit design flaws. These flaws can degrade device performance or even render the device completely inoperable, as exemplified by the infamous Pentium FDIV bug. While logic optimization can improve efficiency, it can also introduce errors into the optimized multiplier. Therefore, a method is needed to verify the correctness of these devices, which is where formal verification comes in. Formal verification, a technique that uses mathematical methods to prove the correctness of a system, is crucial for optimizing optimized multipliers to prevent potentially catastrophic defects.

[0004] There are currently several methods for formally verifying integer multipliers. One class of methods relies on a known correct benchmark multiplier, including binary decision diagram (BDD)-based methods [1] and satisfiability (SAT)-based methods [2, 3]. Both methods prove correctness by proving the unsatisfiability of a miter circuit composed of an optimized multiplier and a benchmark multiplier. Another class of methods utilizes symbolic computer algebra (SCA) techniques [4] without the need for a benchmark multiplier. These techniques represent gates as polynomials and rewrite them step by step from output to input, with the zero polynomial representing correctness.

[0005] However, due to logic optimization, large optimized multipliers often lack structurally similar benchmark references, and the adder boundaries therein are fuzzy. This poses a significant challenge to state-of-the-art methods. BDD-based methods [1] can handle miters of multipliers with different structures, but for large optimized multipliers, node explosion problems will occur. SAT-based methods [3, 5] attempt to reduce the problem size by merging internal equivalent nodes in the miter circuit. They can only handle miters composed of multipliers with similar structures, and cannot handle miters composed of multipliers with different structures due to the scarcity of internal equivalent nodes. SCA-based methods [6, 7, 8] use adder detection and vanishing monomials to prevent polynomial explosion, which is effective for multipliers with clear adder boundaries. However, for optimized multipliers, these boundaries are blurred and memory explosion problems often occur.

[0006] References

[0007] [1] J.Kumar, Y.Miyasaka, A.Srivastava, and M.Fujita, "Formal verification of integermultiplier circuits using binary decision diagrams," TCAD, vol.42, no.4, pp.1365-1378, 2023.

[0008] [2] A.Biere and M.Fleury, "Gimsatul, IsaSAT and Kissat entering the SAT Competition 2022," in SAT Competition, vol.B-2022-1, 2022, pp.10-11.

[0009] [3] A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking," in ICCAD, 2006, p.836-843.

[0010] [4] M. Ciesielski, T. Su, A. Yasin, and C. Yu, “Understanding algebraic rewriting for arithmetic circuit verification: A bit-flow model,” TCAD, vol. 39, no. 6, pp. 1346 - 1357, 2020.

[0011] [5] L. Amarú, F. Marranghello, E. Testa, C. Casares, V. Possani, J. Luo, P. Vuillod, A. Mishchenko, and G. De Micheli, “Sat-sweeping enhanced for logic synthesis,” in DAC, 2020, pp. 1 - 6.

[0012] [6] A. Mahzoon, D. Große, and R. Drechsler, “Revsca-2.0: Sca-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal,” TCAD, vol. 41, no. 5, pp. 1573 - 1586, 2022.

[0013] [7] A. Mahzoon, D. Große, and R. Drechsler, “Polycleaner: Clean your polynomials before backward rewriting to verify million-gate multipliers,” in ICCAD, 2018, pp. 1 - 8.

[0014] [8] A. Mahzoon, D. Große, and R. Drechsler, “Revsca: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers,” in DAC, 2019, pp. 1 - 6.

[0015] Summary of the Invention

[0016] The object of the present invention is to enable verification of an optimized multiplier.

[0017] In order to achieve the above object, the technical solution of the present invention is to provide a formal verification method for optimizing multipliers by SCA-SAT synergy, which is characterized by comprising the following steps:

[0018] Step 1: The reverse engineering algorithm systematically recovers the adder tree from the optimized multiplier to ensure structural similarity. The reverse engineering algorithm includes atomic block detection and adder tree recovery:

[0019] Atomic block detection is used to detect the atomic blocks that make up the optimized multiplier AIG, including half adder HA, full adder FA, exclusive OR gate XOR, and AND gate AND. Based on the constructed library containing the truth tables of these atomic blocks, all Cuts are systematically extracted from AIG using AIGcut enumeration, and the mentioned Cuts are compared with the truth tables in the library. During the comparison, all Cuts are searched, whose output vectors are aligned with an output vector in the atomic block truth table library. When a group of Cuts with common inputs show the same output vector as the atomic block truth table in the library, the group is identified as an atomic block.

[0020] The adder tree recovery algorithm utilizes some retained adder boundaries that provide significant structural information through a breadth-first search method; the adder tree recovery algorithm maintains a frontier queue FQ, which contains half adders HA / full adders FA / AND gates AND that generate / consume unexplored partial products, initialized to generate initial PP ij The adder tree recovery algorithm also maintains a sum of all AND gates from the weight W k The partial product map PPM to the active partial product is initialized to PPM[W k ]={PP ij}, k=i+j, where PPM[W k ] represents the weight W k Mapping to partial products, PP ij represents the partial product generated by the i-th bit of the multiplier and the j-th bit of the multiplier through the AND gate; then, the adder tree recovery algorithm iteratively dequeues an atomic block from the frontier queue FQ, deactivates the consumed partial products, and adds the generated partial products to the partial product map PPM; then, the adder tree recovery algorithm fans out the adder type of the atomic block, whose fan-in half adder HA / full adder FA has been processed and added to the frontier queue FQ; when the frontier queue FQ is empty, the adder tree recovery algorithm terminates, and the visited half adder HA / full adder FA and the connection constitute the partial adder tree, and the remaining partial product map PPM partial products need to be further processed;

[0021] Step 2: For each weight W k, the recovery algorithm preserves R k The partial product is expressed as Where, 0≤k<2n, n represents the number of multiplier input bits, Represents the weight W k R k -1 retains the partial product, and models the reconstructed PPA as a constraint satisfaction problem, which is expressed as an N-step planning process. At each step, two decisions are made: whether to generate a full adder FA / half adder HA, and to select the input of the full adder FA / half adder HA. The generated carry / sum is also tracked as the input of the subsequent full adder FA / half adder HA. For each weight W k The selection matrix Sel and the state matrix State are defined, where;

[0022] The generation process is represented by generating architectural constraints based on the selection matrix Sel and the state matrix State. These constraints include adder input selection constraints, state constraints, FSA constraints, and unresolved pin constraints. These constraints are encoded into the CP-SAT solver to generate a satisfiable solution. Starting with small decision steps, the step size is increased and constraints are re-added until a solution is found or a timeout occurs. The solution is then converted to the actual PPA architecture by checking the selection matrix Sel, and Verilog code for the multiplier is generated for verification.

[0023] Step 3. After generating the Verilog code for the reference multiplier, convert it to an AIG and verify it using an SCA-based approach. Then, create a miter AIG from the optimized and reference multipliers. Use SAT sweeping to accelerate the verification of the satisfiability of the miter AIG. The process begins by simulating the miter AIG using random input vectors. Based on the simulation results, all possible equivalent internal nodes are identified. Next, use the Kissat 3.0 SAT solver to verify whether these nodes are indeed equivalent. Based on the verification results of each possible equivalent node, the equivalent nodes are merged to simplify the miter AIG. Repeat the above process until the satisfiability of the miter AIG is determined. If it is satisfiable, a counterexample is output to diagnose the error. If it is not satisfiable, the correctness of the optimized multiplier is confirmed.

[0024] Preferably, in step 1, the library encapsulates Negation, Permutation and all functions of the Negation class of the atomic block.

[0025] Preferably, in step 2, the size of the selection matrix Sel is N×H=R k+2×N, where each row represents a decision step and the columns represent the generated input candidates for the full adder FA / half adder HA. k The columns correspond to the retained partial products, where Indicates the weight W is selected in step s k The rth retained partial product P k，r , the next 2N columns represent the carry / sum generated from the previous / current weight, where Indicates the weight W is selected in step s k The carry / sum of , which are generated in step i; the state matrix State has a size of N×4, where the i-th row represents the state of the carry / sum generated in step i.

[0026] Preferably, in step 2, the adder input selection constraint is expressed as:

[0027] Where, Denotes the weight W selected in step s k The sums of , where these sums are generated in step i, represents the sum of the sth row of the Sel matrix, represents the weight W of step i k The carry is not generated. represents the weight W of step i k The sum is not generated; constraint (1) is obtained by limiting Sel row The sum is 0, 2 or 3, allowing at most one adder per step, Sel row represents the sum of the sth row of the Sel matrix; constraint (2) restricts the selection of candidate inputs in one step by enforcing a unit column sum in Sel; constraint (3) excludes the selection of the ungenerated i-th sum / carry as the adder input;

[0028] The state constraint is expressed as:

[0029] Where, represents the weight W of step i k The carry bit is used as input by other adders. represents the weight W of step i k The sum is used as input by other adders; Constraint (4) sets the corresponding generation flag when creating the adder; Constraint (5) If selected as input, any sum / carry is marked as consumed;

[0030] The FSA constraint is expressed as:

[0031] Use a Boolean vector variable F of length H k To monitor the remaining partial products, constraint (6) will F k There are at most two remaining partial products to provide the required FSA input; constraint (7) prohibits k contains the consumed partial products, sums, and carries;

[0032] The unresolved pin constraint: For a given weight W k , there are P unresolved pins, build a Boolean matrix U of size P × H k To indicate the partial product of the connection, a Boolean implication constraint is used to model the partial product remaining in the unresolved pin fanout as U k Zeros in the entries; use an intermediate Boolean matrix of size N × H to track sums that have paths that lead to illegal partial products, and if such a path exists, generate implication constraints; finally, U k Each row of sums to one to ensure connectivity of each unresolved pin and constrain the selected partial products to be illegal candidates for feeding into the FSA.

[0033] The present invention proposes RefSCAT, a new verification framework for optimized multipliers, which includes three steps: 1) A reverse engineering algorithm systematically recovers the adder tree from the optimized multiplier to ensure structural similarity; 2) A constraint satisfaction algorithm generates a reference multiplier using only adders under constraints, thereby ensuring clear adder boundaries; 3) A verification method based on SCA and SAT combines the complementary advantages of SCA and SAT to accurately and quickly verify the optimized multiplier. In the aforementioned verification framework, the present invention introduces a reference multiplier generator, which is used to generate a correct reference multiplier. This correct reference multiplier has a structure similar to the optimized multiplier and has clear adder boundaries. The clear adder boundaries make it possible to use SCA-based verification to prove its correctness. Utilizing the structural similarity between the reference multiplier and the optimized multiplier, the reference multiplier is then used as a known correct model for SAT-based verification of the optimized multiplier. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 shows the algorithmic framework proposed in this invention: 1) reverse engineering the optimized multiplier into a structural netlist; 2) innovatively synthesizing an auxiliary benchmark multiplier using constraint programming; 3) formally verifying the benchmark multiplier using SCA; 4) verifying the equivalence between the benchmark multiplier and the optimized multiplier through SAT scan;

[0035] FIG2 illustrates a partial addition tree extraction algorithm proposed in an embodiment of the present invention;

[0036] FIG3 illustrates an automatic multiplier generation algorithm based on constraint satisfiability proposed in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0038] The embodiment of the present invention discloses a formal verification method for optimizing a multiplier by automatically generating a reference multiplier and cooperating with SCA-SAT, which specifically includes the following steps:

[0039] Step 1: The reverse engineering algorithm systematically recovers the adder tree from the optimized multiplier, ensuring structural similarity. The reverse engineering algorithm includes atomic block detection and adder tree recovery. Atomic block detection is used to detect the atomic blocks that make up the optimized multiplier AIG, including half adders (HAs), full adders (FAs), exclusive-OR gates (XORs), and AND gates (ANDs). To facilitate a complete match, the present invention constructs a library containing truth tables for these atomic blocks. This library encapsulates all functions of the atomic block's Negation, Permutation, and Negation (NPN) classes. With this library, all cuts from the optimized multiplier AIG can be systematically extracted using AIGcut enumeration and compared with the truth tables in the library. This process searches for all cuts whose output vectors align with an output vector in the library of atomic block truth tables. When a group of cuts with common inputs displays the same output vector as the atomic block truth table in the library, the group is identified as an atomic block. The result of this process is a structural netlist consisting of interconnected atomic blocks.

[0040] Since the optimization eliminates many adder boundaries, some boundaries that provide significant structural information are retained. The proposed adder tree recovery algorithm exploits this by using a breadth-first search (BFS)-based approach. It maintains a frontier queue FQ containing HA / FA / AND that generate / consume unexplored partial products, initialized to generate the initial PP ij It also maintains a weight W k Partial product mapping (PPM) to active partial products, initialized to PPM[W k ]={PP ij}, k=i+j, where PPM[W k ] represents the weight W k Mapping to partial products, PP ijrepresents the partial product generated by the AND gate of the multiplier bit i and the multiplier bit j. Then, the algorithm iteratively dequeues an atomic block from the FQ, deactivates the consumed partial product, and adds the generated partial product to the PPM. For example, if HA i The input weight is W k , HA i represents the i-th half adder, then the sum generated is / Carry Add to PPM[W k ] and PPM[W k Then, the adder type of the atomic block is fanned out, and its fan-in HA / FA has been processed and added to the queue FQ. When the FQ is empty, the algorithm terminates, and the visited HA / FA and connections constitute the partial adder tree. The remaining PPM partial products need further processing.

[0041] Step 2: For each weight W k , the recovery algorithm preserves R k The partial product is expressed as Where, 0≤k<2n, n represents the number of multiplier input bits, Represents the weight W k R k -1 preserved partial products. The main challenge is to reconstruct the PPA by compressing the PPM using FA and HA and connecting the unresolved pins to the adder tree. We model this as a constraint satisfaction problem, expressed as an N-step planning process. At each step, two decisions are made: whether to generate a FA / HA, and to select the input to the FA / HA. The generated carry / sum is also tracked as the input to the subsequent FA / HA. This is inherently complex due to the dependencies between steps / weights. To facilitate this process, we have a ∑ k Two matrices of Boolean variables are defined:

[0042] 1) A selection matrix Sel, size N×H=R k +2×N, where each row represents a decision step and the columns represent the generated FA / HA input candidates. k The columns correspond to the retained partial products, where Indicates the weight W is selected in step s k The rth retained partial product P k，r The next 2N columns represent the carries / sums generated from the previous / current weights, where Indicates the weight W is selected in step s k The carries / sums of , which are generated in step i.

[0043] 2) A state matrix State of size N×4, where the i-th row represents the state of the carry / sum generated at step i.

[0044] With these variables, we can generate architectural constraints to represent the generation process. Note that the following constraints should be applied to all weights W k , where 0≤k<2n.

[0045] Adder input selection constraints: Determine at which step to use the available input to generate HA / FA, including: Constraint (1) by limiting Sel row The sum is 0, 2 or 3, allowing at most one adder per step, Sel row represents the sum of the sth row of the Sel matrix; constraint (2) restricts the selection of candidate inputs in one step by enforcing a unit column sum in Sel; constraint (3) excludes the selection of the ungenerated i-th sum / carry as the adder input, as shown in the following formula:

[0046] Where, Denotes the weight W selected in step s k The sums of , where these sums are generated in step i, represents the sum of the sth row of the Sel matrix, represents the weight W of step i k The carry is not generated. represents the weight W of step i k The sum is not generated.

[0047] State constraints: Track the generation and consumption of sums and carries, including: constraint (4) sets the corresponding generation flag when creating the adder; constraint (5) marks any sum and carry as consumed if selected as input. Together, these constraints provide the information needed to coordinate other constraints, as shown in the following equation:

[0048] Where, represents the weight W of step i k The carry bit is used as input by other adders. represents the weight W of step i k The sum is taken as input by other adders.

[0049] FSA constraint: Enforces proper connection between PPA and FSA. Use a Boolean vector variable F of length H k To monitor the remaining partial products. Constraint (6) will F k The constraint is that there are at most two partial products remaining to provide the required FSA input. Constraint (7) prohibitsk The consumed partial products, sums, and carries are included in the equation below:

[0050] Unresolved Pin Constraint: Enforces proper connections between adder trees and unresolved pins. For a given weight W k , there are P unresolved pins, build a Boolean matrix U of size P × H k To indicate the partial product of the connection. To avoid combinational loops, Boolean implication constraints are used to model the partial product remaining in the unresolved pin fanout as U k In addition, an intermediate Boolean matrix of size N × H is used to track sums that have paths that lead to illegal partial products and, if such paths exist, to generate implication constraints. Finally, U k Each row of sums to one to ensure connectivity of each unresolved pin and constrain the selected partial products to be illegal candidates for feeding into the FSA.

[0051] The above constraints are encoded into the CP-SAT solver to generate a satisfiable solution. The algorithm starts with small decision steps, increasing the step size and re-applying constraints until a solution is found or a timeout occurs. The solution is then converted to the actual PPA architecture by inspecting the Sel matrix, and Verilog code for the multiplier is generated for verification.

[0052] Step 3: After generating the Verilog code for the reference multiplier, it is converted to an AIG and verified using an SCA-based approach. A miter AIG is then created from the optimized and reference multipliers. SAT sweeping is used to accelerate the verification of the satisfiability of the miter AIG. The process begins by simulating the miter AIG using random input vectors. Based on the simulation results, all potentially equivalent internal nodes are identified. Next, the Kissat 3.0 SAT solver is used to verify that these nodes are indeed equivalent. Based on the verification results for each potentially equivalent node, the confirmed equivalent nodes are merged to simplify the miter AIG. This process is repeated until the miter satisfiability is confirmed. If it is satisfiable, a counterexample is output to diagnose the error. If it is not satisfiable, the correctness of the optimized multiplier is confirmed.

[0053] As shown in Figure 2, the partial addition tree extraction algorithm proposed in the embodiment of the present invention maintains a queue called the "frontier queue" (FQ), which contains half adders (HAs), full adders (FAs) and AND gates (ANDs) that generate or consume unexplored partial products. This queue is initialized to contain all the initial partial products PP generated. ijIn addition, the system also maintains a map called "Partial Product Map" (PPM), which maps the weight W k Mapped to active partial products, initialized to PPM[W k ]={PP ij}, k=i+j. Then, the algorithm iteratively takes an atomic block from the FQ, deactivates the consumed partial products, and adds the newly generated partial products to the PPM. For example, if the half adder HA i The input weight is W k , then the sum / carry generated Will be added to PPM[W k ] and PPM[W k+1 ]. Next, the adder-type fanouts of the atomic blocks whose fan-in half adders / full adders have been processed are added to the queue FQ. When the FQ is empty, the algorithm terminates, and the visited half adders / full adders and their connections form a partial adder tree. The remaining partial products in the PPM require further processing.

[0054] As shown in Figure 3, in the automatic multiplier generation algorithm based on constraint satisfiability proposed in an embodiment of the present invention, the following steps are performed: The decision step size is first initialized to 2, and the constraint programming solver (CP-SAT) is initialized. For each weight, the algorithm sequentially adds adder input selection constraints, adder state constraints, connection constraints between different stages of the multiplier, and unconnected pin constraints to the solver. The solver then performs a solution. If the solution is successful, the algorithm converts the solver output into Verilog code for the multiplier. If the solution fails and there is no timeout, the algorithm reinitializes the constraint programming solver, increases the decision step size, re-adds constraints, and continues the solution.

[0055] The above technical solution is implemented using the C++ language. The proposed multiplier verifier can formally verify the multiplier circuit after high logic optimization. By automatically generating a benchmark multiplier corresponding to the optimized multiplier, the technical solution disclosed in the present invention can quickly formally verify the correctness of the considered multiplier. At the same time, if the considered multiplier is incorrect, the present invention can provide a corresponding input counterexample, indicating under which input the multiplier output is incorrect.

Claims

1. A formal verification method for optimizing multipliers through the synergistic effect of SCA-SAT, characterized in that Including the following steps: Step 1. The reverse engineering algorithm systematically recovers the adder tree from the optimized multiplier to ensure structural similarity. The reverse engineering algorithm includes atomic block detection and adder tree recovery: Atomic block detection is used to detect the constituent atomic blocks of the optimized multiplier AIG, including half adder HA, full adder FA, exclusive OR gate XOR, and AND gate AND. Based on the library constructed with the truth tables of these atomic blocks, all Cuts are systematically extracted from the AIG using the AIGcut enumeration, and the mentioned Cuts are compared with the truth tables in the library. During the comparison, all Cuts are searched, and when the output vector of a group of Cuts with common inputs shows the same output vector as the truth table of an atomic block in the library, this group is identified as an atomic block; The adder tree recovery algorithm utilizes some adder boundaries that provide significant structural information through a breadth-first search-based approach; the adder tree recovery algorithm maintains a frontier queue FQ that contains half adders HA / full adders FA / AND gates AND that generate / consume unexplored partial products, initialized to generate the initial PPs ij of all AND gates AND. The adder tree recovery algorithm also maintains a partial product mapping PPM from the weight W k to the active partial products, initialized to PPM[W k = {PP ij}, where k = i + j. Here, PPM[W k represents the mapping from the weight W k to the partial product, and PP ij represents the partial product generated by the AND gate for the i-th bit of the multiplier and the j-th bit of the multiplier; then, the adder tree recovery algorithm iteratively dequeues an atomic block from the frontier queue FQ, deactivates the consumed partial products, and adds the generated partial products to the partial product mapping PPM; then, the adder tree recovery algorithm fans out the adder type of the atomic block whose fan-in half adder HA / full adder FA has been processed and adds it to the frontier queue FQ; when the frontier queue FQ is empty, the adder tree recovery algorithm terminates, and the accessed half adders HA / full adders FA and connections form a partial adder tree, and the remaining partial products in the partial product mapping PPM need further processing; Step 2. For each weight W k , the restoration algorithm retains R k partial products, denoted as where 0 ≤ k < 2n, and n represents the number of bits of the multiplier input Denote the weight W k of the R k - 1 reserved partial products, the reconstructed PPA is modeled as a constraint satisfaction problem, represented as an N-step planning process, where at each step, two decisions are made: whether to generate a full adder FA / half adder HA, and to select the inputs of the full adder FA / half adder HA, and the generated carry / sum is also used as the input of the subsequent full adder FA / half adder Track the input of the device HA and, for each weight W k Define a selection matrix Sel and a state matrix State, where; Based on the selection matrix Sel and the state matrix State, architecture constraints are generated to represent the generation process, including adder input selection constraints, state constraints, FSA constraints, and unresolved pin constraints. These constraints are encoded into the CP-SAT solver to generate a satisfiable solution: starting from small decision steps, increasing the step size and re-adding constraints until a solution is found or a timeout occurs; then, by checking the selection matrix Sel, the solution is converted into an actual PPA architecture, and the Verilog code of the multiplier is generated for verification; Step 3. After generating the Verilog code of the reference multiplier, it is converted into an AIG and verified by the SCA-based method. Then, a miter AIG is created from the optimized multiplier and the reference multiplier, and SAT sweeping is used to accelerate the verification of the satisfiability of the miter AIG. This process starts with simulating the miter AIG using random input vectors. Based on the simulation results, all possible equivalent internal nodes are identified; then, the Kissat 3.0 SAT solver is used to verify whether these nodes are indeed equivalent. According to the verification results of each possible equivalent node, the confirmed equivalent nodes are merged to simplify the miter AIG; the foregoing process is repeated until the satisfiability of the miter AIG is determined: if it is satisfiable, a counterexample is output to diagnose the error; if it is unsatisfiable, the correctness of the optimized multiplier can be confirmed.

2. The formal verification method for optimizing a multiplier by the synergistic effect of SCA-SAT as described in claim 1, characterized in that In Step 1, the library encapsulates all functions of the Negation, Permutation, and Negation classes of atomic blocks.

3. The formal verification method for optimizing a multiplier by the synergistic effect of SCA - SAT as described in claim 1, wherein In step 2, the size of the selection matrix Sel is N×H=R k +2×N, where each row represents a decision step and the columns represent the input candidates of the generated full adder FA / half adder HA. k The columns correspond to the retained partial products, where Indicates the weight W is selected at step s k The rth retained partial product P k，r , the next 2N columns represent the carry / sum generated from the previous / current weight, where Indicates the weight W is selected at step s k The carry / sum is generated in step i; the state matrix State has a size of N×4, where the i-th row represents the state of the carry / sum generated in step i.

4. The formal verification method for optimizing a multiplier by the synergistic effect of SCA-SAT as described in claim 1, wherein In step 2, the adder input selection constraint is expressed as: Wherein, Denote the sum of the weights W selected in step s, where these sums are generated in step i k and Denotes the sum of the elements in the s-th row of the Sel matrix, Indicates the weight W of step i k No carry is generated Denote the sum of step i weights W k has not been generated; Constraint (1) allows at most one adder per step by restricting the sum of Sel row to be 0, 2, or 3, and Sel row denotes the sum of the s-th row of the Sel matrix; Constraint (2) restricts the selection of candidate inputs in one step by enforcing a unit column sum in Sel; Constraint (3) excludes the selection of the ungenerated i-th sum / carry as an adder input; The state constraint is expressed as: In the formula, Represents the weight \(W\) of step \(i\) k The carry of which is used as an input by other adders Denote the weight \(W\) of step \(i\). k The sum is used as input by other adders; Constraint (4) sets the corresponding generation flag when creating an adder; Constraint (5) marks any sum / carry as consumed if selected as input. The FSA constraint is expressed as: Use a Boolean vector variable F of length H k to monitor the remaining partial products. Then, constraint (6) limits F k to at most the remaining two partial products to provide the required FSA input; constraint (7) prohibits including the already consumed partial products, sums, and carries in F k ; The unsolved pin constraints: For a given weight W k , there are P unsolved pins, and a Boolean matrix U of size P×H is established k to indicate the connected partial products, and the Boolean implication constraint is used to model the partial products retained in the fanout of the unsolved pins as zeros in the U k entries; Use an intermediate layout with dimensions N×H Use a parity matrix to trace sums that have a path leading to an illegal partial product, and if such a path exists, generate an implication constraint; finally, ensure that each row sum of U k is one to ensure the connection of each unresolved pin and constrain the selected partial products to illegal candidates fed into the FSA.

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