Circuit arrangement

Abstract

The present invention relates to a circuit arrangement comprising an application network (10), a first current source (20), a second current source (25), a differential readout circuit (30), and a signal-processing unit (40), wherein: the first current source (20) is designed to impress, via a first connector (11), a first predefined signal (S1) into a first impedance of the application network (10), the first impedance being coupled to the first connector (11); the second current source (25) is designed to impress, via a second connector (12), a second predefined signal (S2) into a second impedance of the application network (10), the second impedance being coupled to the second connector (12); the first current source (20) and the second current source (25) are designed to impress the first signal (S1) and the second signal (S2) into the first impedance and second impedance simultaneously or with a temporal offset; the differential readout circuit (30) is designed to generate a difference signal (SD) on the basis of the voltage applied to the first connector (11) and a voltage applied to the second connector (12); and wherein the signal-processing unit (40) is designed to ascertain, on the basis of the difference signal (SD), a deviation of the circuit arrangement from the target state.

Description

[0001] Description

[0002] title

[0003] Circuit arrangement

[0004] State of the art

[0005] The present invention relates to a circuit arrangement and in particular to a circuit arrangement for determining deviations of the circuit arrangement from a desired state on the basis of a differential readout circuit.

[0006] Differential readout circuits are known from the prior art which check impedances at terminals of an electrical circuit on the basis of a current signal in order to, for example, detect defective connections in a signal transmission path.

[0007] DE000004308280A1 discloses a method for monitoring an electrical connection between a potentiometer and an evaluation electronics, wherein a rectangular alternating voltage is coupled to a wiper line of the potentiometer, as well as a circuit arrangement for carrying out the method.

[0008] Disclosure of the invention

[0009] The circuit arrangement according to the invention comprises an application network, a first current source, a second current source, a differential readout circuit and a signal processing unit.

[0010] The application network, which can in principle be designed in any desired way, is configured to provide an application signal (e.g. a measurement signal of a sensor, in particular a DC signal or a slowly changing signal such as a temperature measurement signal) via a first connection and a second connection.

[0011] The first current source is configured to inject a first predefined signal (i.e., a first current signal) via the first terminal into a first impedance of the application network coupled to the first terminal, while the second current source is configured to inject a second predefined signal (i.e., a second current signal) via the second terminal into a second impedance of the application network coupled to the second terminal. A duration and a fundamental frequency of the first signal and the second signal are each defined identically.

[0012] The first current source and the second current source are configured to impress the first signal and the second signal simultaneously into the first impedance and the second impedance, so that the signal waveforms of the first signal and the second signal are identical or differ by a scaling factor only in their amplitudes.

[0013] Alternatively, the first current source and the second current source are configured to impress the first signal and the second signal into the first impedance and second impedance with a time offset, wherein the second signal is in the middle of two consecutive first signals and wherein a predefined dead time is maintained between the respective first signals and second signals.

[0014] It should be noted that, depending on the application, it may be advantageous to use the first and second signals generated simultaneously or with offsets. It is also conceivable to use the simultaneously generated signals and the offset signals alternately.

[0015] The application signal of the application network lies in a frequency range which, in a desired state of the circuit arrangement (ie, in a fault-free state), is disjoint to a frequency range in which the first signal and the second signal lie.

[0016] Furthermore, the differential readout circuit is configured to generate a differential signal based on a voltage applied to the first terminal and a voltage applied to the second terminal. The differential signal can, for example, be subjected to amplification and / or A / D conversion in order to advantageously perform downstream signal processing based on digital signals, without thereby being limited to digital signal processing.

[0017] The signal processing unit is configured to determine, based on the difference signal, a deviation of the circuit arrangement from the desired state (i.e., a fault-free or deviation-free state). In this case, various deviations are advantageously considered, which are explained in more detail below in the course of the description of advantageous embodiments of the present invention.

[0018] The signal processing unit and / or other components of the circuit arrangement according to the invention are configured, for example, as an ASIC, FPGA, processor, digital signal processor, microcontroller, or similar. Furthermore, it is possible for the signal processing unit and / or other components of the circuit arrangement to be configured together as a single (e.g., integrated) unit and / or at least partially as separate units.

[0019] The first and second signals designed according to the invention, in conjunction with the differential readout circuit, offer the particular advantage that application signals of the application network are not impaired in a fault-free state of the circuit arrangement, that non-critical deviations within the circuit arrangement that could influence the application signal can be compensated for, and that different error states can be identified. Therefore, based on the circuit arrangement according to the invention, particularly reliable operation of the circuit arrangement and / or particularly targeted error handling are possible.

[0020] The subclaims show preferred developments of the invention.

[0021] Further preferably, the application signal of the application network is essentially a DC voltage signal and / or a signal provided by a sensor, and in particular a low-frequency signal. Such a signal can, for example, be a voltage measurement signal and / or a temperature measurement signal and / or a signal deviating therefrom.

[0022] Particularly preferably, the first signal and the second signal are each a square wave signal, without thereby entailing any restriction to such a signal shape. Design as a square wave signal is advantageous because, among other things, this signal shape can be implemented particularly simply and cost-effectively. In the case in which the first signal and the second signal are signals generated at different times, they preferably have identical or essentially identical areas under their respective signal waveforms, wherein respective waveforms of the first signal and the second signal or respective signal shapes of the two signals can differ from one another. Further preferably, the first signal and the second signal each have a duty cycle which corresponds to a value of less than 100%.Particularly preferably, the first signal and the second signal each have a duty cycle of 50% when the signals are generated simultaneously. When the first signal and the second signal are generated with a time delay, they each preferably have a duty cycle of 25%.

[0023] In an advantageous embodiment of the present invention, the signal processing unit is configured to generate a first output signal by filtering the difference signal using a first filter (e.g., a low-pass filter and / or a band-pass filter), the passband of which is adapted to the frequency range of the application signal. In a case in which there is no error or deviation in the circuit arrangement, this signal accordingly corresponds to the application signal, which, in the deviation-free state, can be fed directly for further processing, for example, to downstream processing within and / or outside the circuit arrangement according to the invention. In addition, the signal processing unit is configured to generate a second output signal by filtering the difference signal using a second filter (e.g.,by means of a bandpass filter and / or by means of a high-pass filter) whose passband is adapted to a frequency range of the first signal and the second signal. Particularly advantageously, the second filter is designed as a bandpass filter whose center frequency corresponds to the fundamental frequency of the first signal and the second signal. In the case in which the first signal and the second signal are each generated simultaneously, the signal processing unit is preferably configured to identify, on the basis of a magnitude and / or a polarity of the first output signal and / or the second output signal, an error state of the circuit arrangement and / or a cause of the error state and / or a deviation state of the circuit arrangement in which there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal and the second signal.

[0024] Based on the levels and / or polarities of the first output signal and / or the second output signal, error and / or deviation states described in the following table can be determined, whereby the supply voltage stated therein is a voltage for supplying the

[0025] application network.

[0026] The table also shows that, based on the simultaneously generated first and second signals, a short circuit between the first terminal and the second terminal cannot be clearly determined, since the first output signal and the second output signal in this case do not have any voltage, as in the fault-free case.

[0027] In the case where the first signal and the second signal are each generated simultaneously, the circuit arrangement is further preferably configured to alternately impress the first signal into the first impedance and the second impedance, and to alternately impress the second signal into the other impedance. In this case, the circuit arrangement is further advantageously configured to distinguish, based on information about the alternating impression of the signals into the respective impedances and based on the second output signal, whether the deviation state is caused by a deviation between the impedances or between the signals.

[0028] In the case where the first signal and the second signal are each generated simultaneously, the circuit arrangement is further preferably configured to at least partially correct the deviation state by adjusting an amplitude of the first signal and / or the second signal. This adjustment is preferably carried out on the basis of feedback of the second output signal to the first current source and / or to the second current source in order to compensate for the deviation state by adjusting the first signal and / or the second signal. Alternatively or additionally, the circuit arrangement is further preferably configured to at least partially correct the deviation state by determining, on the basis of the second signal, information about the extent to which the application signal is influenced by the first signal and / or the second signal, and using this information to correct the first output signal.By correcting the first output signal, the first output signal after the correction corresponds to the unadulterated application signal.

[0029] In a further advantageous embodiment of the present invention, in the case of the first signals and second signals generated at different times, the signal processing unit is configured to generate a third output signal by filtering the difference signal using a third filter whose passband is adapted to a frequency corresponding to twice the fundamental frequency of the first signal and the second signal. The signal processing unit is further configured to identify, based on a level of the second output signal and on the basis of a level and / or a polarity of the third output signal, an error state of the circuit arrangement and / or a cause of the error state and / or a deviation state of the circuit arrangement in which a deviation between the first impedance and the second impedance and / or a deviation between the first signal and the second signal exists.A duty cycle of the first signal and the second signal preferably corresponds to 25% each, without thereby imposing a restriction on such a duty cycle.

[0030] In the case where the first signal and the second signal are each generated with a time offset, the first current source and the second current source are preferably the same current source, and the first signal and the second signal are preferably the same signal. Furthermore, the circuit arrangement is configured to alternately impress the signal generated by the current source as a first signal into the first impedance and as a second signal into the second impedance. This avoids the deviation state in which the first signals and the second signals may have different amplitudes due to the use of separate current sources.

[0031] Based on the magnitudes and / or polarities of the second output signal and the third output signal, the error and / or deviation states described in the table below can be determined. The supply voltage is a voltage used to power the application network. Furthermore, the following table is based on the use of a single current source configured to generate the first signal and apply it alternately to the first impedance and the second impedance.

[0032] In the case in which the first signal and the second signal are each generated with a time offset, the signal processing unit is particularly advantageously configured to detect a short circuit between the first terminal and the second terminal when the second output signal and the third output signal each have an amplitude, i.e. a voltage of zero. Alternatively or additionally, the circuit arrangement is configured to at least partially correct the deviation state by determining, on the basis of the third output signal, information about a level of influence on the application signal by the first signal and the second signal and using the information about the level of influence to correct the first output signal. In the corrected state, the corrected first output signal corresponds accordingly to the uncorrected application signal.

[0033] Short description of the drawings

[0034] Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing:

[0035] Figure 1 shows an exemplary embodiment of an inventive

[0036] circuit arrangement;

[0037] Figure 2 shows exemplary signal curves of simultaneously generated first signals and second signals; and

[0038] Figure 3 exemplary signal curves of the first

[0039] signals and second signals.

[0040] Embodiments of the invention

[0041] Figure 1 shows an exemplary embodiment of a circuit arrangement according to the invention, which comprises an application network 10, a first current source 20, a second current source 25, a differential

[0042] Readout circuit 30 and a signal processing unit 40, wherein the application network here is a component of a temperature sensor which is configured to generate an application signal SA which represents temperature measurement values ​​of the temperature sensor.

[0043] The application network 10 is configured to provide the application signal SA to a receiver via a first terminal 11 and via a second terminal 12, wherein the receiver here is, for example, an ASIC, which may include at least some of the components described below.

[0044] The first current source 20 of the circuit arrangement is configured to impress a first predefined signal S1 via the first terminal 11 into a first impedance of the application network 10 coupled to the first terminal 11. The second current source 25 is configured to impress a second predefined signal S2 via the second terminal 12 into a second impedance of the application network 10 coupled to the second terminal 12, wherein a duration and a fundamental frequency of the first signal S1 and the second signal S2 are each identical.

[0045] The first current source 20 and the second current source 25 are configured to simultaneously impress the first signal S1 and the second signal S2 into the first impedance and the second impedance, so that the signal waveforms of the first signal S1 and the second signal S2 are identical or differ by a scaling factor only in their amplitudes

[0046] The first current source 20 and the second current source 25 are also configured to impress the first signal S1 and the second signal S2 alternatively in a time-shifted manner into the first impedance and the second impedance, wherein the second signal S2 is in the middle of two successive first signals S1 and wherein a predefined dead time T is provided between the respective first signals

[0047] 51 and second signals S2 are maintained.

[0048] Both the simultaneously generated first signals S1 and second signals S2 and the temporally offset generated first signals S1 and second signals S2 each have a rectangular shape, whereby the simultaneously generated signals S1,

[0049] 52 each have a duty cycle of 50% and the time-shifted signals each have a duty cycle of 25%.

[0050] Furthermore, the application signal SA of the application network 10 lies in a frequency range which, in a desired state of the circuit arrangement, is disjoint from a frequency range in which the first signal S1 and the second signal S2 lie. The differential readout circuit 30 has an amplifier 80 for amplifying a difference signal SD and an A / D converter 90 for digitizing the amplified difference signal SD, wherein the difference signal SD is generated from a voltage applied to the first terminal 11 and from a voltage applied to the second terminal 12.

[0051] The signal processing unit 40 is configured to generate a first output signal SO1 by filtering the difference signal SD by means of a first filter 50, which is designed as a low-pass filter and which has a passband adapted to the frequency range of the application signal SA.

[0052] The signal processing unit 40 is further configured to generate a second output signal SO2 by filtering the difference signal SD by means of a second filter 60, which is designed as a bandpass filter and has a center frequency corresponding to the fundamental frequency of the first signal S1 and the second signal S2.

[0053] The signal processing unit 40 is also configured to generate a third output signal SO3 by filtering the difference signal SD by means of a third filter 70, which is also designed as a bandpass filter and which has a center frequency corresponding to a frequency that is twice as high as the fundamental frequency of the first signal S1 and the second signal S2.

[0054] Based on an evaluation logic 45, which receives the output signals SO1, SO2, SO3, the signal processing unit 40 is configured to determine deviations of the circuit arrangement from a desired state, wherein the deviations can represent impedance and / or signal deviations and / or error states. Deviations determined according to the invention can be used in a deviation compensation unit 110 of the evaluation logic 40 to correct an influence of a deviation state on the first output signal SO1, so that the application signal SA can be recovered based on the corrected output signal SO1, which can be output for the application signal SA following a downstream processing chain (not shown). The evaluation logic 45 is further configured to determine a specific cause for a deviation and / or an error and to output information in this regard as an error signal SF.

[0055] The circuit arrangement according to the invention is further configured to feed the second output signal SO2 back to the first current source 20 and / or the second current source 25 via a feedback controller 100 in order to compensate, on the basis of the feedback, a deviation between the first signal S1 and the second signal S2 and / or a deviation between the first impedance and the second impedance by means of a control.

[0056] Figure 2 shows exemplary signal curves of simultaneously generated first signals S1 and second signals S2, which are each designed as rectangular signals and each have a duty cycle of 50%, which results from the dead time T.

[0057] In addition, Figure 2 shows the difference signal SD generated according to the invention, which is subjected to an unwanted influence by the first signals S1 and / or the second signals S2 due to an error event 120.

[0058] Figure 3 shows exemplary signal curves of first signals S1 and second signals S2 generated at different times, which are each designed as square-wave signals and each have a duty cycle of 25% and a dead time T between the first signals S1 and the second signals S2.

[0059] In addition, Figure 3 shows the difference signal SD generated according to the invention, which is subjected to an unwanted influence by the first signals S1 and / or the second signals S2 due to an error event 120.

Claims

Claims 1 . Circuit arrangement comprising - an application network (10), - a first power source (20), - a second power source (25), - a differential readout circuit (30), and - a signal processing unit (40), wherein - the application network (10) is configured to provide an application signal (SA) via a first connection (11) and a second connection (12), - the first current source (20) is configured to impress a first predefined signal (S1) via the first terminal (11) into a first impedance of the application network (10) coupled to the first terminal (11), - the second current source (25) is configured to impress a second predefined signal (S2) via the second terminal (12) into a second impedance of the application network (10) coupled to the second terminal (12), - a duration and a fundamental frequency of the first signal (S1) and the second signal (S2) are identical, - the first current source (20) and the second current source (25) are arranged to transmit the first signal (S1) and the second signal (S2) - simultaneously into the first impedance and the second impedance, so that the signal waveforms of the first signal (S1) and the second signal (S2) are identical or differ only in their amplitudes by a scaling factor, or - to be impressed into the first impedance and the second impedance with a time offset, whereby the second signal (S2) is in the middle of two successive first signals (S1) and wherein a predefined dead time (T) is maintained between the respective first signals (S1) and second signals (S2), - the application signal (SA) of the application network (10) lies in a frequency range which, in a desired state of the circuit arrangement, is disjoint to a frequency range in which the first signal (S1) and the second signal (S2) lie, and - the differential readout circuit (30) is arranged on the basis of - to generate a differential signal (SD) between a voltage applied to the first terminal (11) and a voltage applied to the second terminal (12), and - the signal processing unit (40) is configured to determine a deviation of the circuit arrangement from the desired state on the basis of the difference signal (SD).

2. Circuit arrangement according to one of the preceding claims, wherein the application signal (SA) of the application network (10) - essentially a DC signal, and / or - a signal provided by a sensor, in particular a low-frequency signal 3. Circuit arrangement according to one of the preceding claims, wherein the first signal (S1) and the second signal (S2) - are each a square wave signal, and / or - in the case where they are signals (S1, S2) generated at different times, have identical or substantially identical areas under their respective signal waveforms, and / or - each have a duty cycle corresponding to a value of less than 100%.

4. Circuit arrangement according to one of the preceding claims, wherein the signal processing unit (40) is arranged - to generate a first output signal (SO1) by filtering the difference signal (SD) by means of a first filter (50) whose passband is adapted to the frequency range of the application signal (SA), and - to generate a second output signal (SO2) by filtering the difference signal (SD) by means of a second filter (60), whose passband is adapted to the frequency range of the first signal (S1) and the second signal (S2) 5. Circuit arrangement according to claim 4, wherein the signal processing unit (40) is configured, in the case of the simultaneously generated first signals (S1) and second signals (S2), on the basis of a level and / or a polarity of the first output signal (SO1) and / or the second output signal (SO2) - a fault condition of the circuit arrangement, and / or - a cause of the error condition, and / or - to identify a deviation state of the circuit arrangement in which there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal (S1) and the second signal (S2).

6. Circuit arrangement according to claim 5, wherein the circuit arrangement is arranged - impressing the first signal (S1) alternately into the first impedance and the second impedance and impressing the second signal (S2) alternately into the other impedance, and - to distinguish, on the basis of information about the alternating impression of the signals (S1, S2) into the respective impedances and on the basis of the second output signal (SO2), whether the deviation state is caused by a deviation between the impedances or between the signals (S1, S2).

7. Circuit arrangement according to one of claims 4 to 6, wherein the circuit arrangement is arranged to correct the deviation state at least partially by - an amplitude of the first signal (S1) and / or the second signal (S2) is adjusted, and / or - on the basis of the second signal (S2), information about a level of influence of the application signal (SA) by the first signal (S1) and / or by the second signal (S2) is determined and the information is used to correct the first output signal (SO1).

8. Circuit arrangement according to claim 4, wherein the signal processing unit (40) is arranged in the case of the first signals (S1) and second signals (S2) generated at different times, - to generate a third output signal (SO3) by filtering the difference signal (SD) by means of a third filter (70) whose passband is adapted to a frequency corresponding to twice the fundamental frequency of the first signal (S1) and the second signal (S2), and - based on a level of the second output signal (SO2) and based on a level and / or a polarity of the third output signal (SO3), to identify a fault condition of the circuit arrangement, and / or a cause of the fault condition, and / or a deviation condition of the circuit arrangement in which there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal and the second signal.

9. Circuit arrangement according to claim 8, wherein - the first current source (20) and the second current source (25) are the same current source (20) and the first signal (S1) and the second signal (S2) are the same signal (S1), and - the circuit arrangement is arranged to impress the signal (S1) generated by the current source (20) alternately as a first signal (S1) into the first impedance and as a second signal (S2) into the second impedance.

10. Circuit arrangement according to claim 8 or 9, wherein - the signal processing unit (40) is configured to detect a short circuit between the first terminal (11) and the second terminal (12) when the second output signal (SO2) and the third output signal (SO3) each have an amplitude of zero, and / or - the circuit arrangement is designed to correct the deviation state at least partially by providing, on the basis of the third output signal (SO3), information about the extent to which the application signal (SA) is influenced by the first signal (S1) and the second signal (S2) is determined and the information about the level of influence is used to correct the first output signal (SO1).

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