Central processing unit

Abstract

Provided is a central processing unit in which the processing speed is increased by reducing the number of cycles. A CPU (1) is provided with: an arithmetic circuit (4) that executes an operation specified by an instruction code; and a data memory (5) that can store data to be input to the arithmetic circuit (4) and data resulting from an operation by the arithmetic circuit (4). The CPU (1) has, as an executable instruction, a first instruction for executing an operation on a designated address in an address space including the data memory (5) and a designated address in the address space, and storing the result at a designated address in the address space. Furthermore, the arithmetic circuit (4) receives data directly from the data memory (5) without passing through another storage element, and outputs the operation result directly to the data memory (5) without passing through another storage element.

Description

central processing unit

[0001] The present invention relates to a central processing unit.

[0002] In a conventional central processing unit (also called a microcomputer or microprocessor), data input from the outside is temporarily stored in an I / O port, then transferred to a general-purpose register, and then written from the general-purpose register to a data memory. Data to be output to the outside is transferred from the data memory to a general-purpose register, and then stored from the general-purpose register to the I / O port.

[0003] In this way, in conventional central processing units, data is read from and written to an I / O port via a general-purpose register, which increases the number of execution cycles required for data transfer.

[0004] To address the above problem, for example, Patent Document 1 describes a method of reducing the number of cycles required to read from or write to an I / O port by mapping the I / O port to a designated general-purpose register or flag register.

[0005] JP 2007-58330 A

[0006] However, the invention described in Patent Document 1 switches whether to replace an I / O port with a general-purpose register or a flag register. For example, if the number of I / O ports to be switched increases, the number of registers that cannot be used as normal general-purpose registers or flag registers also increases. Furthermore, the amount of circuitry required for switching also increases. Furthermore, the number of program steps, such as setting the I / O map register, also increases.

[0007] Furthermore, the invention described in Patent Document 1 only reduces the number of cycles required to read from or write to an I / O port. However, even in the case of a normal arithmetic instruction, for example, data must be transferred from a data memory to a general-purpose register, and there is room for reducing the number of cycles required to execute the arithmetic instruction.

[0008] SUMMARY OF THE INVENTION The present invention has been made in view of the above background, and has as its object to provide a central processing unit that reduces the number of cycles and increases the processing speed.

[0009] The invention described in claim 1, which has been made to solve the above-mentioned problems, is a central processing unit that executes an instruction code read from an instruction memory, and is equipped with an arithmetic unit that executes an operation specified by the instruction code, and a data memory that can store data that is input to the arithmetic unit and data that is the operation result of the arithmetic unit, and has as an executable instruction a first instruction that calculates a specified address in an address space that includes the data memory and a specified address in the address space and stores the result at the specified address in the address space, and when the arithmetic unit executes the first instruction, data is input directly from the data memory without going through other memory elements, and the operation result is output directly to the data memory without going through other memory elements.

[0010] As described above, according to the present invention, the arithmetic unit has a first instruction, and is configured to receive data directly from the data memory without passing through other storage elements, and to write the operation result directly to the data memory without passing through other storage elements. Therefore, data can be read directly from the data memory without passing through a general-purpose register or the like, and the operation result can be written directly to the data memory. This reduces the number of cycles required for instruction execution, thereby increasing processing speed.

[0011] Fig. 1 is a block diagram showing a CPU according to one embodiment of the present invention. Fig. 2 is a circuit diagram of a memory cell of a static RAM configured as the data memory shown in Fig. 1. Fig. 3 is a circuit diagram showing the overall structure of the static RAM shown in Fig. 2. Fig. 4 is an explanatory diagram showing an example of mapping of address spaces of the data memory and I / O ports shown in Fig. 1. Fig. 5 is an explanatory diagram of the operation of the CPU shown in Fig. 1 when an arithmetic instruction is executed. Fig. 6 is an explanatory diagram of the operation of the CPU shown in Fig. 1 when a data transfer instruction is executed in the data memory shown in Fig. 1.

[0012] A central processing unit (also referred to as a microcomputer or a microprocessor) according to one embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows the configuration of a central processing unit (hereinafter referred to as CPU) 1. Specific hardware for the CPU 1 is assumed to be a single chip on a semiconductor substrate, such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0013] The CPU 1 includes an instruction memory 2 , a control circuit 3 , an arithmetic circuit 4 , a data memory 5 , and an I / O port 6 .

[0014] The instruction memory 2 is a 16-bit data memory having an address space from address 0000H (hexadecimal) to address 7FFFH, for example. The instruction memory 2 stores program data consisting of a plurality of instruction codes to be executed by the CPU 1.

[0015] The control circuit 3 reads instruction codes from the instruction memory 2 and causes the arithmetic circuit 4, data memory 5, and I / O port 6 to perform operations according to the instructions that make up the program. The control circuit 3 includes a program counter (PC) 3a and an instruction register (IR) 3b.

[0016] PC 3a is a register that indicates (indicates) the address of an instruction to be read from instruction memory 2. PC 3a stores an increment value or a predetermined address value based on the result of calculation within control circuit 3. PC 3a is configured with, for example, 16 bits.

[0017] IR3b is a register that stores the instruction code stored at the address indicated by PC3a. The instruction code stored in IR3b is output to the instruction decoder in the control circuit 3. The instruction decoder then decodes the instruction code and outputs the address calculation and control signals as the decoding results to the arithmetic circuit 4, data memory 5, and I / O port 6.

[0018] The arithmetic circuit 4 includes an arithmetic logic unit (ALU), an input register, a flag register, etc., and performs various arithmetic operations and logical operations based on control signals output from the instruction decoder. The arithmetic circuit 4 may also include a multiplier, a divider, etc. in addition to the ALU. That is, the arithmetic circuit 4 functions as an arithmetic unit that executes an operation specified by an instruction code.

[0019] The data memory 5 is a 32-bit data memory having an address space from address 0000H to address 7FFFH, for example (this is a different address space from the instruction memory 2). The results of calculations performed by the arithmetic circuit 4 and data stored in the I / O port 6 are written to the data memory 5 via a data bus or the like based on addresses calculated by the control circuit 3. The stored data is also read out based on addresses calculated by the control circuit 3. The read data is output to the arithmetic circuit 4 and the I / O port 6 via a data bus or the like. In other words, the data memory 5 can store data that is input to the arithmetic circuit 4 (arithmetic unit) and data that is the calculation result of the arithmetic circuit 4 (arithmetic unit).

[0020] The data memory 5 is configured as a well-known static RAM (Random Access Memory) that has word lines and bit lines and activates the word lines and bit lines at a predetermined timing based on an address to read and write data from and to memory cells.

[0021] 2 and 3 show examples of circuit configurations of static RAM configured as data memory 5. FIG. 2 shows a well-known static RAM memory cell (hereinafter referred to as an SRAM cell) configured with six transistors. In the circuit shown in FIG. 2, access transistors N3 and N4 are controlled to be switched ON / OFF in accordance with the voltage level of the first word line WL. Data (stored data) is held by a latch configured with two CMOS (Complementary Metal Oxide Semiconductor) inverters.

[0022] Figure 3 shows the overall structure of a known SRAM in which the SRAM cells shown in Figure 2 are arranged two-dimensionally. In the circuit shown in Figure 3, any SRAM cell is accessed via a first word line WL and a pair of first bit lines BL0 and BL1. For a read operation, the first word line WL is activated in response to a row address signal RA. This turns on access transistors N3 and N4 provided in all SRAM cells connected to the same first word line WL.

[0023] That is, the storage node pair (nodes on the drain terminal side of N3 and N4 in FIG. 2) is connected to the first bit line pair BL0, BL1 (nodes on the source terminal side of N3 and N4) charged to the power supply voltage VDD, and the storage data is output to the first bit line pair BL0, BL1. Next, the first bit line pair BL0, BL1 is selected and output by the bit line pair selector SEL according to the column address signal CA. The signal output from the bit line pair selector SEL is then input to the sense amplifier SA. The potential difference of the signals input to the sense amplifier SA is amplified and output as a read signal. The row address signal RA and column address signal CA are signals generated based on the address input to the static RAM.

[0024] The I / O port 6 inputs and outputs data to and from the outside (for example, an external device 10). The I / O port 6 includes a register for holding data input from the outside and a register for holding data to be output to the outside.

[0025] The external device 10 is a device that inputs and outputs data to and from the CPU 1. Examples of the external device include other semiconductor integrated circuits and external memories.

[0026] Next, the operation of the CPU 1 configured as described above will be described with reference to FIGS. 4 to 6. First, in this embodiment, all storage elements (data memory 5, I / O port 6) that store data necessary for the operation of the CPU 1 are concentrated in an address space that includes the data memory 5. The instruction memory 2 is not included in this address space. For example, as shown in FIG. 4, not only the data memory but also the I / O port 6 is assigned to the address space of the data memory 5 (the shaded area is the I / O port 6). In other words, specifying the address space that includes the data memory 5 may also specify the I / O port 6. In other words, the I / O port 6 is mapped to an address that is consecutive to the data memory 5 in the address space.

[0027] Then, as instructions executable by CPU 1, an instruction to transfer data at a designated address in data memory 5 to a designated address in data memory 5 and an instruction to perform an operation on a designated address in data memory 5 and a designated address in data memory 5 and store the result at a designated address in data memory 5 are added. Although these two instructions are described as data memory 5, they actually indicate addresses in the address space described above. Therefore, the former instruction is an executable instruction that is a second instruction to transfer data at a designated address in the address space containing data memory 5 to a designated address in the address space, and the latter instruction is a first instruction that performs an operation on a designated address in the address space containing data memory 5 and a designated address in the address space and stores the result at a designated address in the address space.

[0028] By adding the above two instructions, it becomes possible, for example, to transfer data at address "0003H" in data memory 5 to address "7FFDH" in I / O port 6. It is also possible to add data at address "0003H" and address "0005H" in data memory 5 and store the result at address "7FFDH" in I / O port 6.

[0029] Although the above-mentioned data transfers and the like have been possible in the past, they required the use of general-purpose registers, resulting in a large number of execution cycles. In the configuration of this embodiment, the general-purpose registers are eliminated, and the I / O port 6 is mapped to the address space of the data memory 5. Furthermore, the first instruction and the second instruction can be used. Therefore, it is possible to transfer data between data memories and write operation results directly to the I / O port 6 without using the general-purpose registers, thereby reducing the number of execution cycles.

[0030] The above will be explained in detail. Figure 5 is an explanatory diagram showing the operation when an arithmetic instruction is executed. That is, Figure 5 shows an example of the operation when the first instruction is executed. Note that Figure 5 only shows the main parts necessary for the explanation.

[0031] The example in FIG. 5 is an example in which the data at address "0003H" and the data at address "0005H" in the data memory 5 are operated on, and the result is stored at "7FFDH" in the I / O port 6.

[0032] This involves reading the instruction code corresponding to the address specified by PC3a into IR3b, and based on the data specified in the instruction code, reading data from a specified address (0003H, 0005H) within the address space to which data memory 5 and I / O port 6 are mapped, and supplying it to ALU4C (arithmetic unit), and control circuit 3 functions as a control unit.

[0033] First, data at address "0003H" in data memory 5 is transferred to input register 4A of arithmetic circuit 4 (FIG. 5(1)). Next, data at address "0005H" in data memory 5 is transferred to input register 4B of arithmetic circuit 4 (FIG. 5(2)). Next, the ALU of arithmetic circuit 4 is started to perform an operation (FIG. 5(3)). Then, the operation result data is transferred to address "7FFDH" in I / O port 6 (FIG. 5(4)).

[0034] In a conventional CPU with a general-purpose register, the above (1) and (2) require the execution of an instruction to transfer data from the data memory 5 to the general-purpose register. Also, the above (4) requires the execution of an instruction to temporarily transfer the operation result data to the general-purpose register. In this embodiment, the above transfer to the general-purpose register is not required.

[0035] That is, when the first instruction is executed, data is input directly from the data memory 5 to the arithmetic circuit 4 (operator) without going through other storage elements such as general-purpose registers, and the arithmetic result is output directly to the data memory 5 without going through other storage elements such as general-purpose registers.

[0036] Next, the operation when a data transfer instruction is executed in the data memory 5 will be described with reference to Fig. 6. That is, Fig. 6 shows an example of the operation when the second instruction is executed.

[0037] 6, the data at memory address "7FFDH" (I / O port 6) is stored at address "0003H" in data memory 5. In other words, the transfer is completed with one instruction.

[0038] In the case of a conventional CPU having a general-purpose register, it was necessary to execute an instruction to transfer data from the I / O port 6 to the general-purpose register. In this embodiment, however, the transfer to the general-purpose register as described above is not necessary.

[0039] That is, data is input to the I / O port 6 directly from the data memory 5 without passing through other storage elements such as general-purpose registers, and data is output directly to the data memory 5 without passing through other storage elements such as general-purpose registers.

[0040] According to this embodiment, the CPU 1 includes an arithmetic circuit 4 that executes an operation specified by an instruction code, and a data memory 5 that can store data that is input to the arithmetic circuit 4 and data that is the operation result of the arithmetic circuit 4. The CPU 1 has, as an executable instruction, a first instruction that performs an operation on a designated address in an address space that includes the data memory 5 and a designated address in the address space, and stores the result at the designated address in the address space. The arithmetic circuit 4 receives data directly from the data memory 5 without passing through other storage elements, and outputs the operation result directly to the data memory 5 without passing through other storage elements.

[0041] By configuring the CPU 1 as described above, it is possible to read data directly from the data memory 5 without going through a general-purpose register, etc., perform calculations, and write the calculation results directly to the data memory, thereby reducing the number of cycles required for instruction execution and increasing processing speed.

[0042] The microcomputer also includes an I / O port 6 for inputting and outputting data to and from the outside, and the I / O port 6 is mapped to an address space continuous with the data memory 5. The executable instructions include a second instruction for transferring data at a specified address in the address space to a specified address in the address space. The I / O port 6 is configured to receive data directly from the data memory 5 without passing through other storage elements, and to write the data directly to the data memory without passing through other storage elements. This configuration eliminates the need for general-purpose registers when inputting and outputting data to the I / O port 6. This further reduces the number of cycles required for instruction execution, thereby enabling faster processing speeds.

[0043] The microcomputer also includes a control circuit 3 that reads data from a predetermined address in the address space based on the address specified in the instruction code and supplies the data to the arithmetic circuit 4. In this way, the first instruction and the second instruction can reduce the number of instruction execution cycles, thereby contributing to faster processing speed.

[0044] The data memory is configured as a static RAM having word lines and bit lines, which are activated at a predetermined timing based on an address to read and write data from and to memory cells. This allows the storage of data within the CPU 1 to be consolidated into a highly integrated, large-capacity storage device. This eliminates the need for general-purpose registers configured with conventional D-type flip-flops.

[0045] The present invention is not limited to the above-described embodiment. In other words, a person skilled in the art can implement various modifications in accordance with conventional knowledge without departing from the gist of the present invention. As long as such modifications still include the configuration of the central processing unit of the present invention, they are of course included in the scope of the present invention.

[0046] 1 CPU (Central Processing Unit) 2 Instruction Memory 3 Control Circuit (Control Unit) 4 Arithmetic Circuit (Calculator) 5 Data Memory (Static RAM) 6 I / O Port

Claims

1. A central processing unit that executes an instruction code read from an instruction memory, comprising: - An arithmetic unit that executes the operation specified by the instruction code; - A data memory capable of storing data that is an input to the arithmetic unit and data that is an operation result of the arithmetic unit; - It has a first instruction that calculates the specified address in the address space including the data memory as an executable instruction and the specified address in the address space, and stores the result in the specified address in the address space. - When the first instruction is executed, the arithmetic unit directly receives data from the data memory without passing through other storage elements, and directly outputs the operation result to the data memory without passing through other storage elements. - A central processing unit characterized by the above.

2. It comprises an I / O port for inputting and outputting data to and from the outside. - The I / O port is mapped to an address continuous with the data memory in the address space. - Further, it has a second instruction that transfers the data at the specified address in the address space to the specified address in the address space as an executable instruction. - The I / O port directly receives data from the data memory without passing through other storage elements and directly outputs data to the data memory without passing through other storage elements. - The central processing unit according to claim 1, characterized by the above.

3. The central processing unit according to claim 1 or 2, characterized by comprising a control unit that reads data from a predetermined address in the address space based on the data specified by the instruction code and supplies it to the arithmetic unit.

4. The data memory has word lines and bit lines, and is composed of a static RAM that activates the word lines and the bit lines at a predetermined timing based on the address to perform reading and writing to the memory cells. - The central processing unit according to claim 3, characterized by the above.

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