Method for manufacturing group iii nitride power semiconductor device, and group iii nitride power semiconductor device manufactured according thereto

Abstract

The present invention relates to a method for manufacturing a group III nitride power semiconductor device, and a group III nitride power semiconductor device manufactured according thereto, and, more specifically, to: a method for manufacturing a group III nitride power semiconductor device in which a GaN buffer layer in a conventional power semiconductor device structure is removed and an AlN intermediate layer having high resistance and high heat dissipation performance is provided; and a group III nitride power semiconductor device manufactured according thereto.

Description

Method for manufacturing a group III nitride power semiconductor device and a group III nitride power semiconductor device manufactured thereby

[0001] The present invention relates to a method for manufacturing a group III nitride power semiconductor device and a group III nitride power semiconductor device manufactured thereby, and more particularly, to a method for manufacturing a group III nitride power semiconductor device in which a GaN buffer layer is removed from the structure of a conventional power semiconductor device and an AlN intermediate layer having high resistance and high heat dissipation performance is provided, and a group III nitride power semiconductor device manufactured thereby.

[0002] In a GaN material-based power semiconductor (HEMT, high electron mobility transistor) device with a horizontal channel structure based on a technology that directly grows GaN material on top of a conventional Si single crystal growth substrate wafer, a design that suppresses the leakage current of the power semiconductor device through a high-quality epitaxial thin film growth technology with high breakdown voltage and high reliability characteristics is essential in order for the device to be operated stably at high temperatures with high voltage and / or high-speed switching functions.

[0003] To this end, the conventional group III nitride semiconductor thin film material and its power semiconductor devices have a structure in which 1) a Si single crystal growth substrate wafer having electrically high resistance characteristics, 2) a melt-back etching prevention layer grown including an AlN material system (nitride or nitride oxide containing an Al composition) to suppress the melt-back etching phenomenon through reaction at high temperatures with the surface layer of the Si single crystal growth substrate wafer, 3) a crack prevention condensation stress layer grown including an AlGaN material system (group III nitride containing an Al or Ga composition), and 4) a power semiconductor active layer grown including a GaN material system (group III nitride containing a Ga composition) are sequentially laminated.

[0004] And the power semiconductor active layer (HEMT, high electron mobility transistor) of the horizontal channel structure including the above-described GaN material system is typically formed by stacking four regions: 1) GaN buffer layer, 2) GaN channel layer (horizontal transistor), 3) AlGaN barrier layer, and 4) capping passivation layer (depletion mode) or p-type nitride semiconductor layer (enhancement mode).

[0005] That is, in the group III nitride power semiconductor HEMT device structure in which a GaN material system is grown directly on top of a conventional Si single crystal growth substrate wafer, a high-resistance Si single crystal growth substrate wafer must be applied along with the formation of a high-resistance GaN buffer layer under the GaN channel layer, but there are the following problems.

[0006] First, in the conventional group III nitride (GaN material-based) power semiconductor HEMT device structure, a process is performed to directly grow a GaN material-based single crystal thin film and a power semiconductor device structure on top of a Si single crystal wafer for group III nitride power semiconductor growth substrate using MOCVD (metal organic chemical vapor deposition) equipment. At this time, a high temperature of around 1000°C and a reducing atmosphere (H2, H + , NH3, radical ions) is basically performed in a single crystal thin film growth (film formation) process of GaN material system containing Ga atoms, and a melt-back etching prevention film area is absolutely necessary to block the active occurrence of Si-Ga metallic eutectic reaction with relatively small energy between the Si single crystal wafer surface layer and Ga atoms.

[0007] This melt-back etching prevention film region typically has a thickness of about 100 nm, and is typically formed by an AlN material layer grown in-situ within a MOCVD chamber. However, in addition, an AlN or AlNO material layer can be formed ex-situ on top of a Si single crystal wafer for group III nitride power semiconductor growth substrates before loading into the MOCVD chamber using other external deposition process equipment (sputter, PLD, ALD).

[0008] However, when forming a melt-back etching prevention film region with the above-described AlN material layer on top of a Si single crystal wafer for a growth substrate having electrically high resistance characteristics, although the level of damage to the surface of the Si growth substrate during the AlN growth is less, there is still a problem that a Si-Al metallic process reaction occurs all over the surface or locally on the Si growth substrate surface to form a conductive interface material layer, which causes a deterioration in the crystal quality of the GaN material system grown in the continuous process. In addition, there is a problem that the crystal quality deteriorates (crystallinity decreases) due to the formation of a conductive interface material (disordered SiAlN) due to damage to the surface of the Si growth substrate, and as a result, the leakage current increases due to an increase in the density of “dislocations,” which are major crystal defects, which ultimately promotes the insulation breakdown phenomenon.

[0009] Second, in the conventional group III nitride (GaN material-based) power semiconductor HEMT device structure described above, when growing (or forming) a material, the process must be carried out by considering the lattice constant (LC) and coefficient of thermal expansion (CTE), which are material-specific values ​​between different heterogeneous materials. However, when the difference in the lattice constant (LC) and coefficient of thermal expansion (CTE) between the two materials is large, micro or macro cracks inevitably occur or the crystal quality deteriorates in the grown (formed) material thin film due to structural and thermo-mechanical stress during or after the growth (formation) process. In particular, when a GaN material or an AlN material is directly grown (or formed) on top of a Si single crystal wafer for a group III nitride power semiconductor growth substrate, a strong tensile stress is generated in terms of the coefficient of thermal expansion (CTE) and / or lattice constant (LC), so that cracking can be easily observed, and a high breakdown voltage and high reliability device can be realized by growing to a predetermined thickness or more, but the thickness of the group III nitride power semiconductor device structure cannot be increased due to the tensile stress.

[0010] Although various technologies have been devised as a means of relieving the tensile stress or suppressing cracks as described above, a crack prevention condensation stress layer is introduced and used by introducing a material and process that artificially generates compressive stress so as to compensate for and buffer the tensile stress, by laminating an AlGaN material system including an Al or Ga composition in a known multilayer structure on the melt-back etching prevention film area as described above to suppress the crack phenomenon.

[0011] However, the crack prevention condensation stress layer of the conventional group III nitride (GaN material system) power semiconductor HEMT device structure described above has the problem that it is difficult to grow a thick layer with high quality when forming an AlGaN material system with a high Al ratio, and dislocations are generated due to a decrease in crystal quality, which promotes an increase in leakage current.

[0012] Thirdly, in the conventional group III nitride (GaN material) power semiconductor HEMT device structure, a GaN buffer layer is typically formed by heavily doping with impurities such as Fe or C to have high resistance in order to suppress leakage current under the GaN channel layer.

[0013] However, according to the conventional group III nitride (GaN material) power semiconductor HEMT device structure, there is a problem that the crystal quality of the GaN material is greatly degraded due to excessive doping of impurities such as Fe or C, and fatal crystal defects, i.e., an increase in dislocation density, promotes an increase in leakage current. In addition, there is a problem that the GaN channel layer and AlGaN barrier layer grown on top of the GaN buffer layer with low crystal quality also have low crystal quality due to the low crystal quality.

[0014] Accordingly, in order to improve crystal quality, the GaN on Sapphire method, which has the next best crystal quality after the power semiconductor devices manufactured using the GaN on GaN method, is widely used, and the epitaxial film deposition technology for this method has already been developed and matured. However, the only drawback of the GaN on Sapphire method is that the heat dissipation ability of sapphire is poor, which limits its application to high-power products.

[0015] To overcome this, high-output products have been developed using SiC and Si growth substrates with high heat dissipation, but they are inferior to epitaxy grown on sapphire growth substrates in terms of performance, crystal quality, defects, and cost.

[0016] Meanwhile, the GaN buffer layer of the power semiconductor active layer with a horizontal channel structure is a material layer grown with the same material as the channel layer to create a high-quality crystalline GaN channel layer, and has a significant impact on the crystal quality of the GaN channel layer. This GaN buffer layer is required to have low-density crystal defects and high resistivity to prevent leakage current. However, if the buffer layer is artificially doped with C (carbon) or Fe (iron) to achieve high resistivity, the trade-off result is that the crystallinity of the corresponding layer is lowered.

[0017] The purpose of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a group III nitride power semiconductor device in which a GaN buffer layer is removed from the structure of a conventional power semiconductor device and an AlN intermediate layer having high resistance and high heat dissipation performance is provided, and a group III nitride power semiconductor device manufactured thereby.

[0018] The above object is achieved by a method for manufacturing a group III nitride power semiconductor device, according to the present invention, comprising: a growth step of sequentially growing a sacrificial layer, an AlN intermediate layer, and a device active layer on a growth substrate; a bonding step of bonding the device active layer to a temporary substrate through an adhesive layer; a first removal step of removing the growth substrate; an etching step of etching and removing the sacrificial layer to expose the AlN intermediate layer; a bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; a second removal step of removing the temporary substrate; and a surface preparation step of removing the adhesive layer to expose the device active layer.

[0019] Additionally, the above-described device active layer may include a channel layer and a barrier layer.

[0020] In addition, the growth step may include a first step of growing a sacrificial layer and an etching layer on the growth substrate and then forming an etching mask layer with a regular or irregular pattern on the etching layer, a second step of etching the etching layer along the pattern of the etching mask layer, a third step of forming a growth promotion layer on the etched etching layer, and a fourth step of growing the AlN intermediate layer through the etching layer on which the growth promotion layer is formed.

[0021] In addition, the etching step forms a regular or irregular pattern on the surface of the exposed AlN intermediate layer, and then forms a surface planarization layer on the surface of the AlN intermediate layer on which the pattern is formed, and the bonding step can bond the surface planarization layer to the support substrate through the bonding layer.

[0022] In addition, the bonding step can bond the AlN intermediate layer to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

[0023] In addition, the bonding step can form a positive or negative pattern at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

[0024] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the support substrate or the second bonding layer.

[0025] In addition, each of the first bonding layer and the second bonding layer may include a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the support substrate, a flattening layer for alleviating roughness of the surface of the AlN intermediate layer or the support substrate, and a bonding layer for bonding the AlN intermediate layer and the support substrate to each other.

[0026] The above object is achieved by a method for manufacturing a group III nitride power semiconductor device, according to the present invention, comprising: a growth step of sequentially growing a buffer layer and a device active layer on a growth substrate; a bonding step of bonding the device active layer to a temporary substrate through an adhesive layer; a first removal step of removing the growth substrate; an etching step of etching and removing the buffer layer to expose the device active layer; a deposition step of depositing an AlN intermediate layer on the exposed device active layer; a bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; a second removal step of removing the temporary substrate; and a surface preparation step of removing the adhesive layer to expose the device active layer.

[0027] Additionally, the above-described device active layer may include a channel layer and a barrier layer.

[0028] In addition, the etching step may form a regular or irregular pattern on the surface of the exposed active layer of the device, and then form a surface planarization layer on the surface of the active layer of the device on which the pattern is formed, and the film formation step may form an AlN intermediate layer on the surface of the surface planarization layer.

[0029] In addition, the bonding step can bond the AlN intermediate layer to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

[0030] In addition, the bonding step can form a positive or negative pattern at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

[0031] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the support substrate or the second bonding layer.

[0032] In addition, each of the first bonding layer and the second bonding layer may include a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the support substrate, a flattening layer for alleviating roughness of the surface of the AlN intermediate layer or the support substrate, and a bonding layer for bonding the AlN intermediate layer and the support substrate to each other.

[0033] The above object is achieved by a method for manufacturing a group III nitride power semiconductor device, according to the present invention, comprising: a growth step of sequentially growing a buffer layer, an etch-stop layer, and a device active layer on a growth substrate; a bonding step of bonding the device active layer to a temporary substrate through an adhesive layer; a first removal step of removing the growth substrate; an etching step of etching the buffer layer to reduce its thickness; a deposition step of depositing an AlN intermediate layer on the buffer layer, the thickness of which has been reduced; a bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; a second removal step of removing the temporary substrate; and a surface preparation step of removing the adhesive layer to expose the device active layer.

[0034] Additionally, the above-described device active layer may include a channel layer and a barrier layer.

[0035] In addition, the etching step may form a regular or irregular pattern on the surface of the buffer layer with a reduced thickness, and then form a surface planarization layer on the surface of the buffer layer on which the pattern is formed, and the film formation step may form an AlN intermediate layer on the surface of the surface planarization layer.

[0036] In addition, the bonding step can bond the AlN intermediate layer to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

[0037] In addition, the bonding step can form a positive or negative pattern at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

[0038] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the support substrate or the second bonding layer.

[0039] In addition, each of the first bonding layer and the second bonding layer may include a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the support substrate, a flattening layer for alleviating roughness of the surface of the AlN intermediate layer or the support substrate, and a bonding layer for bonding the AlN intermediate layer and the support substrate to each other.

[0040] The above object is achieved by a group III nitride power semiconductor device manufactured by a method for manufacturing a group III nitride power semiconductor device according to the present invention.

[0041] According to the present invention, a GaN buffer layer with reduced crystallinity due to intentional or unintentional doping can be replaced with an AlN intermediate layer having high resistance and high heat dissipation, so that the performance of power semiconductor devices such as HEMTs can be significantly improved.

[0042] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0043] Figure 1 is a flowchart of a method for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention.

[0044] FIG. 2 illustrates a process of manufacturing a group III nitride power semiconductor device according to a method for manufacturing a group III nitride power semiconductor device according to a first embodiment of the present invention.

[0045] FIG. 3 illustrates a group III nitride semiconductor template used as a growth substrate in a method for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention.

[0046] Figure 4 illustrates a detailed process of the growth step of a method for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention.

[0047] FIG. 5 and FIG. 6 illustrate the process of forming a surface planarization layer in the etching step of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0048] FIGS. 7 to 9 illustrate the formation of a positive or negative pattern on at least one of the AlN intermediate layer or the first bonding layer in a method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0049] FIGS. 10 to 12 illustrate the formation of a positive or negative pattern on at least one of a support substrate or a second bonding layer in a method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0050] FIG. 13 illustrates that the patterns formed in the first bonding layer of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention are formed at different depths.

[0051] FIG. 14 illustrates an example of a positive or negative pattern shape of a method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0052] FIG. 15 illustrates in detail the first bonding layer and the second bonding layer of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0053] FIG. 16 is a flowchart of a method for manufacturing a group III nitride power semiconductor device according to a second embodiment of the present invention.

[0054] FIG. 17 illustrates a process of manufacturing a group III nitride power semiconductor device according to a method for manufacturing a group III nitride power semiconductor device according to a second embodiment of the present invention.

[0055] Figure 18 is a flowchart of a method for manufacturing a group 3 nitride power semiconductor device according to a third embodiment of the present invention.

[0056] FIGS. 19 to 20 illustrate a process of manufacturing a group III nitride power semiconductor device according to a method for manufacturing a group III nitride power semiconductor device according to a third embodiment of the present invention.

[0057] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0058] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0059] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0060]

[0061] From now on, with reference to the attached drawings, a method (S100) for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention will be described in detail.

[0062] FIG. 1 is a flowchart of a method (S100) for manufacturing a group III nitride power semiconductor device according to a first embodiment of the present invention, and FIG. 2 illustrates a process for manufacturing a group III nitride power semiconductor device according to a method (S100) for manufacturing a group III nitride power semiconductor device according to a first embodiment of the present invention.

[0063] As illustrated in FIGS. 1 and 2, a method (S100) for manufacturing a group III nitride power semiconductor device according to a first embodiment of the present invention includes a growth step (S110), an adhesion step (S120), a first removal step (S130), an etching step (S140), a bonding step (S150), a second removal step (S160), and a surface preparation step (S170).

[0064] The growth stage (S110) is a stage in which a sacrificial layer (N), an AlN intermediate layer (140), and an active layer (150) are sequentially grown epitaxially on the initial growth substrate (G) through MOCVD (metal organic chemical vapor deposition).

[0065] The first growth substrate (G) is removed through the laser lift off (LLO) technique in the first removal step (S130) described below. In this case, it is preferable that the first growth substrate (G) be an optically transparent substrate that can transmit a laser beam (single wavelength light) 100% (theoretically) without absorption and has high temperature resistance. For example, it can be formed of a material such as sapphire (α-phase Al2O3), ScMgAlO4, 4H-SiC, or 6H-SiC, which is polished on both sides. In addition, it is also preferable that the first growth substrate (G) be a patterned sapphire substrate (PSS) that has a protrusion shape that is regularly or irregularly patterned in various dimensions (sizes and shapes) in the microscale or nanoscale on one side in order to minimize crystal defects inside the group III-nitride semiconductor thin film grown thereon.

[0066] Meanwhile, in the present invention, a group III nitride semiconductor template (G1) can be used as the first growth substrate (G).

[0067] FIG. 3 illustrates a group III nitride semiconductor template (G1) used as a growth substrate (G) in a method (S100) for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention.

[0068] As illustrated in FIG. 3, the group III nitride semiconductor template (G1) in the present invention means that a template seed layer (G13) formed of a thin group III nitride is bonded to a template support substrate (G11) formed of optically transparent sapphire via a template bonding layer (G12), and a regular or irregular pattern may be formed on the template seed layer (G13) to improve the quality of a semiconductor layer grown thereon. This group III nitride semiconductor template (G1) can be manufactured by growing a template seed layer (G13) on a sapphire growth substrate, bonding the template seed layer (G13) and a temporary substrate via an adhesive layer (A), removing the sapphire growth substrate, bonding the template seed layer (G13) and the template support substrate (G11) via the template bonding layer (G12), and then removing the temporary substrate.

[0069] The sacrificial layer (N) is a layer that is sacrificed and separated to easily separate the initial growth substrate (G) using a laser beam in the laser lift-off (LLO) technique, and can be grown on the initial growth substrate (G) using a material such as GaN or InGaN.

[0070] The AlN interlayer (140) is grown as a single crystal or quasi-single crystal so that the power semiconductor device has high resistance and high heat dissipation performance. It is grown with AlN or AlON material, etc., and is grown to have a thickness of several to several thousand nm. In the present embodiment, the AlN interlayer (140) is epitaxially grown on a sacrificial layer (N) through CVD (chemical vapor deposition).

[0071] Meanwhile, the above-described AlN intermediate layer (140) is required to be grown as a single crystal thick film of the highest possible quality, but there is a technical difficulty in growing a high-quality AlN intermediate layer (140) on a GaN sacrificial layer (N). Accordingly, in the growth step (S110) of the present invention, the sacrificial layer (N) and the AlN intermediate layer (140) can be sequentially grown through the first step, the second step, the third step, and the fourth step.

[0072] FIG. 4 illustrates a detailed process of a growth step (S110) of a method (S100) for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention.

[0073] As shown in Fig. 4, the first step is to grow a sacrificial layer (N) and an etching layer (E) on an initial growth substrate (G), and then form an etching mask layer (M) with a regular or irregular pattern on the etching layer (E). Here, the etching mask layer (M) is SiN. x It can be formed as a back, and the etching mask layer (M) is formed in the c-plane (0001) region of the etching layer (E) where there is no crystal defect (dislocation).

[0074] The second step is a step of etching the etching layer (E) to a preset depth along the pattern of the etching mask layer (M). In the second step, the etching layer (E) is decomposed and etched to a preset depth through a heat treatment process in a reducing atmosphere.

[0075] The third step is a step of forming a growth promotion layer (U) to promote the growth of the AlN intermediate layer (140) on the etched layer (E) etched along the pattern of the etching mask layer (M). AlN has problems of a slow growth rate and poor crystal quality compared to GaN due to pre-reaction and parasitic growth. Accordingly, in the third step of the present invention, by depositing a growth promotion layer (U) formed of AlN or AlON on the etched layer (E), the growth rate and quality of the AlN intermediate layer (140) grown on the upper portion can be improved, and the growth temperature can be lowered.

[0076] The fourth step is a step of growing an AlN intermediate layer (140) through an etched layer (E) on which a growth promoting layer (U) is formed. That is, in the fourth step, the AlN intermediate layer (140) is grown through primary AlN growth reinforced in the vertical direction and secondary AlN growth reinforced in the horizontal direction by a pattern etched to a preset depth in the etched layer (E). Accordingly, a number of voids that relieve stress inside the thin film are created, thereby significantly improving the quality of the AlN intermediate layer (140), and making it possible to grow the AlN intermediate layer (140) thicker.

[0077] The device active layer (150) is grown on an AlN intermediate layer (140), and includes a channel layer (151) formed of GaN or the like for a power semiconductor device structure such as a HEMT, and a barrier layer (152) formed of AlGaN or the like. Here, the channel layer (151) is formed of a relatively high-quality GaN material with minimized crystal defects such as dislocations, and is formed to have a thickness of 100-500 nm.

[0078] The bonding step (S120) is a step of bonding the device active layer (150) to the intermediate temporary substrate (T) through the bonding layer (A).

[0079] Here, the intermediate temporary substrate (T) is formed of a material having a coefficient of thermal expansion (CTE) equal to or similar to that of the initial growth substrate (G), and is not limited as long as the difference in the coefficient of thermal expansion with that of the initial growth substrate (G) is 2 ppm or less, but is preferably formed of sapphire, which is the same material as the initial growth substrate (G).

[0080] Conventionally, warpage of an epitaxial wafer occurs due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and the group III nitride semiconductor. However, in the present invention, this can be resolved by strongly bonding an intermediate temporary substrate (T) to one surface of the device active layer (150) through an adhesive layer (A). That is, in the case of an epitaxial wafer to which an intermediate temporary substrate (T) is bonded, the wafer bow can be minimized to almost zero (0) in a stress-relieved state, so there is an advantage that it can be applied to wafer sizes of 4 inches, 6 inches, 8 inches, and even 12 inches or more.

[0081] In more detail, in the bonding step (S120), an epitaxy protection layer and a first adhesive layer (A1) are sequentially laminated and formed on one surface of the device active layer (150) (barrier layer (152)), a bonding reinforcement layer, a separation layer, and a second adhesive layer (A2) are sequentially laminated and formed on an intermediate temporary substrate (T), and then the first adhesive layer (A1) and the second adhesive layer (A2) are temporarily pressed against each other to form an adhesive layer (A). That is, in the bonding step (S120), the intermediate temporary substrate (T) on which the second adhesive layer (A2) is formed is turned over to separate the initial growth substrate (G), and the first adhesive layer (A1) is bonded to the initial growth substrate (G) by applying pressure at a temperature of less than 300°C. Here, the epitaxy protection layer can be formed of a material for protecting the device active layer (150), the separation layer can be formed of a material that melts through a thermal-chemical reaction using a laser lift-off technique, and the adhesive layer (A) can be formed of a material that can be bonded under low temperature and pressure.

[0082] The first removal step (S130) is a step of exposing the sacrificial layer (N) by removing the initial growth substrate (G) using the laser lift-off technique (LLO).

[0083] In more detail, in the first removal step (S130), a laser beam is irradiated on the back of the sapphire initial growth substrate (G) so that the laser light is absorbed by the sacrificial layer (N), thereby separating the initial growth substrate (G) from the sacrificial layer (N) by utilizing the phenomenon of melting through material decomposition due to a chemical reaction at high temperature of the sacrificial layer (N).

[0084] The etching step (S140) is a step of exposing the AlN intermediate layer (140) by etching and removing the sacrificial layer (N) through dry etching or wet etching.

[0085] Meanwhile, the surface of the exposed AlN intermediate layer (140) has a nitrogen polar surface (n-polar surface), and the surface of this AlN intermediate layer (140) inevitably has a locally damaged area, and various surface crystal defects are inevitably generated during the growth of the AlN intermediate layer (140). These crystal defects and damaged surfaces cause great difficulties and quality issues in the final support substrate (110) bonding described later, and therefore, it is essential to perform a surface planarization process through a ceramic material deposition and / or a CMP (chemical-mechanical polishing) process to improve this.

[0086] FIG. 5 and FIG. 6 illustrate the process of forming a surface planarization layer (130) in the etching step (S140) of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0087] As illustrated in FIGS. 5 and 7, the etching step (S140) may form a regular or irregular pattern on the surface of the exposed AlN intermediate layer (140), and then form a surface planarization layer (130) on the surface of the AlN intermediate layer (140) on which the pattern is formed. Here, the surface planarization layer (130) may have a multilayer structure, and may be planarized with a SiO2 material or the like by depositing an AlN or AlON material on the surface of the AlN intermediate layer (140) through PVD (physical vapor deposition) such as sputtering, or may be planarized with an AlN or AlON material by depositing an SiO2 material or the like on the surface of the AlN intermediate layer (140) through PVD such as sputtering. For planarization, the SOG (spin on glass) method can be used, and after planarization, the thickness of the surface planarization layer (130) is controlled through CMP (chemical-mechanical polishing). At this time, depending on the degree of CMP, only the surface planarization layer (130) may be exposed, or the surface planarization layer (130) and the AlN intermediate layer (140) may be exposed together.

[0088] The bonding step (S150) is a step of bonding the AlN intermediate layer (140) to the final support substrate (110) through a bonding layer (120) that has electrical conductivity or non-conductivity and high heat resistance.

[0089] Here, the final support substrate (110) is a substrate that supports the AlN intermediate layer (140) and the device active layer (150) on top of the AlN intermediate layer (140) after going through each step of the method for manufacturing a group III nitride power semiconductor device according to the first embodiment of the present invention (S100). It may be formed of a high-cost polycrystalline ceramic material such as AlNcera, SiNcera, SiCcera, or a single-crystal material such as Si, SiC, or sapphire, but is not limited thereto, and may be freely selected according to the purpose and requirements.

[0090] Conventionally, warpage of an epitaxial wafer occurs due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and the group III nitride semiconductor. However, in the present invention, this can be resolved by strongly bonding the final support substrate (110) to the AlN intermediate layer (140) through the bonding layer (120). That is, in the case of an epitaxial wafer to which the final support substrate (110) is bonded, the wafer bow can be minimized to almost zero (0) in a stress-relieved state, so there is an advantage that it can be applied to wafer sizes of 4 inches, 6 inches, 8 inches, and even 12 inches or more.

[0091] Meanwhile, in the bonding step (S150), when a surface planarization layer (130) is formed on the surface of the AlN intermediate layer (140) on which the pattern is formed, the surface planarization layer (130) can be bonded to the support substrate (110) through the bonding layer (120). According to this surface planarization layer (130), the surface can be hardened, so that the bonding strength with the support substrate (110) can be significantly improved.

[0092] Meanwhile, in the bonding step (S150) of the present invention, a first bonding layer (B1) is formed on one surface of the AlN intermediate layer (140), a second bonding layer (B2) is formed on one surface of the support substrate (110), and then the first bonding layer (B1) and the second bonding layer (B2) are bonded to each other, thereby bonding the AlN intermediate layer (140) to the support substrate (110). Furthermore, in the bonding step (S150), a reinforcing layer and a first bonding layer (B1) are sequentially laminated and formed on one surface of the AlN intermediate layer (140), and then the reinforcing layer and the second bonding layer (B2) are sequentially laminated and formed on the final support substrate (110), and then the first bonding layer (B1) and the second bonding layer (B2) are bonded to each other, thereby forming a bonding layer (120).

[0093] Here, the reinforcement layer is a layer for reinforcing the bonding strength with the final support substrate (110) and inducing condensation stress, and the reinforcement layer may include, in more detail, a bonding reinforcement layer and a condensation stress layer.

[0094] The bonding reinforcement layer is a layer introduced to strengthen the bonding strength when the AlN intermediate layer (140) is bonded to the final support substrate (110) through the bonding layer (120), and is formed on the AlN intermediate layer (140) or the final support substrate (110), and the material constituting the bonding reinforcement layer is SiO2, SiN. x It is desirable to select first among the following.

[0095] The condensation stress layer is formed on the bonding reinforcement layer as a layer that causes condensation stress, and the first bonding layer (B1) or the second bonding layer (B2) is formed on the condensation stress layer. The condensation stress layer is formed of a dielectric material having a larger value than the thermal expansion coefficient of the final support substrate (110), such as AlN (4.6 ppm), AlNO (4.6-6.8 ppm), Al2O 3( It is composed of materials that relieve tensile stress, i.e. induce condensation stress, such as SiC (6.8ppm), SiCN (3.8-4.8ppm), GaN (5.6ppm), and GaNO (5.6-6.8ppm), which play a role in improving product quality through stress control.

[0096] In the present invention, the above-described bonding reinforcement layer or condensation stress layer may be omitted in some cases, and in some cases, the entire reinforcement layer may be omitted so that one surface of the AlN intermediate layer (140) and the bonding layer (120) are in direct contact, or the final support substrate (110) and the bonding layer (120) are in direct contact. In such cases, the bonding layer (120) may be formed by depositing a material having a larger coefficient of thermal expansion than that of the final support substrate (110), thereby inducing a condensation stress along with the bonding function.

[0097] Meanwhile, a positive or negative pattern may be formed on the bonding layer (120) of the present invention.

[0098] FIGS. 7 to 9 illustrate the formation of a positive or negative pattern on at least one of the AlN intermediate layer (140) or the first bonding layer (B1) in the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention, and FIGS. 10 to 12 illustrate the formation of a positive or negative pattern on at least one of the support substrate (110) or the second bonding layer (B2) in the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention, and FIG. 13 illustrates the formation of patterns at different depths on the first bonding layer (B1) in the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention, and FIG. 14 illustrates examples of positive or negative pattern shapes in the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0099] Direct wafer bonding requires strict wafer surface roughness, and there is a problem of weakened bonding strength in the event of wafer warpage. Furthermore, there is also the problem of weakened bonding strength or quality issues occurring in subsequent processes due to gas generated within the bonding layer (120) during the wafer bonding process.

[0100] Accordingly, in the present invention, a positive or negative pattern is formed by etching the bonding layer (120), and in some cases, the pattern is also formed on the AlN intermediate layer (140) or the final support substrate (110). By using such a pattern, issues arising from wafer surface roughness and wafer warpage can be resolved, and the bonding strength of the bonding layer (120) can be strengthened by facilitating the discharge of gas generated within the bonding layer (120) to prevent voids from being generated within the bonding layer (120) (void-free). Furthermore, the thermal ductility stress acting on the wafer can be significantly alleviated by the patterns formed on the bonding layer (120).

[0101] More specifically, in the bonding step (S150) of the present invention, the above-described positive or negative pattern can be formed on the bonding layer (120), the AlN intermediate layer (140), or the final support substrate (110) in various ways, and the bonding step (S150) can form the positive or negative pattern on at least one of the AlN intermediate layer (140) or the first bonding layer (B1) at a preset depth. For example, as illustrated in FIG. 7, a positive or negative pattern can be formed only on the first bonding layer (B1), and as illustrated in FIG. 8, a positive or negative pattern can be formed only on the AlN intermediate layer (140), and then the first bonding layer (B1) can be formed along the pattern so that the patterns of the AlN intermediate layer (140) and the first bonding layer (B1) alternate with each other, and as illustrated in FIG. 9, patterns can be formed on each of the AlN intermediate layer (140) and the first bonding layer (B1), but the patterns can be formed so that they are connected to each other.

[0102] In addition, the bonding step (S150) can form a relief or engraved pattern at a preset depth on at least one of the final support substrate (110) or the second bonding layer (B2). For example, as illustrated in FIG. 10, a relief or engraved pattern can be formed only on the second bonding layer (B2), and as illustrated in FIG. 11, a relief or engraved pattern can be formed only on the final support substrate (110), and then the second bonding layer (B2) can be formed along the pattern, so that the patterns of the final support substrate (110) and the second bonding layer (B2) can be formed to alternate with each other, and as illustrated in FIG. 12, patterns can be formed on each of the final support substrate (110) and the second bonding layer (B2), but so that the patterns are connected to each other.

[0103] At this time, as illustrated in FIG. 13, the formed positive or negative pattern may be etched to penetrate the entire first bonding layer (B1) (or the second bonding layer (B2)) or may be etched to penetrate only a portion of the first bonding layer (B1) (or the second bonding layer (B2)), and as illustrated in FIG. 14, the shape of the formed pattern may have, for example, a positive or negative hexagonal, circular, or square shape, but is not limited thereto.

[0104] In addition, as the pattern size becomes smaller, the formation of voids can be easily prevented, but since the bonding surface is reduced accordingly, an issue of reduced bonding strength may occur. Therefore, it is desirable to set the size of the pattern so that the bonding area is secured to be more than half of the total area, and this can be optimized according to the bonding strength of the bonding material. Furthermore, the height of the pattern is preferably set to have a step of 10 nm or more so that the gas generated during bonding can be released, and the thickness can be optimized to vary depending on wafer bowing, surface roughness, bonding material, etc.

[0105] Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) of the present invention may include a bonding reinforcing layer (R), a flattening layer (F), and a bonding layer (J).

[0106] FIG. 15 illustrates in detail the first bonding layer (B1) and the second bonding layer (B2) of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0107] As shown in Fig. 15, the bonding reinforcing layer (R) is for reinforcing the bonding with the AlN intermediate layer (140) or the final support substrate (110), and this bonding reinforcing layer (R) is, for example, SiO x , SiN x , may contain Cr, Ti, Mo or HMDS.

[0108] The flattening layer (F) is intended to alleviate the roughness of the surface of the AlN intermediate layer (140) or the final support substrate (110), and this flattening layer (F) may include, for example, a flowable oxide (FOx) such as spin on glass (SOG) or hydrogen silsesquioxane (HSQ) to improve the surface roughness.

[0109] The bonding layer (J) is for bonding the first bonding layer (B1) and the second bonding layer (B2) to each other to bond the AlN intermediate layer (140) and the final support substrate (110), and can be prepared as a permanent bonding material, for example, SiO 2( 0.8ppm), SiN x(3.7ppm), SiCN(3.8-4.8ppm), AlN(4.5ppm), Al2O3(6.8ppm), amorphous Si, and further, FOx (Flowable Oxides) such as SOG (Spin On Glass, liquid SiO2), HSQ (Hydrogen Silsesquioxane) can be included to improve surface roughness. Furthermore, the bonding layer (J) can be formed of a metal such as Al, W, or Mo, or an alloy thereof.

[0110] The above-described bonding reinforcement layer (R) and flattening layer (F) can be introduced or deleted depending on the process, and when the bonding reinforcement layer (R) and flattening layer (F) are deleted depending on the process, the bonding layer (J) can be directly deposited on the AlN intermediate layer (140) or the final support substrate (110).

[0111] The second removal step (S160) is a step of exposing the adhesive layer (A) by removing the intermediate temporary substrate (T) using the laser lift-off (LLO) technique. When the intermediate temporary substrate (T) is separated, the interior of the AlN intermediate layer (140) and the device active layer (150) transferred to the final support substrate (110) are in a state where stress is completely relieved and remain flat together with the final support substrate (110).

[0112] The surface preparation step (S170) is a step of exposing the device active layer (150) by etching and removing the separation layer, the adhesive layer (A), and the epitaxy protection layer. Here, the separation layer, the adhesive layer (A), and the epitaxy protection layer can be formed through dry etching or wet etching, and it is desirable to completely remove damaged areas, contaminated surface residues, and low-quality single crystal thin film areas due to separation of the intermediate temporary substrate (T). Afterwards, a power semiconductor device chip such as a HEMT is completed through etching and formation of electrodes (source, gate, drain).

[0113] Meanwhile, a group III nitride power semiconductor device manufactured according to the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention ultimately has a structure in which a support substrate (110), a bonding layer (120), a surface planarization layer (130), an AlN intermediate layer (140), and a device active layer (150) are laminated.

[0114]

[0115] From now on, with reference to the attached drawings, a method (S200) for manufacturing a group III nitride power semiconductor device according to the second embodiment of the present invention will be described in detail.

[0116] FIG. 16 is a flowchart of a method (S200) for manufacturing a group III nitride power semiconductor device according to a second embodiment of the present invention, and FIG. 17 illustrates a process for manufacturing a group III nitride power semiconductor device according to a method (S200) for manufacturing a group III nitride power semiconductor device according to a second embodiment of the present invention.

[0117] As illustrated in FIGS. 16 and 17, a method (S200) for manufacturing a group III nitride power semiconductor device according to a second embodiment of the present invention includes a growth step (S210), an adhesion step (S220), a first removal step (S230), an etching step (S240), a film formation step (S250), a bonding step (S260), a second removal step (S270), and a surface preparation step (S280).

[0118] The growth stage (S210) is a stage in which a buffer layer (160) and an active layer of the device (150) are sequentially grown epitaxially on the initial growth substrate (G) through MOCVD (metal organic chemical vapor deposition).

[0119] The first growth substrate (G) is removed through the laser lift off (LLO) technique in the first removal step (S230) described below. In this case, it is preferable that the first growth substrate (G) be an optically transparent substrate that can transmit a laser beam (single wavelength light) 100% (theoretically) without absorption and has high temperature resistance. For example, it can be formed of a material such as sapphire (α-phase Al2O3), ScMgAlO4, 4H-SiC, or 6H-SiC, which is polished on both sides. In addition, it is also preferable that the first growth substrate (G) be a patterned sapphire substrate (PSS) that has a protrusion shape that is regularly or irregularly patterned in various dimensions (sizes and shapes) in the microscale or nanoscale on one side in order to minimize crystal defects inside the group III-nitride semiconductor thin film grown thereon.

[0120] Meanwhile, in the present invention, a group III nitride semiconductor template (G1) can be used as the first growth substrate (G), which is the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, and therefore, a duplicate description is omitted.

[0121] The buffer layer (160) is formed of a relatively low-quality GaN material, and may contain alloy materials such as Al, In, and Sc, and intentionally or unintentionally impurities (C, Fe, Si, etc.), and further may be provided with a number of air voids to relieve stress.

[0122] The device active layer (150) is grown on an AlN intermediate layer (140) and includes a GaN channel layer (151) and an AlGaN barrier layer (152) for a power semiconductor device structure such as a HEMT. Here, the GaN channel layer (151) is formed of a relatively high-quality GaN material with minimized crystal defects such as dislocations, and is formed to have a thickness of 100-500 nm.

[0123] The bonding step (S220) and the first removal step (S230) are the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0124] The etching step (S240) is a step of exposing the device active layer (150) by etching and removing the buffer layer (160) through dry etching or wet etching.

[0125] Meanwhile, the surface of the exposed device active layer (150) has a nitrogen polar surface (n-polar surface), and the surface of this device active layer (150) inevitably has a locally damaged area, and various surface crystal defects are inevitably generated during the growth of the device active layer (150). These crystal defects and damaged surfaces cause difficulties and quality issues during the deposition of the AlN intermediate layer (140) described later, and therefore, it is essential to perform a surface planarization process through a ceramic material deposition and / or a CMP (chemical-mechanical polishing) process to improve this.

[0126] FIG. 5 and FIG. 6 illustrate the process of forming a surface planarization layer (130) in the etching step (S240) of the method for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0127] As illustrated in FIGS. 5 and 7, the etching step (S240) may form a regular or irregular pattern on the surface of the exposed device active layer (150), and then form a surface planarization layer (130) on the surface of the device active layer (150) on which the pattern is formed. Here, the surface planarization layer (130) may have a multilayer structure, and may be formed by depositing an AlN or AlON material on the surface of the device active layer (150) through PVD (physical vapor deposition) such as sputtering and then planarizing with a SiO2 material, or by depositing an SiO2 material on the surface of the device active layer (150) through PVD such as sputtering and then planarizing with an AlN or AlON material. For planarization, the SOG (spin on glass) method can be used, and after planarization, the thickness of the surface planarization layer (130) is controlled through CMP (chemical-mechanical polishing). At this time, depending on the degree of CMP, only the surface planarization layer (130) may be exposed, or the surface planarization layer (130) and the device active layer (150) may be exposed together.

[0128] In addition to PVD such as sputtering described above, AlN, SiN at low temperatures below 500℃ x The same process is also possible through an ALD (atomic level deposition) device that can form SiO2, etc.

[0129] The film formation step (S250) is a step of forming an AlN intermediate layer (140) on the exposed element active layer (150). At this time, if a surface planarization layer (130) is formed in the etching step (S240), the film formation step (S250) can form an AlN intermediate layer (140) on the surface planarization layer (130).

[0130] The AlN interlayer (140) is formed as a single crystal or quasi-single crystal (polycrystalline is also possible) so that the power semiconductor element has high resistance and high heat dissipation performance. It is grown using AlN or AlON material, etc., and is formed to have a thickness of several to several thousand nm. In this embodiment, the AlN intermediate layer (140) can be formed on the device active layer (150) or the surface planarization layer (130) through PVD (physical vapor deposition) such as sputtering, PLD, IAD, and evaporator, or CVD (chemical vapor deposition) such as ALD. In the PVD process, AlON can be formed by including a small amount of oxygen (O) to improve crystallinity, and in the CVD process, in order to solve the large roughness of the GaN surface with nitrogen polarity (n-polarity) and to form AlN with group 3 polarity, a metal layer such as Al, Cr, or Ti having a thickness of several nm can be inserted as a polarity conversion layer.

[0131] The bonding step (S260), the second removal step (S270), and the surface preparation step (S280) are the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, and therefore, a duplicate description is omitted.

[0132] Meanwhile, the group III nitride power semiconductor device manufactured according to the method for manufacturing a group III nitride power semiconductor device (S200) according to the second embodiment of the present invention ultimately has a structure in which a support substrate (110), a bonding layer (120), an AlN intermediate layer (140), a surface planarization layer (130), and a device active layer (150) are laminated.

[0133]

[0134] From now on, with reference to the attached drawings, a method (S300) for manufacturing a group III nitride power semiconductor device according to a third embodiment of the present invention will be described in detail.

[0135] FIG. 18 is a flowchart of a method (S300) for manufacturing a group III nitride power semiconductor device according to a third embodiment of the present invention, and FIGS. 19 to 20 illustrate a process for manufacturing a group III nitride power semiconductor device according to a method (S300) for manufacturing a group III nitride power semiconductor device according to a third embodiment of the present invention.

[0136] As illustrated in FIGS. 18 to 20, a method (S300) for manufacturing a group III nitride power semiconductor device according to a third embodiment of the present invention includes a growth step (S310), an adhesion step (S320), a first removal step (S330), an etching step (S340), a film formation step (S350), a bonding step (S360), a second removal step (S370), and a surface preparation step (S380).

[0137] The growth stage (S310) is a stage in which a buffer layer (160), an etch-stop layer (161), and an element active layer (150) are sequentially grown epitaxially on the initial growth substrate (G).

[0138] The first growth substrate (G) is removed through the laser lift off (LLO) technique in the first removal step (S330) described below. In this case, the first growth substrate (G) is preferably formed of an optically transparent substrate having high temperature resistance that allows 100% (theoretically) transmission of a laser beam (single wavelength light) without absorption. For example, it can be formed of a material such as sapphire (α-phase Al2O3), ScMgAlO4, 4H-SiC, or 6H-SiC, which is polished on both sides. In addition, the first growth substrate (G) is also preferably formed of a patterned sapphire substrate (PSS) having a protrusion shape that is regularly or irregularly patterned in various dimensions (sizes and shapes) in the microscale or nanoscale on one side in order to minimize crystal defects in the group III-nitride semiconductor thin film grown thereon.

[0139] Meanwhile, in the present invention, a group III nitride semiconductor template (G1) can be used as the first growth substrate (G), which is the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, and therefore, a duplicate description is omitted.

[0140] The buffer layer (160) is formed of a relatively low-quality GaN material, and may contain alloy materials such as Al, In, and Sc, and intentionally or unintentionally impurities (C, Fe, Si, etc.), and further may be provided with a number of air voids to relieve stress.

[0141] The etching stop layer (161) is a layer that prevents the device active layer (150) (i.e., the channel layer (151)) from being etched together when a regular or irregular pattern is formed on the surface of the buffer layer (160) whose thickness is reduced in the etching step (S340) described later, and can be formed of AlN, AlInN, etc.

[0142] The device active layer (150) is grown on an etch-stop layer (161) and includes a GaN channel layer (151) and an AlGaN barrier layer (152) for a power semiconductor device structure such as a HEMT. Here, the GaN channel layer (151) is formed of a relatively high-quality GaN material with minimized crystal defects such as dislocations, and is formed to have a thickness of 100-500 nm.

[0143] The bonding step (S320) and the first removal step (S330) are the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0144] The etching step (S340) is a step of reducing the thickness by etching the buffer layer (160) through dry etching or wet etching.

[0145] Meanwhile, the surface of the buffer layer (160) with reduced thickness has a nitrogen polar surface (n-polar surface), and the surface of this buffer layer (160) inevitably has a locally damaged area, and various surface crystal defects are inevitably generated during the growth of the buffer layer (160). These crystal defects and damaged surfaces cause difficulties and quality issues during the deposition of the AlN intermediate layer (140) described later, and therefore, it is essential to perform a surface planarization process through a ceramic material deposition and / or a CMP (chemical-mechanical polishing) process to improve this.

[0146] FIG. 5 and FIG. 6 illustrate a process of forming a surface planarization layer (130) in an etching step (S340) of a method (S300) for manufacturing a group III nitride power semiconductor device according to the first to third embodiments of the present invention.

[0147] As illustrated in FIGS. 5 and 7, the etching step (S340) may form a regular or irregular pattern on the surface of the buffer layer (160) with a reduced thickness, and then form a surface planarization layer (130) on the surface of the buffer layer (160) on which the pattern is formed. Here, the surface planarization layer (130) may have a multi-layer structure, and may be planarized with a SiO2 material or the like by depositing an AlN or AlON material on the surface of the buffer layer (160) through PVD (physical vapor deposition) such as sputtering, or may be planarized with an AlN or AlON material by depositing an SiO2 material or the like on the surface of the buffer layer (160) through PVD such as sputtering. For planarization, the SOG (spin on glass) method can be used, and after planarization, the thickness of the surface planarization layer (130) is controlled through CMP (chemical-mechanical polishing). At this time, depending on the degree of CMP, only the surface planarization layer (130) may be exposed, or the surface planarization layer (130) and the buffer layer (160) may be exposed together.

[0148] In addition to PVD such as sputtering described above, AlN, SiN at low temperatures below 500℃ x The same process is also possible through an ALD (atomic level deposition) device that can form SiO2, etc.

[0149] The film formation step (S350) is a step of forming an AlN intermediate layer (140) on a buffer layer (160) with a reduced thickness. At this time, if a surface planarization layer (130) is formed in the etching step (S340), the film formation step (S350) can form an AlN intermediate layer (140) on the surface planarization layer (130).

[0150] The AlN interlayer (140) is formed as a single crystal or quasi-single crystal to provide a power semiconductor device with high resistance and high heat dissipation performance, and is grown with AlN or AlON materials, etc., and is formed to have a thickness of several to several thousand nm. In the present embodiment, the AlN interlayer (140) can be formed on the buffer layer (160) or the surface planarization layer (130) through PVD (physical vapor deposition) such as sputtering, PLD, IAD, and evaporator, or CVD (chemical vapor deposition) such as ALD. In the PVD process, AlON can be formed by including a small amount of oxygen (O) to improve crystallinity, and in the CVD process, in order to resolve the large roughness of the GaN surface with nitrogen polarity (n-polarity) and to form AlN with group 3 polarity, a metal layer such as Al, Cr, Ti, etc. with a thickness of several nm can be inserted as a polarity conversion layer.

[0151] The bonding step (S360), the second removal step (S370), and the surface preparation step (S380) are the same as the method for manufacturing a group III nitride power semiconductor device (S100) according to the first embodiment of the present invention described above, and therefore, a duplicate description is omitted.

[0152] Meanwhile, a group III nitride power semiconductor device manufactured according to a method for manufacturing a group III nitride power semiconductor device (S300) according to the third embodiment of the present invention ultimately has a structure in which a support substrate (110), a bonding layer (120), an AlN intermediate layer (140), a surface planarization layer (130), a buffer layer (160), an etch-stop layer (161), and a device active layer (150) are laminated.

[0153]

[0154] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0155] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0156] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0157] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. A growth step of sequentially growing a sacrificial layer, an AlN intermediate layer, and an active layer of the device on a growth substrate; A bonding step of bonding the active layer of the device to a temporary substrate through an adhesive layer; A first removal step for removing the above growth substrate; An etching step for exposing the AlN intermediate layer by etching and removing the sacrificial layer; A bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; A second removal step for removing the temporary substrate; and A method for manufacturing a group III nitride power semiconductor device, comprising a surface preparation step of removing the adhesive layer to expose the device active layer.

2. In claim 1, The above-mentioned active layer of the device is, A method for manufacturing a group III nitride power semiconductor device, comprising a channel layer and a barrier layer.

3. In claim 1, The above growth stages are, A method for manufacturing a group III nitride power semiconductor device, comprising: a first step of growing a sacrificial layer and an etching layer on a growth substrate and then forming an etching mask layer having a regular or irregular pattern on the etching layer; a second step of etching the etching layer along the pattern of the etching mask layer; a third step of forming a growth promotion layer on the etched etching layer; and a fourth step of growing the AlN intermediate layer through the etching layer on which the growth promotion layer has been formed.

4. In claim 1, The above etching step is, After forming a regular or irregular pattern on the surface of the exposed AlN intermediate layer, a surface planarization layer is formed on the surface of the AlN intermediate layer on which the pattern is formed. The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that the surface planarization layer is bonded to the support substrate through the bonding layer.

5. In claim 1, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that the AlN intermediate layer is bonded to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

6. In claim 5, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that a positive or negative pattern is formed at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

7. In claim 5, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized by forming a positive or negative pattern to a preset depth on at least one of the support substrate or the second bonding layer.

8. In claim 5, Each of the first bonding layer and the second bonding layer, A method for manufacturing a group III nitride power semiconductor device, comprising: a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the supporting substrate; a planarizing layer for alleviating roughness of a surface of the AlN intermediate layer or the supporting substrate; and a bonding layer for bonding the AlN intermediate layer and the supporting substrate to each other.

9. A growth step of sequentially growing a buffer layer and a device active layer on a growth substrate; A bonding step of bonding the active layer of the device to a temporary substrate through an adhesive layer; A first removal step for removing the above growth substrate; An etching step for exposing the device active layer by etching and removing the buffer layer; A film forming step of forming an AlN intermediate layer on the exposed active layer of the device; A bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; A second removal step for removing the temporary substrate; and A method for manufacturing a group III nitride power semiconductor device, comprising a surface preparation step of removing the adhesive layer to expose the device active layer.

10. In claim 9, The above-mentioned active layer of the device is, A method for manufacturing a group III nitride power semiconductor device, comprising a channel layer and a barrier layer.

11. In claim 9, The above etching step is, After forming a regular or irregular pattern on the surface of the exposed active layer of the device, a surface planarization layer is formed on the surface of the active layer of the device on which the pattern is formed. The above tabernacle stage is, A method for manufacturing a group III nitride power semiconductor device, characterized by forming an AlN intermediate layer on the surface of the above-mentioned surface planarization layer.

12. In claim 9, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that the AlN intermediate layer is bonded to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

13. In claim 12, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that a positive or negative pattern is formed at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

14. In claim 12, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized by forming a positive or negative pattern to a preset depth on at least one of the support substrate or the second bonding layer.

15. In claim 12, Each of the first bonding layer and the second bonding layer, A method for manufacturing a group III nitride power semiconductor device, comprising: a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the supporting substrate; a planarizing layer for alleviating roughness of a surface of the AlN intermediate layer or the supporting substrate; and a bonding layer for bonding the AlN intermediate layer and the supporting substrate to each other.

16. A growth step of sequentially growing a buffer layer, an etch-stop layer, and an active layer of a device on a growth substrate; A bonding step of bonding the active layer of the device to a temporary substrate through an adhesive layer; A first removal step for removing the above growth substrate; An etching step for reducing the thickness by etching the above buffer layer; A film forming step of forming an AlN intermediate layer on the buffer layer with a reduced thickness; A bonding step of bonding the AlN intermediate layer to a support substrate through a bonding layer; A second removal step for removing the temporary substrate; and A method for manufacturing a group III nitride power semiconductor device, comprising a surface preparation step of removing the adhesive layer to expose the device active layer.

17. In claim 16, The above-mentioned active layer of the device is, A method for manufacturing a group III nitride power semiconductor device, comprising a channel layer and a barrier layer.

18. In claim 16, The above etching step is, After forming a regular or irregular pattern on the surface of the buffer layer with reduced thickness, a surface flattening layer is formed on the surface of the buffer layer on which the pattern is formed. The above tabernacle stage is, A method for manufacturing a group III nitride power semiconductor device, characterized by forming an AlN intermediate layer on the surface of the above-mentioned surface planarization layer.

19. In claim 16, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that the AlN intermediate layer is bonded to the support substrate by forming a first bonding layer on one surface of the AlN intermediate layer, forming a second bonding layer on one surface of the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

20. In claim 19, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized in that a positive or negative pattern is formed at a preset depth on at least one of the AlN intermediate layer or the first bonding layer.

21. In claim 19, The above joining step is, A method for manufacturing a group III nitride power semiconductor device, characterized by forming a positive or negative pattern to a preset depth on at least one of the support substrate or the second bonding layer.

22. In claim 19, Each of the first bonding layer and the second bonding layer, A method for manufacturing a group III nitride power semiconductor device, comprising: a bonding reinforcing layer for reinforcing bonding with the AlN intermediate layer or the supporting substrate; a planarizing layer for alleviating roughness of a surface of the AlN intermediate layer or the supporting substrate; and a bonding layer for bonding the AlN intermediate layer and the supporting substrate to each other.

23. A group III nitride power semiconductor device manufactured by a method for manufacturing a group III nitride power semiconductor device according to any one of claims 1 to 22.

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