Array substrate, display panel and driving method therefor, and display apparatus

Abstract

Disclosed in the present disclosure are an array substrate, a display panel and a driving method therefor, and a display apparatus. The array substrate comprises: a base substrate, which comprises a display area and a non-display area located on at least one side of the display area; a common electrode line, which is located in the non-display area and comprises an accommodating groove disposed close to the display area; and a sensor circuit, which is at least partially located in the accommodating groove and is configured to monitor temperature.

Description

Array substrate, display panel, driving method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a driving method thereof, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, driving method thereof, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area;

[0007] a common electrode line located in the non-display area, the common electrode line comprising a receiving groove disposed near the display area;

[0008] A sensor circuit is at least partially located within the receiving groove, and the sensor circuit is configured to monitor temperature.

[0009] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the sensor circuit is a temperature sensing circuit.

[0010] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes an input signal line and a reference signal line wound around the common electrode line;

[0011] The sensor circuit includes a first transistor and a capacitor, wherein the gate of the first transistor is coupled to the input signal line, the first electrode of the first transistor is coupled to the gate of the first transistor, the second electrode of the first transistor is coupled to the first plate of the capacitor, and the second plate of the capacitor is coupled to the reference signal line.

[0012] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the capacitor is located in the receiving groove, and at least a portion of the first transistor is located in the receiving groove.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first transistor is located on a side of the capacitor away from the display area, or the capacitor is located on a side of the first transistor away from the display area.

[0014] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the opening of the accommodating groove faces the side away from the display area, the input signal line extends from the side of the common electrode line away from the display area to the accommodating groove, and the reference signal line extends from the side of the input signal line away from the display area to the accommodating groove.

[0015] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a detection signal line located on a side of the reference signal line away from the common electrode line;

[0016] The sensor circuit also includes a first resistor and a second resistor, the first end of the first resistor is coupled to the first plate of the capacitor, the second end of the first resistor is coupled to the detection signal line, the first end of the second resistor is coupled to the detection signal line, and the second end of the second resistor is coupled to the reference signal line.

[0017] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second resistor is greater than the first resistor.

[0018] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first resistor and the second resistor respectively include multiple winding repetition units, and the number of winding repetition units of the first resistor is less than the number of winding repetition units of the second resistor.

[0019] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a first dummy pattern, which is located on the side of the first resistor facing the display area, the side of the first resistor away from the display area, the side of the second resistor facing the display area, and the side of the second resistor away from the display area. The structure of the first dummy pattern is substantially the same as the structure of the first resistor and the second resistor.

[0020] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the common electrode line, the input signal line, the reference signal line, the detection signal line, the second plate of the capacitor, the first resistor, the second resistor, the first dummy pattern and the gate of the transistor are arranged on the same layer, and the first plate of the capacitor and the first and second electrodes of the transistor are arranged on the same layer.

[0021] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second dummy pattern located in the receiving groove, and the second dummy pattern is arranged in the space surrounded by the input signal line, the reference signal line, and the capacitor.

[0022] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second dummy pattern is provided in the same layer as the gate of the transistor.

[0023] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the common electrode line, the input signal line, the reference signal line, and the second dummy pattern respectively include a plurality of hollow structures.

[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the opening of the receiving groove faces the display area;

[0025] The array substrate further includes a fan-out line located between the common electrode line and the display area, and the input signal line and the reference signal line are located between the fan-out line and the common electrode line.

[0026] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a control signal line located between the input signal line and the reference signal line;

[0027] The sensor circuit also includes a second transistor, a gate of the second transistor is coupled to the control signal line, a first electrode of the second transistor is coupled to the first plate of the capacitor, a second electrode of the second transistor is coupled to the second plate of the capacitor, and a channel width-to-length ratio of the second transistor is greater than the channel width-to-length ratio of the first transistor.

[0028] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the sensor circuit also includes a third transistor, the gate of the third transistor is coupled to the reference signal line, the first electrode of the third transistor is coupled to the second plate of the capacitor, and the second electrode of the third transistor is coupled to the reference signal line.

[0029] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first transistor, the second transistor, and the third transistor are arranged side by side on the same side of the capacitor.

[0030] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, and the second electrode of the third transistor are comb electrodes or block electrodes; the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are block electrodes or include multiple interconnected island electrodes.

[0031] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a switching transistor located in the display area, and the ratio of the channel width-to-length ratio of the first transistor to the channel width-to-length ratio of the switching transistor is greater than or equal to 50.

[0032] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the non-display area includes multiple binding areas, the sensor circuit is located between the binding area and the display area, and / or the sensor circuit is located between the gap between adjacent binding areas and the display area.

[0033] On the other hand, an embodiment of the present disclosure provides a display panel, comprising the array substrate provided in the embodiment of the present disclosure, and an opposite substrate disposed opposite to the array substrate.

[0034] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel.

[0035] On the other hand, an embodiment of the present disclosure provides a method for driving the display panel, including:

[0036] Use sensor circuit to monitor panel temperature;

[0037] A driving parameter is generated according to the panel temperature, and the display panel is controlled by using the driving parameter to display an image.

[0038] In some embodiments, in the driving method provided in the embodiments of the present disclosure, a sensor circuit is used to monitor the panel temperature, specifically including:

[0039] At a fixed moment after the first transistor is turned on each time, the voltage at the connection point between the first resistor and the second resistor is collected, and the panel temperature is determined based on the collected voltage.

[0040] In some embodiments, in the driving method provided in the embodiments of the present disclosure, a sensor circuit is used to monitor the panel temperature, specifically including:

[0041] During each turn-on of the first transistor, the panel temperature is determined by monitoring the peak charging current of the capacitor.

[0042] In some embodiments, in the driving method provided by the embodiments of the present disclosure, after the sensor circuit is used to monitor the panel temperature, the method further includes: turning on the second transistor to discharge the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0044] FIG2 is a schematic diagram of an enlarged structure of the Z1 area in FIG1 ;

[0045] FIG3 is an enlarged structural diagram of the Z2 area in FIG2 ;

[0046] FIG4 is an enlarged structural diagram of the Z3 region in FIG2 ;

[0047] FIG5 is an enlarged structural diagram of the Z4 region in FIG2 ;

[0048] FIG6 is an enlarged structural diagram of the Z5 region in FIG2 ;

[0049] FIG7 is an equivalent circuit diagram of the sensor circuit in FIG2 ;

[0050] FIG8 is a temperature monitoring schematic diagram of the sensor circuit shown in FIG7 ;

[0051] FIG9 is a schematic diagram of an enlarged structure of the Z6 region in FIG1 ;

[0052] FIG10 is an equivalent circuit diagram of the sensor circuit in FIG9 ;

[0053] FIG11 is a temperature monitoring circuit diagram of the sensor circuit shown in FIG10 ;

[0054] FIG12 is a temperature monitoring schematic diagram of the sensor circuit shown in FIG10 ;

[0055] FIG13 is another enlarged structural diagram of the Z6 region in FIG1 ;

[0056] FIG14 is an equivalent circuit diagram of the sensor circuit in FIG13 ;

[0057] FIG15 is a schematic structural diagram of a transistor provided in an embodiment of the present disclosure;

[0058] FIG16 is a schematic diagram of another structure of a transistor provided in an embodiment of the present disclosure;

[0059] FIG17 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0060] FIG18 is a flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

[0061] FIG19 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0063] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0064] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0065] Competition in the TFT-LCD market is becoming increasingly fierce. As the development of high frequency, high refresh rate, and high resolution (PPI) gradually slows down, fat modules and screen empowerment are another way to enhance product competitiveness.

[0066] The present invention adds a sensor circuit within the screen to monitor the panel temperature in real time, and can adjust the panel signal on the circuit. For example, the high level (Vgh) of the gate drive circuit (GOA) in the plane. When the screen temperature increases, the transistor (TFT) driving capability will increase, and Vgh can be appropriately reduced to reduce the drift of TFT characteristics in the screen and increase the lifespan. For example, the driving strength of the line over drive (line od) in the plane controls the response time of the liquid crystal, and can be adjusted in real time according to the temperature to solve the problems such as horizontal and vertical stripes caused by the different response times of the liquid crystal at different temperatures, thereby effectively improving the display quality.

[0067] In some embodiments, FIG1 shows a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure, FIG2 is an enlarged structural diagram of the Z1 region in FIG1 , and FIG3 to FIG6 are enlarged structural diagrams of the Z2 to Z6 regions in FIG2 , respectively. FIG7 is an equivalent circuit diagram of the sensor circuit in FIG2 . As can be seen from FIG1 to FIG7 , the array substrate provided in the present disclosure may include:

[0068] A base substrate 101, comprising a display area AA and a non-display area BB located on at least one side of the display area AA; optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like;

[0069] The common electrode line 102 is located in the non-display area BB. The common electrode line 102 includes a receiving groove 1021 disposed near the display area AA.

[0070] The sensor circuit 103 is at least partially located in the receiving groove 1021. Optionally, the sensor circuit 103 is configured to monitor temperature. It should be understood that after the array substrate and the opposite substrate are assembled to form a display panel, the temperature monitored by the sensor circuit 103 may be the display panel temperature.

[0071] The array substrate provided in the embodiment of the present disclosure integrates the sensor circuit 103, which can adjust the GOA parameters according to the monitoring temperature of the sensor circuit 103 and the line in the display area AA. od parameters, etc., or optionally, the sensor circuit 103 can detect the temperature of the display panel. When the temperature is lower than the threshold temperature, the display panel can be heated. For example, a heating resistor or other structure can be set in the display area and / or the non-display area of ​​the display panel. When the display panel is lower than the threshold temperature, the heating function of the display panel is turned on to ensure normal display. The threshold temperature can be, for example, -5°C to -15°C, or set according to actual needs, which is not limited here. The setting of the sensor circuit 103 can improve the display quality; and, the present disclosure provides the common electrode line 102 with a receiving groove 1021, and at least part of the sensor circuit 103 is located in the receiving groove 1021, which is equivalent to using part of the space originally used for arranging the common electrode line 102 to set the sensor circuit 103, which is conducive to achieving a narrow frame effect; in addition, since the receiving groove 1021 is set close to the display area AA, the temperature monitored by the sensor circuit 103 can take into account the temperature of the non-display area BB and the display area AA, so that the parameters of GOA in the non-display area BB and line in the display area AA can be realized based on the monitored temperature of the sensor circuit 103. od parameters to more accurately adjust the display quality.

[0072] In some embodiments, the sensor circuit 103 of the present disclosure may be a temperature sensing circuit, and as shown in Figures 2 and 3, the array substrate of the present disclosure may further include an input signal line INL and a reference signal line LVGL wound around the common electrode line 102. The input signal line INL and the reference signal line LVGL are arranged around the common electrode line 102 to ensure that the wiring is more compact, which is conducive to reducing the wiring space and achieving a narrow bezel effect. Optionally, the reference signal line LVGL electrically connected to the sensor circuit 103 in this case can be shared with the reference signal line LVGL electrically connected to the gate drive circuit (GOA) set in the non-display area, and the two are the same signal, wherein the reference signal line LVGL is used in the gate drive circuit (GOA) to reduce noise at the pull-up node of the gate drive circuit (GOA), and / or the gate signal output end. The gate drive signal output end can be a cascade output end or an output end electrically connected to the gate line of the display area (AA). Such a shared signal can reduce the display panel bezel.

[0073] In some embodiments, as shown in Figures 1 and 2, the non-display area BB includes multiple binding areas BA (which may correspond one-to-one to the fan-out area FA, and multiple fan-out lines 106 are provided in the fan-out area FA), the sensor circuit 103 is located between the binding area BA and the display area AA, and / or, the sensor circuit 103 is located between the gap between adjacent binding areas BA and the display area AA (for example, the sensor circuit 103 is located in the area between the fan-out lines 106 of two adjacent fan-out areas FA), which is not limited in the present disclosure.

[0074] It should be noted that the present disclosure uses the example of the sensor circuit 103 being arranged at the lower frame for illustration, but in some embodiments, the sensor circuit 103 of the present disclosure may also be arranged at the upper frame, left frame, right frame, etc.

[0075] In some embodiments, as shown in Figures 2, 3, and 7, the sensor circuit 103 includes a first transistor TFT1 and a capacitor C, wherein the gate of the first transistor TFT1 is coupled to the input signal line INL, the first electrode of the first transistor TFT1 is coupled to the gate of the first transistor TFT1, the second electrode of the first transistor TFT1 is coupled to the first plate of the capacitor C, and the second plate of the capacitor C is coupled to the reference signal line LVGL. The gate of the first transistor TFT1 is short-circuited to the first electrode, which can eliminate the problem of reduced turn-on current caused by the threshold voltage (Vth) drift of the first transistor TFT1 as the operating time increases. The input signal provided by the input signal line INL can be a pulse signal of a high voltage Vgh (as shown in Figure 8), or it can be a clock signal (CLK), a frame start signal (STV), etc., that is, the input signal provided by the input signal line INL can be shared with the clock signal (CLK) and the frame start signal (STV) of the gate drive circuit (GOA), etc., and this is not specifically limited in this disclosure. When the input signal line INL provides an input signal to the first transistor TFT1, the first transistor TFT1 charges the capacitor C. Because the on-state current of the first transistor TFT1 varies at different temperatures, the panel temperature can be determined based on the current or voltage of the sensor circuit. In some embodiments, the channel width-to-length ratio of the first transistor TFT1 can be at least 50 times the channel width-to-length ratio of the switching transistor (connected to the pixel electrode pixel) in the display area AA.

[0076] In some embodiments, the first transistor TFT1 in the present disclosure can be an amorphous silicon transistor (a-Si), a polycrystalline silicon (Poly) transistor, an oxide transistor, etc. In view of the high sensitivity of amorphous silicon transistors to temperature and low cost, the present disclosure preferably uses an amorphous silicon transistor as the first transistor TFT1.

[0077] In some embodiments, FIG9 shows an enlarged schematic diagram of the structure of region Z2 in FIG1 . As can be seen from FIG3 and FIG9 , capacitor C is located within receiving groove 1021, and at least a portion of first transistor TFT1 is located within receiving groove 1021. Specifically, in FIG3 , first transistor TFT1 is located within receiving groove 1021, while in FIG9 , most of first transistor TFT1 is located within receiving groove 1021, which is equivalent to first transistor TFT1 being located within receiving groove 1021. This arrangement requires very little, or even no, additional space for first transistor TFT1 and capacitor C, facilitating a narrow bezel effect.

[0078] Alternatively, as shown in FIG3 , the first transistor TFT1 is located on the side of the capacitor C away from the display area AA; or, as shown in FIG9 , the capacitor C is located on the side of the first transistor TFT1 away from the display area AA. The on-state current of the first transistor TFT1 changes with temperature, so placing the first transistor TFT1 closer to the display area AA can more effectively take into account the temperature of the non-display area BB and the display area AA. Thus, based on the monitored temperature of the sensor circuit 103, precise adjustment of the parameters of GOA in the non-display area BB and the parameters of line od in the display area AA can be achieved, which is conducive to effectively improving the display quality. Of course, when the space occupied by the capacitor C is small, the first transistor TFT1 is placed further away from the display area AA relative to the capacitor C, which has little impact on the monitored temperature and can still effectively improve the display quality.

[0079] In some embodiments, as shown in Figures 2 to 6, the opening of the receiving groove 1021 is arranged toward the side away from the display area AA. The input signal line INL extends from the side of the common electrode line 102 away from the display area AA into the receiving groove 1021 to be connected to the gate of the first transistor TFT1 in the receiving groove 1021. The reference signal line LVGL extends from the side of the input signal line INL away from the display area AA into the receiving groove 1021 to be connected to the second plate of the capacitor C. The input signal line INL and the reference signal line LVGL are arranged around the side of the common electrode line 102 away from the display area AA, which can fully utilize the peripheral space of the common electrode line 102 for wiring.

[0080] In some embodiments, as shown in Figures 2 to 7, a detection signal line DTL is further included on a side of the reference signal line LVGL away from the common electrode line 102; the sensor circuit 103 may further include a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is coupled to the first plate of the capacitor C, a second end of the first resistor R1 is coupled to the detection signal line DTL, a first end of the second resistor R2 is coupled to the detection signal line DTL, and a second end of the second resistor R2 is coupled to the reference signal line LVGL. In a specific implementation, the first resistor R1 and the second resistor R2 can achieve a voltage divider effect on the voltage across the capacitor C. Because the on-state current of the first transistor TFT1 varies at different temperatures, as shown in Figure 8, the amount of charge on the capacitor C at a fixed time (e.g., 1 second after the first transistor TFT1 is turned on) is different (equivalent to a different voltage across the capacitor C). As a result, the voltage monitored by the detection signal line DTL at a fixed time and different temperatures is different, so that the panel temperature can be determined based on the monitored voltage. In some embodiments, the detection signal line DTL can be connected to an external circuit (such as a microcontroller unit MCU). The external circuit can use a voltage amplifier circuit to amplify and analyze the voltage difference collected by the detection signal line DTL to more finely divide the temperature range.

[0081] In some embodiments, as shown in FIG7 , the voltage monitored by the detection signal line DTL is equivalent to the voltage divided by the second resistor R2 . Therefore, if the wiring space allows, the larger the second resistor R2 , the easier it is to monitor the voltage. Based on this, the second resistor R2 can be set to be larger than the first resistor R1 in the present disclosure. Optionally, as shown in FIG4 to FIG6 , the first resistor R1 and the second resistor R2 of the present disclosure each include multiple winding repeating units, for example, the winding repeating units are approximately zigzag windings, and of course the winding repeating units can also be s-shaped windings, etc. Optionally, to ensure that the second resistor R2 is larger, the number of winding repeating units of the first resistor R1 can be set to be smaller than the number of winding repeating units of the second resistor R2.

[0082] In some embodiments, as shown in Figures 2 to 6 , the present disclosure may further include a first dummy pattern 104. The first dummy pattern 104 is located on the side of the first resistor R1 facing the display area AA, the side of the first resistor R1 away from the display area AA, the side of the second resistor R2 facing the display area AA, and the side of the second resistor R2 away from the display area AA. The structure of the first dummy pattern 104 is substantially the same as that of the first resistor R1 and the second resistor R2, meaning that the first dummy pattern 104 has a similar or identical winding repeating unit as the first resistor R1 and the second resistor R2. Providing the first dummy pattern 104 on both sides of the first resistor R1 and the second resistor R2 ensures uniform etching of the metal lines.

[0083] In some embodiments, as shown in Figures 2 to 6, a second dummy pattern 105 can be set in the receiving groove 1021. Optionally, the second dummy pattern 105 is set in the space surrounded by the input signal line INL, the reference signal line LVGL, and the capacitor C, so as to effectively ensure the etching uniformity of the pattern in the receiving groove 1021.

[0084] Optionally, the common electrode line 102, the input signal line INL, the reference signal line LVGL, the detection signal line DTL, the second plate of the capacitor C, the first resistor R1, the second resistor R2, the first dummy pattern 104, and the second dummy pattern 105 in the present disclosure are all arranged in the same layer and the same material as the gate of the first transistor TFT1, and the first plate of the capacitor C is arranged in the same layer and the same material as the first pole and the second pole of the first transistor TFT1. In the present disclosure, "same layer" refers to a layer structure formed by a single patterning process using the same film forming process to form a film layer for making a specific pattern, and then using the same mask to form a patterning process. That is, a patterning process corresponds to a mask (mask, also called a photomask). Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0085] In some embodiments, the sealant in the non-display area BB can be irradiated on the side of the base substrate 101 to achieve curing of the sealant. Accordingly, in order to transmit the irradiated light, the present disclosure can be configured to set multiple hollow structures OW for all or part of the signal lines with larger line widths. For example, the common electrode line 102, the input signal line INL, the reference signal line LGVL, and the second dummy pattern 105 each include multiple hollow structures OW. Optionally, the line widths of the first resistor R1, the second resistor R2, and the first dummy pattern 104 are much smaller than the line width of the common electrode line 102, and there are gaps between adjacent lines to allow light to pass through. Therefore, there is no need to set hollow structures OW for the windings of the first resistor R1, the second resistor R2, and the first dummy pattern 104.

[0086] In some embodiments, as shown in Figure 9, the opening of the accommodating groove 1021 faces the display area AA, and the array substrate also includes a fan-out line 106 located between the common electrode line 102 and the display area AA. The input signal line INL and the reference signal line LVGL are located between the fan-out line 106 and the common electrode line 102, so as to utilize the space between the fan-out line 106 and the common electrode line 102 for wiring, thereby maintaining the frame size unchanged.

[0087] Optionally, as shown in Figures 9 and 10, the array substrate may further include a control signal line CTL located between the input signal line INL and the reference signal line LVGL, and the sensor circuit 103 may further include a second transistor TFT2 arranged side by side with the first transistor TFT1 on the same side of the capacitor C, the gate of the second transistor TFT2 is coupled to the control signal line CTL, the first electrode of the second transistor TFT2 is coupled to the first plate of the capacitor C, and the second electrode of the second transistor TFT2 is coupled to the second plate of the capacitor C. To ensure that the monitoring current is determined by the first transistor TFT1, the present disclosure sets the channel width-to-length ratio of the second transistor TFF2 to be greater than the channel width-to-length ratio of the first transistor TFT1.

[0088] In the present disclosure, the input signal line INL provides an input signal to the first transistor TFT1, and the first transistor TFT1 charges the capacitor C. Because the on-state current of the first transistor TFT1 varies at different temperatures, the present disclosure can use an external circuit (such as a microcontroller unit MCU) to monitor the charging peak current of the capacitor C and the temperature of the monitoring panel, as shown in Figures 11 and 12; and the external circuit can use a voltage amplifier circuit to amplify and analyze the difference in the charging peak current of the capacitor C, thereby more finely dividing the temperature range. After collecting the charging peak current of the capacitor C, the second transistor TFT2 can be turned on to quickly discharge the capacitor C.

[0089] In some embodiments, as shown in Figures 13 and 14, the sensor circuit 103 may further include a third transistor TFT3, the gate of the third transistor TFT3 is coupled to the reference signal line LVGL, the first electrode of the third transistor TFT3 is coupled to the second plate of the capacitor C, the second electrode of the third transistor TFT3 is coupled to the reference signal line LVGL, and the third transistor TFT3 is equivalent to a resistor connected in series between the second plate of the capacitor C and the reference signal line LVGL.

[0090] In some embodiments, as shown in FIG13 , the first transistor TFT1 , the second transistor TFT2 , and the third transistor TFT3 are arranged side by side on the same side of the capacitor C to reduce the space occupied by the three transistors and achieve a narrow frame effect.

[0091] In some embodiments, in the present disclosure, the first electrode of the first transistor TFT1, the second electrode of the first transistor TFT1, the first electrode of the second transistor TFT2, the second electrode of the second transistor TFT2, the first electrode of the third transistor TFT3, and the second electrode of the third transistor TFT3 are comb-shaped electrodes or block-shaped electrodes; the gate of the first transistor TFT1, the gate of the second transistor TFT2, and the gate of the third transistor TFT3 are block-shaped electrodes or include multiple interconnected island-shaped electrodes. For example, Figure 15 shows that the first electrode S of the transistor (for example, the first transistor TFT1, the second transistor TFT2, and the third transistor TFT3) is comb-shaped, the second electrode D is comb-shaped, and the gate G is block-shaped; Figure 16 shows that the first electrode S of the transistor (for example, the first transistor TFT1, the second transistor TFT2, and the third transistor TFT3) is comb-shaped, the second electrode D is comb-shaped, and the gate G is island-shaped. A in Figures 15 and 16 represents the active layer of the transistor (for example, the first transistor TFT1, the second transistor TFT2, and the third transistor TFT3).

[0092] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in FIG17 , comprising the array substrate 001 provided in the embodiment of the present disclosure, and an opposing substrate 002 disposed opposite the array substrate 001. Because the principles for solving the problems solved by the display panel are similar to those solved by the array substrate, the implementation of the display panel provided in the embodiment of the present disclosure can refer to the implementation of the array substrate provided in the embodiment of the present disclosure, and any repetitions will not be repeated.

[0093] In some embodiments, as shown in FIG17 , the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer 003 between an array substrate 001 and an opposing substrate 002. In some embodiments, a first polarizer 004 may be provided on a side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be provided on a side of the opposing substrate 002 away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0094] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for the above-mentioned display panel, as shown in FIG18 , which may include the following steps:

[0095] S1801, using sensor circuit to monitor panel temperature;

[0096] S1802: Generate driving parameters according to the panel temperature, and use the driving parameters to control the display panel to display images.

[0097] Optionally, the above step S1801 uses a sensor circuit to monitor the panel temperature, which can be implemented in the following two ways:

[0098] The first method is: at a fixed moment after each turning on of the first transistor, the voltage at the connection point between the first resistor and the second resistor is collected, and the panel temperature is determined based on the collected voltage;

[0099] The second method is: during each turn-on of the first transistor, the panel temperature is determined by monitoring the peak charging current of the capacitor.

[0100] In some embodiments, after the sensor circuit monitors the panel temperature, a step may be performed: turning on the second transistor to discharge the capacitor. Optionally, the second transistor may be used to discharge the capacitor before the display panel is controlled to display an image using the drive parameters, or after the display panel is controlled to display an image using the drive parameters, and this is not specifically limited in this disclosure.

[0101] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG19 , comprising the above-mentioned display panel PNL provided in an embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0102] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-scale micro light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when the micro light-emitting device is used as a backlight source, it can achieve a more precise dynamic backlight effect. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0103] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0104] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0105] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, Comprising: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; A common electrode line, located in the non-display area, the common electrode line including a receiving groove disposed close to the display area; A sensor circuit, at least partially located in the receiving groove, the sensor circuit being configured to monitor temperature.

2. The array substrate according to claim 1, wherein, The sensor circuit is a temperature sensing circuit.

3. The array substrate according to claim 2, wherein, Further including an input signal line and a reference signal line wound around the common electrode line; The sensor circuit includes a first transistor and a capacitor. Wherein, a gate of the first transistor is coupled to the input signal line, a first pole of the first transistor is coupled to the gate of the first transistor, a second pole of the first transistor is coupled to a first electrode plate of the capacitor, and a second electrode plate of the capacitor is coupled to the reference signal line.

4. The array substrate according to claim 3, wherein, The capacitor is located in the receiving groove, and at least a part of the first transistor is located in the receiving groove.

5. The array substrate according to claim 3 or 4, wherein The first transistor is located on a side of the capacitor away from the display area, or the capacitor is located on a side of the first transistor away from the display area.

6. The array substrate according to any one of claims 3 to 5, wherein, An opening of the receiving groove faces away from the display area. The input signal line extends from a side of the common electrode line away from the display area into the receiving groove, and the reference signal line extends from a side of the input signal line away from the display area into the receiving groove.

7. The array substrate according to claim 6, wherein, Further including a detection signal line located on a side of the reference signal line away from the common electrode line; The sensor circuit further includes a first resistor and a second resistor. A first end of the first resistor is coupled to the first electrode plate of the capacitor, a second end of the first resistor is coupled to the detection signal line, a first end of the second resistor is coupled to the detection signal line, and a second end of the second resistor is coupled to the reference signal line.

8. The array substrate according to claim 7, wherein, The second resistor is greater than the first resistor.

9. The array substrate according to claim 8, wherein, The first resistor and the second resistor respectively include a plurality of winding repeating units, and the number of winding repeating units of the first resistor is less than the number of winding repeating units of the second resistor.

10. The array substrate according to claim 9, wherein, Further including a first dummy pattern, the first dummy pattern being located on a side of the first resistor facing the display area, a side of the first resistor away from the display area, a side of the second resistor facing the display area, and a side of the second resistor away from the display area. The structure of the first dummy pattern is substantially the same as the structures of the first resistor and the second resistor.

11. The array substrate according to claim 10, wherein, The common electrode line, the input signal line, the reference signal line, the detection signal line, the second electrode plate of the capacitor, the first resistor, the second resistor, the first dummy pattern are disposed on the same layer as the gate of the transistor, and the first electrode plate of the capacitor is disposed on the same layer as the first and second poles of the transistor.

12. The array substrate according to any one of claims 6 to 11, wherein, Further including a second dummy pattern located in the receiving groove, the second dummy pattern being disposed in a space surrounded by the input signal line, the reference signal line, and the capacitor.

13. The array substrate according to claim 12, wherein, The second dummy pattern is disposed on the same layer as the gate of the transistor.

14. The array substrate according to claim 12 or 13, wherein, The common electrode line, the input signal line, the reference signal line, and the second dummy pattern respectively include a plurality of hollow structures.

15. The array substrate according to any one of claims 3 to 5, wherein, The opening of the accommodation groove faces the display area; The array substrate further includes a fan-out line located between the common electrode line and the display area, and the input signal line and the reference signal line are located between the fan-out line and the common electrode line.

16. The array substrate according to claim 15, wherein, It further includes a control signal line located between the input signal line and the reference signal line; The sensor circuit further includes a second transistor. The gate of the second transistor is coupled to the control signal line, the first pole of the second transistor is coupled to the first electrode plate of the capacitor, the second pole of the second transistor is coupled to the second electrode plate of the capacitor, and the channel width-to-length ratio of the second transistor is greater than that of the first transistor.

17. The array substrate according to claim 16, wherein, The sensor circuit further includes a third transistor. The gate of the third transistor is coupled to the reference signal line, the first pole of the third transistor is coupled to the second electrode plate of the capacitor, and the second pole of the third transistor is coupled to the reference signal line.

18. The array substrate according to claim 17, wherein, The first transistor, the second transistor, and the third transistor are arranged side by side on the same side of the capacitor.

19. The array substrate according to claim 17 or 18, wherein, The first pole of the first transistor, the second pole of the first transistor, the first pole of the second transistor, the second pole of the second transistor, the first pole of the third transistor, and the second pole of the third transistor are comb-shaped electrodes or block electrodes; the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are block electrodes or include a plurality of interconnected island-shaped electrodes.

20. The array substrate according to any one of claims 2 to 19, wherein, It further includes a switching transistor located in the display area, and the ratio of the channel width-to-length ratio of the first transistor to that of the switching transistor is greater than or equal to 50.

21. The array substrate according to any one of claims 1 to 20, wherein, The non-display area includes a plurality of bonding areas, and the sensor circuit is located between the bonding area and the display area, and / or the sensor circuit is located between the gap adjacent to the bonding area and the display area.

22. A display panel, wherein, It includes the array substrate according to any one of claims 1 to 21, and an opposing substrate disposed opposite to the array substrate.

23. A display device, wherein, It includes the display panel according to claim 22, and a backlight module located on the light incident side of the display panel.

24. A driving method of a display panel as described in claim 22, wherein, It includes: Monitoring the panel temperature by using a sensor circuit; Generating driving parameters according to the panel temperature, and controlling the display panel to perform picture display by using the driving parameters.

25. The driving method according to claim 24, wherein, Monitoring the panel temperature by using a sensor circuit, specifically including: At a fixed moment after the first transistor is turned on each time, collecting the voltage at the connection point of the first resistor and the second resistor, and judging the panel temperature according to the collected voltage.

26. The driving method according to claim 24, wherein, Monitoring the panel temperature by using a sensor circuit, specifically including: During the process of turning on the first transistor each time, judging the panel temperature by monitoring the charging peak current of the capacitor.

27. The driving method according to claim 26, wherein, After monitoring the panel temperature by using the sensor circuit, it further includes: turning on the second transistor to discharge the capacitor.

Images