Analog-to-digital converter apparatus and analog foreground correction method

Abstract

Provided in the present application are an analog-to-digital converter apparatus and an analog foreground correction method. The apparatus comprises: a capacitor array, which comprises a quantization capacitor array and an array of capacitors to be corrected; a comparator circuit, which is configured to compare an output voltage of the capacitor array with a predetermined voltage and output a comparison result; and a logic control circuit, which is configured to control, within a correction time period, a ground voltage to be sequentially and electrically connected to each capacitor to be corrected in the array of capacitors to be corrected from a least significant bit to a most significant bit, generate, on the basis of a corresponding comparison result output by the comparator circuit, an error code of each capacitor to be corrected, control, within a quantization time period, a common-mode voltage to be input into the capacitor array, and obtain a correction code on the basis of the corresponding comparison result output by the comparator circuit and the error code, and control, on the basis of the correction code, a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected to the ground voltage or a reference voltage, wherein the sum of the weights of the plurality of target quantization capacitors is equal to the correction code.

Description

Analog-to-digital converter device and analog front-end calibration method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 26, 2024, with application number 202410115779.5 and application name “Analog-to-digital converter device and analog front-end correction method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of analog-to-digital converters, and in particular to an analog-to-digital converter device and an analog foreground correction method. Background Art

[0003] When a SAR ADC (Successive Approximation Register Analog to Digital Converter) is operating, capacitor mismatch in its CDAC (Capacitance Digital to Analog Converter) can cause the actual capacitor weights to deviate from their ideal values. This can result in errors greater than 1 LSB (Least Significant Bit), or even tens of LSBs, affecting the SAR ADC's accuracy. Correction algorithms aim to reduce the impact of capacitor mismatch and increase the effective bit count of the SAR ADC. Correction algorithms are generally categorized in two ways: one based on the amount of correction change, which can be divided into analog and digital correction; the other based on the phase of the correction operation, which can be divided into foreground and background correction.

[0004] Traditional analog front-end correction targets CDAC mismatches in binary search algorithms. This involves two CDACs: one main CDAC for traditional SAR ADCs and the other a correction CDAC. The correction CDAC stores capacitor mismatch values ​​within a certain range and is connected to the main CDAC via a series capacitor. This correction method is only applicable to SAR ADCs using binary search algorithms and requires an additional correction capacitor array. The correction algorithm is complex and consumes significant power. Summary of the Invention

[0005] In view of the above problems, the present application provides an analog-to-digital converter device and an analog foreground calibration method.

[0006] In the first aspect, an embodiment of the application provides an analog-to-digital converter device, comprising: a capacitor array, comprising a quantization capacitor array and a capacitor array to be corrected; a comparator circuit, wherein the input end of the comparator circuit is electrically connected to the upper plate of the capacitor array, configured to compare the output voltage of the capacitor array with a predetermined voltage and output a comparison result; a logic control circuit, configured to: during a correction period, control the ground voltage to be electrically connected to each capacitor to be corrected in the capacitor array to be corrected from low to high in sequence; and generate an error code for each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and during a quantization period, control the common mode voltage to be input to the capacitor array, and obtain a correction code according to the corresponding comparison result and error code output by the comparator circuit; and control multiple target quantization capacitors in the quantization capacitor array to be electrically connected to the ground voltage or the reference voltage according to the correction code, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0007] In one possible embodiment, the upper plate of the capacitor of the capacitor array is connected to the input terminal of the signal to be quantized via a bootstrap switch, and the lower plate of the capacitor array is electrically connected to the logic control circuit, so that the logic control circuit controls one of the reference voltage, the common-mode voltage and the ground voltage to be electrically connected to the lower plate of each capacitor in the capacitor array, wherein the voltage value of the common-mode voltage is half the voltage value of the reference voltage.

[0008] In a possible embodiment, the array of capacitors to be corrected includes N capacitors to be corrected, and the weights of the capacitors to be corrected from the first to the Nth are gradually reduced; the array of quantized capacitors includes M quantized capacitors, and the weights of the capacitors to be corrected from the first to the Mth are gradually reduced, and the weight of the capacitor to be corrected at the Nth position is greater than that of the capacitor to be corrected at the first position, and both N and M are integers greater than 1; the correction period includes the first correction period to the Nth correction period; the logic control circuit is further configured to: in the nth correction period, n is greater than or equal to 1 and less than or equal to N, the control ground voltage is electrically connected to the lower plate of the capacitor to be corrected at the N-n+1th position, and M+1 comparison results are sequentially obtained from the output end of the comparator circuit, wherein, when the m-th comparison result is obtained, one of the ground voltage and the reference voltage is controlled to be electrically connected to the lower plate of the m-th quantization capacitor, and the M+1-th comparison result is obtained after the M-th quantization capacitor is controlled to be electrically connected according to the M-th comparison result, where m is greater than or equal to 1 and less than or equal to M; the actual weight of the N-n+1-th capacitor to be corrected is calculated based on the weights of the M quantization capacitors and the M+1 comparison results; and the error code of the N-n+1-th capacitor to be corrected is calculated based on the actual weight and the ideal weight of the N-n+1-th capacitor to be corrected.

[0009] In a possible embodiment, the logic control circuit is configured to: perform a reset operation before the nth correction period, the reset operation including electrically connecting the bottom plates of all capacitors in the capacitor array and the comparator input terminal to the common mode voltage.

[0010] In one possible embodiment, the logic control circuit is configured as follows: during the nth correction period, when the output voltage of the capacitor array is lower than a predetermined voltage, the mth bit output result of the comparator circuit is 0, and the control reference voltage is connected to the lower plate of the mth bit quantization capacitor; when the output voltage of the capacitor array is higher than the predetermined voltage, the mth bit output result of the comparator circuit is 1, and the control ground voltage is connected to the lower plate of the mth bit quantization capacitor.

[0011] In one possible embodiment, the logic control circuit is configured as follows: when an error code of the N-n+1th capacitor to be corrected is obtained in the nth correction period, the N-n+1th capacitor to be corrected is used as the new first-bit quantized capacitor to obtain the M+n-bit quantized capacitor; and when an error code of the first-bit capacitor to be corrected is obtained in the Nth correction period, the first-bit quantized capacitor to the N-1th quantized capacitor is restored to the second-bit capacitor to be corrected to the Nth capacitor to be corrected.

[0012] In one possible embodiment, the quantization period includes the 1st quantization period to the Nth quantization period, and the logic control circuit is further configured to, during the nth quantization period, control one of the ground voltage and the reference voltage to be electrically connected to the lower plate of the nth capacitor to be corrected according to the nth comparison result obtained from the comparator circuit; calculate the correction code of the nth capacitor to be corrected based on the error code of the nth capacitor to be corrected, the correction code of the n-1th capacitor to be corrected and the nth comparison result; and control the ground voltage to be electrically connected to the lower plates of multiple target quantization capacitors in the quantization capacitor array according to the correction code, for correcting the nth capacitor to be corrected, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0013] In one possible embodiment, the logic control circuit is configured to obtain a first-bit comparison result from the comparator circuit during a first quantization period, control one of a ground voltage and a reference voltage to be electrically connected to a lower plate of the first-bit capacitor to be corrected; and calculate a correction code for the first-bit capacitor to be corrected based on an error code of the first-bit capacitor to be corrected and the first-bit comparison result.

[0014] In one possible embodiment, the logic control circuit is configured as follows: during the nth quantization period, when the output voltage of the capacitor array is lower than a predetermined voltage, the nth bit output result of the comparator circuit is 0, and the control reference voltage is connected to the lower plate of the nth capacitor to be corrected; when the output voltage of the capacitor array is higher than the predetermined voltage, the nth bit output result of the comparator circuit is 1, and the control ground voltage is connected to the lower plate of the nth capacitor to be corrected.

[0015] In one possible embodiment, the capacitor array includes a first capacitor array and a second capacitor array, and the specifications of the first capacitor array and the second capacitor array are completely consistent; the upper plate of the first capacitor array is electrically connected to the positive input terminal of the comparator circuit, and the upper plate of the second capacitor array is electrically connected to the negative input terminal of the comparator circuit;

[0016] In one possible embodiment, the logic control circuit is configured to: in a correction period, sequentially obtain error codes of the first capacitor array and the second capacitor array; in a quantization period, sequentially correct the first capacitor array and the second capacitor array based on the error code and a comparison result output by the comparator circuit.

[0017] In the second aspect, an embodiment of the present application provides an analog foreground correction method, including: a logic control circuit controls the ground voltage to be electrically connected to each capacitor to be corrected in the capacitor array to be corrected from low to high in sequence; the logic control circuit generates an error code for each capacitor to be corrected based on the comparison result output by the comparator circuit, wherein the comparator circuit compares the output voltage of the capacitor array with the preset voltage and outputs the comparison result, and the capacitor array includes a capacitor array to be corrected and a quantization capacitor array; the logic control circuit controls the common mode voltage to be input to the capacitor array; the logic control circuit obtains a correction code based on the comparison result and error code output by the comparator circuit; the logic control circuit controls multiple target quantization capacitors in the quantization capacitor array to be electrically connected to the ground voltage or the reference voltage based on the correction code, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0018] In a possible embodiment, the method further includes:

[0019] The logic control circuit performs a reset operation on the capacitor array;

[0020] The logic control circuit calculates the error code of the capacitor to be corrected based on the comparison result and the quantized capacitor array;

[0021] The logic control circuit updates the weight of the capacitor to be corrected, uses the capacitor to be corrected as the first quantized capacitor of the quantized capacitor array, and determines the error codes of all the capacitors to be corrected;

[0022] The logic control circuit performs weight compensation on the to-be-corrected capacitance by controlling the low-order capacitance in the quantized capacitance array based on the error code.

[0023] In a possible embodiment, the method further includes:

[0024] Based on the weights of the M quantized capacitors and the M+1 comparison results, the actual weight of the N-n+1th capacitor to be corrected is calculated, where N and M are both integers greater than 1;

[0025] An error code of the (N-n+1)th capacitor to be corrected is calculated based on the actual weight and the ideal weight of the (N-n+1)th capacitor to be corrected.

[0026] The analog-to-digital converter device and the analog foreground correction method provided by the embodiment of the present application include: a capacitor array, including a quantized capacitor array and a capacitor array to be corrected; a comparator circuit configured to compare the output voltage of the capacitor array with a predetermined voltage and output a comparison result; a logic control circuit configured to: during the correction period, control the ground voltage to be electrically connected to each capacitor to be corrected in the capacitor array from low to high in sequence; and generate an error code for each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit; and during the quantization period, control the common mode voltage to be input to the capacitor array, obtain a correction code according to the corresponding comparison result and error code output by the comparator circuit; and control the multiple target quantized capacitors in the quantized capacitor array to be electrically connected to the ground voltage or the reference voltage according to the correction code, wherein the sum of the weights of the multiple target quantized capacitors is equal to the correction code. The embodiment of the present application does not require an additional correction capacitor array, the correction algorithm is simple, and the power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0028] FIG1A schematically shows a block diagram of an analog-to-digital converter device according to an embodiment of the present application;

[0029] FIG1B schematically shows another structural block diagram of an analog-to-digital converter device according to an embodiment of the present application;

[0030] FIG1C schematically shows a block diagram of a capacitor array in an analog-to-digital converter device according to an embodiment of the present application;

[0031] FIG2 schematically shows a flow chart of a capacitor array of an analog-to-digital converter device during a calibration period according to an embodiment of the present application;

[0032] FIG3A schematically shows a structural block diagram of a capacitor array of an analog-to-digital converter device according to an embodiment of the present application during a quantization period;

[0033] FIG3B schematically shows a flow chart of an analog-to-digital converter device according to an embodiment of the present application during a quantization period;

[0034] FIG4A schematically shows a simulation result diagram of an analog-to-digital converter device according to an embodiment of the present application without calibration;

[0035] FIG4B schematically shows a simulation result diagram of the analog-to-digital converter device according to an embodiment of the present application when digital correction is performed;

[0036] FIG4C schematically shows a simulation result diagram of an analog-to-digital converter device according to an embodiment of the present application when the analog-to-digital converter device is calibrated using an analog foreground calibration method;

[0037] FIG5 schematically shows a flow chart of a simulated foreground correction method according to an embodiment of the present application;

[0038] FIG6 schematically shows another flow chart of the simulated foreground correction method according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0040] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0041] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0042] When expressions such as "at least one of A, B and C, etc." are used, they should generally be interpreted in accordance with the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0043] An embodiment of the present application provides an analog-to-digital converter device, comprising: a capacitor array, including a quantization capacitor array and a capacitor array to be corrected; a comparator circuit, wherein the input end of the comparator circuit is electrically connected to the upper plate of the capacitor array, and is configured to compare the output voltage of the capacitor array with a predetermined voltage and output a comparison result; a logic control circuit, configured to: during a correction period, control the ground voltage to be electrically connected to each capacitor to be corrected in the capacitor array to be corrected in sequence from low to high; and generate an error code for each capacitor to be corrected based on the corresponding comparison result output by the comparator circuit; and during a quantization period, control the common mode voltage to be input to the capacitor array, obtain a correction code based on the corresponding comparison result and error code output by the comparator circuit; and control multiple target quantization capacitors in the quantization capacitor array to be electrically connected to the ground voltage or the reference voltage based on the correction code, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0044] 1A-1C schematically illustrate a structural block diagram of an analog-to-digital converter device according to an embodiment of the present application.

[0045] As shown in FIG. 1A , the analog-to-digital converter device 10 of this embodiment includes a capacitor array 11 , a comparator circuit 12 , and a logic control circuit 13 .

[0046] The capacitor array 11 includes a quantized capacitor array and a capacitor array to be corrected.

[0047] The positive input terminal of the comparator circuit 12 is electrically connected to the upper plate of the capacitor array 11, and the negative input terminal of the comparator circuit is input with a predetermined voltage. The comparator circuit compares the output voltage of the capacitor array with the predetermined voltage and outputs the comparison result.

[0048] The logic control circuit receives the comparison result of the comparator circuit and controls the connection of the capacitor array based on the comparison result. During the correction period, the ground voltage is controlled to be electrically connected to each capacitor to be corrected in the capacitor array from the lowest to the highest position; an error code is generated for each capacitor to be corrected based on the corresponding comparison result output by the comparator circuit; and during the quantization period, the common mode voltage is controlled to be input to the capacitor array, and a correction code is obtained based on the corresponding comparison result and the error code output by the comparator circuit; and based on the correction code, multiple target quantization capacitors in the quantization capacitor array are controlled to be electrically connected to the ground voltage, where the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0049] The analog-to-digital converter device in the present application includes two working stages: a correction stage and a quantization stage. In the correction stage, the SAR ADC measures and stores the mismatch of the high-order capacitor array through the low-order capacitor array; in the normal working stage, the mismatch stored in the correction stage is converted into an analog quantity through the correction CDAC and superimposed on the high-order capacitor array quantization process, thereby eliminating the mismatch of the high-order capacitor array. Compared with the traditional correction method, the present application does not require an additional correction capacitor array, saves area, and eliminates the step of switching back and forth to generate an error voltage. The correction logic is simple and the power consumption is low.

[0050] FIG1B schematically shows another structural block diagram of an analog-to-digital converter device according to an embodiment of the present application.

[0051] As shown in FIG1B , the upper plate of the capacitor array is connected to the common mode voltage V via the bootstrap switch. CM The lower plate of the capacitor array is electrically connected to the logic control circuit 13 through a multiplexer. The logic control circuit controls the sampling signal V through the multiplexer based on the comparison result output by the comparator circuit. IN , reference voltage V REF , ground voltage GND and common mode voltage V CM One of them is electrically connected to the lower plate of each capacitor in the capacitor array, wherein the common mode voltage V CM The voltage value is the reference voltage V REF One-half of the voltage value.

[0052] FIG1C schematically shows a structural block diagram of a capacitor array in an analog-to-digital converter device according to an embodiment of the present application.

[0053] As shown in FIG1C , the capacitor array 11 includes a quantized capacitor array 11_1 and a capacitor array to be corrected 11_2 .

[0054] The to-be-corrected capacitor array 11_2 may include N to-be-corrected capacitors, with weights gradually decreasing from the first to-be-corrected capacitor to the Nth to-be-corrected capacitor; the quantized capacitor array 11_1 may include M quantized capacitors, with weights gradually decreasing from the first to the Mth quantized capacitor, and the weight of the Nth to-be-corrected capacitor is greater than the weight of the first quantized capacitor, and the weights of all to-be-corrected capacitors and quantized capacitors satisfy a sub-binary condition, where N and M are both integers greater than 1. The sub-binary condition means that, in ascending order of weight, the sum of the weights of the first i capacitors is greater than the weight of the (i+1)th capacitor.

[0055] All capacitors in the capacitor array 11 are divided into high-order capacitors and low-order capacitors according to the capacitance weight, and the high-order capacitors and the low-order capacitors are connected by a bridge capacitor C BR Spaced apart, located at C BRThe capacitor on the left is the low-position capacitor, located at C BR The capacitor on the right is a high-order capacitor. The capacitance weight corresponding to all capacitors in the capacitor array from right to left gradually decreases, wherein the capacitor array 11_2 to be corrected is selected and composed from the high-order capacitors, which are usually several high-order capacitors with the largest capacitance weights. Because the high-order capacitors have a large weight, the impact on ENOB (Effective Number of Bits, effective number of bits) is relatively large when there is a capacitor mismatch, so correction is required. The number of bits of the capacitor to be corrected is not a fixed value, and can be modeled by using simulation tools such as Matlab, and adding capacitor mismatch as an influencing factor. It is better to judge the number of bits of the capacitor to be corrected by simulation verification when the correction effect is better.

[0056] For example, in the 14-bit 20-step SAR ADC used in the embodiment of the present application, the top five high-order capacitors with the highest weight values ​​are selected as the capacitor array to be calibrated, and the remaining high-order capacitors and all low-order capacitors are used as the quantized capacitor array. The weights of all capacitors are arranged as shown in the following table:

[0057] Table 1 Capacitor weight table

[0058] Among them, MSB refers to the high-bit capacitance, and LSB refers to the low-bit capacitance. CM10-CM6 are the 1st to 5th capacitors to be corrected, and CM5-CM1 and CL9-CL1, a total of 14 capacitors, are the 1st to 14th quantized capacitors. Since the CDAC in the 14-bit 20stepSAR ADC is an 8+6 structure, 8 bits refer to the effective number of bits of the high-bit capacitance and 6 bits refer to the effective number of bits of the low-bit capacitance, and because the VCM-based switching method is used, the most significant bit of the capacitance is omitted, so the number of unit capacitors used in the high-segment capacitance array is 2. 7 =128, the number of unit capacitors used in the low-end capacitors is 2 6 -1 = 63, the bridge capacitor is 1 unit capacitor, and the total number of capacitors is 128 + 63 + 1 = 192. The distribution of capacitance values ​​is based on binary splitting and reorganization.

[0059] For example, the sum of the capacitance values ​​of the nine low-order capacitors CL1-CL9 in the table is 63. Based on the six-bit binary representation of 1, 2, 4, 8, 16, and 32, we divide 2 into 1 and 1, 8 into 2 and 6, and 32 into 10 and 22. The undivided digits and the resulting divisors are recombined to yield 1, 1, 1, 2, 4, 6, 10, 16, and 22 as the capacitance values ​​of the nine low-order capacitors. The method for dividing the high-order capacitors is the same as for the low-order capacitors and is not repeated here.

[0060] As shown in the table above, the difference between the capacitance values ​​of high-order capacitors and low-order capacitors is small, but the difference in weight values ​​is large. The weight value can be adjusted by bridging capacitors. The role of the bridging capacitor is to add a weight coefficient to the weight of the low-order capacitor. C LSB Refers to the sum of the capacitance values ​​of the low-level capacitors, C BR It refers to the capacitance value of the bridge capacitor. Therefore, in this application, the weight coefficient of the low-order capacitance weight value is 1 / 64. When each unit capacitance value of the high-order capacitance corresponds to 64 weight values, each unit capacitance value of the low-order capacitance corresponds to 1 weight value.

[0061] The comparator circuit 12 is configured to compare the output voltage of the capacitor array with a predetermined voltage and output a comparison result, with the input terminal of the comparator circuit being electrically connected to the output terminal of the capacitor array.

[0062] When the output voltage is less than the preset voltage, the comparison result is 0, and when the output voltage is greater than the preset voltage, the comparison result is 1. The preset voltage can be the common mode voltage V CM , or it can be preset.

[0063] As shown in FIG. 1A , the comparator circuit may be a differential comparator circuit including a two-terminal input, where the two input terminals are respectively connected to the output terminal of the capacitor array and a preset voltage.

[0064] As shown in Figure 1B, in an embodiment of the present application, the two input terminals of the comparator circuit are electrically connected to the P terminal and the N terminal of the capacitor array, respectively. When the capacitor array at the P terminal is calibrated and quantized, the lower plates of all capacitors at the N terminal are electrically connected to the common mode voltage, and the output voltage at the N terminal can be equivalent to a constant value, which is the same as the common mode voltage. The comparator circuit can also include a two-terminal output, and the comparison results of the two output terminals OUTP and OUTN are different each time they are output. When the comparison result output by one output terminal is 1, the comparison result of the other output terminal is 0. When the input voltage at the P terminal of the capacitor array is input, the comparator circuit uses the output of the output terminal OUTP as the comparison result.

[0065] The logic control circuit 13 can be divided into a correction period and a quantization period.

[0066] During the correction period, the logic control circuit is configured to: control the ground voltage to be electrically connected to each capacitor to be corrected in the capacitor array from low to high; and generate an error code for each capacitor to be corrected according to the corresponding comparison result output by the comparator circuit.

[0067] During the quantization period, the logic control circuit is configured to: control the common-mode voltage input to the capacitor array, obtain a correction code based on the corresponding comparison result and error code output by the comparator circuit; and control the electrical connection of multiple target quantization capacitors in the quantization capacitor array to the ground voltage based on the correction code, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

[0068] In some embodiments of the present application, the capacitor array may include a first capacitor array and a second capacitor array. As shown in Figures 1B and 1C, the capacitor array is divided into a first capacitor array P-end and a second capacitor array N-end, the P-end is the upper half of the capacitor array, and the N-end is the lower half of the capacitor array. The specifications of the first capacitor array and the second capacitor array are exactly the same. The upper plate of the first capacitor array is electrically connected to the positive input terminal of the comparator circuit, and the upper plate of the second capacitor array is electrically connected to the negative input terminal of the comparator circuit. The logic control circuit is configured as follows: in the correction period, the error codes of the first capacitor array and the second capacitor array are obtained in sequence; in the quantization period, the first capacitor array and the second capacitor array are corrected in sequence based on the comparison result of the error code and the comparator circuit output.

[0069] The two output terminals of the comparator circuit respectively output the comparison result OUTP of the first capacitor array terminal and the comparison result OUTN of the second capacitor array segment. When the first capacitor array is quantized and corrected, the lower plates of all capacitors in the second capacitor array are connected to the common mode voltage V CM The electrical connection is equivalent to connecting the output voltage of the first capacitor array to the common mode voltage V CM The comparison is performed, and the comparison result output by the comparator circuit is consistent with OUTP; when the second capacitor array is quantized and corrected, the lower plates of all capacitors in the first capacitor array are aligned with the common mode voltage V CM The electrical connection is equivalent to connecting the output voltage of the second capacitor array to the common mode voltage V CM The comparison result output by the comparator circuit is consistent with OUTN. The calibration principles of the first capacitor array and the second capacitor array are completely consistent and can be performed independently.

[0070] The analog-to-digital converter device in this application uses a SAR ADC with a segmented capacitor array. After the chip is powered on and before normal operation, capacitor mismatch is eliminated in the analog domain. This is suitable for SAR ADCs using non-binary search algorithms, does not require specific capacitor weight distribution, and is highly flexible. Compared with traditional methods, this application does not require an additional correction capacitor array, saving area and eliminating the step of switching back and forth to generate error voltage. The correction logic is simple and power consumption is low.

[0071] FIG2 schematically shows a flow chart of a capacitor array of an analog-to-digital converter device during a calibration period according to an embodiment of the present application.

[0072] The correction period includes the first correction period to the Nth correction period. In the nth correction period, the (N-n+1)th capacitor to be corrected is measured and the error code is stored, and error codes of N capacitors to be corrected are obtained in total within the correction period.

[0073] In an embodiment of the present application, the logic control circuit is further configured as follows: during the nth correction period, n is greater than or equal to 1 and less than or equal to N, the ground voltage is controlled to be electrically connected to the lower plate of the (N-n+1)th capacitor to be corrected, and the M+1 comparison results are obtained in sequence from the output end of the comparator circuit, wherein, when the mth comparison result is obtained, one of the ground voltage and the reference voltage is controlled to be electrically connected to the lower plate of the mth quantization capacitor, and the M+1th comparison result is obtained after the Mth quantization capacitor is controlled to complete the electrical connection according to the Mth comparison result, and m is greater than or equal to 1 and less than or equal to M; the actual weight of the (N-n+1)th capacitor to be corrected is calculated based on the weights of the M quantization capacitors and the M+1 comparison results; and the error code of the (N-n+1)th capacitor to be corrected is calculated based on the actual weight and ideal weight of the (N-n+1)th capacitor to be corrected.

[0074] For example, the device of the present application includes 5 capacitors to be corrected and 14 quantized capacitors. During the first correction period, the ground voltage GND is controlled to be electrically connected to the lower plate of the 5th capacitor to be corrected. At this time, the input voltage of the input terminal electrically connected to the capacitor array in the comparator circuit changes, resulting in a voltage difference between the two input terminals. The comparator circuit outputs the first comparison result based on the voltage magnitude of the two input terminals. The logic control circuit controls the multiplexer based on the first comparison result to select the reference voltage or the ground voltage to be electrically connected to the lower plate of the 1st quantized capacitor. Repeat the two steps of obtaining the comparison result and controlling the connection of the quantized capacitor until a total of M comparison results are obtained and the connection of the M-bit quantized capacitor is completed. The M+1th comparison result is obtained and the first correction period ends. Wherein, when the output voltage of the capacitor array is lower than the predetermined voltage, the mth bit output result of the comparator circuit is 0, and the control reference voltage is connected to the lower plate of the mth quantized capacitor; when the output voltage of the capacitor array is higher than the predetermined voltage, the mth bit output result of the comparator circuit is 1, and the control ground voltage is connected to the lower plate of the mth quantized capacitor.

[0075] In the embodiment of the present application, the actual weight of the N-n+1th capacitor to be corrected is calculated based on the weights of the M quantized capacitors and the M+1 comparison results, and the error code of the N-n+1th capacitor to be corrected is calculated based on the actual weight and ideal weight of the N-n+1th capacitor to be corrected. The specific process is as follows: Actual weight = ∑(1-2×D i )×the i-th quantized capacitor weight+D M+1 ;

[0076] Among them, Di is the comparison result of the i-th bit, D M+1 is the comparison result for the M+1th bit. Taking the 5th quantized capacitor as an example, the comparison result determines the sign of the corresponding quantized capacitor weight value. For example, the quantized capacitor array weights are [256, 128, 64, 64, 64, 22, 16, 10, 6, 4, 2, 1, 1, 1], and the comparison results are [0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1]. The actual weight of the 5th capacitor is 379. The weight sequence is [256, 128, -64, 64, -64, 22, 16, 10, 6, 4, 2, -1, -1, -1]. Summing the weight sequence and the M+1th comparison result yields the error code for the 5th capacitor, which is equal to the actual weight minus the ideal weight: 379 - 384 = -5. The logic control circuit stores the error code in binary code.

[0077] In an embodiment of the present application, when an error code of the N-n+1th capacitor to be corrected is obtained in the nth correction period, the N-n+1th capacitor to be corrected is used as the new first-bit quantized capacitor to obtain the M+n-bit quantized capacitor; and when an error code of the first-bit capacitor to be corrected is obtained in the Nth correction period, the first-bit quantized capacitor to the N-1th quantized capacitor are restored to the second-bit capacitor to be corrected to the Nth capacitor to be corrected.

[0078] For example, after calculating the error code for the fifth capacitor to be corrected during the first correction period, the fifth capacitor to be corrected becomes the new first quantized capacitor in the quantized capacitor array. The calculated actual weight is used as the weight of the first quantized capacitor. The weights of the 14 quantized capacitors in the original quantized capacitor array remain unchanged and become the second to fifteenth quantized capacitors. When quantizing the fourth quantized capacitor, the weights of each quantized capacitor in the quantized capacitor array are: [379, 256, 128, 64, 64, 64, 22, 16, 10, 6, 4, 2, 1, 1, 1].

[0079] The logic control circuit is configured to perform a reset operation before the nth correction period, wherein the reset operation includes electrically connecting the lower plates of all capacitors in the capacitor array and the comparator input terminals to the common mode voltage.

[0080] As shown in Figure 2, during the correction period, the first step is to electrically connect the lower plates of all capacitors in the capacitor array to the common mode voltage to change to a reset state; the second step is the first correction period, in which the lower plate of the fifth capacitor to be corrected is electrically connected to the ground voltage, and the actual weight and error code of the fifth capacitor to be corrected are calculated based on the comparison result and the weight of the quantized capacitor; the third step continues to electrically connect the lower plates of all capacitors in the capacitor array to the common mode voltage to restore to the reset state; the fourth step is the second correction period, in which the fifth capacitor to be corrected is used as a quantized capacitor, and the fourth capacitor to be corrected is electrically connected to the ground voltage for correction; the reset operation and the correction operation are repeated until the actual capacitance and error code of the first capacitor to be corrected are calculated.

[0081] FIG3A schematically shows a structural block diagram of a capacitor array of an analog-to-digital converter device during a quantization period according to an embodiment of the present application.

[0082] FIG3B schematically shows a flow chart of an analog-to-digital converter device in a quantization period according to an embodiment of the present application.

[0083] As shown in FIG3A , the frame represents the low-order capacitors in the quantization capacitor array. During the quantization period, the capacitors to be corrected are corrected and compensated using the low-order capacitors by controlling the lower plates of the capacitors in the frame.

[0084] The quantization period includes a first quantization period to an Nth quantization period. The logic control circuit is further configured to, during the nth quantization period, control one of a ground voltage and a reference voltage to be electrically connected to the lower plate of the nth capacitor to be corrected based on the nth comparison result obtained from the comparator circuit; calculate a correction code for the nth capacitor to be corrected based on the error code of the nth capacitor to be corrected, the correction code of the n-1th capacitor to be corrected, and the nth comparison result; and control the ground voltage or the reference voltage to be electrically connected to the lower plates of multiple target quantization capacitors in the quantization capacitor array based on the correction code, for correcting the nth capacitor to be corrected, wherein the sum of the weights of the multiple target quantization capacitors is equal to the correction code, and n is an integer greater than 0 and less than or equal to N.

[0085] In addition, during the first quantization period, the first comparison result is obtained from the comparator circuit, and one of the control ground voltage and the reference voltage is electrically connected to the lower plate of the first capacitor to be corrected; and the correction code of the first capacitor to be corrected is calculated based on the error code of the first capacitor to be corrected and the first comparison result.

[0086] In the embodiment of the present application, the quantization period is performed during the normal working period of the SAR ADC, and the lower plates of the first capacitor array and the second capacitor array are electrically connected to the input voltage V INN and V INP After the SAR ADC acquires the input signal and completes the signal sampling process, the lower plates of all capacitors are electrically connected to the common mode voltage V CM, enters the quantization period, and quantizes the sampled input signal. At this time, in the first capacitor array and the second capacitor array, the capacitors are electrically connected to the ground voltage and the reference voltage in opposite situations. For example, when the first comparison result is 1, as shown in FIG3A , the first capacitor to be corrected in the first capacitor array is connected to the ground voltage, while the first capacitor to be corrected in the second capacitor array is connected to the reference voltage; when the correction code of the first capacitor array is a positive number, the logic control circuit controls the lower plate of the target quantized capacitor in the first capacitor array to be electrically connected to the reference voltage, and when the correction code of the second capacitor array is a positive number, the logic control circuit controls the lower plate of the target quantized capacitor in the second capacitor array to be electrically connected to the ground voltage.

[0087] As shown in FIG. 3B , the analog-to-digital converter apparatus of this embodiment includes operations S301 to S311 during a quantization period.

[0088] In operation S301, the comparator circuit outputs a first comparison result, and one of a control ground voltage and a reference voltage is electrically connected to the lower plate of the first capacitor to be calibrated.

[0089] In operation S302, a calibration code DOS1 of the first-bit capacitor to be calibrated is calculated according to the comparison result of the first bit. Operation S303 or operation S304 is selected based on the comparison result.

[0090] In operation S303 , when the comparison result is 1, the correction code DOS1 = Diff1 , and the control ground voltage is electrically connected to the lower plate of the first capacitor to be corrected.

[0091] In operation S304 , when the comparison result is 0, the correction code DOS1 =−Diff1 , and the reference voltage is controlled to be electrically connected to the lower plate of the first capacitor to be corrected.

[0092] In operation S305, the first capacitor to be corrected is corrected and compensated according to the first correction code. The logic control circuit selects part of the capacitors in the quantized capacitor array as target quantized capacitors based on the correction code, and controls the lower plate of the target quantized capacitor to be electrically connected to the ground voltage or the reference voltage to achieve quantization of the capacitor to be corrected. The correction code and the lower plate access state of each quantized capacitor in the quantized capacitor array are in a one-to-one correspondence. The correction code is pre-set and stored in the logic control circuit. When the correction code is obtained, the quantized capacitor that needs to be electrically connected to the ground voltage or the reference voltage is selected as the target quantized capacitor. The target quantized capacitor is directly controlled by the logic control circuit, and the sum of the weights of the target quantized capacitor is equal to the calibration code. When the correction code is a positive number, the target quantized capacitor is electrically connected to the reference voltage, and when the correction code is a negative number, the target quantized capacitor is electrically connected to the ground voltage.

[0093] In operation S306 , the comparator circuit outputs an n-th comparison result, where n is an integer greater than 1 and less than N.

[0094] In operation S307, a correction code DOSn of the n-th capacitor to be corrected is calculated according to the n-th comparison result, and operation S308 or operation S309 is selected based on the comparison result.

[0095] In operation S308 , when the comparison result is 1, the ground voltage is controlled to be electrically connected to the lower plate of the nth capacitor to be corrected, and the correction code DOSn of the nth capacitor to be corrected is DOS(n−1)+Diffn.

[0096] In operation S309 , when the comparison result is 0, the ground voltage is controlled to be electrically connected to the lower plate of the n-th capacitor to be corrected, and the correction code DOSn of the n-th capacitor to be corrected is DOS(n−1)−Diffn.

[0097] For example, after quantizing the first capacitor to be corrected, the comparator circuit outputs a second comparison result. The error code for the second capacitor to be corrected is Diff2. If the comparison result is 1, the ground voltage is controlled to be electrically connected to the lower plate of the second capacitor to be corrected, and the correction code for the second capacitor to be corrected, DOS2, is DOS1 + Diff2. If the comparison result is 0, the reference voltage is controlled to be electrically connected to the lower plate of the second capacitor to be corrected, and the correction code, DOS2, is DOS1 - Diff2.

[0098] In operation S310, the n-th capacitor to be calibrated is quantized according to the n-th calibration code DOSn. Operations S306 to S310 are repeated until the N-bit capacitor to be calibrated completes the quantization of the input signal.

[0099] In operation S311, continue to obtain the comparison results from the N+1th to the N+M+1th bits, and quantize the input signal through the quantization capacitor array. Wherein, when the i-th comparison result is obtained (i is an integer greater than N and less than or equal to N+M), if the corresponding quantization capacitor is the target quantization capacitor, the access state of the target quantization capacitor is re-determined based on the comparison result, and whether to change the access state of the target quantization capacitor is determined based on the current access state of the target quantization capacitor. Wherein, when the comparison result is 1, the target quantization capacitor is electrically connected to the ground voltage, and when the comparison result is 0, the target quantization capacitor is electrically connected to the reference voltage. If the corresponding quantization capacitor is not the target quantization capacitor, the access state is not changed. After the logic control circuit controls the Mth quantization capacitor in the quantization capacitor array to complete the quantization of the input signal, the N+M+1th comparison result is obtained, and the quantization period ends.

[0100] For example, if the comparison result is 1, and the lower plate of the corresponding target quantization capacitor is electrically connected to the reference voltage at this time, the lower plate of the corresponding target quantization capacitor is controlled to be electrically connected to the ground voltage; if the comparison result is 1 and the lower plate of the corresponding target quantization capacitor is electrically connected to the ground voltage at this time, the access state is not changed.

[0101] In an embodiment of the present application, after the quantization capacitor is quantized based on the correction code of the 2nd capacitor to be corrected, the comparison results of the 3rd to 5th bits are continued to be obtained, and the 3rd to 5th capacitors to be corrected are quantized according to the correction codes of the 3rd to 5th bits, and then the comparison results of the 6th to 19th bits are obtained, and the quantization capacitors of the 1st to 14th bits are quantized, and the quantization period ends.

[0102] FIG4A schematically shows a simulation result diagram of an analog-to-digital converter device without calibration.

[0103] As shown in FIG4A , without correction, as the capacitance mismatch coefficient increases, the effective number of bits (ENOB) of the SAR ADC shows a downward trend, indicating that the larger the capacitance mismatch coefficient, the greater the impact on the accuracy of the SAR ADC. Therefore, in order to reduce the impact of capacitance mismatch on the SAR ADC, the SAR ADC needs to be calibrated.

[0104] FIG4B schematically shows a simulation result diagram of the analog-to-digital converter device when only digital correction is performed.

[0105] Figure 4C schematically illustrates a simulation result diagram of an analog-to-digital converter device according to an embodiment of the present application when calibrated using an analog foreground calibration method. In the result diagrams of Figures 4A-4C , the horizontal axis represents the capacitance mismatch coefficient, and the vertical axis represents the effective number of bits (ENOB) of the SAR ADC.

[0106] As shown in Figures 4B and 4C, by comparing the simulation results of the digital correction in Figure 4B and the analog foreground correction performed by the device of the present application in Figure 4C, it can be found that when the capacitance mismatch coefficient is below 0.01, that is, the first half of the broken line in the figure, the effective number of bits of the analog foreground correction performed by the present application is significantly higher than that of the digital correction. This is because the ideal situation for analog correction is to be able to correct to a situation close to 0 mismatch, and 0 mismatch means that the effective number of bits ENOB reaches the ideal value of 13.78bit. In the simulation diagram of the analog foreground correction of the present application in Figure 4C, when the capacitance mismatch coefficient is less than 0.01, the corrected ENOB can be close to 13.78bit. Therefore, when the capacitance mismatch is 1% or less, the analog foreground correction scheme of the present design is better than using digital correction.

[0107] FIG5 schematically shows a flow chart of a simulated foreground correction method according to an embodiment of the present application.

[0108] As shown in FIG5 , the simulated foreground correction method of this embodiment includes operations S501 to S504 .

[0109] In operation S501 , the logic control circuit performs a reset operation on the capacitor array.

[0110] In operation S502 , the logic control circuit calculates an error code of the capacitance to be corrected based on the comparison result and the quantized capacitance array.

[0111] In operation S503 , the logic control circuit updates the weight of the capacitor to be corrected, uses the capacitor to be corrected as the first quantized capacitor of the quantized capacitor array, and repeats operations S501 - S503 until error codes of all capacitors to be corrected are obtained.

[0112] In operation S504 , the logic control circuit performs weight compensation on the to-be-corrected capacitance by controlling the low-bit capacitance in the quantized capacitance array based on the error code.

[0113] FIG6 schematically shows another flow chart of the simulated foreground correction method according to an embodiment of the present application.

[0114] As shown in FIG6 , the simulated foreground correction method of this embodiment includes operations S610 to S650 .

[0115] In operation S610 , the logic control circuit controls the ground voltage to be electrically connected to each capacitor to be calibrated in the capacitor array to be calibrated in sequence from the lowest to the highest.

[0116] In operation S620, the logic control circuit generates an error code for each capacitor to be corrected based on a comparison result output by a comparator circuit, wherein the comparator circuit compares an output voltage of a capacitor array with a preset voltage and outputs a comparison result, and the capacitor array includes a capacitor array to be corrected and a quantized capacitor array.

[0117] In operation S630 , the logic control circuit controls the common mode voltage to be input to the capacitor array.

[0118] In operation S640 , the logic control circuit obtains a correction code according to the comparison result output by the comparator circuit and the error code.

[0119] In operation S650 , the logic control circuit controls a plurality of target quantized capacitors in the quantized capacitor array to be electrically connected to a ground voltage or a reference voltage based on the correction code, wherein a sum of weights of the plurality of target quantized capacitors is equal to the correction code.

[0120] The embodiments of the present application have been described in detail with reference to the accompanying drawings. It should be noted that any implementations not depicted or described in the drawings or the main body of the specification are known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods described in the embodiments, and can be easily modified or replaced by those skilled in the art.

[0121] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in understanding the present application.

[0122] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0123] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0124] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0125] It should be noted that, unless it is clearly stated that there is a sequence of execution between different operations shown in the flowcharts in the embodiments of the present application, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order between multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0126] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general-purpose systems can also be used together with the enlightenment based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the application is not directed to any specific programming language. It should be understood that various programming languages ​​can be utilized to implement the content of the application described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the application.

[0127] The present application can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. The various component embodiments of the present application can be implemented in hardware, or implemented in software modules running on one or more processors, or implemented in a combination thereof. Those skilled in the art will appreciate that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the related equipment according to the embodiments of the present application. The application can also be implemented as a device or apparatus program (e.g., computer program and computer program product) for executing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0128] All modules of the embodiments of the present application may be hardware structures, and the physical implementation of the hardware structure includes but is not limited to physical devices, and the physical devices include but are not limited to transistors and memristors.

[0129] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstract and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose. Furthermore, in a unit claim enumerating a number of devices, several of these devices may be embodied by the same item of hardware.

[0130] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present application, various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed application requires more features than those explicitly recited in each claim. Rather, as reflected in the claims below, the disclosed aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0131] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above is only a specific embodiment of this application and is not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. An analog-to-digital converter device, characterized in that, The device includes: a capacitor array, including a quantization capacitor array and a capacitor array to be calibrated; a comparator circuit, the input end of the comparator circuit being electrically connected to the upper plates of the capacitor array, configured to compare the output voltage of the capacitor array with a predetermined voltage and output a comparison result; a logic control circuit, configured to: during a calibration period, control the ground voltage to be sequentially electrically connected to each capacitor to be calibrated in the capacitor array to be calibrated from low to high; and generate an error code for each capacitor to be calibrated according to the corresponding comparison result output by the comparator circuit; and, during a quantization period, control the common-mode voltage to be input to the capacitor array, obtain a calibration code according to the corresponding comparison result output by the comparator circuit and the error code; and control a plurality of target quantization capacitors in the quantization capacitor array to be electrically connected to the ground voltage or a reference voltage according to the calibration code, wherein the sum of the weights of the plurality of target quantization capacitors is equal to the calibration code.

2. The device according to claim 1, characterized in that The upper plates of the capacitors of the capacitor array are connected to the common-mode voltage via a bootstrap switch, and the lower plates of the capacitor array are electrically connected to the logic control circuit through a multiplexer, so that the logic control circuit controls one of a signal to be sampled, a reference voltage, a ground voltage, and the common-mode voltage to be electrically connected to the lower plates of each capacitor in the capacitor array according to the multiplexer, wherein the voltage value of the common-mode voltage is one-half of the voltage value of the reference voltage.

3. [Corrected according to Rule 26 on 06.03.2025] The device according to claim 2, characterized in that, The capacitor array to be calibrated includes N capacitors to be calibrated, and the weights of the capacitors to be calibrated from the first capacitor to be calibrated to the Nth capacitor to be calibrated gradually decrease; the quantization capacitor array includes M quantization capacitors, and the weights of the quantization capacitors from the first quantization capacitor to the Mth quantization capacitor gradually decrease, and the weight of the Nth capacitor to be calibrated is greater than the weight of the first quantization capacitor, and the weights of all the capacitors to be calibrated and the quantization capacitors satisfy the sub-binary condition, and both N and M are integers greater than 1.

4. The device according to claim 3, characterized in that The calibration period includes a first calibration period to an Nth calibration period; The logic control circuit is further configured to: during the nth calibration period, n is greater than or equal to 1 and less than or equal to N; control the ground voltage to be electrically connected to the lower plate of the (N - n + 1)th capacitor to be calibrated, and sequentially obtain M + 1 comparison results from the output end of the comparator circuit. Wherein, when the mth comparison result is obtained, control one of the ground voltage and the reference voltage to be electrically connected to the lower plate of the mth quantization capacitor, and the (M + 1)th comparison result is obtained after controlling the Mth quantization capacitor to complete the electrical connection according to the Mth comparison result, and m is greater than or equal to 1 and less than or equal to M; calculate the actual weight of the (N - n + 1)th capacitor to be calibrated based on the weights of the M quantization capacitors and the M + 1 comparison results; and, calculate the error code of the (N - n + 1)th capacitor to be calibrated based on the actual weight and the ideal weight of the (N - n + 1)th capacitor to be calibrated.

5. The device according to claim 4, wherein The logic control circuit is configured to: perform a reset operation once before the nth calibration period, and the reset operation includes electrically connecting the lower plates of all the capacitors in the capacitor array and the comparator input end to the common-mode voltage.

6. The device according to claim 4, characterized in that, The logic control circuit is configured to: during the nth calibration period, When the output voltage of the capacitance array is lower than the predetermined voltage, the m-th bit output result of the comparator circuit is 0, and the reference voltage is controlled to be connected to the lower plate of the m-th bit quantization capacitance; When the output voltage of the capacitance array is higher than the predetermined voltage, the m-th bit output result of the comparator circuit is 1, and the ground voltage is controlled to be connected to the lower plate of the m-th bit quantization capacitance.

7. The device according to claim 4, characterized in that The logic control circuit is configured to: when obtaining the error code of the (N - n + 1)-th capacitor to be corrected in the n-th correction period, use the (N - n + 1)-th capacitor to be corrected as the new first-bit quantization capacitance to obtain M + n-bit quantization capacitances; And, When obtaining the error code of the first capacitor to be corrected in the N-th correction period, restore the first-bit quantization capacitance to the N-1-th bit quantization capacitance to the second-bit capacitor to be corrected to the N-th capacitor to be corrected.

8. The device according to claim 1 or 4, characterized in that, The quantization period includes the first quantization period to the N-th quantization period, The logic control circuit is further configured to be within the n-th quantization period, According to the n-th bit comparison result obtained from the comparator circuit, control one of the ground voltage and the reference voltage to be electrically connected to the lower plate of the n-th capacitor to be corrected; Based on the error code of the n-th capacitor to be corrected, the correction code of the (n - 1)-th capacitor to be corrected, and the n-th bit comparison result, calculate the correction code of the n-th capacitor to be corrected; According to the correction code, control the ground voltage to be electrically connected to the lower plates of multiple target quantization capacitances in the quantization capacitance array for correcting the n-th capacitor to be corrected, where the sum of the weights of the multiple target quantization capacitances is equal to the correction code.

9. The device according to claim 8, characterized in that, The logic control circuit is configured to, within the first quantization period, obtain the first-bit comparison result from the comparator circuit and control one of the ground voltage and the reference voltage to be electrically connected to the lower plate of the first capacitor to be corrected; Calculate the correction code of the first capacitor to be corrected based on the error code of the first capacitor to be corrected and the first-bit comparison result.

10. The device according to claim 8, characterized in that, The logic control circuit is configured to: within the n-th quantization period, When the output voltage of the capacitance array is lower than the predetermined voltage, the n-th bit output result of the comparator circuit is 0, and the reference voltage is controlled to be connected to the lower plate of the n-th capacitor to be corrected; When the output voltage of the capacitance array is higher than the predetermined voltage, the n-th bit output result of the comparator circuit is 1, and the ground voltage is controlled to be connected to the lower plate of the n-th capacitor to be corrected.

11. The device according to any one of claims 1-10, characterized in that, The capacitance array includes a first capacitance array and a second capacitance array, and the specifications of the first capacitance array and the second capacitance array are exactly the same; the upper plate of the first capacitance array is electrically connected to the positive input terminal of the comparator circuit, and the upper plate of the second capacitance array is electrically connected to the negative input terminal of the comparator circuit.

12. The device according to claim 11, characterized in that, The logic control circuit is configured to: During the correction period, sequentially obtain the error codes of the first capacitance array and the second capacitance array; During the quantization period, sequentially correct the first capacitance array and the second capacitance array based on the error codes and the comparison results output by the comparator circuit.

13. A method for simulating front desk correction, characterized in that, Applied to the device according to any one of claims 1-12, the method includes: The logic control circuit controls the electrical connection of the ground voltage and each capacitor to be calibrated in the capacitor array to be calibrated in sequence from the low bit to the high bit; The logic control circuit generates an error code for each capacitor to be calibrated according to the comparison result output by the comparator circuit, where the comparator circuit compares the output voltage of the capacitor array with a preset voltage and outputs a comparison result, and the capacitor array includes the capacitor array to be calibrated and the quantization capacitor array; The logic control circuit controls the input of the common-mode voltage to the capacitor array; The logic control circuit obtains a correction code according to the comparison result output by the comparator circuit and the error code; The logic control circuit controls the electrical connection of multiple target quantization capacitors in the quantization capacitor array to the ground voltage or the reference voltage based on the correction code, where the sum of the weights of the multiple target quantization capacitors is equal to the correction code.

14. The method according to claim 13, wherein The method further includes: The logic control circuit performs a reset operation on the capacitor array; The logic control circuit calculates the error code of the capacitor to be calibrated based on the comparison result and the quantization capacitor array; The logic control circuit updates the weight of the capacitor to be calibrated, takes the capacitor to be calibrated as the first-bit quantization capacitor of the quantization capacitor array, and determines the error codes of all the capacitors to be calibrated; The logic control circuit performs weight compensation on the capacitor to be calibrated by controlling the low-bit capacitors in the quantization capacitor array based on the error code.

15. The method according to claim 13, characterized in that, The method further includes: Calculating the actual weight of the (N - n + 1)-th capacitor to be calibrated based on the weights of M quantization capacitors and M + 1 comparison results, where both N and M are integers greater than 1; Calculating the error code of the (N - n + 1)-th capacitor to be calibrated based on the actual weight and the ideal weight of the (N - n + 1)-th capacitor to be calibrated.

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