Methods and circuits for a switching floating substrate of a gallium nitride field effect transistor

Abstract

A gallium nitride field effect transistor (GaNFET) power switch includes a substrate, a metal layer, and a control circuit that controls an electrical potential of the metal layer according to an electrical potential of the gate of the GaNFET power switch, The control circuit may control the electrical potential of the metal layer according to at least first and second modes, wherein the first mode is determined by an off state of the GaNFET power switch and the second mode is determined by an on state of the GaNFET power switch, in the first mode the electrical potential of the metal layer may be floating, and in the second mode the electrical potential of the metal layer may be the same as the source electrode, or the same as the gate electrode, or proportional to or a monotonic function of the electrical potential of the gate electrode.

Description

[0001] METHODS AND CIRCUITS FOR A SWITCHING FLOATING SUBSTRATE OF A

[0002] GALLIUM NITRIDE FIELD EFFECT TRANSISTOR

[0003] RELATED APPLICATION

[0004] This application claims the benefit of the filing date of U.S. Application No. 63 / 624,590 filed on January 24, 2024, the contents of which are incorporated herein by reference in their entirety.

[0005] FIELD

[0006] The invention relates generally to the field of high voltage power electronics using gallium nitride (GaN) and gallium arsenide (GaAs) field effect transistors (FETs), specifically, high electron mobility transistors (HEMTs). More specifically, the invention relates to methods for controlling a floating substrate of GaN and GaAs HEMTS to achieve effective control of high voltage leakage and dynamic on-resistance in high voltage power switching applications.

[0007] BACKGROUND

[0008] Gallium nitride field effect transistors (GaNFETs) used in power electronic switching applications are typically made of GaN grown on a silicon substrate. When packaged, the substrate is conductively connected to a bottom lead-frame stage which is usually also the source electrode. Such a method has the shortcoming of large substrate leakage since the resistivity of the silicon substrate is typically rather low (around 100 Ohm-cm) and cannot be made highly resistive.

[0009] Various approaches have been proposed to address the shortcoming. For example, in U.S. Patent No. 11,107,755, issued August 31, 2021, the silicon substrate of the GaNFET was attached to the bottom lead-frame stage, which is typically also the source electrode, using insulating glue or other insulating medium. This prevents the substrate leakage and thus greatly enhances the breakdown voltage of the GaNFET. in this configuration the gate can switch effectively, wherein the gate (usually p-GaN) can deplete (turn off) and enhance (turn on) the carriers in the channel. However, this results in the substrate being electrically floating, which causes difficulty in switching on the device during high frequency switching and thus results in high dynamic on-resistance RON (or RDSON). This is attributed to parasitic capacitance from defects and traps between the drain and the gate and such parasitic capacitance causes the virtual back-gate to affect the channel turn-on negatively (see, e.g., Wang et al, Wang, W., Mechanism analysis of dynamic on-state resistance degradation for a commercial GaN HEMT using double pulse test. Electronics 10:1201, 2021). in another prior approach, GaN epi layers were grown on a sapphire substrate which resulted in a similar issue of high dynamic RDSON- In GaN / sapphire, blocking of vertical leakage is inherently achieved by using sapphire which is a natural insulator with poor thermal conductivity.

[0010] Hence the prior approaches have performance limitations and furthermore, none addresses the general problem in which GaNFETS configured with such insulating layers are subject to current collapse caused by material defects, negatively affecting the GaNFET dynamic behavior and reliability.

[0011] SUMMARY

[0012] One aspect of the invention relates to a field effect transistor (FET) power switch; comprising: a substrate and a metal layer; two or more layers comprising gallium-based material; source, gate, and drain electrodes; and a control circuit that controls an electrical potential of the metal layer according to an electrical potential of the gate of the FET power switch.

[0013] In one embodiment the substrate comprises a semiconductor material; the metal layer is disposed below the substrate and is electrically connected to the substrate; and the two or more layers comprising gallium-based material are disposed above the substrate. in one embodiment the substrate comprises a non-conducting material; the metal layer is disposed above the substrate; and the two or more layers comprising gallium-based material disposed above the metal layer.

[0014] In one embodiment the control circuit controls the electrical potential of the metal layer according to at least first and second modes; wherein the first mode is determined by an off state of the FET power switch and the second mode is determined by an on state of the FET power switch.

[0015] According to one embodiment, in the first mode the electrical potential of the metal layer is floating.

[0016] According to one embodiment, in the second mode the electrical potential of the metal layer is the same as the electrical potential of the source electrode.

[0017] According to one embodiment, in the second mode the electrical potential of the metal layer is the same as the electrical potential of the gate electrode.

[0018] According to one embodiment, in the second mode the electrical potential of the metal layer is proportional to the electrical potential of the gate electrode. According to one embodiment, in the second mode the electrical potential of the metal layer is a monotonic function of the electrical potential of the gate electrode.

[0019] In one embodiment the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are respectively connected to the source and gate electrodes of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer. in one embodiment the smaller FET comprises a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0020] In one embodiment the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are connected together and are connected to the gate electrode of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer.

[0021] In one embodiment the smaller FET comprises a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET. in one embodiment the control circuit comprises a diode; wherein an anode of the diode is connected to the FET power switch gate electrode and a cathode of the diode is connected to the metal layer.

[0022] In one embodiment the diode comprises a GaN diode, a GaAs diode, a silicon diode, or a silicon carbide diode.

[0023] Another aspect of the invention relates to bidirectional switch, comprising two FET power switches each including a control circuit that controls an electrical potential of the metal layer according to an electrical potential of the gate of the FET power switch, according to embodiments described herein.

[0024] Another aspect of the invention relates to a method for controlling a gallium-based FET power switch, comprising: disposing a substrate and a metal layer together with the GaNFET power switch; and using a control circuit to control an electrical potential of the metal layer according to an electrical potential of a gate of the FET power switch.

[0025] In one embodiment of the method, the substrate comprises a semiconductor material and the metal layer is disposed below the substrate and is electrically connected to the substrate; and the FET power switch is disposed above the substrate. in one embodiment of the method, the substrate comprises a non-conducting material and the metal layer is disposed above the substrate; and the FET power switch is disposed above the metal layer. in one embodiment of the method, the control circuit controls the electrical potential of the metal layer according to at least first and second modes; wherein the first mode is determined by an off state of the FET power switch and the second mode is determined by an on state of the FET power switch. in one embodiment of the method, in the first mode the electrical potential of the metal layer is floating. in one embodiment of the method, in the second mode the electrical potential of the metal layer is the same as the electrical potential of a source electrode of the FET power switch. in one embodiment of the method, in the second mode the electrical potential of the metal layer is the same as the electrical potential of the gate electrode of the FET power switch.

[0026] In one embodiment of the method, in the second mode the electrical potential of the metal layer is proportional to the electrical potential of the gate electrode of the FET power switch.

[0027] In one embodiment of the method, in the second mode the electrical potential of the metal layer is a monotonic function of the electrical potential of the gate electrode of the FET power switch. in one embodiment of the method, the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are respectively connected to source and gate electrodes of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer. In one embodiment the smaller FET comprises a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0028] In one embodiment of the method, the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are connected together and are connected to the gate electrode of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer. In one embodiment the smaller FET comprises a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET. in one embodiment of the method, the control circuit comprises a diode; wherein an anode of the diode is connected to the FET power switch gate electrode and a cathode of the diode is connected to the metal layer. In one embodiment the diode comprises a GaN diode, a GaAs diode, a silicon diode, or a silicon carbide diode.

[0029] Another aspect of the invention relates to a high voltage GaNFET based on GaN / sllicon technology with a silicon substrate conductvely connected to a bottom metal plate or a bottom metal coating layer (i.e., a botom metal) which is atached to a botom lead-frame using an insulating medium. One embodiment comprises an electronic control circuit that is synchronized with the main high voltage GaNFET gate driving PWM signal, wherein the control circuit is used to control the potential of the botom metal.

[0030] In one embodiment the control circuit is configured such that when the main GaNFET is in an off state, the botom metal potential is floating. in one embodiment the control circuit is configured such that when the main GaNFET is in an on state, the botom metal potential is connected to a source electrode of the main GaNFET. in one embodiment the control circuit is configured such that when the main GaNFET is in an on state, the botom metal potential is connected to a gate electrode of the main GaNFET.

[0031] In one embodiment the control circuit comprises a sub-GaNFET integrated with the main GaNFET on the same GaN die and the sub-GaNFET has common source and gate with the main GaNFET and a drain of the sub-GaNFET wire bonded or otherwise connected to the botom metal. in one embodiment the control circuit comprises a sub-GaNFET integrated with the main GaNFET on the same GaN die and the sub-GaNFET has a gate and source connected together and to a gate of the main GaNFET, wherein a drain of the sub-GaNFET is wire bonded or otherwise connected to the botom metal. in one embodiment the control circuit comprises a silicon integrated circuit co-packaged within the same lead-frame or power module or PCBA as the main GaNFET. in one embodiment the control circuit comprises a silicon or SiC integrated circuit copackaged within the same lead-frame or power module or PCBA as the main GaNFET. in one embodiment the high voltage GaNFET is implemented as a bidirectional GaNFET with gates of GaNFETs connected to the botom metal using diodes or smaller GaNFETs with source-gate shorted.

[0032] BRIEF DESCRIPTION OF THE DRAWINGS

[0033] For a beter understanding of the invention, and to show more clearly how it may be carried into effect, embodiments will be described, by way of example, with reference to the accompanying drawings, wherein: Fig. 1A is a diagram of a basic structure of a GaNFET grown on a silicon substrate, wherein the virtual gate VG is indicated beneath the gate and possible defects and traps between the gate and drain that may cause parasitic capacitance and are shown, according to the prior art,

[0034] Fig. IB is a diagram of a basic structure of a GaNFET grown on a silicon substrate, as in Fig. 1A, packaged with a lead-frame metal, according to the prior art.

[0035] Fig. 2 is an equivalent circuit model of a GaNFET on silicon substrate including substrate parasitic elements, wherein trap defects are described by a parasitic capacitance and the substrate is connected to the source contact of the GaNFET, according to the prior art.

[0036] Fig. 3 is an equivalent circuit model of a GaNFET on silicon substrate including substrate parasitic elements, wherein trap defects are described by a parasitic capacitance and the substrate is isolated from the other electrodes (floating), according to the prior art.

[0037] Fig. 4 is an equivalent circuit model of a main GaNFET on silicon substrate including substrate parasitic elements, wherein trap defects are described by a parasitic capacitance and a control circuit is implemented with a smaller GaNFET (integrated or co-packaged with the main GaNFET) used as a switch connecting the main GaNFET source and the floating substrate, according to one embodiment.

[0038] Fig. 5 is an equivalent circuit model of a main GaNFET on silicon substrate including substrate parasitic elements, wherein trap defects are described by a parasitic capacitance and a control circuit is implemented with a smaller GaNFET (integrated or co-packaged with the main GaNFET) used as a switch connecting the main GaNFET gate to the substrate when the gate voltage is high and isolating the main GaNFET gate from the substrate when the gate is off, according to one embodiment.

[0039] Figs. 6A and 6B are plots of simulation results for the prior art circuits of Figs. 2 and 3 (Vsub=0 and Vsub floating, respectively) and the embodiments of Figs. 4 and 5 (Vsub s-switch and Vsub g-switch, respectively), showing (Fig. 6A) the full range of the voltage wave form at the virtual gate spot of each circuit, and (Fig. 6B) the near zero voltage wave form at the virtual gate spot of circuit.

[0040] Fig. 7A is a diagram of a structure of a main GaNFET together with a smaller GaNFET as a substrate switching device grown on a silicon substrate, packaged with a metal insertion and lead- frame metal shown with the packaging wire bonding level wherein the drain of the smaller GaNFET is connected to a metal insertion between the bottom lead-frame stage and the silicon substrate, according to one embodiment. Fig. 7B is a diagram showing a partial layout of a main GaNFET together with a smaller GaNFET as a substrate switching device at the all-GaN-IC level where two adjacent finger pairs are separated to isolate the smaller GaNFET from the main power switching GaNFET, according to one embodiment.

[0041] Fig. 7C is a diagram showing a partial layout of a main GaNFET together with a smaller GaNFET as a substrate switching device at the all-GaN-IC level where the smaller GaNFET is isolated from the main GaNFET and the S-G electrodes of the smaller GaNFET are connected together using VIA holes and the PWM-in is connected to the S, and the drain of the smaller GaNFET is connected to a PAD-open which allows wire bonding to connect to the botom metal plate, according to one embodiment.

[0042] Fig. 8 is a diagram of a structure of a main GaNFET together with a smaller GaNFET as a substrate switching device grown on a sapphire substrate and packaged with a lead-frame metal, wherein metal thinfilm or thinfilm grid is used between the sapphire and the GaN epi-layer and a VIA hole is used to connect the substrate switching device (drain of the smaller GaNFET) down to the substrate thinfilm to achieve the substrate potential switching, according to one embodiment. The configuration of the sub-GaNFET is similar to Figs. 7B or 7C.

[0043] Fig. 9A is a diagram showing co-packaging of two GaNFETs, wherein the larger one is the main power switching GaNFET and an input voltage regulator is integrated between the main PWM- in input (Vin) and the main GaNFET gate (G), and the smaller GaNFET is used as a switching device used to control the substrate potential, according to one embodiment.

[0044] Fig. 9B is a drawing showing co-packaging of the two devices in Fig. 9A in a TO247-4 lead frame wherein the smaller GaNFET switching device has S-G shorted and connected to the PWM-in input, according to one embodiment.

[0045] Fig. 9C is a drawing showing co-packaging of the two devices in Fig. 9A in a TO247-4 lead frame wherein the smaller GaNFET switching device implements common source and common gate connections, according to one embodiment.

[0046] Fig. 10A is a diagram showing packaging of a main power switch GaNFET die wherein the control circuit is implemented with a diode, wherein the PWM-in or gate is connected to the anode of the diode and the cathode of diode is connected to the floating metal plate, according to one embodiment. Fig. 10B is a diagram of main GaNFET structure in a space-saving configuration using a diode as in Fig. 10A. wherein the diode bare die is stacked on top of the V-in (or PWM-in or gate) pad of the main GaNFET,

[0047] Fig. HA is a diagram showing packaging of a bidirectional main power GaNFET die wherein the control circuit is implemented with two diodes used to connect from the gates G1 and G2 of the two GaNFETs Ml and M2, respectively, to the bottom metal plate, according to one embodiment,

[0048] Fig. 11B is a diagram showing packaging of a bidirectional main power GaNFET die wherein the control circuit is implemented with two diodes and two resistors to provide proportional control, according to one embodiment.

[0049] Fig. 11C is a diagram showing packaging of a bidirectional main power GaNFET die wherein the control circuit is implemented with two smaller GaNFETs and two resistors to provide proportional control, according to one embodiment.

[0050] DETAILED DESCRIPTION OF EMBODIMENTS

[0051] Embodiments described herein overcome the above-mentioned shortcomings of prior approaches. Principles and features of embodiments may be explained with reference to a model of a GaNFET including the substrate parasitic effects and virtual gate, as illustrated in Figs. 1, 2, and 3. in Fig. 1A the basic structure of a GaNFET grown on a silicon substrate, according to the prior art, is shown. The structure has an AIGaN epitaxial layer (epi-layer) 102 over a 2-dimensional electron gas (2DEG) GaN epi-layer 104, which is grown over a silicon substrate 106. Source S, gate G, and drain D metal contacts or electrodes are disposed on the AIGaN epi layer. Fig. IB is a diagram showing typical packaging of a GanFET grown on silicon, such as the GaNFET of Fig. 1A, wherein the silicon substrate 106 is adhered to a lead-frame package metal 110 using, e.g., an insulating glue 122. The area of the virtual gate VG is indicated beneath the gate. The on-state of the GaNFET is sensitive to negative virtual gate bias and this prevents It from fully turning on, thus increasing dynamic drainsource on resistance RDSON. The concept of a virtual substrate gate is qualitative and it is generally difficult to model on a circuit level due to parametric uncertainties. Possible traps X (i.e., defects) between the gate and drain may cause parasitic capacitance, and their typical locations are also shown in Fig. 1.

[0052] Fig. 2 is an equivalent circuit model of the GaNFET on silicon substrate of Fig. 1, including substrate parasitic elements, within the dashed box. The parasitic elements include gate-drain capacitance Cv-gd, gate-source capacitance Cv-gs, gate-drain resistance R2s, gate-source resistance Rls, and trap defects described by a parasitic capacitance Ctrap. Also shown are the substrate resistance Rs and the substrate back-gate capacitance Cs. According to the prior art, the source contact of the GaNFET is connected to the silicon substrate (i.e., 106 in Figs. 1A and IB), as shown by the connection between the source and point A.

[0053] Fig. 3 is an equivalent circuit model of the GaNFET in another implementation according to the prior art wherein the silicon substrate is isolated or floating, that is, the silicon substrate (point A) is not connected to any of the S, G, and D electrodes of the GaNFET. As discussed above the on-state of the GaNFET is sensitive to negative virtual gate bias which prevents it from fully turning on, and in the prior implementation of Fig. 3 this would result in very high dynamic RDSON.

[0054] Simulations were conducted using LTspice (Analog Devices, inc.) for a typical high voltage GaNFET (e.g., GPI65030 (GaNPower International Inc., Vancouver, Canada) as a representative switch) based on the circuits of Figs, 2 and 3 with the following configuration: total device area 0.3 cm2, silicon substrate 0.03 cm thick, and operating conditions including input pulse width modulation (PWM) signal with pulse of 0 60 20 ns 20ns 0.5 p 1.0 u., tran 0 lOOix 0, load resistance RLoad 100 fi, and bus voltage Vbus 800 V. Since the silicon substrate resistivity is about 100 Ohm-cm, most of the substrate resistance comes from the GaN epi-layer, depending on the definition of the virtual gate spot. Based on the substrate leakage at high voltage, the estimated substrate resistance is of MegOhm (MCI) order while the substrate back-gate capacitance is about 1 pF. it is noted that the Rls, R2s, Cv-gd, and Cv-gs in Figs. 2 and 3 are parasitic resistances and capacitances caused by the GaN-epi layer and silicon substrate bulk materials and they are determined according to their respective device lengths. In this model, the SG and GD spacings were selected such that the ratio of resistances Rls:R2s was 1:10 and the ratio of capacitances Cv-gd:Cv-gs was 10:1. For qualitative analysis, the trap capacitance was set to be 1 / 10 of the substrate capacitance. The simulation results showed that without the trap related parasitic capacitance, the switching wave form had little dependence on the substrate potential and this is in contrast with experimental findings wherein substrate potential (i.e., whether the silicon substrate is connected to the source of the GaNFET or is floating) greatly affects the switching behaviour and on-state dynamic resistance.

[0055] Circuits and methods according to embodiments described herein relate to field effect transistors (FETs), i.e., high electron mobility transistors (HEMTs), implemented in a gallium-based semiconductor material such as gallium nitride (GaN), gallium arsenide (GaAs), etc. Although embodiments are described primarily with respect to GaNFETs, it will be appreciated that embodiments may be readily applied and / or adapted to, e.g., GaAsFETs. Embodiments address material defect issues in these devices, such as, for example, traps in the 2DEG GaN epi layer, to achieve effective control of high voltage leakage and dynamic on-resistance in applications such as high voltage power switching.

[0056] According to embodiments, a connection of a GaNFET power switch to a substrate may be controlled to provide different modes of operation, wherein the different modes provide different substrate potentials. For example, embodiments may provide one or more of a floating substrate mode, a connected substrate mode wherein the substrate potential is the same as the GaNFET source potential, a connected substrate mode wherein the substrate potential is the same as the GaNFET gate potential, a connected substrate mode wherein the substrate potential is proportional to the GaNFET gate potential, and a connected substrate mode wherein the substrate potential is a monotonic function of the GaNFET gate potential. In one embodiment proportional control may be achieved by implementing a linear element such as a resistor (i.e., an ideal resistor) during the on- state of the switching cycle. In one embodiment a monotonic control function may be achieved by implementing a non-linear element (e.g., a diode or a non-linear resistor) during the one-state of the switching cycle.

[0057] Herein, two potentials that are "the same" means that the two potentials are equal or are substantially the same such that any difference produces a negligible effect, if any, on an embodiment's operation or performance.

[0058] Herein, "substrate" refers to the bulk material upon which the GaNFET power switch is grown. The substrate may be a semiconductor material such as, for example, silicon, aluminum nitride (AIN), etc., or a non-conducting material such as, for example, sapphire, quartz, etc. Whereas embodiments are described herein primarily with respect to silicon and sapphire substrates, it will be appreciated that embodiments are not limited thereto.

[0059] Embodiments may include a control circuit (also referred to herein as a floating substrate switching system) for a GaNFET power switching device. Embodiments may include a control circuit having at least one substrate switching device, wherein the substrate switching device is dedicated to switching between a floating substrate mode and a connected substrate mode wherein the potential of the substrate is controlled in sync with the gate of the GaNFET power switch, examples of which are given above. The substrate switching device may be implemented with any device capable of power switching, such as, but not limited to, JFET, MOSFET, or FET, etc., referred to generally herein as a FET, or a diode, etc. In some embodiments the substrate switching device may be a GaNFET. In some embodiments a GaNFET substrate switching device may be integrated on the same chip (i.e., monolithic) with the GanFET power switch. In some embodiments the substrate switching device may be a FET implemented in another semiconductor technology, such as, but not limited to, silicon, SIC, or GaAs. In some embodiments the substrate switching device may be a FET that is smaller than the GaNFET power switching device. Herein, "smaller" refers to a FET having a smaller size and consequently lower current handling than the GaNFET power switch, but having other properties that are similar such as the same or substantially the same breakdown voltage. A smaller size is beneficial since cost is proportional to the semiconductor wafer area.

[0060] Throughout this description the following terms are used interchangeably: gate and G, drain and D, source and S, input voltage and Vin and PWM in (wherein PWM is one possible way of producing an input voltage signal).

[0061] An embodiment will now be described with reference to the circuit diagram of Fig. 4. As shown in Fig. 4, the embodiment includes a GaNFET main power switch Ml (e.g., GPI65030 as a representative switch) based on the model described above and shown in Fig, 2 with parasitic resistances and capacitances, and a control circuit implemented with an additional switch M2 dedicated to switch between the source electrode of the main power switch and the substrate to provide a floating substrate mode and a connected substrate mode. In this embodiment the additional switch M2 is implemented with a FET which may be a smaller device than the main power switch Ml and it may be implemented in GaN (e.g., GPIW100 (GaNPower International Inc.) as a representative switch) or in another semiconductor technology such as silicon. Thus, in the embodiment of Fig, 4, the control circuit switches between a floating substrate mode and a connected substrate mode wherein the substrate (i.e., bottom metal layer) potential is the same as the main power switch Ml source terminal. The embodiment may be packaged with a metal insertion (i.e., a bottom metal layer) below the substrate using conductive glue (also referred to herein as conductive adhesive, cement, etc.) or other conducting medium, so that the metal insertion potential is the same as the substrate.

[0062] In the embodiment of Fig. 4 the gate of the smaller FET M2, also referred to as the substrate switching device, is connected to the main power switch Ml gate, the drain of M2 is connected to the substrate, and the sources of Ml and M2 are connected together. Since the width / size of the smaller FET M2 may be much smaller than the main GaNFET Ml, the extra cost and any side effect to the main GaNFET are negligible. Referring to Fig. 4, when the input driving voltage Vin (or VPWM) is low, the smaller FET M2 is shut off. Therefore, in this mode the substrate remains floating in the off- state of the main FET, achieving high breakdown voltage. When driving voltage VPWM is high, the smaller FET M2 is turned on. In this mode the substrate is connected to the source of the main GaNFET Ml, achieving a connected substrate mode, preventing substrate leakage and enhancing the breakdown voltage of the main GaNFET. implementing the substrate switching device M2 in GaN advantageously allows it to be integrated in an all-GaN integrated circuit with the main power switch, thereby achieving lower cost and ease of implementation, in other embodiments the smaller switch M2 may be implemented in another semiconductor technology such as silicon, and optionally copackaged with the main power switch Ml.

[0063] Another embodiment is illustrated in the circuit diagram of Fig. 5. Similarly to the embodiment of Fig. 4, the embodiment of Fig. 5 includes a GaNFET main power switch Ml (e.g., GPI65030 as a representative switch) based on the model described above and shown in Fig. 5 with parasitic resistances and capacitances, and a control circuit implemented with an additional smaller switch M2 (e.g., a GaNFET such as GPIW100 (GaNPower International inc.) as a representative switch). In the embodiment of Fig. 5 the additional switch M2 is dedicated to connect between the gate electrode of the main power switch Ml and the substrate via reverse conduction (or 4th quarter conduction) of the small FET M2. As shown in Fig. 5, the gate and source of the small switch M2 are connected together and connected to the gate of the main GaNFET Ml, and the drain of M2 is connected to the substrate. When the substrate voltage is higher than the main GaNFET Ml gate voltage, the smaller FET M2 is shut off. Therefore, the substrate remains floating in the off state of the main GaNFET Ml, achieving a floating substrate mode with high breakdown voltage. When gate driving voltage Vln (VPWM) is high, the smaller FET M2 is turned on. in this connected substrate mode the substrate is connected to the gate of the main GaNFET Ml, sending a positive voltage to the floating substrate so that the virtual gate also has a positive voltage to assist turning on the conduction channel of the main FET. implementing the smaller switch M2 in GaN advantageously allows it to be part of an all GaN integrated circuit with the main power switch Ml. In other embodiments the smaller switch M2 may be implemented in another semiconductor technology such as silicon, and optionally co-packaged with the main power switch.

[0064] Using the virtual gate circuit model shown in Fig. 2, circuit simulations were performed using LTspice (Analog Devices, inc.) to confirm the performance and advantages of the embodiments described above and shown in Figs. 4 and 5, and results are presented in Figs. 6A and 6B together with results for the prior approaches of Figs. 2 and 3 discussed above, wherein Vsub=0 is the approach of Fig. 2, Vsub floating is the approach of Fig. 3, Vsub s-switch is the embodiment of Fig. 4, and Vsub g-switch is the embodiment of Fig. 5. Fig. 6A shows the full range of the voltage wave form at the virtual gate spot and Fig. 6B shows near zero voltage of the voltage wave form at the virtual gate spot. From the results it can be concluded that in the prior approaches the trap related capacitor Qrap is fully charged at high Vds of the main GaNFET off state and it is discharged during the main GaNFET on state which causes the virtual gate to be negative biased. Since the on-state of the main GaNFET is sensitive to negative virtual gate bias this prevents the main GaNFET from fully turning on and thus dynamic RDSON would be high for the prior art in Fig. 3. The simulation data in Figs. 6A and 6B also show that for both embodiments (Figs. 4 and 5) the substrate potentials (labeled as Vsub s-switch and Vsub g-switch) generate more positive bias than the prior approaches of Figs. 2 and 3, and they enable better turn-on characteristics than the prior approaches.

[0065] An embodiment on lead-frame packaging level is shown in Fig. 7A wherein a metal plate or insertion 708 is conductively glued 720 to the silicon substrate 706 and insulating glue 722 is used to isolate the metal plate 708 from botom lead-frame stage 710. A high voltage smaller GaNFET and the main GaNFET are grown on the AIGaN and 2-DEG GaN layers 702, 704, respectively, on the silicon substrate 706. The high voltage smaller GaNFET has electrodes D2, G2, and S2, and is located near the edge of the finger array and configured so that it has an independent drain pad D2 which can be wire bonded 726 to the bottom metal plate 708. Fig. 7A shows the main GaNFET electrodes DI and G1 according to an S surrounded by G layout. For convenient wire bonding, the bottom metal plate may be slightly larger than the bare die of the GaN chip or IC but small enough to fit into the lead- frame of the package. The configuration shown in the embodiment of Fig. 7A may be implemented for the circuit embodiments shown in Fig. 4 or Fig. 5. In Fig. 7 A, "periodic" refers to repetition of the layout across a chip or wafer.

[0066] Fig. 7B is a diagram showing a possible layout of an embodiment for a GaN die where a segment of the gate fingers are separated into two active regions and the middle drain finger Is connected using a VIA hole to a top PAD-open which then can be wire bonded to the botom metal plate.

[0067] Fig. 7C is a diagram showing a possible layout of an embodiment wherein a small GaNFET of the control circuit (i.e., the substrate switching device) is formed isolated from the main GaNFET. The S and G electrodes of the small GaNFET are connected together using a VIA hole and the PWM-in electrode is connected to the S. The drain of the smaller GaNFET is connected to a PAD-open which allows wire bonding to connect to the botom metal plate, e.g., similar to Fig. 78.

[0068] Embodiments may also be applied to GaN / sapphire technology where the substrate is sapphire which is a naturally insulating material that maintains the GaN channel floating. An example is shown in the embodiment of Fig. 8, wherein a high voltage smaller GaNFET with electrodes D2, G2, and S2 and the main GaNFET shown with electrodes DI and G1 for an S surrounded by G layout are grown on the AIGaN and 2-DEG GaN layers 802, 804, respectively, on a sapphire substrate 807. A metal thinfilm or metal pattern or metal grid may be formed as the bottom metal 820 beneath the GaN channel 804 and over the sapphire substrate 807 for the purpose of controlling the substrate potential between a first mode wherein the botom metal is floating and a second mode wherein the botom metal is the same as the electrical potential of the source electrode or wherein the electrical potential of the bottom metal layer is the same as, or proportional to, or a monotonic function of the gate electrode potential. A via hole with metal filling 830 may be formed to make a connection between the smaller GaNFET and the bottom metal 820. The sapphire substrate may be attached to the lead-frame metal 810 of the package using a glue 822 which may be insulating or non-insulating.

[0069] Referring to the embodiments of Figs. 4 and 5, implementation on sapphire (as in Fig. 8) would have large Rs and smaller Cs so that electrical control of the virtual gate from beneath the sapphire is not effective, so the point of control would be above Cs and Rs. The goal is still to control the potential of the substrate but in this case the control is from on top of the sapphire instead of from the bottom as in the case of silicon substrate.

[0070] Fig. 9A is a diagram showing two GaNFET dies with the larger one 901 being the main power switch and the smaller one 902 being the controlling FET, i.e., the substrate switching device used to control the substrate potential. In this embodiment the two GaNFETs are implemented discretely and are co-packaged, wherein a conductive glue 920 may be used to atach the GaNFET dies to the botom metal (not shown), in this embodiment the main GaNFET is integrated with an input voltage regulator between the main driving voltage input (PWM-in) and the main GaNFET gate G. In other embodiments the two GaNFETs may be integrated on the same chip as an IC.

[0071] Fig. 9B is a diagram showing an embodiment using the two dies of Fig. 9A in a co-package TO247-4 lead frame implementation where S and G of the controlling GaNFET 902 are shorted and connected to the PWM-in input of the main power switch 901. The two GaNFET dies are attached to a botom metal 908 (e.g., aluminum) using a conductive glue, and the botom metal 908 is attached to the package lead frame metal 910 using an insulating glue 922. The source of the main power switch 901 is connected to the package lead frame metal 910 which is shown as the source S, and to the Kelvin source KS terminal which is a secondary S dedicated to the gate driving loop. Fig. 9C is a diagram showing another embodiment using the two dies of Fig. 9A with a TO247-4 co-package as in the embodiment of Fig. 9B, but with common S and common G connection wherein the substrate switching device 902 has S and G shorted and connected to the PWM-in input of the main GaNFET 901.

[0072] Fig. 10A is a diagram showing an embodiment of a GaNFET main power switch die 1001 that is attached to a bottom metal 1008 (e.g., aluminum) using a conductive glue 1020, and the botom metal 1008 is atached to a package lead frame metal (not shown) using an insulating glue 1022. In this embodiment the control circuit is implemented using a diode 1040 of a different material than GaN, such as silicon or SiC. The diode has an anode connected to the PWM-in input of the main GaNFET 1001 and a cathode connected to the botom metal 1008. The connection is such that when the PWM-in input is positive, the diode controls the bottom metal potential to be approximately the same as the PWM-in potential and when the PWM-in input is zero or negative, the bottom metal potential is floating. Fig. 10B is cross section view of a space-saving embodiment where a bare die of the diode 1040 is stacked on top of the PWM-in input (or Vin) or gate electrode of the main switching device using conductive glue 1020 so that there is an electrical connection to the anode of the diode. A dielectric material 1044 such as, for example, SiN or SiCh may be disposed between the gate, drain, and source electrodes. The embodiment may be implemented for a lead frame metal package wherein a metal plate or insertion 1008 is conductively glued 1020 to the silicon substrate 1006 and insulating glue 1022 is used to isolate the metal plate 1008 from the bottom lead-frame stage 1010. The main GaNFET is grown on the AIGaN and 2-DEG GaN layers 1002, 1004, respectively, on the silicon substrate 1006. The cathode of the diode 1040 may be connected to the bottom metal 1008 by wire bonding 1026.

[0073] Fig. 11A is a diagram of an embodiment configured as a bidirectional switch with two power switching GaNFETs Mil and M22 on a single die 1101. The die 1101 is adhered to a bottom metal 1108 (e.g., aluminum plate) with conductive glue 1120, and the bottom metal is adhered to a package lead-frame metal (not shown) with insulating glue 1122. The two GaNFETs Mil and M22 are configured with diodes 1141, 1142 connected from Gil (the gate of Mil) and G22 (the gate of M22), respectively, to the botom metal 1108 (i.e., the common source Sil and S22 for Mil and M22). For each of Mil and M22, the cathode of the respective diode 1141, 1142 is connected to the gate and the anode is connected to the bottom metal. In this embodiment the S11G11-G22S22 implementation enables Sil and S22 to take turns acting as the drain for the other source, depending on the direction of the high voltage (HV) bias.

[0074] Fig. 118 is a diagram of another embodiment of a bidirectional switch similar to the embodiment of Fig. HA, however in this embodiment the control circuit provides proportional control of the substrate potential. Resistors 1161, 1162 in the range of, e.g., about lOMQ to about 500MQ, are connected from the gates Gil and G22, respectively, to the botom metal 1108.

[0075] Fig. 11C is a diagram of another embodiment of a bidirectional switch similar to the embodiment of Fig. HA, however in this embodiment the control circuit provides proportional control of the substrate potential. Smaller GaNFETs 1151, 1152 are connected to the gates Gil and G22, respectively, of the respective power GaNFETS MH and M22, and resistors 1161, 1162 in the range of, e.g., about 10 M£2 to about 500 MQ, are connected from the gates Gil and G22, respectively to the bottom metal 1108.

[0076] The contents of all cited publications are incorporated herein by reference in their entirety.

[0077] EQUIVALENTS

[0078] While the invention has been described with respect to illustrative embodiments thereof, it will be understood that various changes may be made to the embodiments without departing from the scope of the invention. Accordingly, the described embodiments are to be considered merely exemplary and the invention is not to be limited thereby.

Claims

CLAIMS1. A field effect transistor (FET) power switch; comprising: a substrate and a metal layer; two or more layers comprising gallium-based material; source, gate, and drain electrodes; and a control circuit that controls an electrical potential of the metal layer according to an electrical potential of the gate of the FET power switch.

2. The FET power switch of claim 1, wherein: the substrate comprises a semiconductor material; the metal layer is disposed below the substrate and is electrically connected to the substrate; the two or more layers comprising gallium-based material are disposed above the substrate.

3. The FET power switch of claim 1, wherein: the substrate comprises a non-conducting material; the metal layer is disposed above the substrate; the two or more layers comprising gallium-based material are disposed above the metal layer.

4. The FET power switch of claim 1, wherein the control circuit controls the electrical potential of the metal layer according to at least first and second modes; wherein the first mode is determined by an off state of the FET power switch and the second mode is determined by an on state of the FET power switch.

5. The FET power switch of claim 4, wherein in the first mode the electrical potential of the metal layer is floating.

6. The FET power switch of claim 4, wherein in the second mode the electrical potential of the metal layer is the same as the electrical potential of the source electrode.

7. The FET power switch of claim 4, wherein in the second mode the electrical potential of the metal layer is the same as the electrical potential of the gate electrode.

8. The FET power switch of claim 4, wherein in the second mode the electrical potential of the metal layer is proportional to the electrical potential of the gate electrode.

9. The FET power switch of claim 4, wherein in the second mode the electrical potential of the metal layer is a monotonic function of the electrical potential of the gate electrode.

10. The FET power switch of claim 1, wherein the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are respectively connected to the source and gate electrodes of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer.

11. The FET power switch of claim 1, wherein the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are connected together and are connected to the gate electrode of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer.

12. The FET power switch of claim 1, wherein in the control circuit comprises a diode; wherein an anode of the diode is connected to the FET power switch gate electrode and a cathode of the diode is connected to the metal layer.

13. A bidirectional switch, comprising two FET power switches according to claim 1.

14. A method for controlling a gallium-based field effect transistor (FET) power switch, comprising: disposing a substrate and a metal layer together with the FET power switch; using a control circuit to control an electrical potential of the metal layer according to an electrical potential of a gate of the FET power switch.

15. The method of claim 14, wherein: the substrate comprises a semiconductor material and the metal layer is disposed below the substrate and is electrically connected to the substrate; and the FET power switch is disposed above the substrate.

16. The method of claim 14, wherein: the substrate comprises a non-conducting material and the metal layer is disposed above the substrate; and the FET power switch is disposed above the metal layer.

17. The method of claim 14, wherein the control circuit controls the electrical potential of the metal layer according to at least first and second modes; wherein the first mode is determined by an off state of the FET power switch and the second mode is determined by an on state of the FET power switch.

18. The method of claim 17, wherein in the first mode the electrical potential of the metal layer is floating.

19. The method of claim 17, wherein in the second mode the electrical potential of the metal layer is the same as the electrical potential of a source electrode of the FET power switch.

20. The method of claim 17, wherein in the second mode the electrical potential of the metal layer is the same as the electrical potential of the gate electrode of the FET power switch.

21. The method of claim 17, wherein in the second mode the electrical potential of the metal layer is proportional to the electrical potential of the gate electrode of the FET power switch.

22. The method of claim 17, wherein in the second mode the electrical potential of the metal layer is a monotonic function of the electrical potential of the gate electrode of the FET power switch.

23. The method of claim 14, wherein the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are respectively connected to source and gate electrodes of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer.

24. The method of claim 14, wherein the control circuit comprises a smaller FET having source, gate, and drain electrodes; wherein the smaller FET source and gate electrodes are connected together and are connected to the gate electrode of the FET power switch; wherein the smaller FET drain electrode is connected to the metal layer.

25. The method of claim 14, wherein in the control circuit comprises a diode; wherein an anode of the diode is connected to the FET power switch gate electrode and a cathode of the diode is connected to the metal layer.

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