Backside deposition of Anti-reflective (AR) and high reflective (HR) layer

Abstract

An apparatus for processing a substrate, comprising: a reaction chamber; a substrate support in the reaction chamber configured to support the substrate at or near its periphery such that an active region on a frontside of the substrate does not contact any portion of the reaction chamber, and such that a backside of the substrate is substantially exposed; and a controller controllably, configured to: deposit a sacrificial layer on the backside of the substrate; deposit at least one of an anti-retlective layer and retlective layer on a backside of the substrate; and deposit a stack on a frontside of the substrate.

Description

BACKSIDE DEPOSITION OF ANTI-REFLECTIVE (AR) AND HIGH REFLECTIVE (HR) LAYERCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 625,561, filed lanuary 26, 2024, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] The background description provided here is for the purpose of generally presenting the context of the disclosure. The information described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] Semiconductor device fabrication often involves the deposition of a stack of layers on an underlying wafer substrate. Typically, most deposition and other processing to form the devices occur on the front face of a wafer. As the deposited layers build up, they can introduce stress in the wafer. A sacrificial layer may be deposited on the backside of the wafer to help reduce bowing in addition to reducing damage and contaminants on the backside of the wafer.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of processing a wafer is provided. An anti -reflective layer is deposited on a backside of the wafer. A sacrificial layer is deposited on the anti-reflective layer. A stack is deposited on a frontside of the wafer.

[0005] In another manifestation, a method of processing a wafer is provided. A sacrificial layer is deposited on a backside of the wafer. At least one of an anti-reflective layer or reflective layer is deposited on the sacrificial layer. A stack is deposited on a frontside of the wafer.

[0006] In another manifestation, an apparatus for processing a substrate is provided. A substrate support in a reaction chamber is configured to support the substrate at or near the substrate’s periphery such that an active region on a frontside of the substrate does not contact any portion of the reaction chamber, and such that a backside of the substrate is substantially exposed. A controller is controllably, configured to deposit a sacrificial layer on the backside of the substrate, deposit at least one of an anti-reflective layer and reflective layer on a backside of the substrate, and deposit a stack on a frontside of the substrate.

[0007] These and other features of the present disclosure will be described in more detail below in the detailed description of the disclosure and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0009] FIG. 1A is a flowchart for a method that uses an anti-reflective coating that may be used in some embodiments.

[0010] FIG. IB is a flowchart for a method that uses an anti-reflective coating that may be used in some embodiments.

[0011] FIGS. 2A-D are schematic cross sectional views of a wafer processed in some embodiments according to the processes shown in FIG. 1 A.

[0012] FIGS. 3A-C are graphs of reflectance versus wavelength that illustrate the advantage of some embodiments.

[0013] FIG. 4 is a schematic cross sectional view of a wafer processed in some embodiments according to the process shown in FIG. IB.

[0014] FIG. 5 is a flowchart for a method that uses a reflective coating that may be used in some embodiments.

[0015] FIG. 6 is a schematic cross sectional view of a wafer processed in some embodiments according to the process shown in FIG. 5.

[0016] FIGS. 7A-C are graphs of reflectance versus wavelength for different coating materials.

[0017] FIGS. 8A-B are graphs of the refractive index or extinction coefficient of doped silicon.

[0018] FIGS. 9A-B are schematic views of an apparatus used in some embodiments.

[0019] FIG. 10 is a schematic view of a controller that may be used in some embodiments.

[0020] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0021] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200or 300 mm, though the industry is moving toward the adoption of 450 mm diameter substrates. The description herein uses the terms “front” and “back” to describe the different sides of a wafer substrate. It is understood that the frontside is where most deposition and processing occurs, and where the semiconductor devices themselves are fabricated. The backside is the opposite side of the wafer, which typically experiences minimal or no processing during fabrication.

[0022] The flow rates and power levels provided herein are appropriate for processing on 300 mm substrate unless otherwise specified. One of ordinary skill in the art would appreciate that these flows and power levels may be adjusted as necessary for substrates of other sizes. The following detailed description assumes that the embodiments are implemented on a wafer. However, various embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of some embodiments include various articles such as printed circuit boards and the like.

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.Methods

[0024] The deposition of materials on the front of a wafer substrate can lead to stress and bowing problems in the wafer. These problems are especially likely to occur where large stacks of materials are deposited, for example in the context of three dimensional “not and” (3D- NAND) devices. Wafer bowing can cause complications in subsequent processing steps. For instance, the wafer may fail to chuck correctly if the bowing is too great. Further, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat when processing.

[0025] One technique for combating the stress and bowing issues is to deposit a film on the backside of the wafer. The backside film counteracts the stress from the frontside deposition to result in a neutral stress (or substantially neutral stress, e.g., less than about + / - 150 megapascals (MPa)) wafer that shows no bowing (or substantially no bowing, e.g., less than about 150 pm ofbow height). If the film deposited on the frontside is tensile, then the backside film should also be tensile to balance out the overall stress. Likewise, if the frontside film is compressive, then the backside film should also be compressive. The backside film may be deposited through various reaction mechanisms (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), low pressure chemical vapor deposition (LPCVD), etc.). In various cases, plasma enhanced chemical vapor deposition is used due to the high deposition rate achieved in this type of reaction.

[0026] Certain deposition parameters can be tuned to produce a backside film having a desired stress level. One of these deposition parameters is the thickness of the deposited backside film. Thicker films induce more stress in the wafer, while thinner films (of the same composition and deposited under the same conditions) induce less stress in the wafer.Therefore, in order to minimize the amount of material consumed in forming the backside layer, this layer may be deposited relatively thinly under conditions that promote the formation of a highly stressed film.

[0027] Other parameters that may be adjusted to affect the stress induced by the backside (or frontside) film include the power at which the plasma is generated (e.g., the RF power), the RF frequency of plasma, the exposure time of the plasma, the temperature of the substrate and reaction chamber, pressure within the reaction chamber, the flow of inert gas, composition of reactants, etc. This paragraph relates to the changes seen in a silicon nitride film under different deposition conditions. As the high frequency (HF, e.g., about 13.5 megahertz (MHz)) component of the RF power used to generate the plasma increases, the tensile stress response of the film increases, and the compressive stress response shows substantially no change. For example, HF RF frequencies may range between about 13.56-60 MHz. For example, HF RF powers may range between about 0-2500 Watts per station. As the low frequency (LF, e.g., about 356 kilohertz (kHz)) component of the RF power used to generate the plasma increases, the tensile stress response of the film decreases, and the compressive stress response of the film increases. For example, LF RF frequencies may range between about 200 kHz-4MHz. For example, LF powers may range between about 0-2500 Watts per station. In various cases, the LF + HF powers together may range between about 0-2500 Watts per station. As the plasma exposure time and / or duty cycle increases, the stress response may change as indicated above depending on the frequency used and the type of film stress involved. For example, RF exposure times depend on the type of deposition occurring. For instance, plasma enhancedchemical vapor deposition involves exposure to plasma for relatively long periods of time, while plasma enhanced atomic layer deposition involves repeated exposure to plasma for much shorter periods of time. As the temperature of the substrate during deposition increases, both the tensile and compressive stress responses of the film increase. Example substrate and chamber temperatures also depend on the deposition process, but may be between about 20-400°C. As the pressure in the reaction chamber during deposition increases, the tensile stress response of the film increases, and the compressive stress response of the film decreases. Example chamber pressures range between about 1-4 Torr. As the inert gas flow delivered to the reaction chamber during deposition increases, the tensile stress response shows no change, and the compressive stress response increases. Example flow rates for inert gas may be between about 100-5000 standard cubic centimeters per minute (seem). Another parameter that may affect film stress is the electrode spacing. The electrode spacing is important because it affects the E-field on the wafer, which can effect on-film density. As the electrode spacing increases, there is no response in the tensile stress response, and the compressive stress response decreases. For example, electrode spacing may be between about 5-30 mm. Other reaction parameters related to backside deposition will be further discussed below.

[0028] Another variable that can affect the degree of stress in a film is the hydrogen content of the film which can be controlled by the flow of NH3 or other hydrogen-containing reactant. One or more of the variables discussed above may also directly or indirectly affect the hydrogen content of the film. Films having lower hydrogen content show more neutral stress levels. One technique for modifying the stress induced by the frontside deposition is to form films having lower hydrogen contents (on the wafer frontside). However, the hydrogen content of a film also has a significant effect on the dielectric constant of the film. Thus, there is only a narrow window in which the hydrogen content can be modified while maintaining a desired dielectric constant. Backside deposition overcomes the problem related to the small processing window available for depositing the frontside materials.

[0029] As mentioned, stacks of deposited materials are especially likely to result in wafer stress and bowing. One example stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example stack likely to result in bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of stack materials that may be problematic include but are not limited to, tungsten and titanium nitride. The materials in the stacks may be deposited through chemical vapordeposition techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or bowing are induced due to material present on the frontside of the wafer.

[0030] The frontside stacks may be deposited to any number of layers and thicknesses. In a typical example, the stack includes between about 32-72 layers and has a total thickness of about 2-4 pm. The stress induced in the wafer by the stack may be between about -500 MPa to about +500 MPa, resulting in a bow that is frequently between about 200-400 pm (for a 300 mm wafer), and even greater in some cases.

[0031] The material deposited on the backside of the wafer may be a dielectric material forming a dielectric layer in various embodiments. In some cases, an oxide and / or nitride (e.g., silicon oxide / silicon nitride) is used. Examples of silicon-containing reactants that may be used include, but are not limited to, silanes, halosilanes, and aminosilanes. A silane contains hydrogen and / or carbon groups but does not contain a halogen. Examples of silanes are silane (SiH4), disilane (SizHe), and organo silanes such as methylsilane, ethylsilane, isopropylsilane, t- butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, and the like. A halosilane contains at least one halogen group and may or may not contain hydrogens and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Although halosilanes, particularly fluorosilanes, may form reactive halide species that can etch silicon materials, in certain embodiments described herein, the silicon-containing reactant is not present when a plasma is struck. Specific chlorosilanes are tetrachlorosilane (SiCU), trichlorosilane (HSiCE), dichlorosilane (I ESiCk), monochlorosilane (CISiHs), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec- butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens, and carbons. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilane (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)s and Si(NH2)4, respectively), as well as substituted mono-, di-, tri- and tetra-aminosilanes, for example, t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tertiarybutylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH )2)2, SiHCl-(N(CH )2)2, (SKCHr NHfe and the like. A further example of an aminosilane is trisilylamine (N(SiHs)). Other potential silicon-containing reactants include tetraethyl orthosilicate (TEOS), and cyclic and non-cyclic TEOS variants such as tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), Trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), methyltriethoxysilane (MTEOS), dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane (HMODS), bis(triehtoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis(trimehtylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).

[0032] Example nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, and amines (e.g., amines bearing carbon) such as methylamine, dimethylamine, ethylamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, di-t-butylhydrazine, as well as aromatic containing amines such as anilines, pyridines, and benzylamines. Amines may be primary, secondary, tertiary, or quaternary (for example, tetraalkylammonium compounds). A nitrogen-containing reactant can contain heteroatoms other than nitrogen, for example, hydroxylamine, t-butyloxycarbonyl amine, and N-t-butyl hydroxylamine are nitrogen-containing reactants.

[0033] Examples of oxygen-containing co-reactants include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxide, sulfur dioxide, oxygen-containing hydrocarbons (CxHyOz), water, mixtures thereof, etc.

[0034] The flow rate of these reactants will depend greatly on the type of reaction through which the backside layer is deposited. Where chemical vapor deposition or plasma enhanced vapor deposition (CVD / PECVD) is used to deposit the backside layer, the flow rate of the silicon-containing reactant may be between about 0.5-10 milliliters per minute (mL / min) (before atomization), for example between about 0.5-5 mL / min. The flow rate of a nitrogen-containingreactant, oxygen-containing reactant, or other co-reactant may be between about 3-25 standard liter per minute (SLM), for example between about 3-10 SLM.

[0035] In certain implementations, the backside layer may be removed after further processing. Where this is the case, the composition of the backside layer should be chosen such that it can be easily removed from the substrate at an appropriate time. In this regard, there should be a high selectivity between the material of the backside layer (e.g., the dielectric) and the material of the underlying substrate (e.g., silicon) in the desired removal chemistry.

[0036] The optimal thickness of the backside layer will depend on the amount of stress induced by the deposition on the frontside of the wafer, as well as the conditions under which the backside layer is deposited. The backside layer may be deposited to a thickness at which the stress in the wafer becomes negligible (e.g., less than about 150 MPa). In these or other embodiments, the backside layer may be deposited to a thickness at which the wafer bow height becomes negligible (e.g., less than about 150 pm of bow). In some cases, this corresponds to a backside layer thickness between about 0.1-2 pm, for example between about 0.3-2 pm, or between about 0.1-1 pm, or between about 0.3-1 pm. Where silicon nitride is used to form the backside layer, a film having a thickness of about 0.3 pm is sufficient to mitigate a bow of about 50-200 pm. As mentioned above, a higher stress backside layer may be used to reduce the required thickness of the layer. This helps conserve materials and reduce costs.

[0037] In certain cases, the backside deposition may be accomplished by removing the wafer from a deposition tool, flipping it over, placing it back in the deposition tool upside down, and depositing on the wafer backside while the wafer is in its upside-down position. Additional process steps are required in order to protect the frontside of the wafer during backside deposition. For example, before the wafer is removed and flipped, one or more protective layers may be deposited on the wafer frontside. These protective layers shield the important underlying device layers / structures such that damage to the valuable wafer frontside is minimized. Without deposition of the protective layers, substantial damage to the wafer frontside may occur as the wafer is handled, transferred, chucked, de-chucked, etc. in its upsidedown orientation. For instance, an unprotected wafer frontside may be scraped, dented, or otherwise damaged when it comes into contact with a chuck. Though the protective layers are beneficial in shielding the wafer during backside deposition, the formation of the protective layers involves extra processing steps and material that could be avoided where direct backside deposition is available.

[0038] Thus, in certain other cases, the backside deposition is carried out in an apparatus that is specifically designed to deposit on the backside of a wafer, even when the wafer is in its right-side-up orientation (i.e., with the frontside of the wafer pointing upwards). This approach eliminates the need to form a protective layer on the frontside of the wafer before the backside deposition occurs. The protective layer is no longer needed because backside deposition may occur without anything handling or otherwise contacting the frontside of the wafer. In some embodiments, a deposition apparatus may be used to deposit on both the front and backside of a wafer, without flipping the wafer over (i.e., the deposition apparatus can perform both frontside deposition and backside deposition without altering the orientation of the wafer). Where this is the case, various components of the apparatus may be included at both the top and bottom of the reaction chamber (e.g., showerhead or other inlets, outlets, plates, or other components for providing a thin gap between the current non-plating face of the wafer and the plate, electrical connections, etc.).

[0039] Wafer backside film stack film thickness (consists of silicon oxide (SiO2) / silicon nitride (SiN) mostly) variation will cause light reflectance change, and change the heat adsorption rate during RTP, which can lead to wafer breakage. Tightening the backside film thickness specification to <1% is challenging since customers may deposit more than 6 layers, where each layer can add to the total film thickness variation. Some embodiments engineer the refractive index and the extinction coefficient of the backside film stack to minimize the effect of the variation of the backside film stack thickness on wafer heating nonuniformity.

[0040] Nonuniformities in the backside deposition, either within one wafer or across different wafers may cause uneven heating of the wafer and / or inaccurate measurement of the wafer temperature. The uneven heating or inaccurate temperature measurement may increase defects. Some embodiments use an anti-reflective layer, and some use a high-reflective layer to reduce defects caused by uneven heating or inaccurate measurement of wafer temperature. In some embodiments, the anti -reflective layer is a thermal anti-reflective layer that reduces the reflection of thermal radiant energy, such as light or infrared radiation.

[0041] To facilitate understanding, FIG. 1 A provides a flowchart for a method of processing a wafer that uses an anti-reflective coating that may be used in some embodiments. A wafer is provided in a process chamber (step 104). In some embodiments, the process chamber is a backside deposition chamber. FIG. 2A is a schematic, a cross-sectional view of a wafer 204 that may be processed according to some embodiments. In some embodiments, the wafer is a pure silicon substrate.

[0042] An anti-reflective layer is deposited on the backside of the wafer (step 108). A sacrificial layer is deposited on the backside of the wafer (step 112). FIG. 2B is a schematic cross-sectional view of the wafer 204 after an anti-reflective layer 208 and sacrificial layer 212 have been deposited on the backside of the wafer 204. The sacrificial layer 212 is deposited on the anti-reflective layer 208 so that the anti-reflective layer 208 is between the wafer 204 and the sacrificial layer 212.

[0043] A stack is deposited on a frontside of the wafer (step 116). FIG. 2C is a schematic cross-sectional view of the wafer 204 after a stack 216 was deposited on the frontside of the wafer 204.

[0044] In some embodiments, the stack 216 is processed (step 120). In some embodiments, the processing of the stack 216 comprises one or more processes from the group consisting of etching, deposition, ion implantation, plasma cleaning, and wet cleaning. In some embodiments, the processing of the stack 216 comprises heating the wafer. In some embodiments, the heating is performed by a high power light source. In some embodiments, the infrared light source heats the frontside, backside, or both frontside and backside of the wafer. In some embodiments, the infrared lights are used in a rapid thermal process. The infrared light source may be a halogen lamp or xenon lamp that is able to heat the wafer to a thousand degrees in a few seconds. Some processing chambers may provide light sources on each side of a wafer. Some tools may provide a light source on one side of a wafer and a reflector on the other side of the wafer. Such tools, heat both sides of a wafer to provide fast and more uniform heating.

[0045] FIG. 2D is a schematic view of the wafer 204, anti-reflective layer 208, sacrificial layer 212, and stack 216, in a process chamber, where a lamp 224 provides radiant heat 228 to the stack 216. A pyrometer 232 measures the temperature of the wafer 204.

[0046] In some embodiments, the sacrificial layer 212 and the thermal anti-reflective layer 208 are removed (step 124). The sacrificial layer 212 may be used to prevent bowing of the wafer 204 caused by the stress of depositing the stack 216 on the wafer. If the bowing results in a bow height beyond a threshold, device defects may increase. In addition, the sacrificial layer 212 may also provide a protective layer for preventing the backside of the wafer 204 from contaminants or damage. Instead, the damage or contaminants will be on the sacrificial layer 212 and will be removed with the sacrificial layer.

[0047] If the wafer is heated une venly, then the wafer or stack may crack or the measurement of the temperature of the wafer may be inaccurate causing processing errors and device defects. Uneven heating of the wafer may be caused by a nonuniform thickness orrefractive index (RI) of the sacrificial layer. In some embodiments, one or more pyrometers may be used to measure the temperature of the wafer. Without the thermal anti-reflective layer 208, an uneven thickness of the sacrificial layer 212 may cause an inaccurate measurement by the one or more pyrometers. Pyrometers may be used to measure temperatures at a plurality of points on a wafer to measure the uniformity of temperature across a wafer and the uniformity of temperature from wafer to wafer.

[0048] In some embodiments, the thermal anti-reflective layer 208 is a silicon nitride layer and the sacrificial layer 212 is a silicon oxide layer. In some embodiments, the thermal anti- reflective layer 208 has a thickness of t= X / (4n), where is the wavelength of concern during thermal processing and n is the index of refraction, in order to make the thermal anti-reflective layer 208 to be an anti-reflective coating. In some embodiments, the thermal anti-reflective layer 208 has a thickness to provide the maximum transmission of infrared light with an infrared wavelength of about 0.9 microns. As a result, the thickness of the thermal anti-reflective layer 208 has a thickness of about 100 nanometers (nm) where the thermal anti-reflective layer 208 has an index of refraction of about 2 and the sacrificial layer 212 has an index of refraction of about 1.5 and a thickness of about 2 microns. In some embodiments, the thermal anti-reflective layer 208 comprises a first silicon nitride layer of a thickness of 50 nm and an index of refraction of 2.5 and a second silicon nitride layer of a thickness of 50 nm and an index of refraction of 2.

[0049] FIG. 3A is a graph of a delta 300 of the reflectance versus wavelength for a wafer 304 and sacrificial layer 312 that does not have a thermal anti-reflective layer. FIG. 3B is a graph of a delta 300 of the reflectance versus wavelength for a wafer that has the single thermal anti-reflective layer 308 between a wafer 304 and a sacrificial layer 312. The delta 320 of with the single thermal anti-reflective layer 308 is less than the delta 300 without a thermal anti- reflective layer 208. FIG. 3C is a graph of a delta 324 of the reflectance versus wavelength for a wafer that has the double thermal anti-reflective layer of a first antireflective layer 308 and a second antireflective layer 310 between the wafer 304 and the sacrificial layer 312. The delta 324 with the double thermal anti-reflective layer is less than the delta 300 without a thermal anti-reflective layer and the delta 320 with a single thermal anti-reflective layer.

[0050] In some embodiments, the sacrificial layer is deposited before the anti-reflective layer. To facilitate understanding, FIG. IB provides a flowchart for a method that uses an antireflective coating that may be used in some embodiments. A wafer is provided in a process chamber (step 134). In some embodiments, the process chamber is a backside depositionchamber. A sacrificial layer is deposited on the backside of the wafer (step 138). A thermal anti- reflective layer is deposited on the backside of the wafer (step 142). A stack is deposited on a frontside of the wafer (step 146). FIG. 4 is a schematic view of the wafer 404, anti-reflective layer 408, sacrificial layer 412, and stack 416, in a process chamber, where a lamp 424 provides radiant heat 428 to the stack 416. A pyrometer 432 measures the temperature of the wafer 404. In some embodiments, the stack 416 is processed (step 150). In some embodiments, the processing of the stack 416 comprises one or more processes from the group consisting of etching, deposition, ion implantation, plasma cleaning, and wet cleaning. In some embodiments, the sacrificial layer 412 and the anti-reflective layer 408 are removed (step 154).

[0051] In some embodiments, the sacrificial layer 212 in FIG. 2C or the sacrificial layer 412 in FIG. 4 are laser annealed. The anti-reflective layers 208, 408 improve the efficiency of the laser annealing. In some embodiments, laser annealing may be applied to the frontside of the wafers 204, 404. The anit-reflective layer can reduce reflection of laser and enhance the photon absorption of the film, therefore reducing the laser fluence needed. It can also minimize the laser reflection variation from film thickness and RI variation across the wafer, as a way to improve laser process uniformity.

[0052] In some embodiments, a reflective layer is provided. To facilitate understanding, FIG. 5 provides a flowchart for a method that uses a reflective coating that may be used in some embodiments. A wafer is provided in a process chamber (step 504). In some embodiments, the process chamber is a backside deposition chamber. A sacrificial layer is deposited on the backside of the wafer (step 508). A reflective layer is deposited on the backside of the wafer (step 512). A stack is deposited on a frontside of the wafer (step 516). FIG. 6 is a schematic view of the wafer 604, sacrificial layer 612, reflective layer 608, and stack 616, in a process chamber, where a lamp 624 provides radiant heat 628 to the stack 616. A pyrometer 632 measures the temperature of the wafer 604. In some embodiments, the stack 616 is processed (step 520). In some embodiments, the processing of the stack 616 comprises one or more processes from the group consisting of etching, deposition, ion implantation, plasma cleaning, and wet cleaning. In some embodiments, the sacrificial layer 612 and the reflective layer 608 are removed (step 524).

[0053] In some embodiments, the reflective layer 608 is a highly reflective layer. In some embodiments, the highly reflective layer 608 comprises at least one of tungsten, aluminum, titanium, copper, nickel, high temperature carbon, and doped silicon. In some embodiments, the reflective layer comprises a highly infrared reflective coating comprising at least one ofelectrically conductive films like titanium nitride and elemental tungsten, aluminum, titanium, copper, nickel, or films like carbon, and doped silicon. Such highly infrared reflective coatings may have a high extinction coefficient K. Increasing the extinction coefficient of the thermal high-reflective layer 608 increases the reflectivity of the thermal high-reflective layer 608. In some embodiments, the doped silicon is a heavily doped silicon with a dopant concentration of greater than IO20moles of dopant per cubic centimeter (cm3) of silicon. Such highly reflective coatings may prevent uneven backside heating but may also block black body radiation from the wafer, making the wafer temperature more difficult to measure. However, if the thermal high- reflective layer 608 produces black body radiation, then the black body radiation of the thermal high-reflective layer 608 may be used to measure the temperature of the wafer 604. The block body radiation has a different wavelength than the radiation of the lamp. The reflective layer 608 may be used as a homogenizer for the pyrometer 632.

[0054] FIG. 7A is a graph of reflectance vs wavelength for a tungsten coating. FIG. 7B is a graph of reflectance vs wavelength for an aluminum coating. FIG. 7C is a graph of reflectance vs wavelength for a titanium nitride (TiN) coating. FIG. 8A is a graph of the reflective index versus wavelength for silicon with different dopant concentrations. FIG. 8B is a graph of the extinction coefficient versus wavelength for silicon with different dopant concentrations. These graphs show how increasing a dopant concentration increases reflectivity. In some embodiments, a silicon wafer doped with at least one of boron, phosphorus, antimony, aluminum, gallium, indium, arsenic, and germanium is used. In other embodiments, other substrates and dopants may be used. In some embodiments, a doped layer of silicon or another material may provide the reflective layer 608 deposited after the sacrificial layer 612. In some embodiments, the dopant is at least one of boron, phosphorus, antimony, aluminum, gallium, indium, arsenic, and germanium.

[0055] In some embodiments, the reflective layer may reflect optical or UV light. In some embodiments, the stack may be deposited on the frontside of the wafer before the sacrificial layer is deposited on the backside of the wafer.Apparatus

[0056] The methods described herein may be performed by any suitable apparatus. A suitable apparatus includes hardware for accomplishing the process operations (e.g., hardware for performing a backside deposition without contacting (or minimally contacting) the wafer frontside) and a system controller having instructions for controlling process operations inaccordance with various embodiments. For example, in some embodiments, the hardware may include one or more process stations included in a process tool.

[0057] FIG. 9A shows a cross-sectional view of a simplified version of an apparatus 900 capable of depositing on the backside of a wafer 951 (wafer 951 is shown as a black horizontal line in FIG. 9A). FIG. 9B shows a close up view of a portion of the apparatus 900. In particular, FIG. 9B illustrates how the wafer 951 is supported in the apparatus 900. An upper surface 955 may be a heater, a ground plate, a chamber ceiling, or another type of plate / surface. In many cases this upper surface 955 acts as an electrode. In some embodiments, the height of a front side gap 957 is about 0.5 mm or smaller, for example about 0.35 mm or smaller. In these or other embodiments, the height of the front side gap 957 may be at least about 0. 1 mm or bigger, for example at least about 0.25 mm or bigger. In many cases, this upper surface 955 is substantially parallel to the wafer 951. This upper surface / electrode 955 may also extend around the edge of the substrate as shown in FIG. 9B such that it comes into contact with the wafer support ring 953. The support ring 953 holds the wafer 951 over a deposition region 959. The deposition region 959 is the area where reactant gases are introduced, reacted, and deposited on the wafer 951. A lower surface 963 defines the bottom of the deposition region 959. During deposition, inert gas (e.g., N2, Ar, etc.) is introduced from a front side inlet 965 and passes over the front side of the wafer 951.

[0058] The front side inlet 965 may be positioned at or near the center of the wafer 951 , such that the inert gas flows from the center of the wafer outward. This outward flowing inert gas helps ensure that no deposition-causing gases enter the front side gap 957 or come into contact with the front side of the wafer 951. In other words, the inert gas flow helps ensure that no material is able to deposit on the front side of the wafer 951 during back side deposition. To further protect the front side of the wafer 951 , the front side gap 957 may be designed such that it is smaller than the thickness of the plasma sheath. This helps ensure that the plasma does not enter the front side gap where it could damage the substrate.

[0059] The wafer 951 is supported at or near its periphery by a wafer support ring 953 that provides a substrate support. The support ring 953 may contact the wafer 951 on the wafer’s bottom surface, near the wafer edge in a region referred to as the support contact region. The support contact region is annularly shaped and may be very small such that substantially the entire backside of the wafer (e.g., at least about 95%, or at least about 99%, as measured by surface area) is exposed during deposition. In some embodiments, the support contact region on the bottom of a wafer extends from the edge of the wafer inwards by about 5 mm or less, forexample by about 1 mm or less. In the example of FIGS. 9B, the support contact region is on the bottom of wafer 951, extending inwards from the periphery of the wafer by distance 961. The support ring 953 may also contact the top side of a wafer near the wafer edge. In these cases, the support contact region extends to the top side of the wafer. In this embodiment, the support ring may have a local cross-section that is C-shaped (rather than L-shaped as shown in FIG. 9B), extending both under and over a portion of the wafer at its periphery. Where the support ring contacts the top side of a wafer, care should be taken to ensure that the support ring does not damage the frontside of the wafer. Such care may include ensuring that the support ring only contacts the wafer frontside in a small defined area (the support contact area), and not in an active area. In some embodiments, the support contact area on the top of the wafer extends radially inward from the edge of the wafer by no more than about 0.5 mm, or by no more than about 0.25 mm.

[0060] In some embodiments, the support ring may be replaced with another wafer support mechanism that supports the wafer at / near its periphery. One example is a series of three or more disconnected pegs that support the wafer at different locations around its edge. In some cases, the pegs may wrap around the wafer to better secure it in place during processing. The pegs (or other support mechanisms) may contact the wafer within the support contact regions described above.

[0061] In any case, the mechanism for holding the substrate may be designed such that the frontside of the wafer does not substantially contact any portion of the reactor. As used herein, this means that any contact between the frontside of the wafer 951 and the wafer support mechanism 953 (e.g., support ring, pegs, etc.) or other portions of the apparatus happens only near the edge of the wafer. The frontside of the wafer includes an active region, where devices are fabricated, surrounded by a non-active peripheral region. The non-active peripheral region is present due to the geometry of the wafer and the need to handle the wafer during processing. By ensuring that the active region on the frontside of the wafer does not contact any portion of the reactor, damage to the frontside of the wafer may be minimized or avoided altogether. Contact that occurs at the very edge of the frontside is not problematic in many cases, because the peripheral non-active region is typically removed and discarded when the substrate is cut into individual devices. As such, contact that happens in this region is not fatal to the final devices formed on the wafer.

[0062] Showerhead designs that may be adapted for use in a backside deposition chamber are further discussed in the following U.S. Patents and Patent Applications, each of which isincorporated herein in its entirety: U.S. Patent No. 8,147,648, filed August 15, 2008, and titled “COMPOSITE SHOWERHEAD ELECTRODE ASSEMBLY FOR A PLASMAPROCESSING APPARATUS”; and U.S. Patent Application No. 13,828,176, filed March 14, 2013, and titled “COMPOSITE SHOWERHEAD ELECTRODE ASSEMBLY FOR A PLASMA PROCESSING APPARATUS.”

[0063] In some embodiments, the backside deposition reactor is a bevel cleaning apparatus that has been modified to perform backside deposition. One example of a processing apparatus that may be modified is the Coronus® plasma bevel clean apparatus from Lam Research of Fremont, CA. This apparatus is further discussed in the following U.S. Patents, each of which is incorporated by reference in its entirety: U.S. Patent No. 7,858,898, filed January 26, 2007, and titled “BEVEL ETCHER WITH GAP CONTROL”; U.S. Patent No. 7,943,007, filed January 26, 2007, and titled “CONFIGURABLE BEVEL ETCHER”; and U.S. Patent No. 8,562,750, filed December 17, 2009, and titled “METHOD AND APPARATUS FOR PROCESSING BEVEL EDGE.”

[0064] Suitable apparatus and methods for performing frontside deposition are further discussed in the following U.S. Patents and Patent Applications, each of which is incorporated by reference in its entirety: U.S. Patent Application No. 13 / 084,399, filed April 11, 2011, and titled “PLASMA ACTIVATED CONFORMAL FILM DEPOSITION”; U.S. Application No. 14 / 158,536, filed January 17, 2014, and titled “METHOD AND APPARATUS FOR THE REDUCTION OF DEFECTIVITY IN VAPOR DEPOSITED FILMS”; and U.S. Patent No. 8,101,531, filed September 23, 2010, and titled “PLASMA- ACTIVATED DEPOSITION OF CONFORMAL FILMS.” One example of a suitable apparatus for performing frontside deposition is the VECTOR® product family from Lam Research Corp, of Fremont, CA.

[0065] FIG. 10 is a high level block diagram showing a computer system 1000, which is suitable for implementing a controller used in embodiments. The computer system 1000 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 1000 includes one or more processors 1002 and further can include an electronic display device 1004 (for displaying graphics, text, and other data), a main memory 1006 (e.g., random access memory (RAM)), storage device 1008 (e.g., hard disk drive), removable storage device 1010 (e.g., optical disk drive), user interface devices 1012 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 1014 (e.g., wireless network interface). The communications interface 1014 allows software and data to be transferred between thecomputer system 1000 and external devices via a link. The system may also include a communications infrastructure 1016 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0066] Information transferred via communications interface 1014 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 1014, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communications channels. With such a communications interface 1014, it is contemplated that the one or more processors 1002 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0067] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0068] In some embodiments, the controller is configured to a) deposit a sacrificial layer on the backside of the substrate, b) deposit an anti-reflective layer or reflective layer on the backside of the substrate, and c) deposit a stack on a frontside of the substrate.

[0069] It is to be understood that the configurations and / or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such referencesmay be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof. CONCLUSION

[0070] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean 'only one of A or B or C.’ Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of processing a wafer, comprising: a) depositing an anti-reflective layer on a backside of the wafer; b) depositing a sacrificial layer on the anti-reflective layer; and c) depositing a stack on a frontside of the wafer.

2. The method of claim 1, wherein the anti-reflective layer comprises at least one anti- reflective coating for at least one infrared wavelength.

3. The method of claim 2, wherein the anti-reflective coating comprises silicon nitride and the sacrificial layer comprises silicon oxide.

4. The method of claim 1, wherein the sacrificial layer is a dielectric layer.

5. The method of claim 1, wherein the sacrificial layer is silicon oxide.

6. The method of claim 1, wherein the stack on the frontside causes the wafer to bow, and wherein depositing the sacrificial layer comprises depositing the sacrificial layer to a thickness sufficient to reduce the bow of the wafer to a bow height of about 150 m or less.

7. The method of claim 6, wherein the thickness of the sacrificial layer is less than about 2 pm and is thinner than a thickness of the stack.

8. The method of claim 1, further comprising: processing the stack through one or more processes from the group consisting of etching, deposition, ion implantation, plasma cleaning, and wet cleaning; and removing the sacrificial layer.

9. The method of claim 1, further comprising laser annealing the sacrificial layer.

10. The method of claim 1, further comprising laser annealing the stack.

11. A method of processing a wafer, comprising: a) depositing a sacrificial layer on a backside of the wafer; b) depositing at least one of an anti -reflective layer or reflective layer on the sacrificial layer; and c) depositing a stack on a frontside of the wafer.

12. The method of claim 11, wherein depositing the at least one of an anti-reflective layer or reflective layer on the sacrificial layer deposits an antireflective layer.

13. The method of claim 12, wherein the anti-reflective layer comprises at least one antireflective coating for at least one infrared wavelength.

14. The method of claim 11, wherein the stack on the frontside causes the wafer to bow, and wherein depositing the sacrificial layer comprises depositing the sacrificial layer to a thickness sufficient to reduce the bow of the wafer to a bow height of about 150 pm or less.

15. The method of claim 11, wherein depositing the at least one of an anti-reflective layer or reflective layer on the sacrificial layer deposits a reflective layer.

16. The method of claim 15, wherein the reflective layer comprises at least one of tungsten, aluminum, titanium, copper, nickel, high temperature carbon, and doped silicon.

17. The method of claim 15, wherein the reflective layer comprises at least one electrically conductive film comprising at least one of tungsten, aluminum, titanium, copper, nickel, high temperature carbon, and doped silicon.

18. An apparatus for processing a substrate, comprising: a reaction chamber; a substrate support in the reaction chamber configured to support the substrate at or near its periphery such that an active region on a frontside of the substrate does not contact any portion of the reaction chamber, and such that a backside of the substrate is substantially exposed; and a controller controllably, configured to: a) deposit a sacrificial layer on the backside of the substrate; b) deposit at least one of an anti -reflective layer and reflective layer on a backside of the substrate; and c) deposit a stack on a frontside of the substrate.

19. The apparatus, as recited in claim 18, wherein the deposit at least one of an anti- reflective layer and reflective layer on a backside of the substrate deposits an anti-reflective coating and where either the sacrificial layer is deposited on the anti-reflective coating or the anti-reflective coating is deposited on the sacrificial layer.

20. The apparatus, as recited in claim 18, wherein the deposit of at least one of an anti- reflective layer and reflective layer on a backside of the substrate deposits a reflective coating and where the reflective coating is deposited on the sacrificial layer.

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