Systems and methods for achieving processing rate uniformity using frequency offsets

Abstract

A method for achieving process rate uniformity is described. The method includes receiving a voltage signal measured at an output of an impedance matching circuit. The voltage signal has a plurality of cycles. The method further includes dividing each of the plurality of cycles of the voltage signal into a plurality of bins and determining a plurality of frequency offsets to be applied during a time period of the plurality of bins. During one of the plurality of bins, one of the plurality of frequency offsets is determined to maximize power that is delivered from an RF generator. The method includes controlling the RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity. The power that is delivered is reduced to achieve the process rate uniformity.

Description

SYSTEMS AND METHODS FOR ACHIEVING PROCESSING RATE UNIFORMITY USING FREQUENCY OFFSETSFIELD

[0001] The embodiments described in the present disclosure relate to systems and methods for achieving processing rate uniformity using frequency offsets.BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In a plasma tool, a radio frequency (RF) generator, an impedance matching circuit, and a plasma chamber are used. The RF generator is coupled to the impedance matching circuit, which is coupled to the plasma chamber. Within the plasma chamber, a semiconductor wafer is placed.

[0004] After the semiconductor wafer is placed, the RF generator generates an RF signal and supplies the RF signal via the impedance matching circuit to the plasma chamber. The semiconductor wafer, placed within the plasma chamber, is processed using the RF signal. However, the semiconductor wafer is not processed in a desirable manner.

[0005] It is in this context that embodiments described in the present disclosure arise.SUMMARY

[0006] Embodiments of the disclosure provide systems and methods for achieving processing rate uniformity using frequency offsets. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0007] In an embodiment, a method for achieving process rate uniformity is described. The method includes receiving a voltage signal measured at an output of an impedance matching circuit. The voltage signal has a plurality of cycles. The method further includes dividing each of the plurality of cycles of the voltage signal into a plurality of bins and determining a plurality of frequency offsets to be applied during a time period of the plurality of bins. The plurality of frequency offsets are to be applied with respect to a reference frequency of operation of a high frequency (HF) radio frequency (RF) generator. During one of the plurality of bins, one of the plurality of frequency offsets is determined to maximize power that is delivered from the HF RFgenerator. The method includes controlling the HF RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity. The power that is delivered is reduced to achieve the process rate uniformity.

[0008] In one embodiment, a controller for increasing process rate uniformity is described. The controller includes a processor, which receives a voltage signal measured at an output of an impedance matching circuit. The voltage signal has a plurality of cycles. The processor divides each of the plurality of cycles of the voltage signal into a plurality of bins. The processor determines a plurality of frequency offsets to be applied during a time period of the plurality of bins. The plurality of frequency offsets are applied with respect to a reference frequency of operation of the HF RF generator. During one of the plurality of bins, one of the plurality of plurality of frequency offsets is determined to maximize power that is delivered from the first RF generator. The processor controls the HF RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity. The power that is delivered is reduced to achieve the process rate uniformity. The controller includes a memory device coupled to the processor.

[0009] In an embodiment, a plasma system for increasing process rate uniformity is described. The plasma system includes a low frequency (LF) RF generator that generates an LF RF signal, the HF RF generator that generates an HF RF signal, and an impedance matching circuit coupled to the LF RF generator and the HF RF generator to receive the LF and HF RF signals. The impedance matching circuit generates a modified RF signal based on the LF and HF RF signals. The impedance matching circuit has an output. The plasma system also includes a plasma chamber coupled to the output of the impedance matching circuit to receive the modified RF signal. The plasma system includes a controller coupled to the LF and HF RF generators. The controller receives a voltage signal measured at the output of the impedance matching circuit. The voltage signal has a plurality of cycles. The controller divides each of the plurality of cycles of the voltage signal into a plurality of bins and determines a plurality of frequency offsets to be applied during a time period of the plurality of bins. The plurality of frequency offsets are applied with respect to a reference frequency of operation of the HF RF generator. During one of the plurality of bins, one of the plurality of plurality of frequency offsets is determined to maximize power that is delivered from the HF RF generator. The controller controls the HF RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity. The power that is delivered is reduced to achieve the process rate uniformity.

[0010] Some advantages of the herein described systems and methods include modifying one or more HF offsets of an RF signal. The one or more HF offsets are modified toincrease or decrease the one or more HF offsets to generate one or more modified HF offsets. When the one or more modified HF offsets are applied to control an HF RF generator instead of the one or more HF offsets, although there may be a decrease in delivered power that is output from the HF RF generator, there is an increase in a processing rate uniformity across a surface of a substrate.

[0011] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a diagram of an embodiment of a system to illustrate a plasma tool for achieving uniformity in a processing rate.

[0014] Figure 2A is an embodiment of a graph to illustrate cycles of a measurement voltage signal.

[0015] Figure 2B is an embodiment of a graph to illustrate a measurement voltage signal.

[0016] Figure 2C is an embodiment of a graph to illustrate a modification of high frequency (HF) offsets of a radio frequency (RF) signal to generate HF offsets of another RF signal.

[0017] Figure 3A is an embodiment of a graph to illustrate multiple states of pulsing of power of an HF multi state signal that is generated by an HF RF generator.

[0018] Figure 3B is an embodiment of a graph to illustrate that different HF offsets, such as offset values, are applied by the HF RF generator during different states of power of the HF multi state signal.

[0019] Figure 4 is a diagram of an embodiment of a system to illustrate details of the HF RF generator.

[0020] Figure 5 is an embodiment of a graph to illustrate a reference frequency of the HF RF generator.DETAILED DESCRIPTION

[0021] The following embodiments describe systems and methods for achieving processing rate uniformity using frequency offsets. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0022] Figure 1 is a diagram of an embodiment of a system 100 to illustrate a plasma tool for achieving uniformity in a processing rate. As an example, a processing rate, as used herein, is an etch rate or a deposition rate or a combination thereof. The system 100 includes a host computer 102, a low frequency (LF) radio frequency (RF) generator 104, the high frequency (HF) RF generator 106, a match 108, and a plasma chamber 110. The system 100 further includes a voltage sensor 112 and processing rate measurement devices (PRMDs) 114, 116, and 118.

[0023] An example of the host computer 102 includes a desktop computer or a laptop computer or a smart phone or a tablet or a controller. An example of the LF RF generator 104 is an RF generator having a low frequency, such as a low operating frequency. The low operating frequency is sometimes referred to herein as a low frequency of operation. Examples of the low operating frequency include a frequency in kilohertz (kHz), such as 100 kHz or 400 kHz, and a frequency of 2 MHz. An example of the HF RF generator 106 is an RF generator having a high frequency, such as a high operating frequency, which varies with time. The high operating frequency is sometimes referred to herein as a high frequency of operation. An example of the high operating frequency includes a frequency of operation of 60 MHz having frequency values ranging from 58 MHz to 63 MHz. Another example of the high operating frequency includes a frequency of operation of 60 MHz having frequency values ranging from 59 MHz to 62 MHz.

[0024] Examples of the match 108 include an impedance matching circuit, which is sometimes referred to herein as an impedance match or an impedance matching network. To illustrate, the match 108 includes a network of capacitors and inductors. The capacitors and inductors are sometimes referred to herein as network components. An example of the plasma chamber 110 includes a capacitively coupled plasma (CCP) chamber. An example of a processing rate measurement device that includes an etch rate measurement device (ERMD). To illustrate, an ERMD includes a spectrophotometer that monitors the plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma generated within the plasma chamber 110.

[0025] The host computer 102 includes a processor 120 and a memory device 122. Examples of the processor 120 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 122 include a read-only memory and a random access memory. The HF RF generator 106 includes a power sensor 124 that is coupled to an output 126 of the HF RF generator 106.

[0026] The plasma chamber 110 includes an electrostatic chuck 101 and an upper electrode 103. The upper electrode 103 is situated above the electrostatic chuck 101 to face the electrostatic chuck 101 and form a gap 105 between the electrostatic chuck 101 and the upperelectrode 103. A substrate S, such as a semiconductor wafer on which one or more integrated circuits are to be formed, is placed on a top surface of the electrostatic chuck 101 for being processed. The plasma chamber 110 further includes a window 107, another window 109, and another window 111. The window 107 is associated with, such as coupled to, a left wall 113 of the plasma chamber 110, and the windows 109 and 111 are associated with, such as coupled to, a right wall 115 of the plasma chamber 110.

[0027] The PRMD 114 associated with the window 107, the PRMD 116 is associated with the window 109, and the PRMD 118 is associated with the window 111. For example, the PRMD 114 is attached to the window 107, the PRMD 116 is attached to the window 109, and the PRMD 118 is attached to the window 111. As another example, the PRMD 114 is placed proximate to the window 107, the PRMD 116 is placed proximate to the window 109, and the PRMD 118 is placed proximate to the window 111. As an example, each window 107, 109, and I l l is made of a transparent material, such as glass, that allows light emitted by the plasma to pass through. In various embodiments, each window 107, 109, and 111 is a translucent window.

[0028] The processor 120 is coupled to the memory device 122. The processor 120 is also coupled via a transfer cable 128 to an input of the LF RF generator 104 and via a transfer cable 130 to an input of the HF RF generator 106. An example of a transfer cable includes a universal serial bus (USB) cable or a cable that allows a parallel transfer of data or a cable that enables a serial transfer data. An output 132 of the LF RF generator 104 is coupled via an RF cable 134 to an input 136 of the match 108. Also, the output 126 of the HF RF generator 106 is coupled via an RF cable 138 to an input 140 of the match 108. An output 142 of the match 108 is coupled via an RF transmission line 144 to a lower electrode embedded within the electrostatic chuck 101. An example of the output 142 is a connector that connects the RF transmission line 144 to the network components of match 108.

[0029] The PRMD 114 is coupled to the processor 120 via a transfer cable 146 and has a line of sight via the window 107 into the gap 105 within the plasma chamber 110. The line of sight of the PRMD 114 is directed into a space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 114 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 107. The intensity of radiation emitted by the plasma via the window 107 is directly proportional to a processing rate at a left edge region 148 of the substrate S. As an example, the line of sight of the PRMD 114 is directed to the left edge region 148 of the substrate S.

[0030] Similarly, the PRMD 116 is coupled to the processor 120 via a transfer cable 150 and has a line of sight via the window 109 into the gap 105. The line of sight of the PRMD116 is directed into the space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 116 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 109. The intensity of radiation emitted by the plasma via the window 109is directly proportional to a processing rate at a central region 152 of the substrate S that is processed by the plasma within the plasma chamber 110. As an example, the line of sight of the PRMD 116 is directed to the central region 152 of the substrate S.

[0031] Also, the PRMD 118 is coupled to the processor 120 via a transfer cable 154 and has a line of sight via the window 111 into the gap 105. The line of sight of the PRMD 118 is directed into the space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 118 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 111. The intensity of radiation emitted by the plasma via the window I l l is directly proportional to a processing rate at a right edge region 156 of the substrate S that is processed by the plasma within the plasma chamber 110. As an example, the line of sight of the PRMD 118 is directed to the right edge region 156 of the substrate S. The central region 152 is surrounded by the edge regions 148 and 156. The voltage sensor 112 is coupled to the processor 120 via a transfer cable 115.

[0032] The processor 120 sends a recipe set 156A via the transfer cable 128 to the LF RF generator 104 to control the LF RF generator 104. Also, the processor 120 sends a recipe set 156B via the transfer cable 132 to the HF RF generator 106 to control the HF RF generator 106. The recipe set 156A includes power and frequency information for generating an RF signal 158A and the recipe set 156B includes power and frequency information for generating an RF signal 158B. An example of the frequency information for generating the RF signal 158A includes the low frequency of operation and an example of the frequency information for generating the RF signal 158B includes the high frequency of operation and HF offsets with respect to, such as with reference to or from, the high frequency of operation. As an example, the HF offsets of the recipe set 156B are applied to generate the RF signal 158B during one or more cycles, such as a cycle n, of the RF signal 158A, where n is a positive integer. An example of the RF signal 158A is a continuous wave RF signal. Another example of the RF signal 158A is a mutistate RF signal. Similarly, an example of the RF signal 158B is a continuous wave RF signal and another example of the RF signal 158B is a mutistate RF signal. Each RF signal, as described herein, is a sinusoidal signal.

[0033] The processor 120 also sends a trigger signal via the transfer cables 128 and 132 to the RF generators 104 and 106 to control the RF generators 104 and 106. Upon receiving thetrigger signal, the LF RF generator 104 generates the RF signal 158 A based on the power and frequency information received within the recipe set 156A, and sends the RF signal 158A via the output 132 and the RF cable 134 to the input 136. Moreover, upon receiving the trigger signal, the HF RF generator 106 generates the RF signal 158B based on the power and frequency information received within the recipe set 156B, and sends the RF signal 158B via the output 126 and the RF cable 138 to the input 140.

[0034] Upon receiving the RF signals 158A and 158B, the match 108 matches an impedance of a load coupled to the output 142 with an impedance of a source coupled to the inputs 136 and 140 and combines the RF signals 158A and 158B to generate a modified RF signal 160 at the output 142. An example of the load includes the RF transmission line 144 and the plasma chamber 110, and an example of the source, includes the RF generators 104 and 106 and the RF cables 134 and 138.

[0035] The modified RF signal 160 is sent from the output 142 via the RF transmission line 144 to the lower electrode. When one or more process gases, such as an oxygen-containing gas or a halogen-containing gas or a phosphorus-containing gas or a combination thereof, are supplied to the gap 105 with the modified RF signal 160, the substrate S is processed within the plasma chamber 110. For example, one or more materials are deposited on the substrate S or the substrate S is etched or the substrate S is cleaned or a combination thereof to process the substrate S.

[0036] When the substrate S is being processed, the voltage sensor 112 senses a voltage of the modified RF signal 160 at the output 142 to generate a measurement voltage signal 162, and sends the measurement voltage signal 162 via the transfer cable 115 to the processor 120. As an example, the measurement voltage signal 162 has a frequency that is substantially similar to a frequency of the RF signal 158A generated by the LF RF generator 104. For example, the frequency of the measurement voltage signal 162 is the same as the frequency of the RF signal 158 A. To illustrate, the frequency of the measurement voltage signal 162 is equal to the frequency of the RF signal 158A. In the illustration, the frequency of the RF signal 158A is equal to the low frequency of operation. As another illustration, the frequency of the measurement voltage signal 162 is equal to the frequency of the RF signal 158 A slightly modified by the frequency of the RF signal 158B.

[0037] Moreover, when the substrate S is being processed, the PRMD 114 generates intensity signals 164A and 164B based on the line of sight towards the left edge region 148 of the substrate S, and sends the intensity signals 164A and 164B via the transfer cable 146 to the processor 120. Similarly, the PRMD 116 generates intensity signals 164C and 164D based on the line of sight towards the central region 152 of the substrate S, and sends the intensity signals164C and 164D via the transfer cable 150 to the processor 120. Also, the PRMD 118 generates intensity signals 164E and 164F based on the line of sight towards the right edge region 156 of the substrate S, and sends the intensity signals 164E and 164F via the transfer cable 154 to the processor 120.

[0038] Upon receiving the measurement voltage signal 162, the processor 120 divides each cycle of the measurement voltage signal 162 into multiple time intervals, such as multiple time periods, and each of the time intervals is sometimes referred to herein as a bin. For each bin, based on the intensity signals 164A through 164F, the processor 120 determines a modified HF offset for which uniformity in a processing rate of processing the substrate is achieved, such as increased. Upon determining the modified HF offsets, the processor 120 modifies the recipe set 156B to include modified frequency information, such as the modified HF offsets, to generate a modified recipe set 166, and sends the modified recipe set 166 to the HF RF generator 106.

[0039] Upon receiving the modified recipe set 166, the HF RF generator 106 modifies the RF signal 158B based on the modified frequency information to generate an RF signal 168. For example, the modified recipe set 166 is sent to the HF RF generator 106 to apply the modified recipe set 166 during a following cycle, such as a next cycle, of the RF signal 158 A that follows one or more cycles of the RF signal 158A during which the recipe set 158B is applied. To illustrate, the modified recipe set 166 is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 168 during an (n+l)thcycle of the RF signal 158 A and the recipe set 156B is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 158B during the nthcycle of the RF signal 158 A. In the illustration, the (n+l)thcycle immediately follows the nthcycle. As another illustration, the modified recipe set 166 is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 168 during an (n+t)thcycle of the RF signal 158A and the recipe set 156B is sent to generate the RF signal 158B during the nthcycle of the RF signal 158A, where t is a positive integer. In the illustration, the (n+t)thcycle follows the nthcycle. To further illustrate, the nthcycle occurs preceding to or occurs one or more cycles before an occurrence of the (n+t)thcycle.

[0040] The RF signal 168 is sent from the output 126 via the RF cable 138 to the input 140. Upon receiving the RF signals 158A and 168, the match 108 combines the RF signals 158A and 168, and matches an impedance of the load with the impedance of the source to generate a modified RF signal 170 at the output 142. The modified RF signal 170 is sent via the RF transmission line 144 to the lower electrode to process the substrate S. When the modified RF signal 170 is applied to the lower electrode, the substrate S is processed at a uniform processing rate, such as a uniform etch rate or a uniform deposition rate or a combination thereof. Forexample, although power delivered to the plasma chamber 110 decreases when the modified RF signal 170 is supplied to the plasma chamber 110 compared to when the modified RF signal 160 is supplied to the plasma chamber 110, uniformity in a rate of processing the substrate S is achieved, such as increased.

[0041] In one embodiment, the RF signal 168 is generated for multiple instances, such as a first instance and a second instance. Before generating the RF signal 168 during the second instance and after processing the substrate S with the RF signal 158B and the RF signal 168 generated during the first instance, the substrate S is replaced with another substrate. An example of the other substrate is a semiconductor wafer on which one or more integrated circuits are to be fabricated. The other substrate is placed on the top surface of the electrostatic chuck 101 within the plasma chamber 110.

[0042] In one embodiment, the power sensor 124 is located outside the HF RF generator 106 instead of being located within an enclosure, such as a body or a container, of the HF RF generator 106.

[0043] In an embodiment, instead of substrate S, a dummy substrate, such as a substrate on which an integrated circuit is not to be formed or a substrate made from glass, is used.

[0044] In an embodiment, the processor 120 is coupled to the RF generators 104 and 106 via a single transfer cable.

[0045] In one embodiment, the voltage sensor 112 is coupled at any point on the RF transmission line 144.

[0046] In an embodiment, the terms recipe set and recipe signal are used herein interchangeably.

[0047] Figure 2A is an embodiment of a graph 200 to illustrate cycles n and n+1 of the measurement voltage signal 162 or of the RF signal 158A (Figure 1). The graph 200 includes a plot 202 of a logic level on a y-axis versus time t on an x-axis. An example of the logic level is a voltage level. An example of the plot 202 is a clock signal. To illustrate, the clock signal is generated by the processor 120 (Figure 1) and sent via the transfer cables 128 and 130 (Figure 1) to the RF generators 104 and 106 (Figure 1) to synchronize operation of the RF generators 104 and 106.

[0048] The plot 202 has a logic level of 5, such as 5 volts, from a time tO to a time tlO. It should be noted that times tl, t2, t3, t4, t5, t6, t7, t8, and t9 occur between the times tO and tlO. For example, the times tO through tlO occur in a progressively and consecutively increasing manner. The plot 202 transitions from the logic level 5 to a logic level 0, such as zero volts, at the time tlO. The plot 202 has the logic level of 0 from the time tlO to a time t20. It should be noted that times ti l, t!2, t!3, t!4, t!5, t!6, t!7, t!8, and t!9 occur between the times tlO and t20.For example, the times tlO through t20 occur in a progressively and consecutively increasing manner. The cycle n of the plot 202 occurs from the time tO to the time tlO.

[0049] The plot 202 repeats the cycle n for a second time to form the cycle n+1. For example, the plot 202 transitions from the logic level 0 back to the logic level 5 at the time t20. The plot 202 has the logic level of 5 from the time t20 to a time t30. It should be noted that times t21, t22, t23, t24, t25, t26, t27, t28, and t29 occur between the times t20 and t30. For example, the times t20 through t30 occur in a progressively and consecutively increasing manner. The plot 202 transitions from the logic level 5 to the logic level 0 at the time t30. The cycle n+1 of the plot 202 occurs from the time t20 to a time t40.

[0050] It should be noted that a time interval between any two consecutive times illustrated on the x-axis of the graph 200 is the same. For example, a first time interval between the times tO and tl is equal to a second time interval between the times tl and t2, and the second time interval is equal to a third time interval between the times t2 and t3.

[0051] Figure 2B is an embodiment of a graph 220 to illustrate a measurement voltage signal 222. The measurement voltage signal 222 is a sinusoidal RF signal. The measurement voltage signal 222 is an example of the measurement voltage signal 162 (Figure 1). The graph 220 plots a voltage of the measurement voltage signal 222 on a y-axis and the time t on an x- axis. For example, the x-axis of the graph 220 is the same as the x-axis of the graph 200 (Figure 2A).

[0052] The processor 120 receives the measurement voltage signal 222 and divides each cycle, such as any of the cycles n and n+1, of the measurement voltage signal 222 into a predetermined number of bins, such as m number of bins, where m is an integer greater than one. As an example, m is equal to 20. As another example, m is equal to 10 or 30. To illustrate, the processor 120 divides each cycle, such as the cycle n and the cycle n+1, of the measurement voltage signal 222 into ten bins 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. The bin 1 is a time interval from the time tO to the time t2, the bin 2 is a time interval from the time t2 to the time t4, the bin 3 is a time interval from the time t4 to the time t6, the bin 4 is a time interval from the time t6 to the time t8, and the bin 5 is a time interval from the time t8 to the time tlO. The bin 5 is sometimes referred to herein as a bin 0.

[0053] The bin 6 is a time interval from the time tlO to the time tl2, the bin 7 is a time interval from the time tl2 to the time tl4, the bin 8 is a time interval from the time tl4 to the time tl6, the bin 9 is a time interval from the time tl6 to the time tl 8, and the bin 10 is a time interval from the time tl 8 to the time t20.

[0054] It should be noted that the bins 1 through 10 of each cycle of the measurement voltage signal 222 are equally spaced time intervals. For example, the bin 1 has a time interval that is equal to a time interval of the bin 2 or the bin 3 or the bin 4 and so on until the bin 10.

[0055] The measurement voltage signal 222 has positive voltage values from the time tO to the time t9 and transitions at the time t9 from the positive voltage values to negative voltage values. The time t9 is a time of occurrence of a negative zero crossing of the measurement voltage signal 222. The measurement voltage signal 222 has the negative voltage values from the time t9 to the time tl9 and transitions at the time tl9 from the negative voltage values to positive voltage values. The time tl9 is a time of occurrence of a positive zero crossing of the measurement voltage signal 222. In this manner, the measurement voltage signal 222 repeats the cycle n+1 from the time t20 to the time t40.

[0056] Figure 2C is an embodiment of a graph 240 to illustrate a modification of HF offsets of the RF signal 158B to generate HF offsets of the RF signal 168 (Figure 1). The graph 240 plots the HF offsets of the RF signal 168 on a y-axis and the time t on an x-axis. The x-axis of the graph 240 is the same as the x-axis of the graph 200 (Figure 2). The HF offsets of the RF signal 168 are values that modify, such as increase or decrease, the HF offsets of the RF signal 158B. The HF offsets of the RF signal 158B are values that modify, such as increase or decrease, a reference frequency of the HF RF generator 106. As an example, the reference frequency of the HF RF generator 106 is the high frequency of operation of the HF RF generator 106. To illustrate, the reference frequency of the HF RF generator 106 is an integer multiple of a frequency of operation of the LF RF generator 104. In the illustration, when the frequency of operation of the LF RF generator 104 varies with respect to the time t, the reference frequency of the HF RF generator 106 varies with respect to the time t.

[0057] On the y-axis of the graph 240, there are multiple HF offsets, such as values HF0, HF0.2, HF1, HF2, HF 2.2, and HF4 in an increasing manner. For example, the HF offset HF0.2 is greater than the HF offset HF0, and the HF offset HF1 is greater than the HF offset HF0.2. To illustrate, the value HF0 is an offset value of zero, such as no offset, with respect to the reference frequency of the HF RF generator 106. To further illustrate, there is no change to the reference frequency of the HF RF generator 106 when the value HF0 is applied as an offset to the reference frequency. Also, the HF offset HF2.2 is greater than the HF offset HF1. Each of the HF offsets greater than the HF offset HF0 is an addition to the reference frequency of the HF RF generator 106. Similarly, on the y-axis of the graph 240, there are multiple HF offsets, such as values HF(-0.3), HF(-l), HF(-2), and HF(-4), in a decreasing manner. For example, the HF offset HF(-4) is less than the HF offset HF(-l), and the HF offset HF(-l) is less than the HF offset HF(-0.3). The HF offset HF(-0.3) is less than the HF offset HF0. Each of the HF offsetsless than the HF offset HFO is a subtraction from the reference frequency of the HF RF generator 106.

[0058] As indicated in the graph 240, the HF RF generator 106 generates the RF signal 168 having the HF offset HF(-0.3) during the bins 1 and 2. Moreover, the HF RF generator 106 transitions the RF signal 168 from the HF offset HF(-0.3) to the HF offset HF(-4) at the time t4. The RF signal 168 has the HF offset HF(-4) during the bin 3. Also, the HF RF generator 106 transitions the RF signal 168 from the HF offset HF(-4) to the HF offset HF(-l) at the time t6. The RF signal 168 has the HF offset HF(-l) during the bin 4. The HF RF generator 106 transitions the RF signal 168 from the HF offset HF(-l) to the HF offset HF(0.2) at the time t8. The RF signal 168 has the HF offset HF(0.2) during the bins 5 through 7.

[0059] The HF RF generator 106 transitions the RF signal 168 from the HF offset HFO.2 to the HF offset HF(2.2) at the time tl4. The RF signal 168 has the HF offset HF2.2 during the bin 8. Also, the HF RF generator 106 transitions the RF signal 168 from the HF offset HF2.2 to the HF offset HF1 at the time tl6. The RF signal 168 has the HF offset HF1 during the bin 9. The HF RF generator 106 transitions the RF signal 168 from the HF offset HF1 to the HF offset HF(-0.3) at the time tl8. The RF signal 168 has the HF offset HF(-0.3) during the bin 10. In this manner, the HF RF generator 106 changes its reference frequency with the HF offset values HF(-0.3), HF(-4), HF(-l), HF0.2, HF2.2, HF1, and HF(-0.3) during bins 1 through 10 of each cycle of the measurement voltage signal 222.

[0060] It should be noted that the HF offsets HF(-0.3), HF(-4), HF(-l), HF0.2, HF2.2, HF1, and HF(-0.3) during the bins 1 through 10 of each cycle of the measurement voltage signal 222 are of the RF signal 168 generated by the HF RF generator 106. To illustrate, the HF RF generator 106 is operated at the offsets HF offsets HF(-0.3), HF(-4), HF(-l), HFO.2, HF2.2, HF1, and HF(-0.3) during the bins 1 through 10 to generate the RF signal 168. In a similar manner, the HF offset HFO during the bins 1 and 2, the HF offset HF(-4) during the bin 3, the HF offset HF(- 1) during the bin 4, the HF offset HFO during the bins 5 through 7, the HF offset HF2.2 during the bin 8, the HF offset HF1 during the bin 9, and the HF offset HFO during the bin 10 of each cycle of the measurement voltage signal 222 are of the RF signal 158B (Figure 1). To illustrate, the HF RF generator 106 is operated at the offsets HF offsets HFO, HF(-4), HF(-l), HFO, HF2.2, HF1, and HFO during the bins 1 through 10 to generate the RF signal 158B. For example, to generate the RF signal 158B, the processor 120 sends the recipe set 156B (Figure 1) having the frequency information to the HF RF generator 106 via the transfer cable 130 (Figure 1). The frequency information includes the HF offsets HFO, HF(-4), HF(-l), HFO, HF2.2, HF1, and HFO and the bins 1 through 10 during which the HF offsets HFO, HF(-4), HF(-l), HFO, HF2.2, HF1, and HFO are to be applied. To illustrate, the processor 120 indicates, within the frequencyinformation of the recipe set 156B, that the RF signal 158B is to have the frequency offset HFO during instances, such as time intervals, of the bins 1 and 2 of each cycle of the RF signal 158A. Also, in the illustration, the processor 120 indicates, within the frequency information of the recipe set 156B, that the RF signal 158B is to have the frequency offset HF(-4) during an instance of the bin 3 of each cycle of the RF signal 158A. The processor 120 indicates, within the frequency information of the recipe set 156B, that the RF signal 158B is to have the frequency offset HF(-l) during an instance of the bin 4 of each cycle of the RF signal 158 A, the frequency offset HFO during instances of the bins 5 through 7 of each cycle of the RF signal 158A, the frequency offset HF2.2 during an instance of the bin 8 of each cycle of the RF signal 158A, the frequency offset HF1 during an instance of the bin 9 of each cycle of the RF signal 158A, and the frequency offset HFO during an instance of the bin 10 of each cycle of the RF signal 158A. An example of an instance of a bin is a time interval of the bin. Upon receiving the trigger signal, the HF RF generator 106 generates the RF signal 158B having the HF offsets HFO, HF(-4), HF(-l), HFO, HF2.2, HF1, and HFO during the bins 1 through 10 of each cycle of the RF signal 158 A.

[0061] It should be noted that the HF offsets of the RF signal 158B are determined by the processor 120 to maximize power that is delivered from the HF RF generator 106 to the plasma chamber 110. For example, the HF offset HFO is applied by the processor 120 via the HF RF generator 106 during the bin 1 of any cycle of the measurement voltage signal 222 to achieve an output of a maximum amount of power delivered by the HF RF generator 106. The delivered power is maximum among multiple HF offsets during the bin 1 of any cycle of the measurement voltage signal 222. To illustrate, when instead of the HF offset HFO, the HF offset HF(-0.3) is applied by the processor 120 via the HF RF generator 106 during the bin 1 of any cycle of the measurement voltage signal 222 to generate the RF signal 168, a first amount of delivered power is measured at the output 126 by the power sensor 124. The first amount of delivered power is provided by the power sensor 124 to the processor 120. Also, in the illustration, when the HF offset HFO is applied by the HF RF generator 106 during the bin 1 of any cycle of the measurement voltage signal 222 to generate the RF signal 158B, a second amount of delivered power is measured at the output 126 by the power sensor 124. The second amount of delivered power is sent from the power sensor 124 to the processor 120. The processor 120 compares the first amount of delivered power with the second amount of delivered power to determine the first amount of delivered power is less than the second amount of delivered power. Upon determining that the first amount of delivered power is less than the second amount of delivered power, the processor 120 determines the maximum amount of power is delivered from the HF RF generator 106 when the HF RF generator 106 applies the HF offsetHFO. As another example, the HF offset HFO is applied by the processor 120 via the HF RF generator 106 during the bin 2 of any cycle of the measurement voltage signal 222 to achieve an output of a maximum amount of power delivered by the HF RF generator 106. The delivered power is maximum among multiple HF offsets during the bin 2 of any cycle of the measurement voltage signal 222. As yet another example, the HF offset HFO is applied by the processor 120 via the HF RF generator 106 during the bin 5 of any cycle of the measurement voltage signal 222 to achieve an output of a maximum amount of power delivered by the HF RF generator 106. The delivered power is maximum among multiple HF offsets during the bin 5 of any cycle of the measurement voltage signal 222. It should be noted that power delivered at the output 126 is a difference between an amount of power supplied by HF RF generator 106 at the output 126 and power that is reflected back towards the HF RF generator 106 from the plasma chamber 110. As an example, the power is reflected back via the RF transmission line 144, the match 108, and the RF cable 138 (Figure 1).

[0062] During a time period in which the RF signal 158B (Figure 1) is being supplied by the HF RF generator 106, the processor 120 (Figure 1) receives the intensity signals 164A through 164F and determines a first processing rate uniformity from the intensity signals 164A through 164F. For example, the processor 120 receives the intensity signal 164A at a first primary time from the PRMD 114 (Figure 1) and the intensity signal 164B at a second primary time from the PRMD 114 and calculates a processing rate at the left edge region 148 (Figure 1) from the intensity signals 164A and 164B and the first and second primary times. The second primary time occurs after the first primary time. To illustrate, the processor 120 calculates the processing rate at the left edge region 148 to be a ratio of a first primary difference and a second primary difference. The processor 120 calculates the first primary difference to be a difference between an intensity value indicated within the intensity signal 164B and an intensity value indicated within the intensity signal 164A. Also, the processor 120 calculates the second primary difference to be a difference between the second and first primary times. In the illustration, the second primary time occurs after the first primary time.

[0063] Continuing with the example, the processor 120 receives the intensity signal 164C at the first primary time from the PRMD 116 (Figure 1) and the intensity signal 164D at the second primary time from the PRMD 116 and calculates a processing rate at the central region 152 (Figure 1) from the intensity signals 164C and 164D and the first and second primary times. To illustrate, the processor 120 calculates the processing rate at the central region 152 to be a ratio of a third primary difference and the second primary difference. The processor 120 calculates the third primary difference to be a difference between an intensity value indicatedwithin the intensity signal 164D and an intensity value indicated within the intensity signal 164C.

[0064] Moreover, in the example, the processor 120 receives the intensity signal 164E at the first primary time from the PRMD 118 (Figure 1) and the intensity signal 164F at the second primary time from the PRMD 118 and calculates a processing rate at the right edge region 156 (Figure 1) from the intensity signals 164E and 164F and the first and second primary times. To illustrate, the processor 120 calculates the processing rate at the right edge region 156 to be a ratio of a fourth primary difference and the second primary difference. The processor 120 calculates the fourth primary difference to be a difference between an intensity value indicated within the intensity signal 164F and an intensity value indicated within the intensity signal 164E.

[0065] In the example, the processor 120 determines the first processing rate uniformity from the processing rates at the left edge region 148, the central region 152, and the right edge region 156. To illustrate, the processor 120 determines that a combination of the processing rate at the left edge region 148, the processing rate at the central region 152, and the processing rate at the right edge region 156 is the first processing rate uniformity.

[0066] The processor 120 modifies, such as increases or decreases, one or more of the HF offsets HF0, HF(-4), HF(-l), HF0, HF2.2, HF1, and HF0 used to generate the RF signal 158B to determine a second processing rate uniformity. For example, instead of applying the HF offset HF0 during the bins 1, 2, 5, 6, 7, and 10, the processor 120 applies the HF offset HF(-0.3) during the bins 1 and 2, applies the HF offset HF0.2 during the bins 5 through 7, and applies the HF offset HF(-0.3) during the bin 10. The value HF(-0.3) applied during the bins 1, 2, and 10 and the value HF0.2 applied during the bins 5 through 7 are examples of the modified frequency offsets. To illustrate, the processor 120 decreases the HF offset HF0 to HF(-0.3) during the bins 1 and 2, increases the HF offset HF0 to HF0.2 during the bins 5 through 7, and decreases the HF offset HF0 to HF(-0.3) during the bin 10. As another example, instead of applying the HF offset HF0 during the bins 1 and 2, the processor 120 applies the HF offset HF(-0.3) during the bins 1 and 2. As yet another example, instead of applying the HF offset HF0 during the bins 5 through 7, the processor 120 applies the HF offset HF0.2 during the bins 5 through 7. As another example, instead of applying the HF offset HF0 during the bin 10, the processor 120 applies the HF offset HF(-0.3) during the bin 10.

[0067] To determine the second processing rate uniformity, the processor 120 sends a modified recipe set (not shown), such as the modified recipe set 166, indicating that one or more of the HF offsets HF0, HF(-4), HF(-l), HF0, HF2.2, HF1, and HF0 to be applied during the bins 1 through 10 is to be modified. The modified recipe set (not shown) is sent from the processor 123 via the transfer cable 130 to the HF RF generator 106. Upon receiving the modified recipeset, the HF RF generator 106 generates an RF signal (not shown), such as the RF signal 168, based on one or more of the HF offsets HF(-0.3), HF(-4), HF(-l), HF0.2, HF2.2, HF1, and HF(- 0.3) that are modified and indicated within the modified recipe set. Based on the RF signal (not shown) received from the HF RF generator 106 and the RF signal 158 A, the match 108 outputs a modified RF signal (not shown), such as the modified RF signal 160. The modified RF signal (not shown) is sent via the RF transmission line 144 to the lower electrode.

[0068] When the modified RF signal (not shown) is provided to the lower electrode, and the one or more process gases are supplied to the gap 105 (Figure 1), plasma is stricken or maintained within the plasma chamber 110 (Figure 1). When the plasma is stricken or maintained within the plasma chamber 110, the PRMDs 114, 116, and 118 generate intensity signals and send the intensity signals to the processor 120. For example, the PRMD 114 detects intensity of plasma at the left edge region 148 to generate a first intensity signal at a first secondary time and detects intensity of plasma at the left edge region 148 again to generate a second intensity signal at a second secondary time. The second secondary time occurs after the first secondary time. Also, in the example, the PRMD 116 detects intensity of plasma at the central region 152 to generate a third intensity signal at the first secondary time and detects intensity of plasma at the central region 152 again to generate a fourth intensity signal at the second secondary time. Moreover, in the example, the PRMD 118 detects intensity of plasma at the right edge region 156 to generate a fifth intensity signal at the first secondary time and detects intensity of plasma at the right edge region 156 again to generate a sixth intensity signal at the second secondary time.

[0069] Continuing with the example, the processor 120 determines the second processing rate uniformity from the first through sixth intensity signals in the same manner in which the processor 120 determines the first processing rate uniformity from the intensity signals 164A through 164F. To illustrate, the processor 120 receives the first intensity signal at the first secondary time from the PRMD 114 and the second intensity signal at the second secondary time from the PRMD 114 and calculates a processing rate at the left edge region 148 from the first and second intensity signals and the first and second secondary times. The processor 120 calculates the processing rate at the left edge region 148 to be a ratio of a first secondary difference and a second secondary difference. The processor 120 calculates the first secondary difference to be a difference between an intensity value indicated within the second intensity signal and an intensity value indicated within the first intensity signal. Also, the processor 120 calculates the second secondary difference to be a difference between the second and first secondary times.

[0070] Continuing with the illustration, the processor 120 receives the third intensity signal at the first secondary time from the PRMD 116 and the fourth intensity signal at the second secondary time from the PRMD 116 and calculates a processing rate at the central region 152 from the third and fourth intensity signals and the first and second secondary times. The processor 120 calculates the processing rate at the central region 152 to be a ratio of a third secondary difference and the second secondary difference. The processor 120 calculates the third secondary difference to be a difference between an intensity value indicated within the fourth intensity signal and an intensity value indicated within the third intensity signal.

[0071] Moreover, in the illustration, the processor 120 receives the fifth intensity signal at the first secondary time from the PRMD 118 and the sixth intensity signal at the second secondary time from the PRMD 118 and calculates a processing rate at the right edge region 156 from the fifth and sixth intensity signals and the first and second secondary times. The processor 120 calculates the processing rate at the right edge region 156 to be a ratio of a fourth secondary difference and the second secondary difference. The processor 120 calculates the fourth secondary difference to be a difference between an intensity value indicated within the sixth intensity signal and an intensity value indicated within the fifth intensity signal.

[0072] In the illustration, the processor 120 determines the second processing rate uniformity from the processing rates at the left edge region 148, the central region 152, and the right edge region 156. To further illustrate, the processor 120 determines that a combination of the processing rate at the left edge region 148, the processing rate at the central region 152, and the processing rate at the right edge region 156 is the second processing rate uniformity.

[0073] The processor 120 further determines whether the second processing rate uniformity is greater than the first processing rate uniformity. For example, the processor 120 determines whether a first difference between the processing rate at the left edge region 148 used to calculate the second processing rate uniformity and the processing rate at the central region 152 used to calculate the second processing rate uniformity is less than a second difference. The second difference is between the processing rate at the left edge region 148 used to calculate the first processing rate uniformity and the processing rate at the central region 152 used to calculate the first processing rate uniformity. The first and second differences are calculated by the processor 120. The processor 120 further determines whether a third difference between the processing rate at the right edge region 156 used to calculate the second processing rate uniformity and the processing rate at the central region 152 used to calculate the second processing rate uniformity is less than a fourth difference. The fourth difference is between the processing rate at the right edge region 156 used to calculate the first processing rate uniformity and the processing rate at the central region 152 used to calculate the first processing rateuniformity. The third and fourth differences are calculated by the processor 120. Upon determining that the first difference is less than the second difference and the third difference is less than the fourth difference, the processor 120 determines that the second processing rate uniformity is greater than the first processing rate uniformity.

[0074] In response to determining that the second processing rate uniformity is greater than the first processing rate uniformity, the processor 120 determines to control the HF RF generator 106 based on the modified recipe set 166 instead of the recipe set 156B. The HF RF generator 106 is controlled based on the modified recipe set 166 to apply the modified recipe set 166. For example, to process the substrate S, the processor 120 sends the modified recipe set 166 to the HF RF generator 106 for generating the RF signal 168 (Figure 1). As another example, when the substrate S is replaced with the other substrate in the plasma chamber 110, the processor 120 sends the modified recipe set 166 to the HF RF generator 106 for generating the RF signal 168 (Figure 1). The RF signal 168 is supplied to process the other substrate.

[0075] It should be noted that when the modified recipe set 166 is provided to the HF RF generator 106 by the processor 120, based on the HF offsets HF(-0.3), HF0.2, and HF(-0.3) during the bins 1, 2, 5, 6, 7, and 10 occurring during one or more cycles, such as the cycle (n+t), of the RF signal 158 A, there is a decrease in powered that is delivered from the HF RF generator 106 to the plasma chamber 110. The power that is delivered decreases compared to an amount of power that is delivered when the recipe set 156B is provided to the HF RF generator 106 by the processor 120. The recipe set 156B includes the frequency information indicating to apply the HF offset HF0 during the bins 1, 2, 5, 6, 7, and 10 during each cycle, such as the cycle n, of the RF signal 158A. Although during the application of the modified recipe set 166, there is a decrease in the delivered power at the output 126, there is an increase in processing rate uniformity from the first processing rate uniformity to the second processing rate uniformity. As such, a process benefit of the increase in the processing rate uniformity is achieved.

[0076] The delivered power at the output 126 when the recipe set 166 is applied by the processor 120 decreases compared to an amount of delivered power at the output 126 when the recipe set 156B is applied by the processor 120. For example, a first amount of delivered power at the output 126 is measured by the power sensor 124 when the HF offset HF0 is applied during the bin 1 and a second amount of delivered power at the output 126 is measured by the power sensor 124 when, instead of the HF offset HF0, the HF offset HF(-0.3) is applied during the bin 1. In the example, the first amount of delivered power is greater than the second amount of delivered power. As another example, a first amount of delivered power at the output 126 is measured by the power sensor 124 when the HF offset HFO is applied during the bin 5 and a second amount of delivered power at the output 126 is measured by the power sensor 124 when,instead of the HF offset HFO, the HF offset HF0.2 is applied during the bin 5. In the example, the first amount of delivered power is greater than the second amount of delivered power. The delivered power at the output 126 decreases when the recipe set 166 is applied by the processor 120

[0077] Figure 3A is an embodiment of a graph 300 to illustrate multiple states of pulsing of power of an HF multistate signal, which is an example of the RF signal 168, that is generated by the HF RF generator 106 (Figure 1). The graph 300 includes a plot 302 of power levels, such as power values P0, Pl, P2, P3, and P4, of the HF multistate signal on a y-axis and the time t on an x-axis. The x-axis of the graph 300 is the same as the x-axis of the graph 200 (Figure 2A). During each cycle of the RF signal 158A generated by the LF RF generator 104 (Figure 1), power of the HF multistate signal ranges from the power value of Pl to the power value of P4. For example, the power of the HF multistate signal ranges has the power values Pl, P2, P3, and P4 during the cycle n. To illustrate, the power of the HF multistate signal has the power value P4 from the time tO to the time t20 during the cycle n. The HF multistate signal transitions from the power value P4 to the power value Pl at the time t20 and maintains a power value Pl from the time t20 to the time t40 during the cycle n. The HF multistate signal transitions from the power value Pl to the power value P4 at the time t40 during the cycle n. In a similar manner, the HF multistate signal transitions between the power values P4 and Pl during the cycle n+1. The power value P4 represents a state SI of the HF multistate signal and the power value Pl represents another state S2 of the HF multi state signal.

[0078] It should be noted that the power values P0 through P4 are in an increasing order. For example, the power value Pl is greater than the power value P0, the power value P2 is greater than the power value Pl, the power value P3 is greater than the power value P2, and the power value P4 is greater than the power value P3. To illustrate, each of the power values Pl and P4 is a zero-to-peak power value of the HF multi state signal.

[0079] In one embodiment, the HF multistate signal generated by the HF RF generator 106 has more than two states. For example, the multistate RF signal generated by the HF RF generator 106 has three states or four states or five states or six states.

[0080] In an embodiment, an LF multistate signal, which is an example of the RF signal 158A (Figure 1), is synchronized in conjunction with the HF multistate signal. For example, when the HF multi state signal has the state SI, such as a high state, the LF multi state signal has a high state. On the other hand, when the HF multistate signal has the state S2, such as a low state, the LF multistate signal has a low state. Moreover, at a time at which the LF multistate signal transitions from the high state to the low state, the HF multistate signal transitions from the high state to the low state to synchronize the transition of the LF multistate signal with thetransition of the HF multistate signal. Also, at a time at which the LF multistate signal transitions from the low state to the high state, the HF multistate signal transitions from the low state to the high state to synchronize the transition of the LF multistate signal with the transition of the HF multi state signal. The high state of the LF multi state signal has a power value, such as a zero-to- peak power value, that is greater than a power value, such as a zero-to-peak power value, of the low state of the LF multistate signal.

[0081] Figure 3B is an embodiment of a graph 320 to illustrate that different HF offsets, such as offset values, are applied by the HF RF generator 106 (Figure 1) during different states of power of the HF multistate signal generated by the HF RF generator 106. The graph 320 plots HF offsets of the HF multistate signal on a y-axis and the time t on an x-axis. The x-axis of the graph 320 is the same as the x-axis of the graph 200 (Figure 2A). The HF offset values, illustrated in the graph 320, include a value HF0.5, the value HF2, a value HF3, and the value HF4. The value HF0.5 is greater than the value HF0.2 and less than the value HF1. The value HF2 is greater than the value HF1 and less than the value HF3. The value HF3 is less than the value HF4. Also, the HF offset values, illustrated in the graph 320, include a value HF(-0.5), the value HF(-2), a value HF(-3), and the value HF(-4). The value HF(-0.5) is less than the value HF(-0.3) and greater than the value HF(-l). The value HF(-2) is less than the value HF(-l) and greater than the value HF(-3). The value HF(-3) is less than the value HF(-2) and greater than the value HF (-4).

[0082] It should be noted that during a time period, from the time tO to the time t20, in which the HF multistate signal has the state SI, the HF offsets, as illustrated in the graph 320, are the same as those illustrated in the graph 240 (Figure 2C). However, during a time period, from the time t20 to the time t40, in which the HF multistate signal has the state S2, the HF offsets illustrated in the graph 320 are different from those during the state SI of the HF multistate signal. As an example, during the state S2 of the HF multistate signal and the during the bin 4 of the cycle n+1, the HF multistate signal has the HF offset HF(-0.5). The HF offset HF(-0.5) is different from the HF offset HF(-l) during the state SI of the HF multistate signal and the during the bin 4 of the cycle n. As another example, during the state S2 of the HF multistate signal and the during the bins 8 and 9 of the cycle n+1, the HF multistate signal has the HF offset HF(0.5). The HF offset HF(0.5) is different from the HF offsets HF2.2 and HF1 during the state SI of the HF multistate signal and the during the bins 8 and 9 of the cycle n.

[0083] It should be noted that the HF offsets HF(-0.5) and HF0.5 that are applied during the state S2 of the HF multistate signal and during the bins 4, 8, and 9 are determined in a manner similar to the determination of the HF offsets HF(-0.3) and HF0.2 that are applied during the state SI of the HF multistate signal and during the bins 1, 2, 5, 6, 7, and 10. For example, theHF offset HF(-0.5) is applied during the bin 4 of the cycle n+1 of the RF signal 158A generated by the LF RF generator 104 (Figure 1) and the HF offset HF0.5 is applied during the bins 8 and 9 of the n+1 of the RF signal 158A when the processor 120 determines that a processing rate uniformity is achieved, such as increased, during the state S2 of the HF multistate signal. The processing rate uniformity is increased compared to a processing rate uniformity that is achieved when the HF offset HFO is applied by the HF RF generator 106 during the bins 4, 8, and 9 of a cycle of the RF signal 158 A occurring before the cycle n+t of the RF signal 158 A and during the state S2 of the RF signal 158A. Also, with the application of the HF offsets HF(-0.5) and HFO.5 during the state S2 of the RF signal 158A, there is a decrease in power delivered by the HF RF generator 106 to the plasma chamber 110. The power delivered is decrease compared to the application of the HF offset HFO during the state S2 of the RF signal 158 A and during the bins 4, 8, and 9.

[0084] The processor 120 controls the HF RF generator 106 to generate the RF signal 166 having the HF offsets HF(-0.3) and HFO.2 during the state SI of the RF signal 166 and having the HF offsets HF(-0.5) and HFO.5 during the state S2 of the RF signal 166. For example, the processor 120 indicates within the recipe set 166 that the HF RF generator 106 is to generate the RF signal 166 having the HF offsets HF(-0.3) and HFO.2 during the state SI of the RF signal 166 and during the bins 1, 2, 5, 6, 7, and 10 and having the HF offsets HF(-0.5) and HFO.5 during the state S2 of the RF signal 166 and during the bins 4, 8, and 9.

[0085] It should further be noted that during the state S2 of the HF multistate signal, the bins 4, 8, and 9 for which the HF offsets are modified from the HF offset HFO are different from the bins 1, 2, 5, 6, 7, and 10 during the state SI of the HF multi state signal. During the state SI of the HF multistate signal, during the bins 1, 2, 5, 6, 7, and 10, the HF offset is modified from the HF offset HFO.

[0086] Figure 4 is a diagram of an embodiment of a system 400 to illustrate details of an HF RF generator 402, which is an example of the HF RF generator 106 (Figure 1). The HF RF generator 402 includes a digital signal processor (DSP) 404, a driver and amplifier circuit 406, power controllers PWRS1, PWRS2, and so on until a power controller PWRSp, where p is an integer greater than zero. Also, the HF RF generator 402 includes frequency controllers AFTSlbinl and AFTSlbinml, where ml is a positive integer. To illustrate, ml is an example of the number of bins m. The HF RF generator 402 further includes frequency controllers AFTSpbinl and AFTSpbinml. As an example, a controller includes a processor and a memory device. The processor of the controller is coupled to the memory device of the controller. The driver and amplifier circuit 406 includes a driver circuit and an amplifier. An example of thedriver circuit includes one or more transistors that are coupled to each other. The HF RF generator 402 further includes a power supply 408, such as an RF oscillator.

[0087] The processor 120 is coupled via the transfer cable 130 to the DSP 404. The DSP 404 is coupled to the power controllers PWRS1, PWRS2, and PWRSp. Also, the DSP 404 is coupled to the frequency controllers AFTSlbinl, AFTSlbinml, AFTSpbinl, and AFTSpbinml. The power controllers PWRS1, PWRS2, and PWRSp and the frequency controllers AFTSlbinl, AFTSlbinml, AFTSpbinl, and AFTSpbinml are coupled to the driver and amplifier circuit 406. The driver and amplifier circuit 406 is coupled to the power supply 408. The power supply 408 is coupled to the RF cable 138.

[0088] The processor 120 receives the measurement voltage signal 162 from the voltage sensor 112 (Figure 1) and divides the cycle, such as a cycle n or the cycle n+1, of the voltage signal 162 into the predetermined number of bins, such as the m bins. The processor 120 generates a recipe set 410 and sends the recipe set 410 via the transfer cable 130 to the DSP 404 to generate an RF signal 412. As an example, the recipe set 410 is the recipe set 156B (Figure 1) when the RF signal 158B (Figure 1) is to be generated. As another example, the recipe set 410 is the recipe set 166 (Figure 1) when the RF signal 168 is to be generated. The RF signal 158B is an example of the RF signal 412. Another example of the RF signal 412 is the RF signal 168 (Figure 1).

[0089] The recipe set 410 includes a number of states, such as the states SI through Sp, of the RF signal 412 to be generated by the HF RF generator 402 and a time interval of each of the states SI through Sp. As an example, each state, as described herein, is of an RF signal, and represents a power level of the RF signal. Also, the recipe set 410 includes HF offsets of the RF signal 412 for the predetermined number of bins and for each state of the RF signal 412. For example, when the RF signal 412 is the RF signal 158B and is a continuous wave signal, the recipe set 410 includes the HF offset HF0 to be applied during the bins 1 and 2, the HF offset HF(-4) to be applied during the bin 3, the HF offset (-1) to be applied during the bin 4, the HF offset HF0 to be applied during the bins 5 through 7, the HF offset HF2.2 to be applied during the bin 8, the HF offset HF 1 to the applied during the bin 9, and the HF offset HF0 to be applied during the bin 10. As another example, when the RF signal 412 is the RF signal 158B and is the HF multistate signal, the recipe set 410 includes the HF offsets, mentioned in the preceding example, to be applied during the bins 1 through 10 of the state SI of the RF signal 158B. Moreover, in the example, the recipe set 410 includes the HF offset HF (-2) to be applied during the bin 1 of the state S2 of the RF signal 158B, the HF offset HF(-3) to be applied during the bin 2 of the state S2 of the RF signal 158B, the HF offset (-4) to be applied during the bin 3 of the state S2 of the RF signal 158B, the HF offset HF0 to be applied during the bin 4 of the state S2of the RF signal 158B, the HF offset HF2 to be applied during the bin 5 of the state S2 of the RF signal 158B, the HF offset HF3 to the applied during the bin 6 of the state S2 of the RF signal 158B, and the HF offset HF2 to be applied during the bin 7 of the state S2 of the RF signal 158B, the HF offset HFO to be applied during the bins 8 and 9 of the state S2 of the RF signal 158B, and the HF offset HF(-2) to be applied during the bin 10 of the state S2 of the RF signal 158B.

[0090] As another example, when the RF signal 412 is the RF signal 168 and is a continuous wave signal, the recipe set 410 includes the HF offset HF(-0.3) to be applied during the bins 1 and 2, the HF offset HF(-4) to be applied during the bin 3, the HF offset (-1) to be applied during the bin 4, the HF offset HFO.2 to be applied during the bins 5 through 7, the HF offset HF2.2 to be applied during the bin 8, the HF offset HF1 to the applied during the bin 9, and the HF offset HF(-0.3) to be applied during the bin 10. As another example, when the RF signal 412 is the RF signal 168 and is the HF multistate signal, the recipe set 410 includes the HF offsets, mentioned in the preceding example, to be applied during the bins 1 through 10 of the state SI of the RF signal 168. Moreover, in the example, the recipe set 410 includes the HF offset HF (-2) to be applied during the bin 1 of the state S2 of the RF signal 168, the HF offset HF(-3) to be applied during the bin 2 of the state S2 of the RF signal 168, the HF offset (-4) to be applied during the bin 3 of the state S2 of the RF signal 168, the HF offset HF(-0.5) to be applied during the bin 4 of the state S2 of the RF signal 168, the HF offset HF2 to be applied during the bin 5 of the state S2 of the RF signal 168, the HF offset HF3 to the applied during the bin 6 of the state S2 of the RF signal 168, and the HF offset HF2 to be applied during the bin 7 of the state S2 of the RF signal 168, the HF offset HFO.5 to be applied during the bins 8 and 9 of the state S2 of the RF signal 168, and the HF offset HF(-2) to be applied during the bin 10 of the state S2 of the RF signal 168.

[0091] Upon receiving the recipe set 410, the DSP 404 identifies the number of states of the RF signal 412, power levels of the states, the time intervals of the states, and the HF offsets for each of the states. For example, when the number of states of the RF signal 412 is one, the DSP 404 identifies the number of states to be one and identifies the RF signal 412 to be the continuous wave signal. As another example, when the number of states of the RF signal 412 is two or three or four or five or more, the DSP 404 identifies the number of states to be two and identifies the RF signal 412 to be the HF multistate signal.

[0092] The DSP 404 sends the power level of the state SI of the RF signal 412 to the power controller PWRS1, the power level of the state S2 of the RF signal 412 to the power controller PWRS2, and so on until the power level of the state Sp of the RF signal 412 is sent to the power controller PWRSp.

[0093] Also, the DSP 404 sends the HF offsets to be applied during the bins 1 through ml to the frequency controllers AFTSlbinl through AFTSlbinml. For example, when the RF signal 412 is the continuous wave signal, the DSP 404 sends the HF offsets to be applied during the bins 1 through 10 for generating the RF signal 412. The HF offsets are sent to the frequency controllers AFTSlbinl through AFTSlbinml. Further, in the example, when the RF signal 412 to be generated is the HF multistate signal, the DSP 404 sends the HF offsets to be applied during the bins 1 through 10 and during the state SI for generating the RF signal 412. The HF offsets to be applied during the bins 1 through 10 and during the state SI are sent to the frequency controllers AFTSlbinl through AFTSlbinml. Also, in the example, when the RF signal 412 to be generated is the HF multistate signal, the DSP 404 sends the HF offsets to be applied during the bins 1 through 10 and during the state Sp for generating the RF signal 412. The HF offsets to be applied during the bins 1 through 10 and during the state Sp are sent to the frequency controllers AFTSpbinl through AFTSpbinml.

[0094] When the trigger signal is received from the processor 120 via the transfer cable 130 after receiving the recipe set 410, the DSP 404 controls the power controllers PWRS1 through PWRSp to generate the power levels of the states SI through Sp of the RF signal 412. For example, in response to receiving the trigger signal, the DSP 404 generates and sends an on control signal to the power controller PWRS1. Upon receiving the on control signal, the power controller PWRS1 generates a current signal based on the power level of the state SI, and sends the current signal to the driver of the driver and amplifier circuit 406. In response to receiving the current signal, the driver and amplifier circuit 406 generates a current signal to achieve the power level of the state SI, and sends the current signal to the power supply 408. The power supply 408 converts the current signal received from the driver and amplifier circuit 406 into the RF signal 412 having the power level of the state SI to generate the RF signal 412 having the state SI for the time period of the state SI . Also, the power supply 408 generates the RF signal 412 having the reference frequency during the time period of the state SI.

[0095] Continuing with the example, the DSP 404 determines whether the time period of the state SI of the RF signal 412 has passed and upon determining so, generates and sends an off control signal to the power controller PWRS1. Upon receiving the off control signal, the power controller PWRS1 stops generating the current signal based on the power level of the state SI. When the current signal is not received from the power controller PWRS1, the driver and amplifier circuit 406 stops generating the current signal to transition from the power level of the state SI. When driver and amplifier circuit 406 stops generating the current signal, the power supply 408 stops converting the current signal into the power level of the state SI of the RF signal 412 to transition from the power level of the state SI to the power level of another state,such as the state Sp, of the RF signal 412 and to finish generating the RF signal 412 having the state SI for the time period of the state SI.

[0096] Moreover, in the example, during a time period in which the off control signal is sent to the power controller PWRS1, the DSP 404 generates and sends an on control signal to the power controller PWRSp. Upon receiving the on control signal, the power controller PWRSp generates a current signal based on the power level of the state Sp, and sends the current signal to the driver of the driver and amplifier circuit 406. In response to receiving the current signal, the driver and amplifier circuit 406 generates a current signal to achieve the power level of the state Sp, and sends the current signal to the power supply 408. The power supply 408 converts the current signal received from the driver and amplifier circuit 406 into the RF signal 412 having the power level of the state Sp to generate the RF signal 412 having the state Sp for the time period of the state Sp. Also, the power supply 408 generates the RF signal 412 having the reference frequency during the time period of the state Sp.

[0097] Continuing with the example, the DSP 404 determines whether the time period of the state Sp of the RF signal 412 has passed and upon determining so, generates and sends an off control signal to the power controller PWRSp. In response to receiving the off control signal, the power controller PWRSp stops generating the current signal based on the power level of the state Sp. When the current signal is not received from the power controller PWRSp, the driver and amplifier circuit 406 stops generating the current signal to transition from the power level of the state Sp. When the driver and amplifier circuit 406 stops generating the current signal, the power supply 408 stops converting the current signal into the power level of the state Sp of the RF signal 412 to transition from the power level of the state Sp to the power level of another state, such as the state SI, of the RF signal 412 and to finish generating the RF signal 412 having the state Sp for the time period of the state Sp.

[0098] It should be noted that when the RF signal 412 to be generated is the continuous wave signal, the RF signal 412 has a single state, such as the state SI during all cycles of the RF signal 158A (Figure 1) generated by the LF RF generator 104 (Figure 1). To generate the single state of the RF signal 412, the DSP 404 controls the power controller PWRS1 in the manner described above without controlling any of the other power controllers PWRS1 and PWRSp. The DSP 404 controls the power controller to output the state SI of the RF signal 412. Also, the DSP 404 does not send the off control signal to the power controller PWRS1 until power of the RF signal 412 supplied by the power supply 408 is to be turned off.

[0099] Moreover, when the trigger signal is received and during the time period in which the state Sp of the RF signal 412 is generated, the DSP 404 controls the frequency controllers AFTSpbinl through AFTSpbinml to apply the HF offsets to the reference frequencyduring the ml bins and during the state Sp. For example, during the time period in which the state Sp of the RF signal 412 is generated, the DSP 404 generates and sends an on control signal to the frequency controller AFTSpbinl at a start of the time interval of the bin 1. Upon receiving the on control signal, the frequency controller AFTSpbinl generates a current signal based on the HF offset to be applied during the bin 1 and during the state Sp of the RF signal 412, and sends the current signal to the power supply 408. To illustrate, when the HF offset to be applied during the bin 1 is greater than the reference frequency, a magnitude of the current signal generated by the frequency controller AFTSpbinl increases compared to a magnitude of the current signal generated by the frequency controller AFTSpbinl to apply the reference frequency. Moreover, the greater the value of the HF offset to be applied during the bin 1 compared to the reference frequency, the greater the magnitude of the current signal generated by the frequency controller AFTSpbinl. On the other hand, when the HF offset to be applied during the bin 1 is less than the reference frequency, a magnitude of the current signal generated by the frequency controller AFTSpbinl decreases compared to the magnitude of the current signal generated by the frequency controller AFTSpbinl to apply the reference frequency. Also, in the illustration, the lower the value of the HF offset to be applied during the bin 1 compared to the reference frequency, the lower the magnitude of the current signal generated by the frequency controller AFTSpbinl. In response to receiving the current signal, the power supply 408 converts the current signal into the RF signal 412 having the HF offset during the bin 1 to generate the RF signal 412 having the HF offset for the bin 1.

[0100] Continuing with the example, during the time period in which the state Sp of the RF signal 412 is generated, the DSP 404 determines whether the time interval of the bin 1 has ended and upon determining so, generates and sends an off control signal to the frequency controller AFTSpbinl. Upon receiving the off control signal, the frequency controller AFTSpbinl stops generating the current signal based on the HF offset for the bin 1. When the current signal is not received from the frequency controller AFTSpbinl, the power supply 408 stops generating the HF offset of the RF signal 412 to transition from the HF offset for the bin 1 to an HF offset for another bin.

[0101] Moreover, in the example, during a time period in which the DSP 404 determines that the time interval of the bin 1 has ended and during the state Sp, the DSP 404 determines, from the recipe set 410, that the HF offset for the bin ml is to be applied after immediately applying the HF offset for the bin 1. Upon determining that the HF offset for the bin ml is to be applied, the DSP 404 generates and sends an on control signal to the frequency controller AFTSpbinml at a start of the time interval of the bin ml. In response to receiving the on control signal, the frequency controller AFTSpbinml generates a current signal based on theHF offset to be applied during the bin ml and during the state Sp of the RF signal 412, and sends the current signal to the power supply 408. To illustrate, when the HF offset to be applied during the bin ml is greater than the reference frequency, a magnitude of the current signal generated by the frequency controller AFTSpbinml increases compared to a magnitude of the current signal generated by the frequency controller AFTSpbinml to apply the reference frequency. Moreover, the greater the value of the HF offset to be applied during the bin ml compared to the reference frequency, the greater the magnitude of the current signal generated by the frequency controller AFTSpbinml. On the other hand, when the HF offset to be applied during the bin ml is less than the reference frequency, a magnitude of the current signal generated by the frequency controller AFTSpbinml decreases compared to the magnitude of the current signal generated by the frequency controller AFTSpbinml to apply the reference frequency. Also, in the illustration, the lower the value of the HF offset to be applied during the bin ml compared to the reference frequency, the lower the magnitude of the current signal generated by the frequency controller AFTSpbinml. In response to receiving the current signal, the power supply 408 converts the current signal into the RF signal 412 having the HF offset during the bin ml to generate the RF signal 412 having the HF offset for the bin ml .

[0102] Continuing with the example, during the time period in which the state Sp of the RF signal 412 is generated, the DSP 404 determines whether the time interval of the bin ml has ended and upon determining so, generates and sends an off control signal to the frequency controller AFTSpbinml. Upon receiving the off control signal, the frequency controller AFTSpbinml stops generating the current signal based on the HF offset for the bin ml. When the current signal is not received from the frequency controller AFTSpbinml, the power supply 408 stops generating the HF offset of the RF signal 412 to transition from the HF offset for the bin ml to an HF offset for another bin. The power supply 412 supplies the RF signal 412 via the RF cable 138 to the match 108 (Figure 1).

[0103] Figure 5 is an embodiment of a graph 500 to illustrate a reference frequency HFref, which is an example of the reference frequency of the HF RF generator 106 (Figure 1). The graph 500 frequency values of the reference frequency HFref on a y-axis and the time t on an x-axis. The x-axis of the graph 500 is the same as the x-axis of the graph 220 (Figure 2B). The reference frequency HFref is a plot 502, which has a substantially inverse relationship, such as an inverse relationship, with respect to the voltage signal 222. For example, the plot 502 has a substantially inverse shape compared to a shape of the voltage signal 222 (Figure 2B). To illustrate, during a time interval in which a magnitude of the voltage signal 222 increases, a frequency value of the plot 502 decreases. Further, in the illustration, during a time interval inwhich a magnitude of the voltage signal 222 decreases, a frequency value of the plot 502 increases.

[0104] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessorbased or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0105] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and / or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with the system.

[0106] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0107] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combinationthereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0108] In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[0109] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and / or manufacturing of semiconductor wafers.

[0110] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a CCP chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor within the ICP plasma chamber.

[0111] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other toolcomponents, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0112] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are those that manipulate physical quantities.

[0113] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0114] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0115] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0116] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0117] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0118] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

CLAIMS1. A method for achieving process rate uniformity, comprising: receiving a voltage signal measured at an output of an impedance matching circuit, wherein the voltage signal has a plurality of cycles; dividing each of the plurality of cycles of the voltage signal into a plurality of bins; determining a plurality of frequency offsets to be applied during a time period of the plurality of bins, wherein the plurality of frequency offsets are to be applied with respect to a reference frequency of operation of a first radio frequency (RF) generator, wherein for one of the plurality of bins, one of the plurality of frequency offsets is determined to maximize power that is delivered from the first RF generator; and controlling the first RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity, wherein the power that is delivered is reduced to achieve the process rate uniformity.

2. The method of claim 1, wherein the output of the impedance matching circuit is coupled to a plasma chamber.

3. The method of claim 1, wherein said modifying one of the plurality of frequency offsets occurs to output a modified frequency offset, the method further comprising: receiving a first amount of power that is delivered to the plasma chamber when the first RF generator is operated at the one of the plurality of offsets; receiving a second amount of power that is delivered to the plasma chamber when the first RF generator is operated at the modified frequency offset; determining a first process rate uniformity when the first RF generator is operated at the one of the plurality of frequency offsets; determining a second process rate uniformity when the first RF generator is operated at the modified frequency offset, wherein the second amount of power delivered is less than the first amount of power delivered; determining that the second process rate uniformity is greater than the first process rate uniformity; determining to apply the modified frequency offset instead of the one of the plurality of plurality of frequency offsets upon determining that the second process rate uniformity is greater than the first process rate uniformity.

4. The method of claim 1, wherein said modifying one of the plurality of frequency offsets includes increasing or decreasing the one of the plurality of frequency offsets from the reference frequency of operation of the first RF generator.

5. The method of claim 1, wherein the one of the plurality of frequency offsets is zero.

6. The method of claim 1, wherein a frequency of the voltage signal is equal to a frequency of a second RF generator, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator.

7. The method of claim 1, wherein the process rate uniformity is etch rate uniformity or deposition rate uniformity or a combination thereof.

8. The method of claim 1, wherein the first RF generator is controlled to modify the one of the plurality of frequency offsets during a time period of the one of the plurality of bins of a following cycle of an RF signal generated by a second RF generator, wherein the following cycle follows the plurality of cycles, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator.

9. The method of claim 1, wherein the first RF signal has a first state and a second state, the method further comprising: controlling a second RF generator to generate a second RF signal, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator, wherein the first RF signal has a first state and a second state, wherein the second RF signal transitions from the first state to the second state in synchronization with a transition from the first state to the second state of the first RF signal, wherein said controlling the first RF generator occurs during the first state or the second state of the first RF signal to modify one of the plurality of frequency offsets.

10. A controller for increasing process rate uniformity, comprising: a processor configured to: receive a voltage signal measured at an output of an impedance matching circuit, wherein the voltage signal has a plurality of cycles; divide each of the plurality of cycles of the voltage signal into a plurality of bins; determine a plurality of frequency offsets to be applied during a time period of the plurality of bins, wherein the plurality of frequency offsets are applied with respect to a reference frequency of operation of a first radio frequency (RF) generator, wherein for one of the plurality of bins, one of the plurality of plurality of frequency offsets is determined to maximize power that is delivered from the first RF generator; andcontrol the first RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity, wherein the power that is delivered is reduced to achieve the process rate uniformity; and a memory device coupled to the processor.

11. The controller of claim 10, wherein the output of the impedance matching circuit is coupled to a plasma chamber.

12. The controller of claim 10, wherein the one of the plurality of frequency offsets is modified to output the modified frequency offset, wherein the processor is configured to: receive a first amount of power that is delivered to the plasma chamber when the first RF generator is operated at the one of the plurality of offsets; receive a second amount of power that is delivered to the plasma chamber when the first RF generator is operated at the modified frequency offset; determine a first process rate uniformity when the first RF generator is operated at the one of the plurality of frequency offsets; determine a second process rate uniformity when the first RF generator is operated at the modified frequency offset, wherein the second amount of power delivered is less than the first amount of power delivered; determine that the second process rate uniformity is greater than the first process rate uniformity; determine to apply the modified frequency offset instead of the one of the plurality of plurality of frequency offsets upon determining that the second process rate uniformity is greater than the first process rate uniformity.

13. The controller of claim 10, wherein to modify the one of the plurality of frequency offsets, the processor is configured to increase or decrease the one of the plurality of frequency offsets from the reference frequency of operation of the first RF generator.

14. The controller of claim 10, wherein the one of the plurality of frequency offsets is zero.

15. The controller of claim 10, wherein a frequency of the voltage signal is equal to a frequency of a second RF generator, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator.

16. The controller of claim 10, wherein the process rate uniformity is etch rate uniformity or deposition rate uniformity or a combination thereof.

17. The controller of claim 10, wherein the first RF generator is controlled to modify the one of the plurality of frequency offsets during a time period of the one of the plurality of bins of a following cycle of an RF signal generated by a second RF generator, wherein the followingcycle follows the plurality of cycles, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator.

18. The controller of claim 10, wherein the first RF signal has a first state and a second state, wherein the processor is configured to: control a second RF generator to generate a second RF signal, wherein the second RF generator has a frequency of operation lower than the reference frequency of operation of the first RF generator, wherein the first RF signal has a first state and a second state, wherein the second RF signal transitions from the first state to the second state in synchronization with a transition from the first state to the second state of the first RF signal, wherein the first RF generator is controlled during the first state or the second state of the first RF signal to modify one of the plurality of frequency offsets.

19. A plasma system for increasing process rate uniformity, comprising: a low frequency (LF) radio frequency (RF) generator configured to generate an LF RF signal; a high frequency (HF) RF generator configured to generate an HF RF signal; an impedance matching circuit coupled to the LF RF generator and the HF RF generator to receive the LF and HF RF signals, wherein the impedance matching circuit is configured to generate a modified RF signal based on the LF and HF RF signals, wherein the impedance matching circuit has an output; and a plasma chamber coupled to the output of the impedance matching circuit to receive the modified RF signal; and a controller coupled to the LF and HF RF generators, wherein the controller is configured to: receive a voltage signal measured at the output of the impedance matching circuit, wherein the voltage signal has a plurality of cycles; divide each of the plurality of cycles of the voltage signal into a plurality of bins; determine a plurality of frequency offsets to be applied during a time period of the plurality of bins, wherein the plurality of frequency offsets are applied with respect to a reference frequency of operation of the HF RF generator, wherein for one of the plurality of bins, one of the plurality of plurality of frequency offsets is determined to maximize power that is delivered from the HF RF generator; and control the HF RF generator to modify one of the plurality of frequency offsets during the one of the plurality of bins to increase the process rate uniformity, wherein the power that is delivered is reduced to achieve the process rate uniformity.

20. The plasma system of claim 19, wherein the one of the plurality of frequency offsets is modified to output the modified frequency offset, wherein the controller is configured to: receive a first amount of power that is delivered to the plasma chamber when the HF RF generator is operated at the one of the plurality of offsets; receive a second amount of power that is delivered to the plasma chamber when the HF RF generator is operated at the modified frequency offset; determine a first process rate uniformity when the HF RF generator is operated at the one of the plurality of frequency offsets; determine a second process rate uniformity when the HF RF generator is operated at the modified frequency offset, wherein the second amount of power delivered is less than the first amount of power delivered; determine that the second process rate uniformity is greater than the first process rate uniformity; determine to apply the modified frequency offset instead of the one of the plurality of plurality of frequency offsets in response to the determination that the second process rate uniformity is greater than the first process rate uniformity.

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