Semiconductor switch component, manufacturing method, wafer, packaging structure, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor switch component, a manufacturing method, a wafer, a packaging structure, and an electronic device, which are used to decrease power switch component on-resistance while satisfying power switch component breakdown voltage requirements. The semiconductor switch component comprises a substrate, a channel layer, a barrier layer, at least one transistor, and a regrowth semiconductor layer. The regrowth semiconductor layer is located in a first area that is provided with one transistor or multiple transistors connected in parallel, and a second area that is not provided with a transistor, and the regrowth semiconductor layer is provided on the side of the barrier layer facing a gate electrode. The portion of the regrowth semiconductor layer located in the first area is used to reduce on-resistance, and the portion of the regrowth semiconductor layer located in the second area is used to balance the supply of a gas growth source in a thin-film growth process, thereby achieving a uniform material growth thickness and material compounding ratio.

Description

Semiconductor switching device and manufacturing method, wafer, packaging structure and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 31, 2024, with application number 202410146486.3 and invention name “Semiconductor switching device and manufacturing method, wafer, packaging structure and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor switching device and a manufacturing method, a wafer, a packaging structure and an electronic device. Background Art

[0003] With the continuous development of power semiconductor devices, traditional silicon-based power semiconductor devices, due to their low bandgap width, can no longer meet product requirements such as high voltage resistance, high temperature resistance, high efficiency, and high frequency. Therefore, wide bandgap power semiconductors, such as gallium nitride, have gradually replaced traditional silicon-based materials. Based on this, power switching devices made with wide bandgap power semiconductors have a high on-resistance per unit area to meet the design requirement of a high breakdown voltage, which can reduce the power switching device's conductive performance.

[0004] Summary of the Invention

[0005] The present application provides a semiconductor switching device and a manufacturing method, a wafer, a packaging structure and an electronic device, which are used to reduce the on-resistance of a power switching device while meeting the breakdown voltage requirements of the power switching device.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In one aspect of the present application, a semiconductor switching device is provided, which has a second region and a first region, and the second region is arranged around the first region. In addition, the semiconductor switching device includes a substrate, a channel layer, a barrier layer, at least one transistor and a regrown semiconductor layer. The channel layer is arranged on the substrate. The barrier layer is arranged on the side of the channel layer facing away from the substrate. At least one transistor is located in the first region, and the gate of the transistor is arranged on the side of the barrier layer facing away from the channel layer. The first region is a region where one transistor or multiple transistors in parallel are arranged, and the second region is a region where the above-mentioned transistors are not arranged. The regrown semiconductor layer is located in the first region and the second region, and the regrown semiconductor layer is arranged on the side of the barrier layer facing the gate.

[0008] In this case, the channel layer and the barrier layer can form a heterojunction. The polarization effect in the heterojunction can cause a two-dimensional electron gas to form at the interface between the channel layer and the barrier layer. The regrown semiconductor layer located in the first region can increase the concentration of the two-dimensional electron gas. This can increase the current of the semiconductor switching device and reduce the on-resistance per unit area (Ron) of the semiconductor switching device, thereby improving the conduction performance of the semiconductor switching device. Furthermore, the regrown semiconductor layer can be located in the second region. In this way, when forming the regrown semiconductor layer, the opening area of ​​the mask material used can expose not only the first region but also the second region. Based on this, the elements released by the gas growth source that fall into the first region through the opening area of ​​the mask material can form the portion of the regrown semiconductor layer located in the first region. Furthermore, the elements that fall into the second region through the opening area of ​​the mask material can form the portion of the regrown semiconductor layer located in the second region. This can achieve a balanced supply of the gas growth source during thin film growth, achieving uniform material growth thickness and material compound ratio. This can reduce the probability of unconsumed elements falling into the edge of the first region, resulting in a thicker edge of the regrown semiconductor layer in the first region, thereby improving the uniformity of the thickness of the regrown semiconductor layer in the first region.

[0009] In an optional embodiment, the bandgap of the regrown semiconductor layer is greater than the bandgap of the channel layer. Therefore, the regrown semiconductor layer can enhance the polarization effect in the heterojunction formed between the barrier layer and the channel layer, thereby increasing the concentration of the two-dimensional electron gas.

[0010] In one optional embodiment, the regrown semiconductor layer includes a first regrown layer and a second regrown layer. The first regrown layer is disposed in the first region, and a vertical projection of the first regrown layer on the substrate does not overlap with a vertical projection of the gate on the substrate, thereby mitigating the effect of the first regrown layer on the breakdown voltage of the semiconductor switching device. Furthermore, the second regrown layer is disposed in the second region and connected to the first regrown layer, such that the thickness of the first regrown layer facing the second region is uniform.

[0011] In an optional embodiment, the semiconductor switching device includes two adjacent transistors, and the two adjacent transistors are connected in parallel. In this way, the length of the gate of each transistor does not need to be too long, thereby reducing the size of the entire semiconductor switching device along the gate length direction. In addition, multiple transistors connected in parallel can reduce the resistance of the semiconductor switching device. In addition, the first regrown layer includes at least one first strip-type structure, and a first strip-type structure is arranged between the gates of two adjacent transistors. Along the extension direction of the gate, the two ends of the first strip-type structure are connected to the second regrown layer. In this way, the first strip-type structure can be arranged on one side of the gate, thereby avoiding overlapping with the gate, resulting in a reduction in the breakdown voltage of the semiconductor switching device. In addition, in the case where there are multiple strip-type gates in the first region, the first strip-type structure can be arranged alternately with the strip-type gates, so that the distribution of the multiple first strip-type structures has a certain regularity, which is conducive to simplifying the manufacturing process.

[0012] In an optional embodiment, the first regrown layer includes a plurality of parallel first stripe-shaped structures, with the first stripe-shaped structures extending in the same direction as the gate. This allows the gate and the first stripe-shaped structures to be arranged in parallel, resulting in a regular distribution of the plurality of first stripe-shaped structures, which facilitates a simplified manufacturing process.

[0013] In an optional embodiment, the second regrown layer is an annular structure, arranged around the first regrown layer. In this case, the plurality of first strip-shaped structures can be placed within the hollow region of the second regrown layer, with both ends of the first strip-shaped structures connected to the second regrown layer. Similarly, this allows the second regrown layer to consume the gas growth source at both ends of the first strip-shaped structures toward the second region, ensuring that the thickness at both ends of the first strip-shaped structures is consistent or approximately consistent with the thickness at the center.

[0014] In one optional embodiment, the line width of the second regrown layer is 10 μm to 1000 μm. This allows the amount of gas source consumed when forming the second regrown layer in the second region to be comparable to the amount of gas source consumed when forming the first regrown layer in the first region. This allows the thickness at the edge of the first regrown layer to be comparable to the thickness at the center, effectively ensuring uniform thickness across the first regrown layer.

[0015] In an optional embodiment, the vertical projection area of ​​the second regrown layer on the substrate is the same as the area of ​​the second region. This allows the surface of the semiconductor switch device in the second region to be relatively flat, thereby facilitating the preparation of other devices, such as pads.

[0016] In an optional embodiment, the second regrown layer includes a solid portion and a hollow portion that penetrates the solid portion. The solid portion includes at least two first annular structures nested in sequence, the hollow portion is located between two adjacent first annular structures, and the first annular structure is arranged around the first regrown layer. In addition, among the at least two first annular structures nested in sequence, the first annular structure located in the innermost circle is connected to both ends of the first strip structure. In this way, by controlling the number or area of ​​the first annular structures and the number and area of ​​the hollow portions in the second regrown layer, the first zone and the second zone consume the same amount of elements released by the gas growth source during the formation of the above-mentioned first regrown layer and the second regrown layer, which is conducive to improving the uniformity of the thickness of the first regrown layer.

[0017] In an optional embodiment, the second regrown layer includes a solid portion and a hollow portion passing through the solid portion. The solid portion includes a second annular structure and a second strip structure. The second annular structure is arranged around the first regrown layer. The second strip structure is located in the hollow area of ​​the second annular structure, the first end of the second strip structure is connected to the second annular structure, and the second end of the second strip structure is connected to the first strip structure; the hollow portion is located between the second strip structures that respectively connect two adjacent first strip structures. Similarly, by controlling the number or area of ​​the second strip structures and the number and area of ​​the hollow portions in the second regrown layer, the first and second regions can consume the same amount of elements released by the gas growth source during the formation of the above-mentioned first regrown layer and the second regrown layer, thereby improving the uniformity of the thickness of the first regrown layer.

[0018] In an optional embodiment, the first and second strip-shaped structures are connected to each other with the same line width. In this way, the first and second strip-shaped structures can be connected to form an integrated structure with uniform line width. Therefore, during the preparation of the first and second regrown layers, the first and second strip-shaped structures can be connected to form an integrated structure through the same opening area in the mask material, thereby simplifying the structure of the mask material.

[0019] In an optional embodiment, the third strip structure is located in the hollow area of ​​the second annular structure, and the second strip structure is located on the side of the third strip structure facing the first zone. The third strip structure is arranged in parallel with the first strip structure, and a gate is provided between the third strip structure and the first strip structure. Both ends of the third strip structure are connected to the second annular structure. The hollow portion is also located between the third strip structure and the second strip structure. Based on this, in the first zone, the outermost gate faces the side of the second zone, and by setting the above-mentioned third strip structure and the hollow area, and controlling the number or area of ​​the third strip structure, as well as the number and area of ​​the hollow portions, the gas growth source consumption on the side of the outermost gate facing the second zone in the first zone is equivalent to the gas growth source consumption at other positions in the first zone, so as to improve the uniformity of the thickness of the first regrown layer at various locations.

[0020] In an optional embodiment, the solid portion further includes a fourth strip-type structure, which is located in the hollow area of ​​the second annular structure. The fourth strip-type structure is located on the side of the third strip-type structure away from the second strip-type structure, and both ends of the fourth strip-type structure are connected to the second annular structure. The hollow portion is also located between the fourth strip-type structure and the third strip-type structure. Similarly, in the first region, the outermost gate faces the side of the second region. By setting the third strip-type structure, the fourth strip-type structure and the hollow portion, and controlling the number or area of ​​the third strip-type structure and the fourth strip-type structure, as well as the number and area of ​​the hollow portions, the consumption of the gas growth source at the edge position and the center position in the first region is made equivalent, so as to improve the uniformity of the thickness of the first regrown layer at various locations.

[0021] In one optional embodiment, the vertical projection area of ​​the solid portion on the substrate is equal to the vertical projection area of ​​at least one first stripe-shaped structure in the first regrown layer on the substrate. Similarly, during the formation of the first and second regrown layers, the first and second regions can consume comparable amounts of elements released by the gas growth source.

[0022] In an optional embodiment, the line width of the entity portion is 10 μm to 1000 μm. The technical effect of the line width of the entity portion is similar to the technical effect and value of the line width of the second regrown layer, and will not be repeated here.

[0023] In an optional embodiment, the transistor further includes a first electrode and a second electrode, the gate of the transistor being located between the first electrode and the second electrode, and the first electrode and the second electrode being disposed on a side of the channel layer facing away from the substrate. The first regrown layer is disposed closer to at least one of the first electrode or the second electrode relative to the gate. This allows the first regrown layer to be positioned away from the gate, preventing the first regrown layer from being affected by the greater electric field strength at the gate, which could reduce the breakdown voltage of the semiconductor switching device and affect its breakdown resistance.

[0024] In one optional embodiment, a portion of the first regrown layer is located between the first electrode and the substrate, and between the second electrode and the substrate. The vertical projections of the first electrode and the second electrode on the substrate overlap with the vertical projections of the first regrown layer on the substrate, respectively. The first electrode and the second electrode are in ohmic contact with the first regrown layer. Alternatively, vias are formed in the first regrown layer and the barrier layer, such that the first electrode and the second electrode contact the channel layer through different vias.

[0025] In one optional embodiment, the regrown semiconductor layer includes a compound of at least one of gallium, aluminum, and indium and nitrogen. In this manner, the material of the regrown semiconductor layer can be a Group III nitride semiconductor material, which can provide a stable semiconductor structure. For example, the material of the regrown semiconductor layer can be InN, GaN, AlN, InGaN, InAlN, AlGaN, or AlInGaN.

[0026] In one optional embodiment, the thickness of the regrown semiconductor layer is 5 nm to 100 nm. When the thickness of the regrown semiconductor layer is less than 5 nm, the manufacturing precision of the semiconductor switch device is required to be high, which is not conducive to simplifying the manufacturing process and reducing production costs. In addition, when the thickness of the regrown semiconductor layer is greater than 100 nm, the thickness of the regrown semiconductor layer is too thick, resulting in an uneven surface of the film layer subsequently prepared above the regrown semiconductor layer, and also causing the overall thickness of the semiconductor switch device to increase, which is not conducive to the design of ultra-thin devices.

[0027] In one optional embodiment, the first regrown layer includes a first portion and a second portion, wherein the first portion is closer to the second region than the second portion, and the thickness of the first portion is 0.5 to 1.5 times the thickness of the second portion. In this way, the thickness of the first portion located at the edge of the first region can be comparable to the thickness of the second portion located at the center of the first region, thereby achieving the purpose of improving the thickness uniformity of the first regrown layer within the first region.

[0028] In an optional embodiment, the transistor includes a gate semiconductor layer, which is located between the gate and the barrier layer and is in direct contact with the gate and the barrier layer, and the gate semiconductor layer is a P-type semiconductor layer. The gate semiconductor layer can adjust the semiconductor energy band so that there is no two-dimensional electron gas under the gate. In this case, the semiconductor switching device is a normally closed semiconductor switching device. The first electrode of the transistor is the source electrode, and the second electrode is the drain electrode, or the first electrode is the drain electrode and the second electrode is the source electrode. Based on this, when the gate-source voltage is greater than zero, a two-dimensional electron gas is formed at the interface between the barrier layer (including AlGaN) and the channel layer (including GaN) under the P-type semiconductor layer, and a conductive channel is formed between the first electrode and the second electrode of the transistor, and the semiconductor switching device is turned on.

[0029] In an optional embodiment, the gate of the transistor is in direct contact with the barrier layer. The semiconductor switch device is a normally-on semiconductor switch device.

[0030] In an optional embodiment, the semiconductor switching device further comprises a first dielectric layer, the first dielectric layer being located in the first region and covering the barrier layer. The first dielectric layer is provided with a first window and a second window. The first regrown layer is located within the first window, and the gate contacts the barrier layer through the second window. Therefore, during the preparation of the first dielectric layer, the coverage area of ​​the first regrown layer and the distance between the first regrown layer and the gate can be adjusted as needed by adjusting the opening area and position of the first window. For example, if the breakdown voltage of the semiconductor switching device meets design requirements and the on-state performance of the semiconductor switching device needs to be improved, the opening area of ​​the first window can be increased to increase the coverage area of ​​the first regrown layer, thereby improving the on-state performance of the semiconductor switching device. Alternatively, if the on-state performance of the semiconductor switching device meets design requirements and the breakdown voltage of the semiconductor switching device needs to be improved, the position of the first window can be adjusted so that the first window is closer to the first or second terminal of the transistor, thereby positioning the first regrown layer within the first window away from the gate, thereby improving the breakdown voltage of the semiconductor switching device.

[0031] Another aspect of the present application provides a wafer comprising at least two semiconductor switching devices of any one of the above-described types, wherein a scribe line of the wafer overlaps with a second region of the semiconductor switching device. The wafer has the same technical effects as the semiconductor switching devices provided in the aforementioned embodiments and will not be further described here.

[0032] Another aspect of the present application provides a packaging structure comprising a packaging substrate and any one of the semiconductor switching devices described above, wherein the semiconductor switching device is disposed on the packaging substrate. The packaging substrate has the same technical effects as the semiconductor switching device provided in the aforementioned embodiment, and will not be described in detail here.

[0033] Another aspect of the present application provides an electronic device comprising a circuit board and any one of the packaging structures described above, wherein the packaging structure is electrically connected to the circuit board. The electronic device has the same technical effects as the packaging structure provided in the above embodiment, and will not be described in detail here.

[0034] On the other hand, the present application provides a method for manufacturing a semiconductor switching device. The semiconductor switching device has a first region and a second region, and the second region is arranged around the periphery of the first region. The manufacturing method includes: forming a channel layer and a barrier layer on a substrate in sequence. Next, a mask material is formed on the side of the barrier layer facing away from the substrate, and the opening area of ​​the mask material exposes the first region and the second region. Next, a regrown semiconductor layer is formed in the second region and the first region. Next, at least one transistor is formed in the first region on the side of the barrier layer facing away from the channel layer. The first region is a region where one transistor or multiple transistors in parallel are provided, and the second region is a region where the above-mentioned transistors are not provided. The manufacturing method of the above-mentioned semiconductor switching device has the same technical effect as the semiconductor switching device provided in the aforementioned embodiment, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0036] FIG2 is a schematic diagram of a circuit structure of the power management chip in FIG1 ;

[0037] FIG3 is a schematic structural diagram of a wafer provided in an embodiment of the present application;

[0038] FIG4 is a schematic structural diagram of a packaging structure provided in an embodiment of the present application;

[0039] FIG5 is a schematic structural diagram of a semiconductor switch device provided in an embodiment of the present application;

[0040] FIG6 is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0041] FIG7 is a schematic diagram of region division of a semiconductor switch device provided in an embodiment of the present application;

[0042] FIG8 is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0043] FIG9 is a top view taken along the direction B in FIG8 ;

[0044] FIG10 is a schematic diagram of a semiconductor switch device manufacturing process provided in an embodiment of the present application;

[0045] FIG11( a ) and FIG11( b ) are schematic diagrams of the structure at a1 in FIG9 ;

[0046] FIG12(a) and FIG12(b) are schematic structural diagrams of position a2 in FIG9 ;

[0047] FIG13 is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0048] FIG14 is a top view taken along the direction C in FIG13;

[0049] FIG15A is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0050] FIG15B is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0051] FIG15C is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0052] FIG15D is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0053] FIG16 is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0054] FIG17A is another top view taken along the direction C in FIG13;

[0055] FIG17B is another top view taken along the direction C in FIG13;

[0056] FIG18 is a schematic structural diagram of another semiconductor switch device provided in an embodiment of the present application;

[0057] FIG19 is a cross-sectional view taken along the dotted line O1-O2 in FIG18;

[0058] FIG20 is a schematic structural diagram of another semiconductor switching device provided in an embodiment of the present application.

[0059] Reference numerals:

[0060] 01-Electronic device; 100-PCB; 101-Bus; 102-SoC; 103-Second RAM; 104-Communication chip; 105-Power management chip; 112-AP; 122-GPU; 132-First RAM; 1051-AC-DC voltage converter; 10511-First rectifier filter; 10512-Transformer; 10513-Control circuit; 10514-Second rectifier filter; 10515-Feedback circuit; 20-Semiconductor switching device; 200-Wafer; 201-Substrate; 2010-Dicing road; 30-Packaging structure; 301-Packaging substrate; 1001-First region; 1002-Second region; 202-Channel layer; 203-Barrier layer; 20 4-transistor; 205-regrowth semiconductor layer; 206-2DEG; 207-gate semiconductor layer; 31-mask material; 31-opening area; 32-gas growth source; 2051-first regrown layer; 20511-first part; 20512-second part; 2052-second regrown layer; 208-first dielectric layer; 401-first window; 402-second window; 218-third dielectric layer; 209-second dielectric layer; 210-field plate; 501-first strip-type structure; 502-solid part; 5021-first ring-shaped structure; 503-hollow part; 5022-second ring-shaped structure; 5023-second strip-type structure; 5024-third strip-type structure; 5025-fourth strip-type structure. DETAILED DESCRIPTION

[0061] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. When describing a single component, device, or system, multiple such components, devices, or systems can perform related functions. For example, one or more processors can perform the functions described in relation to one processor.

[0062] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0063] The limitations such as parallel, perpendicular, orthogonal, identical (for example, identical length, identical width, etc.) mentioned in the embodiments of the present application are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense. There may be a deviation of a predetermined angle between two components that are parallel or perpendicular to each other. In one embodiment, the predetermined threshold value may be less than or equal to a threshold value of 1 mm, for example, the predetermined threshold value may be 0.5 mm, or may be 0.1 mm. In one embodiment, the predetermined angle may be an angle within a range of ±10°, for example, the predetermined angle deviation is ±5°.

[0064] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated one; or, "connection" can be a direct connection, or an indirect connection through an intermediate medium. In addition, unless otherwise clearly specified and limited, the term "coupling" should be understood in a broad sense, for example, "coupling" can be a direct electrical connection, for example, physical contact and electrical conduction between two components, or it can be understood as the electrical connection between different components in the circuit structure through a physical line that can transmit electrical signals such as printed circuit board (PCB) copper foil or wire to transmit electrical signals for the purpose of transmitting electrical signals; or, "coupling" can be an indirect electrical connection between two components through an intermediate medium; or, "coupling" can be an electrical connection between two components in an airless / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0065] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0066] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; openings, holes and the like are represented by guide lines with wavy lines at the ends.

[0067] The embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology and other future communication technologies. The electronic device in the embodiment of the present application can be a (mobile phone), a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet, a smart headset), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device may also be a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, an electronic device in a 5G network, or an electronic device in a future evolved public land mobile communication network (PLMN), etc. The embodiments of the present application are not limited to this.

[0068] For example, as shown in FIG1 , the electronic device 01 may include a circuit board (e.g., the PCB) 100, a bus 101 disposed on the PCB 100 and electrically connected to the PCB 100, and a processor connected to the bus 101, such as a system on chip (SoC) 102. The SoC 102 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SoC 102 may include an application processor (AP) 112 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first RAM 132 for caching high-speed data. The first RAM 132 may be a static random access memory (SRAM) or an embedded flash memory (EFlash), etc. The AP 112, GPU 122, and first RAM 132 may be integrated into a single die, or may be separately disposed in multiple dies.

[0069] In addition, as shown in Figure 1, the electronic device 01 may further include a second RAM 103 connected to the SoC 102 through the bus 101. The second RAM 103 may be a dynamic random access memory (DRAM). The second RAM 103 may be used to store volatile data, such as temporary data generated by the SoC 102. The storage capacity of the second RAM 103 may generally be larger than the first RAM 132, but the reading speed is generally slower than the first RAM 132. In addition, the electronic device 01 may further include a communication chip 104 and a power management chip 105 connected to the SoC 102 through the bus 101. The communication chip 104 may be used for processing the protocol stack, or for amplifying, filtering, and other processing of analog RF signals, or for realizing the above functions simultaneously. The power management chip 105 may be used to power other chips.

[0070] For example, the communication chip 104 may include a radio frequency front-end chip, which may include a transmitting path and a receiving path. The transmitting path and the receiving path may be composed of a radio frequency power amplifier, a radio frequency filter, a duplexer, a radio frequency switch, a radio frequency low-noise amplifier, etc. Among them, the radio frequency power amplifier may use a semiconductor switching device, such as a high electron mobility power transistor (HEMT) to convert the power of a power supply into a current that varies according to the input signal, thereby playing the role of current and voltage amplification.

[0071] In addition, the power management chip 105 is an integrated circuit chip for managing and controlling the power supply system. The power management chip 105 can monitor, adjust and protect the power supply voltage, current and power to ensure the normal operation and optimal performance of the electronic device, while also saving energy and extending battery life. For example, the power management chip 105 may include a power switch, a power converter, a battery charger, a power monitor, an overvoltage protector, an undervoltage protector, etc. The above-mentioned power converter may include an alternating current (AC)-direct current (DC) voltage converter, referred to as an AC-DC voltage converter, a DC-DC voltage converter, a low dropout regulator (LDO), etc. Among them, the above-mentioned power converter may include a semiconductor switching device, such as a HEMT.

[0072] The following uses an AC-DC voltage converter as an example to illustrate the configuration of a semiconductor switching device, such as a HEMT, in the AC-DC voltage converter. For example, as shown in FIG2 , the AC-DC voltage converter 1051 may include a first rectifier filter 10511, a transformer 10512, a semiconductor switching device 20, a control circuit 10513, a second rectifier filter 10514, and a feedback circuit 10515.

[0073] Among them, the first rectifier filter 10511 is used to input the AC power V in-AC (For example, the mains 220V) is rectified to output a voltage with a pulsating waveform. The feedback circuit 10515 is based on the output DC voltage V out-DC The first rectifier filter 10511 is configured to receive a first voltage (e.g., 5V) and input a feedback signal to the control circuit 10513. The control circuit 10513 can perform pulse width modulation (PWM) control on the semiconductor switch device 20 according to the feedback signal to modulate the waveform of the electrical signal from the first rectifier filter 10511. The transformer 10512 can step down the electrical signal modulated by the semiconductor switch device 20. In addition, the second rectifier filter 10514 can rectify and filter the electrical signal from the transformer 10512 to output a DC voltage V to the load (e.g., a battery). out-DC , thereby charging the load, such as a battery.

[0074] The above is an example of the configuration of the semiconductor switch device 20 using the AC-DC voltage converter 1051. The application of the semiconductor switch device 20 in DC-DC voltage converters, radio frequency power amplifiers, etc. will not be described in detail here.

[0075] Based on this, the semiconductor switch device 20 can be independently packaged in a packaging structure, or packaged with other devices or chips in the same package chip, for example, using packaging technologies such as 2.5D (dimension) or 3D packaging. This application does not limit this.

[0076] Before packaging the semiconductor switching device 20, an embodiment of the present application may provide a wafer 200 as shown in FIG3 . The wafer 200 may include a plurality of the semiconductor switching devices 20 described above. The substrate 201 of the wafer 200 has cross-set scribing lanes 2010 , which may separate two adjacent semiconductor switching devices 20 . By cutting the wafer 200 along the scribing lanes 2010 , a plurality of semiconductor switching devices 20 as bare chips (dies) may be obtained. In order to facilitate the illustration of the structure of the semiconductor switching device 20 , an XYZ coordinate system is established in the accompanying drawings. As shown in FIG3 , the XY plane may be parallel to the surface of the substrate 201 .

[0077] Next, the semiconductor switch device 20 is packaged in a package structure 30 as shown in FIG4 . The semiconductor switch device 20 can be disposed on a package substrate 301 of the package structure 30. Furthermore, the package substrate 301 is disposed on a circuit board 100 of an electronic device so that the semiconductor switch device 20 can be electrically connected to the circuit board 100 via the package substrate 301.

[0078] The structure of the semiconductor switching device 20 described above is exemplified below. In some embodiments of the present application, as shown in FIG5 , the semiconductor switching device 20 may include a substrate 201, a channel layer 202, a barrier layer 203, at least one transistor 204, and a regrown semiconductor layer 205. The channel layer 202 is stacked on the substrate 201, and the barrier layer 203 is stacked on the side of the channel layer 202 facing away from the substrate 201. The transistor 204 may include a gate (G), a first electrode, and a second electrode. For example, the first electrode may be a source (S), and the second electrode may be a drain (D). Alternatively, for another example, the first electrode may be a drain, and the second electrode may be a source. For convenience of explanation, the following examples are all based on the example of the transistor 204 having the first electrode S and the second electrode D. In addition, the gate G is located between the first electrode S and the second electrode G, and the first electrode S and the second electrode G are arranged on the side of the channel layer 202 facing away from the substrate 201.

[0079] 5 may be the stacking direction of the substrate 201 , the channel layer 202 , the barrier layer 203 and the regrown semiconductor layer 205 , and the X direction may be the line width direction of the gate G, the first electrode S and the second electrode D.

[0080] On this basis, the gate G of the transistor 204 can be disposed on the side of the barrier layer 203 facing away from the channel layer 202. The regrown semiconductor layer 205 can be disposed on the side of the barrier layer 203 facing the gate G. Based on this, the channel layer 202, the barrier layer 203, and the regrown semiconductor layer 205 can constitute the epitaxial layer of the semiconductor switching device 20. The substrate 201 can serve as a carrier for the epitaxial layer.

[0081] For example, the substrate 201 may be at least one of a silicon (Si) substrate, a sapphire (Al2O3) substrate, or a silicon carbide (SiC) substrate. The channel layer 202 may include a group III nitride, such as gallium nitride (GaN). In other embodiments of the present application, the epitaxial layer of the semiconductor switching device 20 may further include a buffer layer (not shown in the figure) located between the substrate 201 and the channel layer 202. For example, the material of the buffer layer may include at least one of GaN, aluminum nitride (AlN), and aluminum gallium nitride (AlGaN). The buffer layer can reduce the probability of occurrence of phenomena such as interface mismatch, defects, or trap effects between the substrate 201 and the channel layer 202.

[0082] In addition, for example, the channel layer 202 may include a group III nitride, such as gallium nitride (GaN). The barrier layer 203 may include AlGaN. The barrier layer 203 and the channel layer 202 may form an AlGaN / GaN heterojunction. When two or more different semiconductor materials form a stacked structure, due to the difference in the lattice constant and band gap width of the two materials, there is a band difference at the interface of the two materials, forming the above-mentioned heterojunction. Based on this, in the above-mentioned heterojunction, due to the spontaneous polarization and piezoelectric polarization effects, the discontinuous band structure will form a potential well at the interface (the interface between the channel layer 202 and the barrier layer 203), and the electrons will be bound in the potential well, so that the electrons basically move in a direction parallel to the interface and the direction of electron movement is restricted in a direction perpendicular to the interface. In this way, a two-dimensional electron gas (2DEG) 206 can be formed at the above-mentioned interface. The 2DEG 206 can improve the mobility of electrons.

[0083] Therefore, the semiconductor switch device 20 provided in the embodiment of the present application can be a GaN-based HEMT device. Compared with Si-based or silicon carbide (SiC)-based semiconductor devices, the GaN-based HEMT device has higher electron mobility, saturation electron velocity, and breakdown electric field, and is more suitable for high-frequency or high-voltage and high-power applications, such as power adapters, vehicle charging, data centers, etc.

[0084] Based on this, as shown in FIG5 , in the process of manufacturing the semiconductor switching device 20, a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process can be used to sequentially epitaxially grow the channel layer 202, the buffer layer (not shown), and the barrier layer 203 on the substrate 201. Then, a patterning process is used to form the gate G, the first electrode S, and the second electrode D of the transistor 204. The gate G can be in Schottky contact with the barrier layer 203, and the first electrode S and the second electrode D can be in ohmic contact with the 2DEG 206.

[0085] For example, any one of the gate G, the first electrode S, and the second electrode D may include at least one of platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), or gold (Au). Alternatively, for another example, any one of the gate G, the first electrode S, and the second electrode D may also include a metal compound such as titanium nitride (TiN), tantalum nitride (TaN), tungsten titanium (WTi), etc. The materials of the gate G, the first electrode S, and the second electrode D may be the same or different, and this application does not limit this.

[0086] The above-mentioned patterning process includes an etching step and may also include other processes such as printing and inkjet for forming a predetermined pattern.

[0087] Based on this, as shown in FIG5 , the semiconductor switching device 20 may further include a gate semiconductor layer 207 , which may include P-type GaN. The gate semiconductor layer 207 may be referred to as a P-type semiconductor layer. The gate semiconductor layer 207 can adjust the semiconductor energy band so that there is no 2DEG 206 beneath the gate G. In this case, the semiconductor switching device 20 is a normally-off HEMT. When the gate-source voltage is greater than zero, a 2DEG 206 forms at the interface between the barrier layer 203 (comprising AlGaN) and the channel layer 202 (comprising GaN) beneath the P-type semiconductor layer (i.e., the gate semiconductor layer 207), forming a conductive channel between the first electrode S and the second electrode D, and the semiconductor switching device 20 is turned on.

[0088] Alternatively, in other embodiments of the present application, as shown in FIG6 , the gate G of the transistor 204 can be stacked on the surface of the barrier layer 203. In this case, a conductive channel is formed between the first electrode S and the second electrode D in the 2DEG 206, and the semiconductor switch device 20 is a normally-on HEMT. When the gate-source voltage is less than zero, the conductive channel between the first electrode S and the second electrode D is disconnected, and the semiconductor switch device 20 is turned off.

[0089] On this basis, the semiconductor switch device 20 shown in FIG. 5 or FIG. 6 may include a second region 1002 and a first region 1001. For example, the second region 1002 may be a passive area, and the first region 1001 may be an active area. The first region 1001 (i.e., the active area) may be a region of the semiconductor switch device 20 where one transistor 204 or multiple transistors 204 connected in parallel are disposed.

[0090] In this case, the active region may be the effective region when the transistor 204 is turned on, i.e., the region where the 2DEG 206 formed in the semiconductor switching device 20 is located. FIG6 illustrates an example in which a transistor 204 is disposed in the first region 1001. In this case, when the transistor 204 is turned on, the region where the 2DEG 206 formed in the semiconductor switching device 20 is located is the first region 1001.

[0091] Alternatively, in other embodiments of the present application, as shown in FIG8 , a plurality of transistors 204 may be provided in the first region 1001 , and the plurality of transistors 204 may be connected in parallel (i.e., adjacent transistors 204 may share a first electrode S or a second electrode D). In this case, when the plurality of transistors 204 connected in parallel are turned on, the 2DEGs 206 formed by the respective transistors 204 may be connected, and thus the region within the semiconductor switching device 20 where the connected 2DEGs 206 are located may be the first region 1001 .

[0092] Furthermore, the second region 1002 (i.e., the inactive region) is the region of the semiconductor switching device 20 excluding the first region 1001. Therefore, the second region 1002 may be a region where the transistor 204 is not disposed. As shown in FIG7 (a top view taken along the direction A in FIG5 ), the second region 1002 may be disposed around the first region 1001. FIG7 illustrates an example where the second region 1002 surrounds the first region 1001. In other embodiments of the present application, the second region 1002 need not surround the first region 1001.

[0093] For example, the semiconductor switching device 20 in FIG3 may include a device region (black portion) and a non-device region (white portion) disposed around the periphery of the device region. The non-device region (white portion) may overlap a portion of the dicing street 2010. The non-device region (white portion) may be the second region 1002 of the semiconductor switching device 20 in FIG7 . Furthermore, the semiconductor switching device 20 may further include a pad, which may be disposed in the non-device region (white portion) of the semiconductor switching device 20.

[0094] Alternatively, for another example, the second region 1002 of the semiconductor switch device 20 may also be disposed within the device region (black portion) of the semiconductor switch device 20 in FIG3 . The device region (black portion) may be a region having a semiconductor device, such as the transistor 204. This application does not limit the number of the second region 1002 and the first region 1001 in the semiconductor switch device 20.

[0095] For example, when the device region (black portion) in FIG. 3 has one transistor 204, the semiconductor switching device 20 may have one first region 1001 (i.e., active region), in which one transistor 204 is disposed. Alternatively, when the device region (black portion) in FIG. 3 has multiple transistors 204 connected in parallel, the semiconductor switching device 20 may have one first region 1001 (i.e., active region), in which multiple transistors 204 are connected in parallel.

[0096] Alternatively, when the device region (black portion) in FIG. 3 has multiple non-parallel, mutually independent transistors 204, the semiconductor switch device 20 may have multiple first regions 1001, each of which may have a transistor 204 disposed therein, and adjacent first regions 1001 may be separated by a second region 1002 (i.e., an inactive region). Alternatively, when the device region (black portion) in FIG. 3 has, in addition to multiple parallel transistors 204, an independent transistor that is non-parallel to the multiple transistors, the semiconductor switch device 20 may have two first regions 1001 (i.e., active regions), one of which may have multiple parallel transistors 204 disposed therein, and the other of which may have the independent transistor disposed therein, and the two first regions 1001 may be separated by a second region 1002 (i.e., an inactive region).

[0097] For ease of explanation, the following description uses the normally-off HEMT shown in FIG. 5 as an example, with multiple transistors 204 connected in parallel disposed within the first region 1001. FIG. 7 illustrates the first region 1001 and the second region 1002 as rectangular shapes, but does not limit the shapes of the first region 1001 and the second region 1002. The shapes of the first region 1001 and the second region 1002 may also be circular or polygonal.

[0098] In this case, as shown in FIG9 (a top view taken along the direction B in FIG8 ), a plurality of parallel-connected gates G of the transistors 204 may be provided in the first region 1001 , wherein the gates G are strip-shaped, and the Y direction may be the extending direction of the gates G.

[0099] Based on this, compared to a solution in which only one transistor is provided in the semiconductor switch device, since the multiple transistors 204 are connected in parallel, the length of the gate G of each transistor 204 along the Y direction does not need to be too long, thereby reducing the size of the entire semiconductor switch device 20 along the Y direction. In addition, the multiple transistors 204 connected in parallel can reduce the resistance of the semiconductor switch device 20.

[0100] On this basis, it can be seen from the above that the semiconductor switching device 20 can further include a regrown semiconductor layer 205 as shown in FIG8 . The regrown semiconductor layer 205 can be disposed on the side of the barrier layer 203 facing the gate G of the transistor 204, and the bandgap of the regrown semiconductor layer 205 is greater than the bandgap of the channel layer 202. In addition, the regrown semiconductor layer 205 can be disposed in the first region 1001.

[0101] In this case, as shown in FIG8 , within the first region 1001 , a regrown semiconductor layer 205 is provided on the side of the barrier layer 203 facing the gate G of the transistor 204 , and the bandgap of the regrown semiconductor layer 205 is greater than the bandgap of the channel layer 202 . Therefore, the regrown semiconductor layer 205 can enhance the polarization effect in the heterojunction formed between the barrier layer 203 and the channel layer 202 , thereby increasing the concentration of the 2DEG 206 . This can increase the current of the semiconductor switch device 20 and reduce the on-resistance per unit area (Ron) of the semiconductor switch device 20 , thereby improving the conduction performance of the semiconductor switch device 20 . The concentration of the 2DEG 206 refers to the surface density of the 2DEG. When other properties of the semiconductor switch device 20 (such as electron mobility) remain unchanged, the greater the concentration of the 2DEG, the greater the current of the semiconductor switch device 20 .

[0102] Furthermore, while maintaining the overall on-resistance of the semiconductor switch device 20 to meet breakdown voltage design requirements, reducing the on-resistance per unit area of ​​the semiconductor switch device 20 can reduce the area of ​​the semiconductor switch device 20, thereby improving the integration of electronic devices. This allows the semiconductor switch device 20 to have a high breakdown voltage and good on-state performance while also being compact.

[0103] Furthermore, while the regrown semiconductor layer 205 in the first region 1001 improves the on-state performance of the semiconductor switching device 20, it also reduces the breakdown resistance of the semiconductor switching device 20 (e.g., reduces the breakdown voltage). Therefore, when the semiconductor switching device 20 is in the off state, due to the high electric field intensity near the gate G, in the first region 1001, to mitigate the effect of the regrown semiconductor layer 205 on the breakdown voltage of the semiconductor switching device 20, for example, as shown in FIG9 , the vertical projection of the regrown semiconductor layer 205 on the substrate 201 (as shown in FIG8 ) may not overlap with the vertical projection of the gate G of the transistor 204 on the substrate 201.

[0104] For example, the regrown semiconductor layer 205 may include a compound of at least one of gallium (Ga), aluminum (Al), and indium (In) and nitrogen (N). Thus, the material of the regrown semiconductor layer 205 may be a Group III nitride semiconductor material, which can provide the regrown semiconductor layer 205 with a stable semiconductor structure. For example, the material of the regrown semiconductor layer 205 may be InN, GaN, AlN, InGaN, InAlN, AlGaN, or AlInGaN. The bandgap of Group III nitride semiconductor materials can range from 0.63 eV for InN to 3.40 eV for GaN and then to 6.28 eV for AlN.

[0105] Based on this, it can be seen from the above that the MOCVD process can be used, as shown in Figure 10, to form the regrown semiconductor layer 205 on the barrier layer 203 in the first region 1001. During the MOCVD process, a mask material 31 is required to be placed above the barrier layer 203. The gas growth source 32 releases elements along the arrows. These elements pass through the openings 310 of the mask material 31 and fall onto the surface of the barrier layer 203, where they react to form a crystal structure and ultimately form the regrown semiconductor layer 205.

[0106] However, as shown in FIG10 , some elements released from the gas growth source 32 remain unconsumed and thus fall onto the non-opening portions of the mask material 31. Around the openings of the mask material 31, these unconsumed elements attached to the mask material 31 migrate to the surface of the barrier layer 203 as indicated by the dashed arrows in the figure, thereby causing uneven thickness of the regrown semiconductor layer 205 in the first region 1001 and, in turn, affecting the performance of the semiconductor switch device 20.

[0107] For example, position a1 of the first region 1001 in FIG9 is located at one of the four corners of the first region 1001 and is the boundary between the first region 1001 and the second region 1002. Specifically, as shown in FIG11(a), there are three regions around position a1, namely region ①, region ②, and region ③, all of which are located within the second region 1002 (as shown in FIG9). Therefore, during the preparation of the regrown semiconductor layer 205 in the first region 1001, the elements deposited on the mask material 31 (as shown in FIG10) in regions ①, ②, and ③ will migrate to position a1 of the regrown semiconductor layer 205.

[0108] Based on this, as shown in FIG11(b), the thickness D1 at position a1 in the regrown semiconductor layer 205 is greater than the thickness D0 of the regrown semiconductor layer 205 near the center position a0 shown in FIG9. For example, as shown in Table 1, D1 can be 2.5 to 3.5 times D0. The regrown semiconductor layer 205 shown in FIG11(b) is flanked by the gate semiconductor layer 207 below the gate G of the transistor. Since the gate G is strip-shaped, the gate semiconductor layer 207 is also strip-shaped.

[0109] In addition, as shown in FIG9 , position a2 of the first region 1001 is located at the edge of the first region 1001 and not at a corner. This position is also the boundary between the first region 1001 and the second region 1002. Specifically, as shown in FIG12 (a), there is an area around position a2, namely, area ①, which is located within the second region 1002 (as shown in FIG9 ). Therefore, during the preparation of the above-mentioned regrown semiconductor layer 205 in the first region 1001, the elements deposited on the mask material 31 (as shown in FIG10 ) in the above-mentioned area ① will migrate to position a1 of the regrown semiconductor layer 205. Based on this, as shown in FIG12 (b), the thickness D2 of the regrown semiconductor layer 205 at position a2 is greater than the thickness D0 of the regrown semiconductor layer 205 near the center position a0 shown in FIG9 . For example, as shown in Table 1, D2 can be 2 to 3 times D0.

[0110] Table 1

[0111] In this case, to ensure uniform thickness across the regrown semiconductor layer 205 within the first region 1001, as shown in FIG13 , in the semiconductor switch device 20 provided in an embodiment of the present application, the regrown semiconductor layer 205 may also be located within the second region 1002. In this manner, the aforementioned MOCVD process can be employed on the barrier layer 203, such that the elements released by the gas growth source 32 (as shown in FIG10 ) that fall within the first region 1001 form the portion of the regrown semiconductor layer 205 located within the first region 1001, while the elements that fall within the second region 1002 form the portion of the regrown semiconductor layer 205 located within the second region 1002. This balances the supply of the gas growth source during thin film growth, achieving uniform material growth thickness and compound ratio. This reduces the probability of unconsumed elements falling within positions a1 and a2 (as shown in FIG9 ) of the first region 1001, thereby improving the thickness uniformity of the regrown semiconductor layer 205 within the first region 1001.

[0112] For example, when the regrown semiconductor layer 205 is disposed in both the first region 1001 and the second region 1002 of the semiconductor switching device 20, the thickness D1 at position a1 and the thickness D2 at position a2 shown in FIG14 (a top view taken along direction C of FIG13) are as shown in Table 2. Specifically, as shown in FIG11(a), regions ①, ②, and ③ surrounding position a1 are all located within the second region 1002 (as shown in FIG14). Therefore, during the formation of the regrown semiconductor layer 205 within the first region 1001 and the second region 1002, regions ①, ②, and ③ consume elements provided by the gas growth source, resulting in the thickness D1 of the regrown semiconductor layer 205 at position a1 being less than the thickness D0 of the regrown semiconductor layer 205 near the center position a0 shown in FIG14. For example, as shown in Table 2, D1 can be 0.5 to 1.5 times D0.

[0113] Similarly, when the regrown semiconductor layer 205 is disposed in both the first region 1001 and the second region 1002 of the semiconductor switching device 20, there is a region surrounding position a2 in the first region 1001 in FIG14 , namely, region ①, located within the second region 1002 (as shown in FIG14 ). Therefore, during the formation of the regrown semiconductor layer 205 in the first and second regions 1001 and 1002, region ① consumes elements provided by the gas growth source, resulting in a thickness D2 of the regrown semiconductor layer 205 at position a2 being smaller than a thickness D0 of the regrown semiconductor layer 205 near the center position a0 shown in FIG14 . For example, as shown in Table 2, D2 can be 0.5 to 1.5 times D0.

[0114] Table 2

[0115] As can be seen from the above description, the regrown semiconductor layer 205 is located within the first region 1001 and the second region 1002 of the semiconductor switching device 20. Based on this, as shown in FIG14 , the regrown semiconductor layer 205 may include a first regrown layer 2051 located within the first region 1001 and a second regrown layer 2052 located within the second region 1002. The first regrown layer 2051 includes a first portion 20511 and a second portion 20512. The first portion 20511 is closer to the second region 1002 than the second portion 20512. Therefore, the center position a0 of the first region 1001 may be the location of the second portion 20512, and the edge position a1 (or a2) of the first region 1001 may be the location of the first portion 20511. Since the thickness of position a1 (or a2) is 0.5 to 1.5 times that of the center position a0, the thickness of the first portion 20511 may be 0.5 to 1.5 times that of the second portion 20512. In this way, in the first regrown layer 2051 of the first zone 1001, the thickness of the first part 20511 located at the edge of the first zone 1001 can be equivalent to the thickness of the second part 20512 located at the center of the first zone 1001, thereby achieving the purpose of improving the thickness uniformity of the first regrown layer 2051 in the first zone 1001.

[0116] On this basis, the thickness of the above-mentioned regrown semiconductor layer 205 (the dimension along the Z direction in Figure 13) can be 5nm to 100nm. When the thickness of the regrown semiconductor layer 205 is less than 5nm, the manufacturing precision of the semiconductor switch device 20 is required to be high, which is not conducive to simplifying the manufacturing process and reducing production costs. In addition, when the thickness of the regrown semiconductor layer 205 is greater than 100nm, the thickness of the regrown semiconductor layer 205 is too thick, which will cause the surface of the film layer subsequently prepared above the regrown semiconductor layer 205 to be uneven, and will also cause the overall thickness of the semiconductor switch device 20 to increase, which is not conducive to the design of ultra-thin devices. The thickness of the above-mentioned regrown semiconductor layer 205 can be 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0117] Furthermore, the above description is based on an example in which the semiconductor switch device 20 includes a single regrown semiconductor layer 205. In other embodiments of the present application, the semiconductor switch device 20 may further include multiple regrown semiconductor layers 205. Different regrown semiconductor layers 205 may contain different elements, or different regrown semiconductor layers 205 may contain the same elements but with different proportions of the elements. This application does not impose any limitation on this.

[0118] In order to make the thickness of the first regrown layer 2051 on the side facing the second zone 1002 as shown in Figure 15A uniform, the first regrown layer 2051 and the second regrown layer 2052 are connected, so that the second regrown layer 2052 can consume the gas growth source at the edge position of the first regrown layer 2051 facing the second zone 1002, so that the thickness at the edge position of the first regrown layer 2051 is consistent or approximately consistent with the thickness at the center position, thereby achieving the purpose of making the thickness of the first regrown layer 2051 uniform.

[0119] Based on this, in some embodiments of the present application, as shown in FIG. 15A , it can be seen from the above that, in order to mitigate the impact of the regrown semiconductor layer 205 on the breakdown voltage of the semiconductor switch device 20, the vertical projection of the regrown semiconductor layer 205 on the substrate 201 does not overlap with the vertical projection of the gate G of the transistor 204 on the substrate 201. Therefore, the vertical projection of the first regrown layer 2051 on the substrate 201 does not overlap with the vertical projection of the gate G on the substrate 201.

[0120] On this basis, as shown in FIG15A , to further reduce the impact of the first regrown layer 2051 on the breakdown voltage of the semiconductor switch device 20, the first regrown layer 2051 can be disposed closer to at least one of the first electrode S or the second electrode D of the transistor 204 relative to the gate G. This allows the first regrown layer 2051 to be positioned away from the gate G, preventing the first regrown layer 2051 from being affected by the larger electric field strength at the gate G, which could lower the breakdown voltage of the semiconductor switch device 20 and affect its breakdown resistance.

[0121] Based on this, in order to allow the first regrown layer 2051 to be positioned close to at least one of the first electrode S or the second electrode D of the transistor 204, a first dielectric layer 208 is provided as shown in FIG15A . The first dielectric layer 208 can be located in the first region 1001 and cover the barrier layer 203. Furthermore, as shown in FIG15B , a first window 401 and a second window 402 are provided on the first dielectric layer 208. The first regrown layer 2051 (shown in FIG15A ) is located within the first window 401, and the gate G (shown in FIG15A ) passes through the second window 402. If the semiconductor switching device 20 includes a gate semiconductor layer 207, the gate G located within the second window 402 can contact the gate semiconductor layer 207.

[0122] For example, the first dielectric layer 208 may include at least one of silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and gallium oxide (Ga 2 O 3 ).

[0123] Based on this, during the preparation of the first dielectric layer 208, the coverage area of ​​the first regrown layer 2051 and the distance between the first regrown layer 2051 and the gate G can be adjusted as needed by setting the opening area and position of the first window 401. For example, when the breakdown voltage of the semiconductor switch device 20 meets the design requirements and the conduction performance of the semiconductor switch device 20 needs to be improved, the opening area of ​​the first window 401 can be increased to increase the coverage area of ​​the first regrown layer 2051, thereby improving the conduction performance of the semiconductor switch device 20.

[0124] Or, as another example, when the conduction performance of the semiconductor switching device 20 meets the design requirements and the breakdown voltage of the semiconductor switching device 20 needs to be increased, the position of the above-mentioned first window 401 can be adjusted so that the first window 401 can be closer to the first pole D or the second pole S of the transistor 204, so that the first regrown layer 2051 located in the first window 401 can be arranged away from the gate G, thereby achieving the purpose of increasing the breakdown voltage of the semiconductor switching device 20.

[0125] Based on this, the method for manufacturing the semiconductor switching device 20 may include: first, sequentially forming a channel layer 202, a barrier layer 203, and a gate semiconductor layer 207 located on a side of the barrier layer 203 facing away from the substrate 201 on a substrate 201 as shown in FIG15C . Next, forming a dielectric material layer covering the gate semiconductor layer 207 and the barrier layer 203. The dielectric material layer may include at least one of SiN, SiO2, Al2O3, AlN, and Ga2O3. Next, an etching process may be used to remove a portion of the dielectric layer material to form a first dielectric layer 208 having the first window 401 and the second window 402. The first window 401 and the second window 402 may be formed through two etching processes.

[0126] For example, a first opening 401 as shown in FIG15C can be formed by an etching process. Next, a mask material 31 is formed on the side of the barrier layer 203 facing away from the substrate 201. The opening region 310 of the mask material 31 exposes the first region 1001 and the second region 1002. Next, using the mask material 31 as a mask and employing the aforementioned MOCVD process, the elements released by the gas growth source 32 fall into the first region 1001 and the second region 1002, thereby forming a regrown semiconductor layer 205 within the first region 1001 and the second region 1002 (as shown in FIG15A).

[0127] The first dielectric layer 208 shown in FIG. 15C can then be removed, and a third dielectric layer 218 can be formed as shown in FIG. 15D . The third dielectric layer 218 can cover the regrown layer (including the first regrown layer 2051). A second window 402 can then be formed on the third dielectric layer 218 by an etching process. Next, a gate G as shown in FIG. 15A is formed within the second window 402. Thereafter, a first electrode S and a second electrode D of the transistor 204 are formed to form at least one transistor 204 located in the first region 1001 on the side of the barrier layer 203 facing away from the channel layer 202. Alternatively, for another example, after forming the first regrown layer 2051 within the first window 401, the first dielectric layer 208 can be retained, and then a second window 402 as shown in FIG. 15B can be formed on the first dielectric layer 208. Next, the gate G of the transistor 204 is formed as described above, followed by the first electrode S and the second electrode D.

[0128] For example, the vertical projections of the first electrode S and the second electrode D on the substrate 201 overlap with the vertical projections of the first regrown layer 2051 on the substrate 201, respectively. The first electrode S and the first electrode D can be directly formed on the surface of the first regrown layer 2051 facing away from the substrate 201, and an annealing process is performed to make the first electrode S and the first electrode D ohmic contact with the first regrown layer 2051. Alternatively, for another example, vias can be formed in the first regrown layer 2051 and the barrier layer 203, so that the first electrode S and the first electrode D contact the channel layer 202 through the vias. This is not limited in this application.

[0129] In addition, as shown in FIG16 , the method for manufacturing the semiconductor switch 20 may further include forming at least one second dielectric layer 209 and a field plate (FP) 210 on the side of the gate G of the transistor 204 facing away from the substrate 201. The second dielectric layer 209 is used to insulate the field plate 210 from the gate G, or the second dielectric layer 209 is also used to insulate the adjacent field plate 210. The field plate 210 may be electrically connected to at least one of the gate G, the first electrode S, and the second electrode D of the transistor 204 to adjust the electric field. This application does not limit the number and arrangement of the field plates 210. FIG16 only illustrates two field plates 210 as an example.

[0130] The shapes of the first regrown layer 2051 and the second regrown layer 2052 are exemplified below. In some embodiments of the present application, as described above, when the semiconductor switching device 20 includes multiple transistors 204 connected in parallel, as shown in FIG17A , the gates G of the multiple transistors within the first region 1001 are strip-shaped and arranged side by side. Based on this, the first regrown layer 2051 can include at least one first strip-shaped structure 501, with one first strip-shaped structure 501 disposed between the gates G of two adjacent transistors. Along the extension direction of the gates G (i.e., the Y direction), both ends of the first strip-shaped structure 501 are connected to the second regrown layer 2052.

[0131] In this way, the first stripe-shaped structure 501 can be disposed on one side of the gate G, thereby avoiding overlapping with the gate G and reducing the breakdown voltage of the semiconductor switch device 20. Furthermore, when multiple stripe-shaped gates G are present within the first region 1001, the first stripe-shaped structures 501 can be alternately disposed with the stripe-shaped gates G, so that the distribution of the multiple first stripe-shaped structures 501 has a certain regularity, which helps simplify the structure of the MOCVD mask material and achieves the purpose of simplifying the manufacturing process. For example, the line width of the multiple first stripe-shaped structures 501 can be the same, further simplifying the manufacturing process.

[0132] Furthermore, as shown in FIG17A , the second regrown layer 2052 in the second region 1002 can be annular and arranged around the first regrown layer 2051. In this case, the plurality of first strip-shaped structures 501 can be disposed within the hollow region of the second regrown layer 2052, with both ends of the first strip-shaped structures 501 connected to the second regrown layer 2052. Similarly, in this manner, the second regrown layer 2052 can consume the gas growth source of the first strip-shaped structures 501 at both ends of the second region 1002, thereby ensuring that the thickness at both ends of the first strip-shaped structures 501 is consistent or approximately consistent with the thickness at the center.

[0133] On this basis, in some embodiments of the present application, as further shown in FIG. 17A , the line width H of the second regrown layer 2052 can be between 10 μm and 1000 μm. When the line width H of the second regrown layer 2052 is less than 10 μm, the consumption of elements released by the gas growth source at the edge of the first regrown layer 2051 during the formation of the second regrown layer 2052 is relatively low. This results in a significant difference between the thickness at the edge of the first regrown layer 2051 and the thickness at the center of the first regrown layer 2051, reducing the thickness uniformity of the first regrown layer 2051. Furthermore, when the line width H of the second regrown layer 2052 is greater than 1000 μm, while the difference between the thickness at the edge of the first regrown layer 2051 and the thickness at the center of the first regrown layer 2051 can be effectively reduced, the wider width H of the second regrown layer 2052 occupies a larger space, hindering a compact device layout.

[0134] Based on this, when the line width H of the second regrown layer 2052 is within a range of 10 μm to 1000 μm, the amount of gas source consumed when forming the second regrown layer 2052 in the second region 1002 can be comparable to the amount of gas source consumed when forming the first regrown layer 2051 in the first region 1001. This allows the thickness at the edge of the first regrown layer 2051 to be comparable to the thickness at the center, effectively ensuring uniform thickness across the first regrown layer 2051. For example, the line width H can be 10 μm, 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, 200 μm, 400 μm, 600 μm, 800 μm, or 1000 μm.

[0135] Alternatively, in other embodiments of the present application, as shown in FIG17B , the vertical projection area of ​​the second regrown layer 2052 on the substrate 201 (as shown in FIG16 ) can be the same or approximately the same as the area of ​​the second region 1002. This allows the surface of the semiconductor switch device 20 in the second region 1002 to be relatively flat, thereby facilitating the fabrication of other devices, such as pads 60. FIG17B only illustrates the location of the pads 60 and does not limit the number, shape, or structure of the pads 60.

[0136] The above is an example of the first regrown layer 2051 and the second regrown layer 2052 shown in Figure 17A or Figure 17B, in which the first regrown layer 2051 in the first zone 1001 includes a plurality of first strip structures 501 arranged at intervals, and the second regrown layer 2052 in the second zone 1002 is a ring.

[0137] In other embodiments of the present application, as shown in FIG18 , similarly, the first regrown layer 2051 within the first region 1001 includes a plurality of first strip-shaped structures 501 spaced apart from each other. The arrangement and technical effects of the first strip-shaped structures 501 are the same as described above and will not be further elaborated here. The difference is that the second regrown layer 2052 may include a solid portion 502 and a hollow portion 503 extending through the solid portion 502. As shown in FIG19 (a cross-sectional view taken along the dashed line O1-O2 in FIG18 ), the hollow portion 503 refers to a hole structure formed by removing a portion of the thin film layer used to form the second regrown layer 2052 through the patterning process. The hollow portion 503 can expose the film layer of the second regrown layer 2052 facing below the substrate 201, such as the barrier layer 203. Furthermore, the solid portion 502 refers to the portion of the thin film layer used to form the second regrown layer 2052 that has not been removed.

[0138] Continuing with FIG. 18 , the solid portion 502 may include at least two first annular structures 5021 nested in sequence, each of which is disposed around the first regrown layer 2051. Furthermore, the hollow portion 503 may be located between two adjacent first annular structures 5021. Furthermore, the innermost first annular structure 5021 of the at least two nested first annular structures 5021 may be connected to both ends of the first strip-shaped structure 501 in the first regrown layer 2051, thereby connecting the edge of the first strip-shaped structure 501 to the second regrown layer 2052.

[0139] In this way, by controlling the number or area of ​​the first annular structures 5021 and the number and area of ​​the hollow portions 503 in the second regrown layer 2052, it is possible to ensure that in the process of forming the above-mentioned first regrown layer 2051 and the second regrown layer 2052, the first zone 1001 and the second zone 1002 consume the same amount of elements released by the gas growth source, which is beneficial to improving the uniformity of the thickness of the first regrown layer 2051 at various locations.

[0140] Based on this, in order to ensure that the first zone 1001 and the second zone 1002 consume the same amount of elements released by the gas growth source during the formation of the above-mentioned first regrown layer 2051 and the second regrown layer 2052, the area of ​​the vertical projection of the solid part 502 (including multiple first ring structures 5021) shown in Figure 18 on the substrate 201 (as shown in Figure 16) can be the same as the area of ​​the vertical projection of at least one first strip structure 501 in the first regrown layer 2051 on the substrate 201.

[0141] Alternatively, in some other embodiments of the present application, as shown in FIG20 , when the second regrown layer 2052 includes a solid portion 502 and a hollow portion 503, the solid portion 502 may include a second ring-shaped structure 5022 and a second strip-shaped structure 5023. The second ring-shaped structure 5022 is disposed around the first regrown layer 2051. The second strip-shaped structure 5023 is located within the hollow region of the second ring-shaped structure 5022, and a first end of the second strip-shaped structure 5023 is connected to the second ring-shaped structure 5022, while a second end of the second strip-shaped structure 5023 is connected to the first strip-shaped structure 501.

[0142] In this case, a second strip-type structure 5023 can be set at each end of a first strip-type structure 501, so that the first strip-type structure 501 can be connected to the second ring structure 5022 through the second strip-type structures 5023 at both ends, so that the first regrown layer 2051 located in the first zone 1001 and the second regrown layer 2052 located in the second zone 1002 are connected.

[0143] For example, the line widths of the connected first strip-shaped structures 501 and second strip-shaped structures 5023 can be the same. In this way, the first strip-shaped structures 501 and second strip-shaped structures 5023 can be connected to form an integrated structure with uniform line width. Therefore, during the process of preparing the first regrown layer 2051 and second regrown layer 2052 using MOCVD, the first strip-shaped structures 501 and second strip-shaped structures 5023 connected to form an integrated structure can be formed through the same opening area in the mask material, thereby simplifying the structure of the mask material.

[0144] Furthermore, the hollow portion 503 can be located between the second strip-shaped structures 5023 that connect two adjacent first strip-shaped structures 501. That is, along the X-direction, the hollow portion 503 can be provided between two adjacent second strip-shaped structures 5023. Similarly, by controlling the number or area of ​​the second strip-shaped structures 5023 and the number and area of ​​the hollow portions 503 in the second regrown layer 2052, the first region 1001 and the second region 1002 can consume comparable amounts of elements released by the gas growth source during the formation of the first regrown layer 2051 and the second regrown layer 2052, thereby improving the thickness uniformity of the first regrown layer 2051.

[0145] Continuing with FIG20 , the solid portion 502 may further include a third stripe-shaped structure 5024 located within the hollow region of the second ring-shaped structure 5022. The second stripe-shaped structure 5023 is located on the side of the third stripe-shaped structure 5024 facing the first region 1001. The third stripe-shaped structure 5024 may be arranged parallel to the first stripe-shaped structure 501, with a gate G disposed between the third stripe-shaped structure 5024 and the first stripe-shaped structure 501. Both ends of the third stripe-shaped structure 5024 are connected to the second ring-shaped structure 5022. The hollow portion 503 is also located between the third stripe-shaped structure 5024 and the second stripe-shaped structure 5023.

[0146] In this case, since the third stripe structure 5024 is located in the second region 1002 and there is a gate G between the third stripe structure 5024 and the first stripe structure 501 , the gate G between the third stripe structure 5024 and the first stripe structure 501 is the outermost gate in the first region 1001 .

[0147] Based on this, in the first zone 1001, the outermost gate G is located on the side facing the second zone 1002. By setting the above-mentioned third strip-type structure 5024 and the hollow portion 503, and controlling the number or area of ​​the third strip-type structure 5024, as well as the number and area of ​​the hollow portions 503, the gas growth source consumption on the side of the outermost gate G in the first zone 1001 facing the second zone 1002 is equivalent to the gas growth source consumption at other positions in the first zone 1001, so as to improve the uniformity of the thickness of the first regrown layer 2051 at various locations.

[0148] Continuing with FIG20 , the solid portion 502 may further include a fourth strip-shaped structure 5025, which may be located within the hollow region of the second annular structure 5022. The fourth strip-shaped structure 5025 is located on the side of the third strip-shaped structure 5024 facing away from the second strip-shaped structure 5023, with both ends of the fourth strip-shaped structure 5025 connected to the second annular structure 5022. The hollow portion 503 is also located between the fourth strip-shaped structure 5025 and the third strip-shaped structure 5024.

[0149] Similarly, in the first region 1001, the outermost gate G faces the side of the second region 1002. By setting the above-mentioned third strip-type structure 5024, fourth strip-type structure 5025 and hollow portion 503, and controlling the number or area of ​​the third strip-type structure 5024 and the fourth strip-type structure 5025, as well as the number and area of ​​the hollow portion 503, the consumption of gas growth source at the edge position and the center position in the first region 1001 is made equivalent, so as to improve the uniformity of the thickness of the first regrown layer 2051 at various locations.

[0150] Furthermore, in order to ensure that the consumption of elements released from the gas growth source by the first zone 1001 and the second zone 1002 is equivalent during the formation of the above-mentioned first regrown layer 2051 and the second regrown layer 2052, the area of ​​the vertical projection of the solid part 502 shown in Figure 20 (including the second ring structure 5022, the second strip structure 5023, the third strip structure 5024 and the fourth strip structure 5025) on the substrate 201 (as shown in Figure 16) can be the same as the area of ​​the vertical projection of at least one first strip structure 501 in the first regrown layer 2051 on the substrate 201.

[0151] In addition, the line width of the solid portion 502 shown in FIG20 can be 10 μm to 1000 μm. For example, when the solid portion 502 includes a second ring structure 5022, a second strip structure 5023, a third strip structure 5024, and a fourth strip structure 5025, along the Y direction, the line width L1 of the solid portion 502 can be the sum H1 of the line width of the second ring structure 5022 and the length L2 of the second strip structure 5023, that is, H1 = L1 + L2, and H1 is 10 μm to 1000 μm. In addition, along the X direction, the line width of the solid portion 502 can be the sum H2 of the line width L1 of the second ring structure 5022, the line width L3 of the third strip structure 5024, and the line width L4 of the fourth strip structure 5025, that is, H2 = L1 + L3 + L4, and H2 is 10 μm to 1000 μm.

[0152] Similarly, the technical effects and values ​​of the line width of the solid portion 502 ranging from 10 μm to 1000 μm can be obtained similarly to the technical effects and values ​​of the line width H of the second regrown layer 2052 shown in FIG17A , and are not further described here. Furthermore, the above is merely an example of the shape of the solid portion of the second regrown layer 2052. In other embodiments of the present application, the solid portion may also include a plurality of inclined, spaced-apart strip-shaped structures, or a cross-shaped strip-shaped structure, which are not further described here.

[0153] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor switching device, characterized in that: The semiconductor switching device comprises a first area and a second area, wherein the second area is arranged around the first area; the semiconductor switching device comprises: substrate; a channel layer, disposed on the substrate; a barrier layer, disposed on a side of the channel layer facing away from the substrate; at least one transistor, located in the first region, with a gate of the transistor disposed on a side of the barrier layer facing away from the channel layer; the first region is a region where one transistor or a plurality of transistors connected in parallel are disposed, and the second region is a region where no transistor is disposed; The regrown semiconductor layer is located in the first region and the second region, and the regrown semiconductor layer is arranged on a side of the barrier layer facing the gate.

2. The semiconductor switching device according to claim 1, wherein The regrown semiconductor layer comprises: a first regrown layer disposed in the first region; a vertical projection of the first regrown layer on the substrate having no overlap with a vertical projection of the gate on the substrate; The second regrown layer is disposed in the second region, and the second regrown layer is connected to the first regrown layer.

3. The semiconductor switching device according to claim 2, wherein: The semiconductor switch device includes two adjacent transistors, and the two adjacent transistors are connected in parallel; The first regrown layer includes at least one first stripe structure, and one first stripe structure is provided between the gates of two adjacent transistors; along the extension direction of the gate, both ends of the first stripe structure are connected to the second regrown layer.

4. The semiconductor switching device according to claim 2 or 3, characterized in that: The second regrown layer is a ring-shaped structure, and the second regrown layer is arranged around a circle of the first regrown layer.

5. The semiconductor switching device according to claim 4, wherein: The line width of the second regrown layer is 10 μm to 1000 μm.

6. The semiconductor switching device according to claim 4 or 5, characterized in that: An area of ​​a vertical projection of the second regrown layer on the substrate is the same as an area of ​​the second region.

7. The semiconductor switching device according to claim 3, wherein: The second regrown layer includes a solid portion and a hollow portion passing through the solid portion; The solid portion includes at least two first annular structures nested in sequence, and the hollow portion is located between two adjacent first annular structures; the first annular structure is arranged around a circumference of the first regrown layer; Among the at least two first annular structures nested in sequence, the first annular structure located in the innermost circle is connected to both ends of the first strip structure.

8. The semiconductor switching device according to claim 3, wherein: The second regrown layer includes a solid portion and a hollow portion penetrating the solid portion; the solid portion includes: a second annular structure disposed around the first regrown layer; The second strip-shaped structure is located in the hollow area of ​​the second ring-shaped structure, the first end of the second strip-shaped structure is connected to the second ring-shaped structure, and the second end of the second strip-shaped structure is connected to the first strip-shaped structure; the hollow portion is located between the second strip-shaped structures that respectively connect two adjacent first strip-shaped structures.

9. The semiconductor switching device according to claim 8, wherein: The first strip-type structure and the second strip-type structure that are connected have the same line width.

10. The semiconductor switching device according to claim 8 or 9, characterized in that: The entity part also includes: The third strip structure is located in the hollow area of ​​the second annular structure, and the second strip structure is located on the side of the third strip structure facing the first area; the third strip structure is arranged parallel to the first strip structure, and the gate is provided between the third strip structure and the first strip structure; both ends of the third strip structure are connected to the second annular structure; and the hollow portion is also located between the third strip structure and the second strip structure.

11. The semiconductor switching device according to claim 10, wherein: The entity part also includes: The fourth strip-shaped structure is located in the hollow area of ​​the second ring-shaped structure, and the fourth strip-shaped structure is located behind the third strip-shaped structure. On the side away from the second strip-shaped structure, both ends of the fourth strip-shaped structure are connected to the second annular structure; and the hollow portion is also located between the fourth strip-shaped structure and the third strip-shaped structure.

12. The semiconductor switching device according to any one of claims 7 to 11, characterized in that: An area of ​​a vertical projection of the solid portion on the substrate is the same as an area of ​​a vertical projection of the at least one first strip-shaped structure in the first regrown layer on the substrate.

13. The semiconductor switching device according to any one of claims 7 to 12, characterized in that: The line width of the entity portion is 10 μm to 1000 μm.

14. The semiconductor switching device according to any one of claims 2 to 13, characterized in that: The transistor further includes: a first electrode and a second electrode, the gate being located between the first electrode and the second electrode, and the first electrode and the second electrode being arranged on a side of the channel layer facing away from the substrate; Wherein, relative to the gate, the first regrown layer is arranged close to at least one of the first pole or the second pole.

15. The semiconductor switching device according to claim 14, wherein: A portion of the first regrown layer is located between the first electrode and the substrate, and between the second electrode and the substrate; the vertical projections of the first electrode and the second electrode on the substrate overlap with the vertical projections of the first regrown layer on the substrate, respectively, and the first electrode and the second electrode are in ohmic contact with the first regrown layer.

16. The semiconductor switching device according to any one of claims 1 to 15, characterized in that: The regrown semiconductor layer includes a compound of at least one of gallium, aluminum, and indium and nitrogen.

17. The semiconductor switching device according to any one of claims 1 to 16, characterized in that: The thickness of the regrown semiconductor layer is 5 nm to 100 nm.

18. The semiconductor switching device according to any one of claims 2 to 17, characterized in that: The first regrown layer includes a first portion and a second portion. The first portion is closer to the second region than the second portion. The thickness of the first portion is 0.5 to 1.5 times that of the second portion.

19. A wafer, characterized in that: include: At least two semiconductor switching devices according to any one of claims 1 to 18; the dicing lane of the wafer overlaps with the second region of the semiconductor switching device.

20. A packaging structure, characterized in that: include: Package substrate; The semiconductor switching device according to any one of claims 1 to 18, wherein the semiconductor switching device is arranged on the packaging substrate.

21. An electronic device, characterized in that: include: circuit boards, The packaging structure according to claim 20, wherein the packaging structure is electrically connected to the circuit board.

22. A method for manufacturing a semiconductor switching device, characterized in that: The semiconductor switch device has a first region and a second region, wherein the second region is arranged around the first region; the manufacturing method includes: forming a channel layer and a barrier layer in sequence on the substrate; forming a mask material on a side of the barrier layer facing away from the substrate, wherein an opening area of ​​the mask material exposes the first area and the second area; forming a regrown semiconductor layer in the second region and the first region; At least one transistor is formed in the first region on a side of the barrier layer away from the channel layer; wherein the first region is a region where one transistor or multiple transistors connected in parallel are provided, and the second region is a region where no transistor is provided.

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