Power semiconductor module

Abstract

There is provided a power semiconductor module (100). The power semiconductor module (100) comprises: a substrate (3); at least one power semiconductor device (11, 15) mounted on the substrate (3); a circuit board (41) overlying the substrate; a power management circuit (52, 53) and a gate driver circuit (54) which are mounted on the circuit board (41), wherein the power management circuit (52, 53) is configured to generate a power supply VDD, VSS for use by the gate driver circuit (54), and the gate driver circuit (54) is configured to generate a control signal GATE, KELVIN SOURCE which controls an operation of the at least one power semiconductor device (11, 15); and a housing (1) configured to enclose the at least one power semiconductor device (11, 15), the circuit board (41), the power management circuit (52, 53), the gate driver circuit (54) and at least a part of the substrate (3).

Description

[0001] Power Semiconductor Module

[0002] Technical Field

[0003] This disclosure relates to a power semiconductor module and a method of manufacturing the same. More particularly, but not exclusively, this disclosure relates to a power semiconductor module which includes an internal power management circuit and an internal gate driver circuit to drive a power semiconductor device housed within the module.

[0004] Background

[0005] Wide bandgap (WBG) power semiconductor devices such as Gallium-Nitride High- electron-mobility transistors (GaN HEMTs) are capable of switching with faster slew rates than traditional silicon-based power semiconductor devices, such as metal-oxide- semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). Energy loss during a switching transition is directly related to the time duration of the transition. Therefore, the ability to switch with faster slew rates leads to a reduction in switching energy loss and is a key advantage of power semiconductor devices made from WBG materials rather than silicon.

[0006] Traditional power modules, used for packaging silicon-based power semiconductor devices, are manufactured using patterned copper-clad ceramic substrates, wire bonds and auxiliary pins to make the interconnections between the copper tracks and the chips. Furthermore, traditional power modules are usually driven by external gate driver boards, the module gate circuit connections for which are usually at one or both ends of the module or along one edge of the module.

[0007] Figure 1 shows the layout of a traditional power module 100’ which realises a half-bridge circuit. The module 100’ includes a high-side switch (including switching devices 11’-1 , 11’-2) and a low-side switch (including switching devices 15’-1 , 15’-2), which are enclosed within a housing T. While it is not shown in Figure 1 , the traditional power module 100’ typically includes a substrate and a printed circuit board (PCB) above the substrate. The switching devices 1 T and 15’ are mounted on the substrate. In the event that the switching devices 11’, 15’ are power MOSFETs, gate and Kelvin source connections of the high-side switching devices 11’ are routed from the substrate to the PCB by way of auxiliary pins 23’, 24’, respectively, and gate and Kelvin source connections of the low-side switching devices 15’ are routed from the substrate to the PCB by way of auxiliary pins 25’, 26’, respectively. Power terminals 30’ (e.g., DC+), 3T (e.g. DC-) and 32’ (e.g., AC) of the module 100’ are typically mounted on the substrate, while gate circuit terminals 33’ to 36’ are typically mounted on the PCB. The gate circuit terminals 33’ and 34’ are the gate control terminal and the Kelvin source control terminal of the high-side switching devices 1 T, while the gate circuit terminals 35’ and 36’ are the gate control terminal and the Kelvin source control terminal of the low-side switching devices 15’.

[0008] The current flow paths in the gate circuit of the module 100’ are shown in Figure 2. For the low-side switching devices 15’-1 and 15’-2, the gate current follows a flow path 60’. More specially, the gate current is picked up by the gate control terminal 35’, and is routed to the respective auxiliary pin 25’-1 or 25’-2 by conductive traces of the PCB. The current then travels through the respective auxiliary pin 25’-1 or 25’-2, conductive traces on the substrate as well as bonding wires (not shown) to the respective gate pad of each switching device 15’-1 or 15’-2. The current then returns to the respective auxiliary pin 26’-1 or 26’-2 from the respective source pad of each switching device, and travels back to the Kelvin source control terminal 36’ from the respective auxiliary pin 26’-1 or 26’-2. The gate current for the high-side switching devices 11’-1 , 11’-2 runs in a similar fashion from the gate control terminal 33’ to the Kelvin source control terminal 34’ through the auxiliary pins 23’-1 / 23’-2 and 24’-1 / 24’-2. The high-side gate current follows a flow path 70’.

[0009] In this example, the gate circuit terminals 33’ to 36’ are positioned along the right-side edge of the module 100’. The positioning of the gate circuit terminals 33’ to 36’ creates large current loops in the gate circuit of the module 100’, especially for the low-side switching devices 15’ which are positioned at the opposite left side of the module 100’. These large current loops contribute to high inductance in the gate circuit loop (i.e. , the parasitic inductance along the current path 60’ between the gate circuit terminals 35’, 36’).

[0010] High inductance is incompatible with switching at the faster slew rates enabled by WBG semiconductors, because the high current slew rates (di / dt) interact with parasitic inductances generating voltage overshoots and oscillations. The present disclosure is mainly concerned with voltage overshoots and oscillations in the gate loop, however the issues presented can affect the power loop as well.

[0011] Voltage oscillations appearing between the gate and source, caused by the interaction between the current slew rate (di / dt) and the stray inductance of the gate loop, has two effects: (1) spurious voltages caused by parasitic inductances are opposite in polarity to the driving voltage. This slows down the switching transition, which in turn increases energy losses by increasing the V * I product of the drain-source voltage and drain current during the switching transition; (2) if the magnitude of the voltage oscillations exceeds or drops below the device’s threshold voltage, it can cause false turn-on or false turn-off, which can potentially damage the device.

[0012] GaN enhancement-mode HEMTs have maximum gate to source voltages of 5V or 6V, and very low threshold voltages, typically 1 ,5V. But the device requires 4 to 5V to be fully turned on. This leaves very small margins for the gate-source voltage, and increases the device sensitivity to false turn-on / turn-off when switching at faster slew rates.

[0013] Therefore, the high gate circuit loop inductance within the module 100’ limits the maximum performance of WBG-based semiconductor modules. To extract the ultimate performance of WBG semiconductors, packaging designs with reduced inductance are required.

[0014] Further, the gate current loops of individual devices within the same power switch (either high-side or low-side) have different sizes. For example, the low-side switching device 15’-2 has a longer gate current loop than the low-side switching device 15’-1. Similarly, the high-side switching device 11’-1 has a longer gate current loop than the high-side switching device 11’-2. This means that the gate loop parasitics of individual devices within the same power switch are not balanced. Unbalanced gate loop parasitics would lead to unsynchronised switching of the individual devices, which is a detriment to the switching performance of the power switch as a whole.

[0015] High switching speeds also interact with parasitic capacitances and inductances to cause electromagnetic interference (EMI). High dv / dt transients interact with parasitic capacitances to produce displacement currents. High di / dt transients interact with parasitic inductances to produce fluctuations in voltages. Current loops can cause radiated EMI. To minimise EMI, physical current loop sizes should be as small as possible, and parasitic inductances should be minimised and balanced.

[0016] It is an object of the present disclosure, among others, to provide an improved power semiconductor module that solves problems associated with conventional power semiconductor modules, whether identified herein or otherwise.

[0017] Summary

[0018] According to a first aspect of the present disclosure, there is provided a power semiconductor module comprising: a substrate; at least one power semiconductor device mounted on the substrate; a circuit board overlying the substrate; a power management circuit and a gate driver circuit which are mounted on the circuit board, wherein the power management circuit is configured to generate a power supply for use by the gate driver circuit, and the gate driver circuit is configured to generate a control signal which controls an operation of the at least one power semiconductor device; and a housing configured to enclose the at least one power semiconductor device, the circuit board, the power management circuit, the gate driver circuit and at least a part of the substrate.

[0019] It would be understood that the housing encloses an entirety of the power semiconductor device, the circuit board, the power management circuit and the gate driver circuit. In other words, the circuit board together with the power management circuit and the gate driver circuit are internal components of the power semiconductor module. This arrangement allows the size of gate current loop to be significantly reduced as compared to prior modules which rely upon external gate drive circuitry. Reducing the size of the gate current loop is helpful for reducing the inductance of the gate circuit loop. Advantageously, the reduced inductance of the gate circuit loop improves the switching speed of the power semiconductor device, and also reduces the risks of falsely triggering the power semiconductor device, thereby allowing full exploitation of the fast-switching capabilities of WBG power semiconductor devices for use within the module.

[0020] Making the power management circuit and the gate driver circuit internal components of the module also makes driving the power semiconductor device simpler and greatly simplifies the use of the power semiconductor module for an end user. Further, the internal power management circuit and the gate driver circuit can be fine-tuned to the particular configuration and characteristics of the module, and allows the efficiency and reliability of the module to be optimised.

[0021] The power management circuit and the gate driver circuit typically operate at a much lower voltage level than the power semiconductor device. By mounting the power semiconductor device on the substrate, and mounting the power management circuit and the gate driver circuit on a separate circuit board overlying the substrate, the power semiconductor module has separated the two zones of different voltage ratings. This is beneficial for improving the thermal performance and the reliability of the power semiconductor module.

[0022] The power management circuit provides an internal power supply to the gate driver circuit. Because the power management circuit and the gate driver circuit are mounted on the same circuit board, the two circuits can be placed as close as possible to one another, and meanwhile sufficiently separated from the power connections of the power semiconductor device which often cause radiated EMI. This arrangement is useful for maintaining the internal power supply clean and steady.

[0023] The at least one power semiconductor device may be arranged between the substrate and the circuit board.

[0024] The circuit board may also be referred to as a laminate structure.

[0025] The power supply may determine a magnitude of the control signal.

[0026] The substrate may be thermally coupled to a heat removal structure. The power semiconductor module may be a single-side cooled module.

[0027] The power semiconductor module may further comprise a first control terminal for receiving a pulse-width-modulation, PWM, input signal. The first control terminal may be mounted on the circuit board and extend beyond the housing to an exterior of the power semiconductor module. The gate driver circuit may be configured to generate the control signal based upon the PWM input signal. The power semiconductor module may further comprise a second control terminal for receiving a voltage input. The second control terminal may be mounted on the circuit board and extend beyond the housing to an exterior of the power semiconductor module. The power management circuit may be configured to generate the power supply based upon the voltage input.

[0028] The second control terminal may comprise a pair of control terminals across which the voltage input is received.

[0029] The power management circuit may comprise a voltage regulator which generates the power supply.

[0030] The power management circuit may further comprise a DC-DC converter which is configured to generate, based upon the voltage input, a further power supply for use by the voltage regulator.

[0031] The at least one power semiconductor device may comprise a first power semiconductor device, and the first power semiconductor device may comprise a first gate electrode, a first power electrode and a second power electrode.

[0032] The control signal generated by the gate driver circuit may comprise a gate control signal and an auxiliary control signal. The first gate electrode may be configured to receive the gate control signal, and the first power electrode may be configured to receive the auxiliary control signal.

[0033] The first power semiconductor device may be configured to block a voltage with a higher potential at the second power electrode than at the first power electrode. In other words, the second power electrode may be the drain electrode and the first power electrode may be the source electrode if the first power semiconductor device is a power MOSFET.

[0034] The circuit board may comprise a plurality of electrically conductive layers stacked with a plurality of electrically insulating layers along a stacking direction. At least one of the electrically insulating layers may be arranged between adjacent ones of the electrically conductive layers. The stacking direction may be perpendicular to a surface of one or more of the electrically insulating layers.

[0035] The plurality of electrically conductive layers may comprise first, second and third electrically conductive layers which are spaced apart from one another along the stacking direction. The power management circuit and the gate driver circuit may be mounted on the first electrically conductive layer, and the second and third electrically conductive layers may be internal layers of the circuit board. A conductive pathway for the gate control signal to travel from the gate driver circuit to the first gate electrode may comprise at least a part of the second electrically conductive layer, and a conductive pathway for the auxiliary control signal to travel from the gate driver circuit to the first power electrode may comprise at least a part of the third electrically conductive layer.

[0036] In other words, the at least a part of the second electrically conductive layer may be the gate control layer of the first power semiconductor device, and the at least a part of the third electrically conductive layer may be the Kelvin source control layer of the first power semiconductor device.

[0037] The second and third electrically conductive layers may be separated by a single electrically insulating layer along the stacking direction.

[0038] The at least a part of the second electrically conductive layer and the at least a part of the third electrically conductive layer may partially or wholly overlap when viewed along the stacking direction.

[0039] This arrangement allows the capacitance between the gate and Kelvin source potentials of the first power semiconductor device to be tailored, by varying the area of overlap and the thickness of insulation between the two electrically conductive layers.

[0040] The at least one power semiconductor device may further comprise a second power semiconductor device. The second power semiconductor device may comprise a second gate electrode configured to receive the gate control signal, a third power electrode configured to receive the auxiliary control signal and a fourth power electrode. The first power electrode may be electrically connected to the third power electrode, and the second power electrode may be electrically connected to the fourth power electrode. In other words, the first and second power semiconductor devices are electrically connected in parallel and collectively form (part of) a power switch.

[0041] The gate driver circuit may comprise an output terminal which output the gate control signal. The circuit board may be configured to route the gate control signal to a first location of the circuit board, from where the gate control signal leaves the circuit board and travels to the first gate electrode. The circuit board may be configured to route the gate control signal to a second location of the circuit board, from where the gate control signal leaves the circuit board and travels to the second gate electrode. The output terminal of the gate driver circuit may be arranged equidistant from the first location and the second location.

[0042] The equidistant arrangements allows the gate loop parasitics of the first and second power semiconductor devices to be balanced, which is useful for synchronising the switching of the first and second power semiconductor devices. The auxiliary control signal may be routed to the first and second power semiconductor devices in a similar way.

[0043] Alternatively, the at least one power semiconductor device may further comprise a second power semiconductor device which comprises a second gate electrode, a third power electrode and a fourth power electrode. The second power electrode may be electrically connected to the third power electrode. The power semiconductor module may further comprise first, second and third power terminals, with the first power terminal electrically connected to the first power electrode, the second power terminal electrically connected to the second and third power electrodes, and the third power terminal electrically connected to the fourth power electrode.

[0044] The second power semiconductor device may be configured to block a voltage with a higher potential at the fourth power electrode than at the third power electrode. In other words, the first and second power semiconductor devices may be connected to form a half bridge circuit.

[0045] The gate driver circuit may comprise a first gate driver circuit configured to generate a first control signal which controls an operation of the first power semiconductor device, and a second gate driver circuit configured to generate a second control signal which controls an operation of the second power semiconductor device.

[0046] The PWM input signal received by the first control terminal may be a first PWM input signal, and the first gate driver circuit may be configured to generate the first control signal based upon the first PWM input signal. The power semiconductor module may further comprise a third control terminal for receiving a second PWM input signal, and the second gate driver circuit may be configured to generate the second control signal based upon the second PWM input signal.

[0047] The third control terminal may have similar features to those of the first control terminal.

[0048] A distance between the first gate driver circuit and the first power semiconductor device may be less than a distance between the second gate driver circuit and the first power semiconductor device.

[0049] Similarly, a distance between the second gate driver circuit and the second power semiconductor device may be less than a distance between the first gate driver circuit and the second power semiconductor device. In other words, the first / second gate driver chips may be preferably placed as close as possible to the gate and Kelvin source inputs of the respective first / second power semiconductor device. This arrangement is useful for minimising the size (hence minimising the parasitic inductances) of the gate current loop of the first / second power semiconductor device. The distance may be measured between the output of the first / second gate driver circuit and the gate & Kelvin source input pins of the first / second power semiconductor device.

[0050] The power management circuit may comprise a first power management circuit configured to generate a first power supply for use by the first gate driver circuit, and a second power management circuit configured to generate a second power supply for use by the second gate driver circuit.

[0051] The first power management circuit may be configured to generate the first power supply based upon the voltage input received by the second control terminal. The second power management circuit may be configured to generate the second power supply based upon the same voltage input received by the second control terminal. A distance between the first power management circuit and the first gate driver circuit may be less than a distance between the second power management circuit and the first gate driver circuit.

[0052] Similarly, a distance between the second power management circuit and the second gate driver circuit may be less than a distance between the first power management circuit and the second gate driver circuit. In other words, the first / second power management circuit may be preferably placed as close as possible to the respective first / second gate driver chips. This arrangement is useful for protecting the power supply generated by the first / second power management circuit from electromagnetic interferences. The distance may be measured between an output of the first / second power management circuit (which output the first / second power supply) and an input of the first / second gate driver circuit (which receives the first / second power supply).

[0053] The circuit board may comprise a fourth electrically conductive layer which forms a surface of the circuit board that faces the at least one power semiconductor device. The fourth electrically conductive layer may be isolated from voltage potentials of the electrodes of the at least one power semiconductor device.

[0054] Advantageously, the fourth electrically conductive layer may be used as a shielding layer, to shield the sensitive control circuitry from any radiated EMI emissions from the power circuit of the at least one power semiconductor device.

[0055] The power semiconductor module may further comprise an electrically insulating material that fills a space between the circuit board and the substrate.

[0056] The electrically insulating material provides isolation between circuit board and substrate. The electrically insulating material may comprise one or more of epoxy and silicone gel.

[0057] The at least one power semiconductor device may comprise a wide bandgap power semiconductor device. The wide bandgap power semiconductor device may be a GaN power semiconductor device, in particular a GaN HEMT.

[0058] According to a second aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor module. The method comprises: mounting at least one power semiconductor device on a substrate; mounting a power management circuit and a gate driver circuit on a circuit board, wherein the power management circuit is configured to generate a power supply for use by the gate driver circuit, and the gate driver circuit is configured to generate a control signal which controls an operation of the at least one power semiconductor device; positioning the circuit board above the substrate; and enclosing the at least one power semiconductor device, the circuit board, the power management circuit, the gate driver circuit and at least a part of the substrate by a housing.

[0059] It would also be understood that the terms “first” to “fourth” are simply used in the present disclosure to label the relevant elements (e.g., “power electrode”, “electrically conductive layer” etc.) for the ease of description, and do not imply any limitations to the sequence, locations or total number of the relevant elements.

[0060] Within the present disclosure, the term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may or may not exist between the electrically coupled elements.

[0061] Where appropriate any of the optional features described above in relation to one of the aspects of the disclosure may be applied to another one of the aspects of the disclosure.

[0062] Brief Description of the Drawings

[0063] In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a top plan view of a known power semiconductor module;

[0064] Figure 2 schematically illustrates paths of gate circuit currents within the power semiconductor module of Figure 1 ;

[0065] Figure 3 schematically illustrates a top plan view of a power semiconductor module (with the module housing removed for clarity) according to an embodiment of the present disclosure;

[0066] Figure 4 is a schematic representation of a cross-sectional view of the power semiconductor module of Figure 3;

[0067] Figure 5 schematically illustrates a top plan view of a substrate assembly within the power semiconductor module of Figure 3;

[0068] Figure 6 schematically illustrates a top plan view of a PCB assembly within the power semiconductor module of Figure 3;

[0069] Figure 7 is a schematic representation of gate drive circuitry within the power semiconductor module of Figure 3;

[0070] Figure 8 schematically illustrates paths of gate circuit currents within the power semiconductor module of Figure 3;

[0071] Figure 9 schematically illustrates processing steps of a method for manufacturing a power semiconductor module according to the present disclosure.

[0072] In the figures, like parts are denoted by like reference numerals.

[0073] It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.

[0074] Detailed Description of the Preferred Embodiments Figures 3 to 7 schematically illustrate the structure of a power semiconductor module 100 (hereinafter, “module 100”) according to an embodiment of the present disclosure. Figure 4 is a cross-sectional view of the module 100 along the XZ plane when the module 100 is cut along a line IV-IV’ in Figure 3. The module 100 realises a half-bridge circuit. In the module 100, each of the high-side and low-side power switches of the half bridge includes two individual power devices connected in parallel. The reference numerals of the two power devices and their associated connections follow the format of ‘# - T, ‘# - 2’, which can be collectively referred to as '#’ for brevity.

[0075] As shown in Figures 3 and 4, the module 100 includes a housing 1 , a baseplate 2, a substrate 3 mounted on the baseplate 2, high-side power semiconductor devices (hereinafter, “HS devices”) 11-1 , 11-2 and low-side power semiconductor devices (hereinafter, “LS devices”) 15-1 , 15-2 mounted on the substrate 3, and a circuit board 41 overlying the substrate 3 and the devices 11 , 15.

[0076] The baseplate 2 is typically made of metal. In use, the bottom surface of the baseplate 2 may be thermally coupled to a heat removal structure (such as a heat sink) to cool the module 100. In other words, the module 100 may be a single-side cooled power module. The substrate 3 includes an electrically insulating layer 4, a patterned electrically conductive layer 57 arranged on its top surface, and another electrically conductive layer 10 arranged on its opposite bottom surface. The electrically insulating body 4 is typically made of ceramic or a suitable polymer. The conductive layers 57, 10 may be made of copper or other suitable conducting material such as aluminum, copper-molybdenum alloy, or copper-tungsten alloy etc. The substrate may be a direct bonded copper (DBC) substrate, a directed bonded aluminium (DBA) substrate or an active metal brazed (AMB) substrate. The top electrically conductive layer 57 is patterned to separate regions of difference potentials. The bottom electrically conductive layer 10 may be kept plain.

[0077] In an example, the HS and LS devices 11 , 15 are GaN transistors (e.g., GaN HEMTs). Each of the devices 11 , 15 has a gate electrode 14 or 18, a source electrode (not labelled) and a drain electrode 13 or 17, all of which are formed at the top surface of the device. The gate electrode 14 or 18 is a control electrode, and the source and drain electrodes are power electrodes. In particular, a voltage difference between the gate electrode and the source electrode determines the on / off status of a power current path between the drain electrode and the source electrode. The bottom surfaces of the devices 11 , 15 are semiconductor substrates and are directly bonded to the substrate 3 by bonding materials 12 or 16 (e.g., solder or sintering paste). Therefore, the devices 11 , 15 are thermally coupled to the substrate 3. The source and drain electrodes may be referred to as “first power electrode” and “second power electrode”, respectively.

[0078] Figure 5 shows a top plan view of a substrate assembly along the XY plane. The substrate assembly includes the substrate 3, with the HS and LS devices 11 , 15 (and their associated connections) and power terminals 30 (DC+), 31 (DC-) and 32 (AC) mounted on the top electrically conductive layer 57 of the substrate 3.

[0079] As shown in Figure 5, the top electrically conductive layer 57 includes conductive tracks 5 to 9 and 58 to 59 which are spaced apart (hence electrically isolated) from one another. The conductive track 5 has a C shape and is positioned close to a boundary of the substrate 3. The two DC+ terminals 30 are mounted on the conductive track 5. The right side of a clip 27 is bonded to the drain electrodes 13 of the HS devices 11 . The top and bottom sides of the clip 27 is bonded to the conductive track 5. Therefore, the drain electrodes 13 of the HS devices 11 are connected to the DC+ terminal 30. Clips 29 are used to connect the source electrodes of the HS devices 11 to a conductive track 7, on which the AC terminal 32 is mounted. Clips 62 (Figure 4) are used to connect the drain electrodes 17 of the LS devices 15 to the conductive track 7. Clips 28 are used to connect the source electrodes of the LS devices 15 to a conductive track 6, on which the DC- terminal 31 is mounted. Therefore, the LS devices 15 and the HS devices 11 are electrically connected to form a half-bridge topology. It would be understood that the number of the switching devices at the high side or at the low side can be suitably varied depending upon the required current rating. The devices 11 , 15 may be pre-packaged bare dies or packaged chips. The clips 27 to 29 and 62 are power connections, and may be made from copper or other suitable conducting materials (such as copper- molybdenum-copper or silver, etc.)

[0080] Bond wires 19 are used to connect the gate electrodes 14 of the HS devices 11 to the respective conductive tracks 58, to which auxiliary pins 23 are bonded (e.g., by soldering or sintering). Bond wires 20 are used to connect the source electrodes of the HS devices 11 to the respective conductive tracks 59, to which auxiliary pins 24 are bonded. Bond wires 21 are used to connect the gate electrodes 18 of the LS devices 15 to the respective conductive tracks 8, to which auxiliary pins 25 are bonded. Similarly, bond wires 22 are used to connect the source electrodes of the LS devices 15 to the respective conductive tracks 9 to which auxiliary pins 26 are bonded.

[0081] The circuit board 41 sits above the substrate assembly of Figure 5, and is attached by solder to the multiple auxiliary pins 23 to 26. In particular, the circuit board 41 has plated through holes 51-1 to 51-8 (Figure 6), and each of the auxiliary pins 23 to 26 is inserted into a respective plated through hole 51 and bonded to the inner plating of the through hole 51 to achieve an electrical connection. Within the circuit board 41 itself, the inner plating of a plated through hole 51 is selectively connected to particular conductive layer(s) of the circuit board 41. This is described below in more detail. The auxiliary pins 23 to 26 also function as spacers to maintain a clearance between the substrate 3 and the circuit board 41 along a vertical direction Z that is perpendicular to surfaces of the substrate 3. The clearance ensures the electrical isolation between the circuit board 41 and the power connections (e.g., the clips 27, 28, 29, 62, the power terminals 30, 31 , 32) mounted on the substrate 3.

[0082] The circuit board 41 has a laminate structure, and includes an electrically insulating layer stacked with electrically conductive layers. With reference to Figure 4, the circuit board 41 includes four electrically conductive layers 43 to 46, and adjacent ones of the electrically conductive layers are separated by a single electrically insulating layer 42. The conductive layer 43 forms an upper surface of the circuit board 41 and the conductive layer 46 forms a lower surface of the circuit board 41 that faces the devices 11 , 15. In an example, the electrically insulating layers 42 are made of a glass-reinforced epoxy laminate material such as FR-4, and each has a thickness of around 0.5mm. In this way, the electrically insulating layers 42 are generally rigid. The electrically conductive layers 43 to 46 may be made of copper and each has a thickness of around 35pm. The layers of the circuit board 41 may adopt other thicknesses depending on the application, but thick conductive layers and thin insulating layers are preferred where possible. The circuit board 41 is generally rigid so as to support control terminals 37 to 40 and the gate drive circuitry (which are described below) mounted thereon. The circuit board 41 may be manufactured by common PCB processes. The electrically conductive layers 43 to 46 may be referred to as first to fourth electrically conductive layers.

[0083] Figure 6 shows a top plan view of the circuit board assembly along the XY plane. Gate drive circuitry of the module 100 are mounted on the upper conductive layer 43 of the circuit board 41. With reference to Figure 6, the gate drive circuitry includes HS drive circuitry and LS drive circuitry which drives the HS devices 11 and the LS devices 15, respectively. The HS drive circuitry includes a DC-DC converter 52-H, a voltage regulator 53-H and a gate driver circuit 54-H along with necessary passive components 55-H. The LS drive circuitry includes a DC-DC converter 52-L, a voltage regulator 53-L, a gate driver circuit 54-L and passive components 55-L.

[0084] Control terminals 37 to 40 of the module 100 are mounted on the upper conductive layer 43 of the circuit board 41 , and remain in the same locations as the control terminals 35’, 36’, 33’, 34’ of the module 100’ (Figure 2), but are re-purposed to provide inputs to the HS and LS drive circuitries. Therefore, the module 100 can be easily retrofitted into existing power switching assemblies (which are used with the conventional module 100’). The control terminals 37 and 38 receive a 5V input voltage and a 0V input, respectively, while the control terminals 39 and 40 receive a HS switch PWM input and a LS switch PWM input, respectively.

[0085] The HS drive circuitry and the LS drive circuitry are generally identical to one another. Figure 7 shows an example of the HS or LS drive circuitry, although other implementations are possible. In Figure 7, the DC-DC converter 52 is based on the PESE1-M series of DC-DC converters by CUI Inc., the voltage regulator 53 is a low- dropout (LDO) voltage regulator based on the TPS7A39 dual model by Texas Instruments, and the gate driver circuit 54 is based on the Si827x series by Skyworks Inc. The application circuit for the gate driver circuit 54 is taken from GaN systems, GS66508B-EVBDB1 650 GaN E-HEMT evaluation board technical manual’, since a suitable application circuit for a single driver was not available in the Si827x series datasheet. The DC-DC converter 52 receives the 5V voltage input from the control terminals 37 and 38. The output voltage (between the ‘+Vo’ and ‘-Vo’ pins) of the DC- DC converter 52 is fed into the voltage regulator 53, which generates a first voltage output ‘VDD’ and a second voltage output ‘VSS’. Typical voltages for ‘VDD’ and ‘VSS’ for driving GaN enhancement-mode HEMTs are 6V and -3V respectively. The gate driver circuit 54 receives a PWM input signal (‘PWMJN’) from one of the control terminals 39 and 40, the 5V voltage input from the control terminals 37 and 38 as well as the VDD and VSS voltages from the voltage regulator 53, and outputs a gate control signal ‘GATE’ and a Kelvin source control signal ‘KELVIN SOURCE’. The output signals ‘GATE’ and ‘KELVIN SOURCE’ are voltage signals to be applied to the gate electrodes and the source electrodes of HS or LS devices 11 , 15, so as to control the on / off switching of the HS or LS devices 11 , 15. The VDD and VSS voltages provide the necessary current drive to charge and discharge the gate capacitance of the HS or LS devices 11 , 15, and also determine the magnitude of the gate control signal ‘GATE’. The use of the Kelvin source control signal is beneficial for reducing common-source inductances of the devices within the same HS or LS power switch, which is important to minimise for successful switching of GaN HEMTs. The DC-DC converter 52 and the gate driver circuit 54 shown in Figure 7 are isolated so as to prevent external transients from affecting the output signals of those circuits. GND represents the isolated ground reference.

[0086] While it is not shown in Figure 6, it would be understood that the upper conductive layer 43 of the circuit board 41 is suitably patterned into separate pads and traces so as to realise the electrical connections between the HS / LS drive circuitries and the control terminals 37 to 40. Conductive through-layer vias (not shown) are provided to selectively connect the upper conductive layer 43 to the underneath conductive layers 44 to 46. In particular, the conductive layer 44 functions as a gate layer, and includes two spacedapart conductive tracks which are electrically connected (using through-layer vias) to the gate control signals ‘GATE’ output by the gate driver circuits 54-H, 54-L, respectively. Similarly, the conductive layer 45 functions as a Kelvin source layer, and includes two spaced-apart conductive tracks which are electrically connected (using another set of through-layer vias) to the Kelvin source control signals ‘KELVIN SOURCE’ output by the gate driver circuits 54-H, 54-L, respectively.

[0087] The conductive track (of the conductive layer 44) connected to the ‘GATE’ output of the gate driver circuit 54-H is electrically connected to plated through holes 51-6, 51-7 (Figure 6) of the circuit board 41 , which are further connected to the gate electrodes 14 of the HS devices 11 by way of the auxiliary pins 23-1 , 23-2. The conductive track (of the conductive layer 44) connected to the ‘GATE’ output of the gate driver circuit 54-L is electrically connected to plated through holes 51-2, 51-3 (Figure 6), which are further connected to the gate electrodes 18 of the LS devices 15 by way of the auxiliary pins 25- 1 , 25-2.

[0088] The conductive track (of the conductive layer 45) connected to the ‘KELVIN SOURCE’ output of the gate driver circuit 54-H is electrically connected to plated through holes 51- 5, 51-8 (Figure 6) of the circuit board 41 , which are further connected to the source electrodes of the HS devices 11 by way of the auxiliary pins 24-1 , 24-2. The conductive track (of the conductive layer 45) connected to the ‘KELVIN SOURCE’ output of the gate driver circuit 54-L is electrically connected to plated through holes 51-1 , 51-4 (Figure 6), which are further connected to the source electrode of the LS devices 15 by way of the auxiliary pins 26-1 , 26-2.

[0089] The bottom conductive layer 46 of the circuit board 41 may provide the ground plane for the system ground (0V potential). In an example, the conductive layer 46 may be used as a shielding layer to shield the sensitive gate circuit from any radiated EMI emissions from the power connections 27 to 29 and 62. Alternatively, the circuit board 41 may include a fifth conductive layer further below the conductive layer 46, and the fifth conductive layer may function as a shielding layer. The shielding layer may be connected to a stable voltage supply, the ground, or be left floating, depending upon various applications. In any event, the shielding layer would not be connected to any voltage potential of the electrodes of the HS and LS devices 11 , 15.

[0090] The circuit board 41 and the gate drive circuitry (52, 53, 54, 55) mounted thereon are internal components of the module 100, because they are completely enclosed by the housing 1 of the module 100. The power terminals 30 to 32 and the control terminals 37 to 40 protrude outside of the housing 1 to provide connections to an electrical environment of the module 100. The housing 1 does not fully cover the bottom conductive layer 10 of the substrate 3, so as to allow the bonding between the bottom conductive layer 10 and the baseplate 2. It would be appreciated that the baseplate 2 may be omitted such that bottom electrically conductive layer 10 is directly coupled to a heatsink.

[0091] Making the gate drive circuitry an internal component of the module 100 makes driving the devices 11 , 15 simpler and greatly simplifies the use of the module 100 for an end user. Further, the gate drive circuitry can be fine-tuned to the particular configuration and characteristics (e.g., dead time, minimised ringing) of the module 100, and allows the efficiency and reliability of the module 100 to be optimised.

[0092] The housing 1 may take the form of a plastic frame with an insulating material (such as silicone gel) filling the space between the circuit board 41 and the substrate 3. Alternatively, the housing 1 may be made by a moulding compound (e.g., epoxy) in a transfer moulding or vacuum casting process. In any event, an insulating material (e.g., silicone gel or epoxy) is provided to electrically isolate the two different voltage levels present in the power circuit mounted on the substrate 3 and in the gate drive circuitry mounted on the circuit board 41. The operating voltage of the power devices 11 , 15 is typically anywhere from 600V to 1.2kV, whereas the operating voltage of the gate drive circuitry is typically around 5V.

[0093] Therefore, by mounting the gate drive circuitry (including the DC-DC converter 52, the voltage regulator 53 and the gate driver circuit 54) on the circuit board 41 , the power semiconductor module has separated the two levels of different voltage ratings along the Z direction. This is beneficial for improving the thermal performance and the reliability of module 100. In some of the existing power modules, both gate drive circuitry and power devices are mounted on a single PCB to create a complete half-bridge circuit. This approach has a disadvantage that the PCB has posed a significant limit to the power rating of the module, because of the limitations of PCB in terms of thermal management and also potential lifetime issues (due to the nature of the PCB materials and potential CTE mismatches). On the other hand, the power rating of the module 100 is not severely affected by the use of the circuit board 41 , because of the use of the substrate 3 (which is thermally coupled to a heatsink) and the use of the insulating material between the substrate 3 and the circuit board 41.

[0094] Making the gate drive circuitry an internal component of the module 100 is also beneficial for reducing and balancing the gate circuit loop inductances of the module 100. This is described below with reference to Figure 8.

[0095] Figure 8 shows paths of gate circuit currents on the XY plane. The path PL1 indicates a gate circuit current path of the LS device 15-1. The path PL2 indicates a gate circuit current path of the LS device 15-2. The path PH1 and PH2 indicate gate circuit current paths of the HS device 11-1 and 11-2, respectively.

[0096] For each of the paths PL1 , PL2, the gate circuit current flows out of the ‘GATE’ pin of the gate driver circuit 54-L and is then routed on a conductive track of the conductive layer 44 to the plated through hole 51-2 or 51-3. The gate circuit current then flows along the auxiliary pin 25-1 or 25-2 and the bonding wire 21-1 or 21-2 to the gate electrode 18 of the device 15-1 or 15-2. The gate circuit current then flows from the source electrode of the device 15-1 or 15-2, through the bonding wire 22-1 or 22-2, the auxiliary pin 26-1 , 26-2, the plated through hole 51-1 , 51-4, and a conductive track of the conductive layer 45, back to the ‘KELVIN SOURCE’ pin of the gate driver circuit 54-L.

[0097] Similarly, for each of the paths PH1 , PH2, the gate circuit current flows out of the ‘GATE’ pin of the gate driver circuit 54-H and is then routed on another conductive track of the conductive layer 44 to the plated through hole 51-6 or 51-7. The gate circuit current then flows along the auxiliary pin 23-1 or 23-2 and the bonding wire 19-1 or 19-2 to the gate electrode 14 of the device 11-1 or 11-2. The gate circuit current then flows from the source electrode of the device 11-1 or 11-2, through the bonding wire 20-1 or 20-2, the auxiliary pin 24-1 , 24-2, the plated through hole 51-5, 51-8, and another conductive track of the conductive layer 45, back to the ‘KELVIN SOURCE’ pin of the gate driver circuit 54-H.

[0098] By comparing Figure 8 and Figure 2, it is clear that the gate circuit current paths PL1 , PL2 for the LS devices 15 are significantly shorter than the path 60’ for the LS devices 15’, and that gate circuit current paths PH1 , PH2 for the HS devices 11 are significantly shorter than the path 70’ for the HS devices 1 T. Reducing the length of the gate circuit current path is helpful for reducing the parasitic inductance of the gate circuit loop. The reduced inductance of the gate circuit loop improves the switching speed of the devices 11 , 15, and also reduces the risks of falsely triggering the devices 11 , 15, thereby allowing full exploitation of fast-switching capabilities of WBG power semiconductor devices (e.g., GaN HEMTs) within the module 100.

[0099] Further, the gate circuit current paths PL1 , PL2 for the LS devices 15-1 , 15-2 have substantially the same length. Similarly, the gate circuit current paths PH1 , PH2 for the HS devices 11-1 , 11-2 have substantially the same length. This means that the gate loop parasitics of individual devices within the same power switch are equally balanced, thereby allowing the switching of the individual devices to be synchronised which is beneficial for improving the switching speed of the power switch as a whole.

[0100] To balance the gate loop parasitics of individual devices within the same power switch, it is preferable that the ‘GATE’ pin of the gate driver circuit 54-L is positioned equidistant from the plated through holes 51-2 and 51-3, and that the ‘KELVIN SOURCE’ pin of the gate driver circuit 54-L is positioned equidistant from the plated through holes 51-1 and 51-4. Further, it is preferable that the conductive layer 44 provides conductive tracks (which may or may not be spaced apart from one another) with identical length and width to the plated through holes 51-2 and 51-3, respectively. Equally, it is preferable that the conductive layer 45 provides conductive tracks with identical length and width to the plated through holes 51-1 and 51-4, respectively. In the event that an output pin of the gate driver circuit 54-L cannot achieve the equidistant arrangement with the corresponding plated through holes, the conductive tracks within the conductive layer 44 or 45 may be suitably patterned such that wider conductive tracks are used for connecting further-away plated through holes. The above description similarly applies to the gate drive connections for the HS devices 11.

[0101] In general, by making the gate drive circuitry an internal component of the module 100, the gate driver circuits 54 can be placed as close as possible to the respective HS and LS gate and Kelvin source auxiliary pins 23 to 26. This arrangement allows the inductances of the gate circuit loops to be kept as small as possible and equally balanced.

[0102] Further, the DC-DC converters 52 and the voltage regulators 53 can be placed as close as possible to the gate driver circuits 54. This arrangement allows the internal power supply (i.e., VDD, VSS), provided by the DC-DC converters 52 and the voltage regulators 53 to the gate driver circuits 54, to be kept clean and steady. This is because the internal power supply is sufficiently separated from the power connections of the devices 11 , 15 which often cause radiated EMI, and therefore the internal power supply suffers less EMI interference. In some of the existing power modules, both power devices and circuits generating the internal power supply are mounted on the same substrate. In that arrangement, the quality of the internal power supply is often lower and suffers from EMI interference. Further, that arrangement mixes the low power rating of the circuits and the high power rating of the power devices, and thus may have thermal management and reliability issues which could lead to early failure of the circuits.

[0103] In addition, the multi-layered design of the circuit board 41 as described above is also helpful for improving the performance of the module 100.

[0104] Firstly, the circuit board 41 uses an internal conductive layer 44 to route the gate control signals to the power devices 11 , 15, and another internal conductive layer 45 to route the Kelvin source control signals to the power devices 11 , 15. This arrangement allows the use of relatively wide conductive planes in the gate circuit loop, which is beneficial for further reducing the parasitic inductances and resistances of the gate circuit loop.

[0105] Secondly, the circuit board 41 allows the capacitance between the gate and Kelvin source potentials to be tailored, by varying the area of mutual overlap between the conductive layers 44, 45 and the thickness of insulating layer 42 between the conductive layers 44, 45. Tailoring the capacitance between the gate and Kelvin source potentials can have benefits by allowing the adjustment of the gate drive circuit impedance, which can help improve dv / dt immunity.

[0106] Thirdly, if enough layers are included in the circuit board 41 , one layer (e.g., the conductive layer 46) could be used as a shielding layer, to shield the sensitive gate driver circuit components from the EMI emissions emanating from the power circuit beneath the circuit board 41.

[0107] Fourthly, de-coupling capacitors could be added to the circuit board 41 to help further reduce and balance the power loop inductance.

[0108] The module 100 can be assembled in various different ways. In one example, the HS and LS devices 11 , 15 are attached to the substrate 3 by way of either soldering or sintering processes. The power connections 27 to 29 and 62 are bonded to the devices 11 , 15 and substrate 3, again by either soldering or sintering processes. The gate and source electrodes of the devices 11 , 15 are bonded to the respective conductive tracks 58, 59, 8, 9 using single ultrasonically welded wire-bond connections. Power terminals 30 to 32 and auxiliary pins 23 to 26 are also attached to the substrate 3 by soldering or sintering processes. The above steps form the substrate assembly as shown in Figure 5. The substrate assembly is then attached to the baseplate 2 by soldering or sintering processes. The circuit board 41 is assembled separately, where the DC-DC converters 52, voltage regulators 53, and gate driver chips 54 are attached by a soldering process, along with the passive components 55 and the control terminals 37 to 40, thereby resulting a circuit board assembly as shown in Figure 6. Subsequently, the PCB assembly is placed over the auxiliary pins 23 to 26 and is fixed in place by soldering the auxiliary pins 23 to 26 to the plated through holes 51 of the circuit board 41 . Finally, the module is encapsulated by way of a transfer moulding or vacuum casting process. The encapsulation forms the module housing 1. It would be appreciated that these examples are in no way limiting, and the module 100 may be assembled by any suitable process.

[0109] In the examples described above, the devices 11 , 15 are GaN transistors (e.g., GaN HEMTs). It would be appreciated that the devices 11 , 15 may be other types of WBG power transistors, or may be based upon non-WBG semiconductor materials (e.g., Silicon). In the event that the devices 11 , 15 are IGBT-based, the Kelvin source control signal may be referred to as auxiliary emitter control signal. The Kelvin source control signal and the auxiliary emitter control signal may be collectively referred to as “auxiliary control signal”.

[0110] Within the module 100, each of the devices 11 , 15 is a lateral power device, meaning that its power electrodes are formed on the same side (e.g., the top surface) of the device and that a power current flows laterally between the power electrodes. It would be appreciated that the devices 11 , 15 may be replaced by vertical power devices.

[0111] The module 100 described above is for a half-bridge circuit topology. It would further be appreciated that the module 100 may be modified to contain a single power switch or to realise other circuit topologies (such as, a multi-phase power converter, at least one phase of a three-level neutral point clamped inverter, etc.).

[0112] In addition, the control terminals 37 to 40 of the module 100 could be positioned protruding from the top of the module 100, instead of from one end of the module 100, or along one or both edges of the module. Indeed, because the gate drive circuitry are mounted on the internal circuit board 41 of the module 100, the module 100 offers a much greater degree of design flexibility in the positioning of the control terminals 37 to 40 than the module 100’.

[0113] In the module 100, each of the HS and LS power switches includes two power devices. For more than two devices in parallel per switch, multiple gate driver chips could be used per switch to maintain the small gate circuit current loops, and balancing of the gate circuit current loops.

[0114] The DC-DC converter 52 and the voltage regulator 53 may be collectively referred to as a power management circuit. It would be appreciated that one of the DC-DC converter 52 and the voltage regulator 53 may be omitted or that the power management circuit may have a different topology.

[0115] Figure 12 schematically illustrates processing steps of a method for manufacturing a power semiconductor module (e.g., the module 100).

[0116] At step S1 , at least one power semiconductor device (e.g., the devices 11 , 15) is mounted on a substrate (e.g., the substrate 3). The mounting may be performed by either soldering or sintering processes.

[0117] At step S2, a power management circuit (e.g., one or both of the DC-DC converter 52 and the voltage regulator 53) and a gate driver circuit (e.g., the gate driver circuit 54) are mounted on a circuit board (e.g., the circuit board 41). The power management circuit is configured to generate a power supply (e.g., ‘VDD’, ‘VSS’) for use by the gate driver circuit, and the gate driver circuit is configured to generate a control signal (e.g., ‘GATE’, ‘KELVIN SOURCE’) which controls an operation of the at least one power semiconductor device.

[0118] At step S3, the circuit board (with the power management circuit and the gate driver circuit mounted thereon) is positioned above the substrate. The at least one power semiconductor device may be arranged between the circuit board and the substrate.

[0119] At step S4, the at least one power semiconductor device, the circuit board, the power management circuit, the gate driver circuit and at least a part of the substrate are enclosed by a housing (e.g., the housing 1).

[0120] It would be appreciated that the steps may be performed in a temporal order that is different from the order of description. For example, steps S1 and S2 may be performed simultaneously before step S3 and S4.

[0121] The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated structures, elements or features but not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘left’, ‘right’, ‘top’, ‘upper’, ‘lower’, ‘above’, ‘vertical’, etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:1 . A power semiconductor module comprising: a substrate; at least one power semiconductor device mounted on the substrate; a circuit board overlying the substrate; a power management circuit and a gate driver circuit which are mounted on the circuit board, wherein the power management circuit is configured to generate a power supply for use by the gate driver circuit, and the gate driver circuit is configured to generate a control signal which controls an operation of the at least one power semiconductor device; and a housing configured to enclose the at least one power semiconductor device, the circuit board, the power management circuit, the gate driver circuit and at least a part of the substrate.

2. A power semiconductor module according to claim 1 , further comprising a first control terminal for receiving a pulse-width-modulation, PWM, input signal, wherein the first control terminal is mounted on the circuit board and extends beyond the housing to an exterior of the power semiconductor module, and wherein the gate driver circuit is configured to generate the control signal based upon the PWM input signal.

3. A power semiconductor module according to claim 1 or 2, further comprising a second control terminal for receiving a voltage input, wherein the second control terminal is mounted on the circuit board and extends beyond the housing to an exterior of the power semiconductor module, and wherein the power management circuit is configured to generate the power supply based upon the voltage input.

4. A power semiconductor module according to any preceding claim, wherein the power management circuit comprises a voltage regulator which generates the power supply.

5. A power semiconductor module according to claim 4 as dependent from claim 3, wherein the power management circuit further comprises a DC-DC converter which is configured to generate, based upon the voltage input, a further power supply for use by the voltage regulator.

6. A power semiconductor module according to any preceding claim, wherein the at least one power semiconductor device comprises a first power semiconductor device, and the first power semiconductor device comprises a first gate electrode, a first power electrode and a second power electrode.

7. A power semiconductor module according to claim 6, wherein the control signal generated by the gate driver circuit comprises a gate control signal and an auxiliary control signal, and wherein the first gate electrode is configured to receive the gate control signal, and the first power electrode is configured to receive the auxiliary control signal.

8. A power semiconductor module according to any preceding claim, wherein the circuit board comprises a plurality of electrically conductive layers stacked with a plurality of electrically insulating layers along a stacking direction, and at least one of the electrically insulating layers is arranged between adjacent ones of the electrically conductive layers.

9. A power semiconductor module according to claim 8 as dependent from claim 7, wherein the plurality of electrically conductive layers comprises first, second and third electrically conductive layers which are spaced apart from one another along the stacking direction, and wherein: the power management circuit and the gate driver circuit are mounted on the first electrically conductive layer, and the second and third electrically conductive layers are internal layers of the circuit board; a conductive pathway for the gate control signal to travel from the gate driver circuit to the first gate electrode comprises at least a part of the second electrically conductive layer, and a conductive pathway for the auxiliary control signal to travel from the gate driver circuit to the first power electrode comprises at least a part of the third electrically conductive layer.

10. A power semiconductor module according to claim 9, wherein the at least a part of the second electrically conductive layer and the at least a part of the third electrically conductive layer partially or wholly overlap when viewed along the stacking direction.

11. A power semiconductor module according to any preceding claim as dependent from claim 7, wherein the at least one power semiconductor device further comprises a second power semiconductor device, and the second power semiconductor device comprises a second gate electrode configured to receive the gate control signal, a third power electrode configured to receive the auxiliary control signal and a fourth power electrode, and wherein the first power electrode is electrically connected to the third power electrode, and the second power electrode is electrically connected to the fourth power electrode.

12. A power semiconductor module according to claim 11 as dependent from claim 9, wherein: the gate driver circuit comprises an output terminal which output the gate control signal; the circuit board is configured to route the gate control signal to a first location of the circuit board, from where the gate control signal leaves the circuit board and travels to the first gate electrode, and is configured to route the gate control signal to a second location of the circuit board, from where the gate control signal leaves the circuit board and travels to the second gate electrode; and the output terminal of the gate driver circuit is arranged equidistant from the first location and the second location.

13. A power semiconductor module according to any of claims 1 to 10 as dependent from claim 6, wherein: the at least one power semiconductor device further comprises a second power semiconductor device, and the second power semiconductor device comprises a second gate electrode, a third power electrode and a fourth power electrode; the second power electrode is electrically connected to the third power electrode; and the power semiconductor module further comprises first, second and third power terminals, with the first power terminal electrically connected to the first power electrode, the second power terminal electrically connected to the second and third power electrodes, and the third power terminal electrically connected to the fourth power electrode.

14. A power semiconductor module according to claim 13, wherein the gate driver circuit comprises a first gate driver circuit configured to generate a first control signal which controls an operation of the first power semiconductor device, and a second gate driver circuit configured to generate a second control signal which controls an operation of the second power semiconductor device.

15. A power semiconductor module according to claim 14 as dependent from claim 2, wherein: the PWM input signal received by the first control terminal is a first PWM input signal, and the first gate driver circuit is configured to generate the first control signal based upon the first PWM input signal; and the power semiconductor module further comprises a third control terminal for receiving a second PWM input signal, and the second gate driver circuit is configured to generate the second control signal based upon the second PWM input signal.

16. A power semiconductor module according to claim 14 or 15, wherein a distance between the first gate driver circuit and the first power semiconductor device is less than a distance between the second gate driver circuit and the first power semiconductor device.

17. A power semiconductor module according to any one of claims 14 to 16, wherein the power management circuit comprises a first power management circuit configured to generate a first power supply for use by the first gate driver circuit, and a second power management circuit configured to generate a second power supply for use by the second gate driver circuit.

18. A power semiconductor module according to claim 17, wherein a distance between the first power management circuit and the first gate driver circuit is less than a distance between the second power management circuit and the first gate driver circuit.

19. A power semiconductor module according to any preceding claim as dependent from claim 9, wherein the circuit board comprises a fourth electrically conductive layer which forms a surface of the circuit board that faces the at least one power semiconductor device, and the fourth electrically conductive layer is isolated from voltage potentials of the electrodes of the at least one power semiconductor device.

20. A power semiconductor module according to any preceding claim, further comprising an electrically insulating material that fills a space between the circuit board and the substrate.21 . A power semiconductor module according to any preceding claim, wherein the at least one power semiconductor device comprises a wide bandgap power semiconductor device.

22. A method of manufacturing a power semiconductor module, comprising: mounting at least one power semiconductor device on a substrate; mounting a power management circuit and a gate driver circuit on a circuit board, wherein the power management circuit is configured to generate a power supply for use by the gate driver circuit, and the gate driver circuit is configured to generate a control signal which controls an operation of the at least one power semiconductor device; positioning the circuit board above the substrate; and enclosing the at least one power semiconductor device, the circuit board, the power management circuit, the gate driver circuit and at least a part of the substrate by a housing.

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