Multiprocessor device

Abstract

A multiprocessor device (1) according to the present disclosure comprises: shared resources (41, 42) that include a plurality of processors (11, 12) on one semiconductor chip, are shared by the plurality of processors (11, 12), receive a request signal from any one of the plurality of processors (11, 12), and transmit a response signal corresponding to the request signal to the processor that has transmitted the request signal; and a plurality of response control units (21, 22) that are respectively provided in correspondence to the plurality of processors, monitor the request signal and the response signal corresponding to the request signal, and control a response to the request signal.

Description

Multiprocessor Device

[0001] The present disclosure relates to a multiprocessor device having multiple processors on a single semiconductor chip.

[0002] In systems that require high reliability, such as infrastructure and industrial equipment, system redundancy is used to prevent loss of safety due to failures. One known method of redundancy is to multiplex the processors that control the system, so that in the event of a failure, at least one processor continues to operate normally, maintaining a safe state. In recent years, with the increase in semiconductor integration, it has become possible to implement multiple processors on a single semiconductor chip, and methods have been proposed to achieve redundancy using a single semiconductor chip, i.e., on-chip redundancy.

[0003] A redundant system may have not only duplicated components but also shared resources that are not duplicated. In this case, if a failure occurs in a shared resource and it becomes unable to respond, if all of the duplicated processors access the shared resource, all of the processors will continue to wait for a response, and redundancy will be lost. One solution to this problem is to have a mechanism that monitors requests issued by processors and outputs a pseudo-response if there is no response for a certain period of time.

[0004] JP 2012-248205 A

[0005] However, in a conventional mechanism for outputting a pseudo response, the system controller itself, which is the mechanism for outputting the pseudo response, is a shared resource, and if an abnormality occurs in the system controller, the pseudo response cannot be output.

[0006] The present disclosure has been made in consideration of the above circumstances, and aims to provide a technique that can improve the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip.

[0007] In order to achieve the above object, the multiprocessor device of the present disclosure has a plurality of processors on a single semiconductor chip, a shared resource that is shared by the plurality of processors and receives a request signal from any one of the plurality of processors and transmits a response signal corresponding to the request signal to the processor that issued the request signal, and a plurality of response control units that are provided corresponding to each of the plurality of processors and monitor the request signal and the response signal corresponding to the request signal and control the response to the request signal.

[0008] According to the present disclosure, it is possible to provide a technique that can improve the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip.

[0009] A diagram showing an example of a configuration of a multiprocessor device according to an embodiment. A diagram showing an example of a request receiving process executed by a response control unit included in the multiprocessor device according to the embodiment. A diagram showing an example of a history management table according to the embodiment. A diagram showing an example of a response receiving process executed by a response control unit included in the multiprocessor device according to the embodiment. A diagram showing an example of a timeout process executed by a response control unit included in the multiprocessor device according to the embodiment.

[0010] Hereinafter, an additive manufacturing apparatus according to a first embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

[0011] 1 is a diagram showing the configuration of a multiprocessor device 1 according to an embodiment. The multiprocessor device 1 is, for example, a device in which multiple processors are mounted on a single semiconductor chip. The processors are, for example, microprocessors.

[0012] The multiprocessor device 1 includes a processor 11, a processor 12, a response control unit 21, a response control unit 22, an internal bus control unit 31, an internal bus control unit 32, a shared resource 41, a shared resource 42, a signal transmission unit 51, a signal transmission unit 52, an insulation unit 60, a power input unit 71, and a power input unit 72.

[0013] The processor 11 is connected to a shared resource 41 via a response control unit 21 and an internal bus control unit 31. The internal bus control unit 31 is a general component that interconnects the components of a semiconductor chip. The internal bus control unit 31 interconnects, for example, the response control unit 21, the shared resource 41, and the signal transmission unit 51. The processor 12 is connected to a shared resource 42 via a response control unit 22 and an internal bus control unit 32. The internal bus control unit 32 is a general component that interconnects the components of a semiconductor chip. The internal bus control unit 32 interconnects, for example, the response control unit 22, the shared resource 42, and the signal transmission unit 52.

[0014] 1, in the multiprocessor device 1, an area including processor 11 and an area including processor 12 are electrically insulated by an insulating unit 60 inside a semiconductor chip included in the multiprocessor device 1. At this time, the internal bus control unit 31 and the shared resource 42 are connected across the insulating unit 60 by a signal transmission unit 51. Furthermore, the internal bus control unit 32 and the shared resource 41 are connected across the insulating unit 60 by a signal transmission unit 52.

[0015] Of the two electrically isolated regions, the region including processor 11 shares power from external power supply 101 via power supply input unit 71. On the other hand, the region including processor 12 shares power from external power supply 102 via power supply input unit 72. In other words, the region including processor 11 and the region including processor 12 share power supplies independently of each other.

[0016] In FIG. 1 , shared resources 41 and 42 are components of a semiconductor chip that are shared by multiple processors and receive requests from the multiple processors. For example, shared resources 41 and 42 receive request signals from processor 11 or processor 12 and generate response signals in response to the request signals. Shared resources 41 and 42 transmit the generated response signals to processor 11 or processor 12. Shared resources 41 and / or 42 may be, for example, internal memory, an external memory interface, an external input / output interface, an external communication interface, etc. Note that shared resources 41 and / or 42 may be elements that are used in common by multiple processors and perform part of an internal bus control function. Furthermore, the number of shared resources is not limited to the number shown in FIG. 1 and may be one, three, or more.

[0017] In FIG. 1, signal transmission units 51 and 52 are typical elements within a typical semiconductor chip, and transmit signals across insulated regions.

[0018] 1, each area separated by an insulating unit 60 is insulated from the others and is supplied with power independently, so that the components included in each area can operate normally even if an abnormality occurs in the other external power supply. For example, if the supply of external power supply 101 stops and the supply of external power supply 102 is normal, the processor 11, response control unit 21, internal bus control unit 31, and shared resource 41 will stop operating, but the processor 12, response control unit 22, internal bus control unit 32, and shared resource 42 will continue to operate normally. In other words, power supply redundancy can be achieved.

[0019] 1 , the response control unit 21 is provided corresponding to the processor 11, monitors request signals from the processor 11 and response signals corresponding to the request signals, and controls responses to the request signals from the processor 11. The response control unit 21 has a history management table 211. The history management table 211 is a table for managing the history of request signals and response signals corresponding to the request signals. The history management table 211 manages, for example, the history of request signals received from the processor 11. The request signals received from the processor 11 are, for example, request signals transmitted to the shared resource 41 or the shared resource 42. The history management table 211 also manages the history of response signals received from the shared resource 41 or the shared resource 42 via the internal bus control unit 31. The response control unit 21 also uses the history management table 211 to manage the number of response signals requested by the request signals. The response control unit 21 controls responses to the processor 11, for example, depending on the number of response signals actually received relative to the number of response signals requested.

[0020] 1 , the response control unit 22 is provided corresponding to the processor 12, monitors request signals from the processor 12 and response signals corresponding to the request signals, and controls responses to the request signals from the processor 12. The response control unit 22 has a history management table 221. The history management table 221 is a table for managing the history of request signals or response signals. The history management table 221 manages, for example, the history of request signals received from the processor 12. The request signals received from the processor 12 are, for example, request signals transmitted to the shared resource 41 or the shared resource 42. The history management table 221 also manages the history of response signals received from the shared resource 41 or the shared resource 42 via the internal bus control unit 32. The response control unit 22 also uses the history management table 221 to manage the number of response signals requested by the request signals. The response control unit 22 controls responses to the processor 12, for example, depending on the number of response signals actually received relative to the number of response signals requested.

[0021] The processing executed by the multiprocessor device 1 configured as above will be described with reference to FIGS. 2, 3, 4 and 5. FIG.

[0022] First, the request reception process will be described. FIG. 2 is a diagram showing an example of the request reception process executed by the response control units 21 and 22 included in the multiprocessor device 1 according to the embodiment. Here, as an example, the request reception process executed by the response control unit 21 will be described using FIG. 2. In this embodiment, it is assumed that the request signal received by the response control unit 21 from the processor 11 includes information indicating the number of transmissions, which indicates the number of responses required, along with information on the destination to which the request signal is sent. The number of transmissions is, for example, the number of data transmissions that indicates how many transmissions are required to transmit the total amount of data including response signals corresponding to the request signal. In addition to the information indicating the number of transmissions, the request signal may also include information indicating the transmission size.

[0023] In FIG. 2, the response control unit 21 receives, for example, a request signal from the processor 11 (step S11).

[0024] When the response control unit 21 receives a request signal from the processor 11, it refers to the information indicating the number of transmissions included in the request signal and determines the number of response signals corresponding to the received request signal (step S12).

[0025] The response control unit 21 associates the request signal received in step S11 with the number of responses determined in step S12 and registers them in the history management table 211 (step S13). FIG. 3 is a diagram showing an example of the history management table 211 or 221 according to an embodiment. According to FIG. 3, for example, the history management table 211 is configured with a "request signal" field that identifies the request signal and a "number of responses" field that indicates the number of responses to the request. As shown in FIG. 3, values ​​stored in the "request signal" field are, for example, "A," "B," "C," and "D." Furthermore, values ​​stored in the "number of responses" field are, for example, "1," "5," "3," and "2."

[0026] In FIG. 2, the response control unit 21 outputs the request signal received in step S11 to the internal bus control unit 31 (step S14).

[0027] Next, a response reception process will be described. Fig. 4 is a diagram showing an example of the response reception process executed by the response control units 21 and 22 provided in the multiprocessor device 1 according to the embodiment. Here, as an example, the response reception process executed by the response control unit 21 will be described using Fig. 4. In this embodiment, it is assumed that a corresponding record is registered in the history management table 211 for a response signal received by the response control unit 21 from the internal bus control unit 31, and that the record shown in Fig. 3 is a record having "B" in the "request signal" field and "5" in the "number of responses" field.

[0028] In FIG. 4, the response control unit 21 receives a response signal that is generated by the shared resource 41 and transmitted via the internal bus control unit 31 (step S21).

[0029] When the response control unit 21 receives the response signal from the internal bus control unit 31, it refers to the history management table 211 (step S22).

[0030] The response control unit 21 determines whether or not there is a record of a received signal corresponding to the received response signal (step S23).

[0031] Because there is a record in which the "request signal" field is set to "B" and the "number of responses" field is set to "5" corresponding to the received response signal (Yes in step S23), the response control unit 21 updates the history management table 211 (step S24). Specifically, for the record in which the "request signal" field is set to "B," the response control unit 21 subtracts 1 from the value "5" in the "number of responses" field to update it to "4." If the value of the "number of responses" field after the subtraction is "0," the response control unit 21 deletes from the history management table 211 the record of the request signal in which the value of the "number of responses" field is "0." In this way, the response control unit 21 manages the number of response signals requested by a request signal using the history management table 211. As a result, even if, for example, a response signal in response to a request signal issued by the processor 11 is divided into multiple pieces, the divided data constituting the response signal can be reliably managed and the response signal can be accurately output.

[0032] 4, if there is no record of a received signal corresponding to the received response signal (No in step S23), the response control unit 21 discards the received response signal (step S25). This makes it possible to prevent an abnormal state, such as a state in which the processor 11 becomes inoperable due to excessive response signals being output to the processor 11, for example.

[0033] When discarding the response signal, the response control unit 21 may transmit an abnormality signal to the processor 11 or 12 to notify that an abnormality has occurred. At this time, the processor 11 or 12 that receives the abnormality signal from the response control unit 21 executes processing required to maintain the system in a safe state. Processing required to maintain the system in a safe state includes, for example, stopping the entire system by applying an emergency stop, or continuing operation of the entire system using alternative components. As a result, even if some of the requested number of response signals are not returned, the processor can detect the abnormality and take appropriate action, thereby preventing the abnormal state from continuing.

[0034] Finally, a timeout process will be described. Fig. 5 is a diagram showing an example of the timeout process executed by the response control units 21 and 22 provided in the multiprocessor device 1 according to the embodiment. Here, as an example, the timeout process executed by the response control unit 21 will be described using Fig. 5. In this embodiment, the response control unit 21 monitors request signals registered in the history management table 211.

[0035] At this time, the response control unit 21 has, for example, a watchdog timer and monitors the request signal using the watchdog timer. The watchdog timer is, for example, a timer with a monitoring function that notifies of an abnormality when the time measurement value exceeds a predetermined time. Note that the timeout processing may be realized using a method other than a watchdog timer, and any method that can perform timeout processing may be used. For example, when registering a request signal, the response control unit 21 may register the registration time in the history management table 211, and then, at predetermined intervals, perform timeout processing if the elapsed time from the registration time is equal to or exceeds a predetermined time.

[0036] In FIG. 5, the response control unit 21 receives a timeout notification for a specific request signal from the watchdog timer (step S31).

[0037] For example, when the response control unit 21 receives a timeout notification for a specific request signal from a watchdog timer, it refers to the history management table 211 and extracts the value of the "number of responses" item associated with the specific request signal (step S32).

[0038] The response control unit 21 generates pseudo response signals in the number of which is equal to the value of the "number of responses" extracted in step S32 (step S33). The response control unit 21 generates, for example, three pseudo response signals.

[0039] Next, the response control unit 21 outputs the pseudo response signals generated in step S33 to the processor 11 (step S34). The response control unit 21 outputs, for example, three pseudo response signals. This makes it possible to output the correct number of pseudo response signals even if a failure occurs that causes a shortage of multiple response signals.

[0040] Finally, the response control unit 21 updates the history management table 211 (step S35). Specifically, the response control unit 21 deletes from the history management table 211, for example, the record corresponding to the request signal for which the pseudo response signal was output in step S34.

[0041] When the response control unit 21 outputs the pseudo response signal, the response control unit 21 may transmit an abnormality signal to notify the processor 11 or 12 that an abnormality has occurred. In this case, the processor 11 or 12 that receives the abnormality signal from the response control unit 21 executes the necessary processing to maintain the system in a safe state.

[0042] According to the above embodiment, the multiprocessor device 1 has processors 11 and 12 on a single semiconductor chip, and has shared resources 41 and 42 that are shared by processors 11 and 12, receive request signals from either of processors 11 and 12, and transmit response signals corresponding to the request signals to the processor that issued the request signal, and response control units 21 and 22 that are provided corresponding to each of processors 11 and 12, monitor the request signals and the response signals corresponding to the request signals, and control the responses to the request signals.

[0043] As a result, even if an abnormality occurs in the shared resource 41 or 42 and one of the response control units 21 and 22 also fails, the other remains normal, so that the operation of the system that functions the multiprocessor device 1 can be maintained in a safe state. In other words, a fault-tolerant system can be realized.

[0044] Therefore, according to this embodiment, it is possible to improve the reliability of a multiprocessor device in which a plurality of processors are mounted on a single semiconductor chip.

[0045] The shared resource 41 and / or the shared resource 42 are not limited to those described in the above embodiment. For example, the shared resource 41 or the shared resource 42 may be a communication control unit that controls a black channel. A black channel is a channel for communicating with an external device by making data redundant over a single physical transmission path. In this case, even if the communication control unit is a single physical element, it is possible to logically duplicate communication.

[0046] In the above embodiment, the multiprocessor device 1 is configured to include two processors, processor 11 and processor 12, but this is not limited to this. For example, the multiprocessor device 1 may be configured to include three or more processors. In this case, the processors included in the multiprocessor device 1 are electrically insulated from each other. Furthermore, a response control unit, an internal bus control unit, a power input unit, etc. are provided corresponding to each processor included in the multiprocessor device 1.

[0047] The present disclosure allows various embodiments and modifications without departing from the broad spirit and scope of the present disclosure. Furthermore, the above-described embodiments are intended to explain the present disclosure and do not limit the scope of the present disclosure. That is, the scope of the present disclosure is defined by the claims, not the embodiments. Various modifications made within the scope of the claims and the meaning of equivalent disclosures are considered to be within the scope of the present disclosure.

[0048] According to the present disclosure, it is possible to provide a multiprocessor device that can improve the reliability of a multiprocessor device in which multiple processors are mounted on a single semiconductor chip.

[0049] REFERENCE SIGNS LIST 1 multiprocessor device, 11, 12 processors, 21, 22 response control units, 31, 32 internal bus control units, 41, 42 shared resources, 51, 52 signal transmission units, 60 insulation units, 71, 72 power supply input units, 211, 221 history management tables, 101, 102 external power supplies.

Claims

1. A multiprocessor device having a plurality of processors on a single semiconductor chip, comprising: a shared resource that is shared by the plurality of processors and receives a request signal from any one of the plurality of processors and transmits a response signal corresponding to the request signal to the processor that issued the request signal; and a plurality of response control units that are provided corresponding to each of the plurality of processors and monitor the request signal and the response signal corresponding to the request signal and control the response to the request signal.

2. The multiprocessor device according to claim 1, wherein said plurality of processors are electrically isolated from one another and each processor has a power supply input.

3. A multiprocessor device as described in claim 1 or 2, wherein the response control unit has a history management table that manages the history of the request signals and the response signals corresponding to the request signals, and uses the history management table to manage the number of response signals requested by the request signals.

4. A multiprocessor device as described in claim 3, wherein if the response control unit does not receive the number of response signals required by the request signal within a specified time, it sends an abnormality signal indicating an abnormality to the processor that issued the request signal.

5. A multiprocessor device according to any one of claims 1 to 4, wherein the shared resource is a communication control unit that controls a black channel for communicating with an external device by making data redundant over a single physical transmission path.

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