Optical semiconductor element, semiconductor substrate, method for manufacturing semiconductor substrate, and method for manufacturing optical semiconductor element

Abstract

This optical semiconductor element includes a first portion and a second portion, an intermediate portion located between the first portion and the second portion in a plan view, and a light emitting layer located below the first semiconductor portion. The first portion, the second portion, and the intermediate portion include a nitride semiconductor. The first portion includes a projection group located on the upper surface side. The thickness of the intermediate portion is greater than the thickness of the second portion.

Description

Optical semiconductor element, semiconductor substrate, method for manufacturing semiconductor substrate, and method for manufacturing optical semiconductor element

[0001] The present disclosure relates to an optical semiconductor device and a semiconductor substrate.

[0002] Patent Document 1 discloses a method for forming a light emitting element on a substrate obtained by laterally growing a GaN (gallium nitride) based semiconductor layer on a mask pattern.

[0003] Japanese Patent Publication No. 2013-251304

[0004] The optical semiconductor element comprises a first portion and a second portion, an intermediate portion located between the first portion and the second portion in a planar view, and a light-emitting layer located below the first portion, wherein the first portion, the second portion, and the intermediate portion include nitride semiconductors, the first portion includes a group of protrusions located on the upper surface side, and the thickness of the intermediate portion is greater than the thickness of the second portion.

[0005] 1 is a perspective view showing the configuration of an optical semiconductor element according to the present embodiment; FIG. 2 is a perspective view showing an example of the shape of a protrusion group; FIG. 3 is a perspective view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 4 is a perspective view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 5 is a flowchart showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 7 is a perspective view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 8 is a perspective view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 9 is a perspective view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 10 is a perspective view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 12 is a perspective view showing a method for manufacturing a semiconductor substrate according to the embodiment; FIG. 13 is a cross-sectional view showing a method for manufacturing an optical semiconductor element according to the embodiment; FIG. 14 is a block diagram showing an apparatus for manufacturing a semiconductor substrate according to the present embodiment; FIG. 15 is a block diagram showing an apparatus for manufacturing an optical semiconductor element according to the present embodiment; FIG. 16 is a schematic view showing the configuration of a semiconductor device according to the present embodiment.

[0006] [Embodiment] Fig. 1 is a perspective view showing the configuration of an optical semiconductor element according to this embodiment. As shown in Fig. 1, an optical semiconductor element (light-emitting element) 20 according to this embodiment includes a first portion H1 and a second portion H2, an intermediate portion HM located between the first and second portions H1 and H2 in a plan view, and a light-emitting layer 9A located below the first portion H1. The first portion H1, the second portion H2, and the intermediate portion HM include nitride semiconductors. The first portion H1 includes a group of protrusions PG located on the upper surface side. The thickness of the intermediate portion HM is greater than the thickness of the second portion H2. A view normal to the light extraction surface of the optical semiconductor element 20 (including a perspective view) is referred to as a plan view.

[0007] In the optical semiconductor element 20, the projection group PG is formed above the light-emitting layer 9A, thereby improving the light extraction efficiency. This allows, for example, a semiconductor device including the optical semiconductor element 20 to have a higher resolution. Furthermore, because the thickness of the intermediate portion HM located between the first and second portions H1 and H2 is greater than the thickness of the second portion H2, the risk of the intermediate portion HM breaking due to an external force applied during mounting of the optical semiconductor element 20 and separating the first and second portions H1 and H2 is reduced. The optical semiconductor element 20 may also have both an intermediate portion HM and a portion thinner than the second portion H2 between the first and second portions H1 and H2.

[0008] When the light extraction direction of the optical semiconductor element 20 is upward, the protrusion group PG is located on the upper surface side of the first portion H1, and the lower surface of the first portion H1 is a gallium polar surface (+C-plane).When the light extraction direction of the optical semiconductor element 20 is downward, the protrusion group PG is located on the lower surface (rear surface) side of the first portion H1, and the upper surface of the first portion H1 is a gallium polar surface (+C-plane).

[0009] The optical semiconductor element 20 may have a functional layer 9 located below the first portion H1. For example, the functional layer 9 may be a layer that constitutes an LED (Light Emitting Diode). The functional layer 9 may include a layer including a superlattice structure. The functional layer 9 may not be located below the second portion H2. The functional layer 9 may not be located below the intermediate portion HM. The functional layer 9 may be located below the second portion H2 or the intermediate portion HM. In a planar view, the area of ​​the first portion H1 may be the same as the area of ​​the functional layer 9. In a planar view, the area of ​​the first portion H1 may be smaller than the area of ​​the functional layer 9.

[0010] The functional layer 9 may include a light-emitting layer 9A and a p-type layer 9P. The light-emitting layer 9A may have a GaN-based multiple quantum well structure. The light-emitting layer 9A may include InGaN or AlGaN. The p-type layer 9P may be a p-type GaN layer. The functional layer 9 may have a light-receiving layer instead of the light-emitting layer 9A. The light-emitting layer 9A may be located below the second portion H2. The light-emitting layer 9A does not have to be located below the second portion H2.

[0011] FIG. 2 is a perspective view showing an example of the shape of the protrusion group. As shown in FIG. 2, each of the multiple protrusions P included on the upper surface U1 of the first portion H1 may be pyramidal (pyramidal). Each of the multiple protrusions P may be conical. The heights of the multiple protrusions P may be different. The shapes of the multiple protrusions P may be different. The multiple protrusions P may be located over the entire upper surface U1 of the first portion H1. The multiple protrusions P may be located on only a portion of the upper surface U1 of the first portion H1.

[0012] The protrusion P protrudes upward from the first portion H1. The protrusion P has a slope W inclined with respect to the thickness direction of the first portion H1. The cross section of the protrusion P in the thickness direction of the first portion H1 may be trapezoidal. The cross section of the protrusion P in the direction perpendicular to the thickness direction of the first portion H1 may be polygonal. Here, "polygonal shape" does not necessarily mean a strict polygonal shape and includes, for example, a polygon with rounded vertices. The protrusion P may have a shape with a rounded upper portion. The slope W included in the protrusion P may include a (10-1-1) plane inclined with respect to the (0001) plane (c-plane). The entire slope W may be a (10-1-1) plane. The height of the protrusion P may be 20 nm or more, 50 nm or more, or 100 nm or more. The height of the protrusion P may be 1000 nm or less or 750 nm or less. The range of the height of the protrusions P can be defined by appropriately combining any value selected from the above-mentioned multiple upper limit values ​​with any value selected from the above-mentioned multiple lower limit values.

[0013] The upper surface UM of the intermediate portion HM is located above the upper surface U2 of the second portion H2. The upper surface UM of the intermediate portion HM is located above the upper surface U1 of the first portion H1. The projection group PG includes a plurality of projections P, and the upper surface UM of the intermediate portion HM is located above the apex of each of the plurality of projections P. The compositions of the first portion H1, the second portion H2, and the intermediate portion HM may be the same as or different from one another. The upper surface UM of the intermediate portion HM may have an uneven shape. The upper surface UM of the intermediate portion HM may include a plane other than the (0001) plane (c-plane).

[0014] The intermediate portion HM may include a ridge portion R that protrudes upward above the second portion H2. The ridge portion R protrudes upward above the first portion H1. The ridge portion R may be located on a base portion B. The thickness of the ridge portion R may be smaller than the thickness of the second portion H2. The upper surface of the ridge portion R may be the upper surface UM of the intermediate portion HM. The intermediate portion HM may include a base portion B that connects to the first and second portions H1 and H2. The base portion B is located between the first portion H1 and the second portion H2. A part of the side surface of the base portion B on the first portion H1 side may be exposed. A nitrogen-polar surface NS of the nitride semiconductor may be exposed on the upper surface side of the first portion H1. The nitrogen-polar surface NS may be located below the upper surface U2 of the second portion H2.

[0015] The protrusion group PG includes multiple protrusions P, and the height of each of the multiple protrusions P may be smaller than the thickness of the second portion H2. The surface roughness of the upper surface U2 of the second portion H2 may be smaller than the surface roughness of the upper surface U1 of the first portion H1. High flatness of the upper surface U1 facilitates handling. Furthermore, the surface roughness of the upper surface U2 of the second portion H2 being smaller than the surface roughness of the upper surface U1 of the first portion H1 facilitates preferential light extraction from the upper surface U1 of the first portion H1. The surface roughness of the upper surface U2 of the second portion H2 and the surface roughness of the upper surface U1 of the first portion H1 can be calculated and compared, for example, by determining the number of protrusions Q per area from AFM (Atomic Force Microscope) measurement results or SEM images. The surface roughness of the upper surface U2 of the second portion H2 and the surface roughness of the upper surface U1 of the first portion H1 may be the maximum height roughness Rz that can be measured, for example, by AFM. The surface roughness can be measured in the same manner on other surfaces of the optical semiconductor element 20 .

[0016] The threading dislocation density of the first portion H1 may be smaller than the threading dislocation density of the intermediate portion HM. The threading dislocation density of the first portion H1 may be 1 / 10 or less of the threading dislocation density of the intermediate portion HM. The threading dislocations in the first portion H1 can be observed by CL (Cathode Luminescence) measurement or by mapping the peak shift of a Raman scattering spectrum. The dislocation density of the first portion H1 can be calculated and compared by determining the number of dislocations observed by the above measurement. The dislocation density can also be measured in other portions of the optical semiconductor element 20 in a similar manner. By forming a protrusion group PG in the first portion H1, which has a low threading dislocation density, the light extraction efficiency can be improved.

[0017] The first and second portions H1 and H2 and the intermediate portion HM constitute a first semiconductor layer (first semiconductor layer) 8A containing a nitride semiconductor. The first semiconductor layer 8A contains a nitride semiconductor as a main component. The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0018] The first and second portions H1 and H2 may be GaN crystals or may be GaN-based mixed crystals (ternary or quaternary mixed crystals) containing at least one of Al and In. The first portion H1 may be a GaN base material, an AlGaN base material, an AlInGaN base material, or an InGaN base material.

[0019] The thickness of the first portion H1, the second portion H2, and the intermediate portion HM may be, for example, 1.0 μm or more and 15 μm or less. The thickness of the base portion B may be, for example, 1.0 μm or more and 15 μm or less. The thickness of the ridge portion R may be, for example, 50 nm or more.

[0020] The first semiconductor layer 8A may be doped (e.g., n-type containing a donor) or non-doped. １７ / cm ３ The first semiconductor layer 8A may contain an n-type dopant at a concentration greater than 5×10 １７ / cm ３ When the concentration of SiO 2 is higher than 1, the etching rate of the first portion H1 described below is increased.

[0021] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor layer 8A (nitride semiconductor crystal). The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor layer 8A. The thickness direction X3 of the first semiconductor layer 8A may be the c-axis direction (<0001> direction) of the first semiconductor layer 8A.

[0022] The first semiconductor layer 8A may be formed by an epitaxial lateral overgrowth (ELO) method starting from a seed portion. The first semiconductor layer 8A may include a ridge portion R that is bonded to the seed portion, and a base portion B that is connected to the ridge portion R and the first portions H1 and H2. The base portion B may be a region with many threading dislocations, and the first portion H1 may be a region with a lower threading dislocation density than the base portion B. The threading dislocation density of the first portion H1 may be 5×10 ６ [pcs / cm ２ ] or less.

[0023] 1 , the projection group PG may be located over the entire upper surface of the first portion H1. The surface roughness of the upper surface UM of the intermediate portion HM may be greater than the surface roughness of the upper surface U2 of the second portion H2 (second wing portion). The surface roughness of the upper surface UM of the intermediate portion HM may be greater than the surface roughness of the upper surface U1 of the first portion H1 (first wing portion). The threading dislocation density of the upper surface UM of the intermediate portion HM may be 10.0 times or more the threading dislocation density of the upper surface U2 of the second portion H2 (second wing portion).

[0024] In a plan view, the first and second portions H1 and H2 are aligned in a first direction X1, and the widths (lengths in the first direction X1) of the first and second portions H1 and H2 may be greater than the width (lengths in the first direction X1) of the intermediate portion HM. The first direction X1 may be the a-axis direction of the nitride semiconductor included in the first and second portions H1 and H2.

[0025] The upper surface U2 of the second portion H2 may be located at the same position in the vertical direction (thickness direction X3) as or higher than the tips of the plurality of protrusions P. For example, the upper surface U2 of the second portion H2 may be located higher than all of the protrusions P.

[0026] An anode EA is located below the light-emitting layer 9A. The anode EA is located below the first portion H1. The anode EA is located below the p-type layer 9P. The anode EA is in contact with the p-type layer 9P. A cathode EC is located below the second portion H2. The cathode EC is in contact with the second portion H2.

[0027] 3 and 4 are perspective views showing the configuration of a semiconductor substrate according to this embodiment. As shown in Fig. 3 and 4, the semiconductor substrate 10 includes a template substrate TS including a first growth-inhibited portion D1, a second growth-inhibited portion D2, and a first seed portion S1 located between the first and second growth-inhibited portions D1 and D2 in a plan view, and a first semiconductor layer 8A including a nitride semiconductor, the first semiconductor layer 8A having a base portion B located above the first seed portion S1, a first wing portion F1 located above the first growth-inhibited portion D1 and with a gap JD between it and the first growth-inhibited portion D1, and a second wing portion F2 located above the second growth-inhibited portion D2, the first wing portion F1 including a group of protrusions PG located on its underside, and a surface roughness at a lower surface U2 of the second wing portion F2 being smaller than a surface roughness at a lower surface U1 of the first wing portion F1.

[0028] A semiconductor substrate means a substrate containing a semiconductor, and the main substrate 1 included in the template substrate TS may or may not contain a semiconductor (e.g., silicon, silicon carbide). An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate. The template substrate TS is also sometimes called a growth substrate. The main substrate 1 may be a free-standing substrate (wafer). The first seed portion S1 can be formed using a sputtering method. Of course, it may also be formed using a metal organic chemical vapor deposition (MOCVD) method, molecular beam epitaxy (MBE) method, or the like.

[0029] The first growth inhibitor D1 may be the mask portion M1, the second growth inhibitor D2 may be the mask portion M2, and the first seed portion S1 may be a part of the base layer 4 exposed in the gap (opening K) between the mask portions M1 and M2. The mask portions M1 and M2 may be any layer (film) that inhibits the growth of the nitride semiconductor in the C-axis direction, and may be a silicon-based insulating film (silicon oxide film, silicon nitride film). The base layer 4 may be, for example, GaN, AlN, or a mixed crystal film of gallium and aluminum (e.g., AlGaN, InGaN, AlInGaN).

[0030] The first and second growth suppression portions D1 and D2 are not limited to the mask portions M1 and M2, and may be, for example, modified layers obtained by modifying (for example, plasma processing) the material of the base layer 4 (for example, aluminum nitride).

[0031] 3 and 4, the semiconductor substrate 10 includes a second semiconductor layer 8C adjacent to the first semiconductor layer 8A in the first direction X1 via a gap GP. The second semiconductor layer 8C has a third wing portion F3 and a fourth wing portion F4, and only one of the third wing portion F3 and the fourth wing portion F4 may include a protrusion group PG located on its lower surface. As shown in FIG. 3, the first wing portion F1 and the third wing portion F3 are adjacent to each other via the gap GP, and the surface roughness of the lower surface U3 of the third wing portion F3 may be smaller than the surface roughness of the lower surface U4 of the fourth wing portion F4. As shown in FIG. 4, the first wing portion F1 and the third wing portion F3 are adjacent to each other via the gap GP, and the surface roughness of the lower surface U3 of the third wing portion F3 may be greater than the surface roughness of the lower surface U4 of the fourth wing portion F4.

[0032] FIG. 5 is a flowchart illustrating a method for manufacturing a semiconductor substrate according to an embodiment. FIG. 6 is a cross-sectional view illustrating the method for manufacturing a semiconductor substrate according to an embodiment. FIGS. 7 and 8 are perspective views illustrating the method for manufacturing a semiconductor substrate according to an embodiment. As illustrated in FIGS. 5 to 8 , the method for manufacturing a semiconductor substrate includes the steps of: preparing a template substrate TS including a first growth-inhibited portion D1, a second growth-inhibited portion D2, and a first seed portion S1 located between the first and second growth-inhibited portions D1 and D2 in a planar view; forming a first semiconductor layer 8A including a nitride semiconductor, the first semiconductor layer 8A having a base portion B located above the first seed portion S1, a first growth layer L1 located above the first growth-inhibited portion D1 and with a gap JD between the first growth-inhibited portion D1 and the first growth-inhibited portion D1; and etching a lower surface U1 of the first growth layer L1 by introducing an etching solution EL into the gap DJ without introducing an etching solution EL between the second growth-inhibited portion D2 and the second growth layer L2.

[0033] The etching solution EL can be an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH). Although etching is possible at room temperature, the etching rate increases when heated to about 80° C. The etching rate can be controlled by adjusting the concentration and temperature of the etching solution EL.

[0034] The first semiconductor layer 8A may have a first wing portion F1 as the first growth layer L1. A protrusion group PG may be formed on the lower surface of the first wing portion F1 by etching the lower surface of the first wing portion F1. The lower surface, which is a nitrogen-polar surface, the upper surface, which is a Ga-polar surface, and the side surfaces of the first wing portion F1 are simultaneously etched, but among these surfaces, the etching rate of the nitrogen-polar surfaces (lower surface and back surface) is extremely high, so that the nitrogen-polar surfaces are almost selectively etched. The first semiconductor layer 8A may include a base portion B adjacent to the first and second growth layers L1 and L2, and a ridge portion (tether portion) R extending from the first seed portion S1 in the c-axis direction of the nitride semiconductor and connected to the base portion B.

[0035] As shown in FIGS. 6 to 8 , the first semiconductor layer 8A may have a second wing portion F2 as the second growth layer L2. The second growth-inhibiting portion D2 includes a mesa portion DM (wall portion) that overlaps an end of the second wing portion F2 in a plan view. The mesa portion DM (wall portion) protrudes upward compared to a region of the second growth-inhibiting portion D2 other than the mesa portion DM. The mesa portion DM may inhibit the intrusion of the etching solution EL between the second growth-inhibiting portion D2 and the second wing portion F2. The mesa portion DM and the second wing portion F2 may be in contact with each other. The mesa portion DM and the second wing portion F2 may not be in contact with each other. The lower surface of the second wing portion F2 may have a concave shape in the region in contact with the mesa portion DM. A space (void) may be formed between the mesa portion DM and the second wing portion F2.

[0036] The template substrate TS may include a mask pattern 6 having a first mask portion M1 functioning as a first growth suppression portion D1, a second mask portion M2 functioning as a second growth suppression portion D1, and an opening K overlapping the first seed portion S1. The mesa portion MD may be obtained by locally thickening the second mask portion M2. As shown in FIGS. 6 and 7 , the mask pattern 6 can be formed by patterning the mask material MZ on the base layer 4 twice (first to form the mesa portion DM and second to form the opening K).

[0037] 9 is a perspective view showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIG. 9 , the main substrate 1 may be locally recessed so that the upper surface of the first growth inhibitor D1 is positioned lower than the upper surface of the second growth inhibitor D2. A gap JD may be formed between the first growth inhibitor D1 and the first wing F1, while the second growth inhibitor D2 and the second wing F2 are in contact with each other. In other words, no gap is formed between the second growth inhibitor D2 and the second wing F2. This prevents the etching solution EL from penetrating between the second growth inhibitor D2 and the second wing F2.

[0038] 10 is a perspective view showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIG. 10, the method may include a step of forming (filling) a resist Z between the second growth inhibitor D2 and the second wing F2, and the resist Z may prevent the etching solution EL from entering between the second growth inhibitor D2 and the second wing F2. In this case, the resist Z may be removed after etching the lower surface U1 of the first growth layer L1.

[0039] 11 and 12 are perspective views showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIGS. 11 and 12 , in the process of forming the first semiconductor layer 8A, the crystal growth of the first semiconductor layer 8A may be controlled based on light TA irradiated onto the mesa portion DM and light TB reflected by the mesa portion DM or the second wing portion F2 overlapping the mesa portion DM. For example, by utilizing the difference in optical reflectivity between the mesa portion DM (e.g., a mask material) and the second wing portion F2 (e.g., a nitride semiconductor), the growth of the wing portions growing in opposite directions can be stopped before they meet. When the mask material MZ is patterned twice as shown in FIGS. 6 and 7 , the surface of the mesa portion DM becomes rough and its optical reflectivity increases, which can be used as a growth marker.

[0040] FIG. 13 is a perspective view showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIGS. 8 and 13 , a second semiconductor layer 8C may be formed adjacent to a first semiconductor layer 8A via a gap GP, and an etchant EL may be introduced through the gap GP. As shown in FIG. 8 , the etchant EL may be introduced between the first growth inhibitor D1 and the first wing F1, but not between the first growth inhibitor D1 and the third wing F3. As shown in FIG. 13 , the etchant EL may be introduced between the first growth inhibitor D1 and the first wing F1 and between the first growth inhibitor D1 and the third wing F3.

[0041] 14 and 15 are perspective views showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIGS. 14 and 15 , a template substrate TS includes a second seed portion S2. In a plan view, a second growth-inhibiting portion D2 is located between the first and second seed portions S1 and S2. The nitride semiconductors grown from the first and second seed portions S1 and S2 may be joined above the second growth-inhibiting portion D2 to obtain a first growth layer L1 (first wing portion F1) and a second growth layer L2. That is, the semiconductor substrate 10 includes a third semiconductor layer 8S that grows from the second seed portion S2 and includes a region located above the second growth-inhibiting portion D2. The first semiconductor layer 8A grown from the first seed portion S1 and the third semiconductor layer 8S grown from the second seed portion S2 join above the second growth-inhibiting portion D2. In this case, the width of the first growth-inhibiting portion D1 (the length in the first direction X1) may be greater than the width of the second growth-inhibiting portion D2. Then, as shown in Figure 15, the etching liquid EL is introduced into the gap DJ without introducing the etching liquid EL between the second growth suppression portion D2 and the second growth layer L2, thereby etching the lower surface U1 (back surface, -c plane) of the first growth layer L1 (first wing portion F1).

[0042] 15 , the ridge portion R rising from the first seed portion S1 and the ridge portion R rising from the second seed portion S2 prevent the etchant EL from penetrating between the second growth suppression portion D2 and the second growth layer L2. After etching the lower surface U1, a step of dividing the second growth layer L2, which is a bridging portion, to obtain the second wing portion F2 may be performed. For example, the second wing portion F2 may be obtained by etching the second growth layer L2, which is a bridging portion. For example, the second wing portion F2 may be obtained by etching a region of the second growth layer L2 where the threading dislocation density is greater than a predetermined value.

[0043] 16 is a perspective view showing a method for manufacturing a semiconductor substrate according to an embodiment. As shown in FIG. 16 , the template substrate TS includes a second seed portion S2 and a third seed portion S3. In plan view, a second growth inhibitor portion D2 is located between the first and second seed portions S1 and S2, and a first growth inhibitor portion D1 is located between the first and third seed portions S1 and S3. The nitride semiconductors grown from the first and second seed portions S1 and S2 may be combined above the second growth inhibitor portion D2, and the nitride semiconductors grown from the first and third seed portions S1 and S3 may be combined above the first growth inhibitor portion D1 to form an initial layer SL. The initial layer SL may then be divided to obtain a first growth layer L1 (first wing portion F1) and a second growth layer L2. The steps from FIG. 16 onward are the same as those shown in FIG. 15 . The initial layer SL can be divided by dry etching using a resist Z.

[0044] Fig. 17 is a flowchart showing a method for manufacturing an optical semiconductor element according to this embodiment. Fig. 18 is a perspective view showing a method for manufacturing an optical semiconductor element according to this embodiment. Fig. 19 is a cross-sectional view showing a method for manufacturing an optical semiconductor element according to this embodiment. As shown in Figs. 17 to 19, the method for manufacturing an optical semiconductor element includes a step S60 of preparing a semiconductor substrate 10 and a step S70 of forming a light-emitting layer 9A above a first wing portion F1. It may also include a step S80 of forming an anode EA above the first wing portion F1 and a cathode EC above the second wing portion F2.

[0045] The template substrate TS includes a mask pattern 6 having a first mask portion M1 functioning as a first growth inhibitor portion D1, a second mask portion M2 functioning as a second growth inhibitor portion D2, and an opening K overlapping with the first seed portion S1, and the first and second mask portions M1 and M2 may be removed before or after the light emitting layer 9A is formed. In step S70, a functional layer 9 including a GaN-based p-type layer 9P and a GaN-based light emitting layer 9A may be formed.

[0046] 18 , the first semiconductor layer 8A may include a base portion B adjacent to the first and second wing portions F1 and F2, and a ridge portion R extending from the first seed portion S1 in the c-axis direction of the nitride semiconductor (third direction X3) and connected to the base portion B. Element isolation may be performed by dividing the first and second wing portions F1 and F2 and the functional layer 9 into multiple pieces and exposing a portion of the ridge portion R. As shown in FIG. 19 , after element isolation, the ridge portion R may be fractured to separate the first semiconductor layer 8A from the template substrate TS. This allows the optical semiconductor element 20 to be obtained.

[0047] 19 , in the manufacturing direction of the optical semiconductor element 20, a step of forming a group of protrusions PG on the lower surface U1 of the first growth layer L1 (F1) may be performed without forming a group of protrusions on the lower surface of the second growth layer L2. That is, a step of etching the lower surface U1 of the first growth layer L1 may be performed by introducing the etching liquid EL into the gap DJ without introducing the etching liquid EL between the second growth suppression portion D2 and the second growth layer L2.

[0048] Fig. 20 is a cross-sectional view showing a method for manufacturing an optical semiconductor element according to an embodiment. Fig. 19 shows an element formation process in which a wing portion (F1) having a projection group PG and a wing portion (F3) not having a projection group PG are adjacent to each other with a gap GP therebetween (a repeating structure), but this is not limiting. As shown in Fig. 20, element formation can also be performed in a similar manner in which a wing portion (F1) having a projection group PG and a wing portion (F3) having a projection group PG are adjacent to each other with a gap GP therebetween (a mirror structure).

[0049] Fig. 21 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 of Fig. 5, an apparatus M20 (e.g., an MOCVD apparatus) that performs step S20 of Fig. 5, an apparatus M30 (a wet etching apparatus) that performs step S30 of Fig. 5, and a control device M5 that controls the apparatuses M10 to M30.

[0050] Fig. 22 is a block diagram showing an optical semiconductor element manufacturing apparatus according to this embodiment. The optical semiconductor element manufacturing apparatus 90 includes an apparatus M60 that performs step S60 of Fig. 17, an apparatus M70 (e.g., an MOCVD apparatus) that performs step S70 of Fig. 17, an apparatus M80 (e.g., a sputtering apparatus) that performs step S80 of Fig. 17, and a control device M9 that controls the apparatuses M70 to M90.

[0051] 23 is a schematic diagram showing the configuration of a semiconductor device according to this embodiment. The semiconductor device 30 may include an optical semiconductor element 20, a drive substrate 23 on which the optical semiconductor element 20 is mounted, and a control circuit 27 that controls the drive substrate 23. The semiconductor device 30 may be a light-emitting device, an exposure device, a display device, a measurement device, an illumination device, a communication device, an information processing device, or the like.

[0052] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0053] [Summary] The optical semiconductor element in aspect 1 of the present disclosure comprises a first portion and a second portion, an intermediate portion located between the first portion and the second portion in a planar view, and a light-emitting layer located below the first portion, wherein the first portion, the second portion, and the intermediate portion include nitride semiconductors, the first portion includes a group of protrusions located on the upper surface side, and the thickness of the intermediate portion is greater than the thickness of the second portion.

[0054] In the optical semiconductor element according to aspect 2 of the present disclosure, in accordance with aspect 1, the upper surface of the intermediate portion is located higher than the upper surface of the second portion.

[0055] In the optical semiconductor element according to aspect 3 of the present disclosure, in addition to aspect 1 or 2, a nitrogen-polar face of the nitride semiconductor is exposed on the upper surface side of the first portion.

[0056] In an optical semiconductor element according to a fourth aspect of the present disclosure, in any one of the first to third aspects, the surface roughness of the upper surface of the second portion is smaller than the surface roughness of the upper surface of the first portion.

[0057] In the optical semiconductor element of aspect 5 of the present disclosure, in any one of aspects 1 to 4, a nitrogen-polar face of the nitride semiconductor is exposed on the upper surface side of the first portion, and the nitrogen-polar face is located below the upper surface of the second portion.

[0058] In an optical semiconductor element according to a sixth aspect of the present disclosure, in any one of the first to fifth aspects, the intermediate portion includes a ridge portion that protrudes upwardly beyond the second portion.

[0059] In a seventh aspect of the present disclosure, in the optical semiconductor element of the sixth aspect, the thickness of the ridge portion is smaller than the thickness of the second portion.

[0060] In an eighth aspect of the present disclosure, in the optical semiconductor element of any one of the first to seventh aspects, the group of protrusions includes a plurality of protrusions, and the height of each of the plurality of protrusions is equal to or less than the thickness of the second portion.

[0061] In an optical semiconductor element according to Aspect 9 of the present disclosure, in any one of Aspects 1 to 8, the threading dislocation density of the first portion is 1 / 10 or less of the threading dislocation density of the intermediate portion.

[0062] In an optical semiconductor element according to a tenth aspect of the present disclosure, in any one of the first to ninth aspects, the group of protrusions is located across the entire top surface of the first portion.

[0063] In an eleventh aspect of the present disclosure, in the optical semiconductor element of any one of the first to tenth aspects, the surface roughness of the upper surface of the intermediate portion is greater than the surface roughness of the upper surface of the second portion.

[0064] In aspect 12 of the present disclosure, the optical semiconductor element is any one of aspects 1 to 11, wherein the first and second portions are positioned side by side in a first direction when viewed in a plan view, and each of the first and second portions has a width in the first direction greater than that of the intermediate portion.

[0065] In an optical semiconductor element according to a thirteenth aspect of the present disclosure, in the twelfth aspect, the first direction is the a-axis direction of the nitride semiconductor.

[0066] In the optical semiconductor element according to aspect 14 of the present disclosure, in any one of aspects 1 to 13, the upper surface of the second portion is located at the same position as or above the tips of the projections in the vertical direction.

[0067] A semiconductor substrate in aspect 15 of the present disclosure comprises a template substrate including a first growth inhibition portion, a second growth inhibition portion, and a first seed portion located between the first and second growth inhibition portions in a planar view, and a first semiconductor layer including a nitride semiconductor, wherein the first semiconductor layer has a base portion located above the first seed portion, a first wing portion located above the first growth inhibition portion and with a gap between it and the first growth inhibition portion, and a second wing portion located above the second growth inhibition portion, wherein the first wing portion includes a group of protrusions located on its underside, and the surface roughness of the underside of the second wing portion is smaller than the surface roughness of the underside of the first wing portion.

[0068] A method for manufacturing an optical semiconductor element in aspect 16 of the present disclosure includes the steps of preparing a semiconductor substrate having a first semiconductor layer including a nitride semiconductor, including a first growth inhibition portion and a second growth inhibition portion, a first seed portion located between the first and second growth inhibition portions in a planar view, a first growth layer located above the first growth inhibition portion and with a gap located between the first growth inhibition portion and the first growth inhibition portion, and a second growth layer located above the second growth inhibition portion, and forming a group of protrusions on the underside of the first growth layer without forming a group of protrusions on the underside of the second growth layer.

[0069] In aspect 17 of the present disclosure, the method for manufacturing an optical semiconductor element is the same as in aspect 16, in which the underside of the first growth layer is etched by introducing an etching solution into the gap without introducing an etching solution between the second growth suppression portion and the second growth layer.

[0070] In the method for manufacturing an optical semiconductor element according to aspect 18 of the present disclosure, in addition to aspect 16 or 17, a group of protrusions is formed on the lower surface of the first growth layer by etching the lower surface of the first growth layer.

[0071] The method for manufacturing an optical semiconductor element in aspect 19 of the present disclosure is, in any one of aspects 16 to 18, wherein the first semiconductor layer includes a base portion connected to the first and second growth layers, and a ridge portion extending from the first seed portion in the c-axis direction of the nitride semiconductor and connected to the base portion.

[0072] The method for manufacturing an optical semiconductor element in aspect 20 of the present disclosure is, in any one of aspects 16 to 19, wherein the first semiconductor layer includes a first wing portion as the first growth layer and a second wing portion as the second growth layer.

[0073] In aspect 21 of the present disclosure, the method for manufacturing an optical semiconductor element is the same as aspect 20, wherein the second growth suppression portion includes a mesa portion that overlaps with an end of the second wing portion in a planar view, and the mesa portion suppresses penetration of an etching solution between the second growth suppression portion and the second wing portion.

[0074] The method for manufacturing an optical semiconductor element in aspect 22 of the present disclosure is any one of aspects 17 to 21 (citing aspect 17), in which the semiconductor substrate has a second semiconductor layer adjacent to the first semiconductor layer via a gap, and the etching solution is introduced through the gap.

[0075] In aspect 23 of the present disclosure, the method for manufacturing an optical semiconductor element is the same as in aspect 21, wherein the semiconductor substrate has a first mask portion that functions as the first growth inhibition portion, a second mask portion that functions as the second growth inhibition portion, and an opening that overlaps with the first seed portion, and the mesa portion includes a locally thick region in the second mask portion.

[0076] The method for manufacturing an optical semiconductor element in aspect 24 of the present disclosure is any one of aspects 16 to 23, wherein the semiconductor substrate has a second seed portion and a third semiconductor layer including a region extending from the second seed portion and located above the second growth inhibition portion, and in a planar view, the second growth inhibition portion is located between the first and second seed portions, and the first semiconductor layer and the third semiconductor layer meet above the second growth inhibition portion.

[0077] In aspect 25 of the present disclosure, the method for manufacturing an optical semiconductor element in aspect 24 is such that a ridge portion rising from the first seed portion and a ridge portion rising from the second seed portion prevent an etching solution from penetrating between the second growth suppression portion and the second growth layer.

[0078] The method for manufacturing an optical semiconductor element in aspect 26 of the present disclosure includes, in aspect 24 or 25, a step of obtaining a second wing portion as the second growth layer by dividing the first semiconductor layer and the third semiconductor layer.

[0079] A method for manufacturing an optical semiconductor element according to Aspect 27 of the present disclosure is any one of Aspects 20 to 26 (citing Aspect 20) and includes forming a light-emitting layer above the first wing portion.

[0080] In aspect 28 of the present disclosure, the method for manufacturing an optical semiconductor element is the same as in aspect 27, wherein the semiconductor substrate includes a mask pattern having a first mask portion that functions as the first growth inhibition portion, a second mask portion that functions as the second growth inhibition portion, and an opening that overlaps with the first seed portion, and the first and second mask portions are removed before or after the light-emitting layer is formed.

[0081] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 6 Mask pattern 8A First semiconductor layer 8C Second semiconductor layer 9 Functional layer 10 Semiconductor substrate 20 Optical semiconductor element P Protrusion PG Protrusion group R Ridge portion B Base portion L1 First growth layer L2 Second growth layer F1 First wing portion F2 Second wing portion H1 First portion H2 Second portion HM Intermediate portion JD Void S1 First seed portion S2 Second seed portion D1 First growth inhibition portion D2 Second growth inhibition portion TS Template substrate

Claims

1. An optical semiconductor element comprising a first portion and a second portion, an intermediate portion located between the first portion and the second portion in a planar view, and a light-emitting layer located below the first portion, wherein the first portion, the second portion, and the intermediate portion comprise nitride semiconductors, the first portion includes a group of protrusions located on its upper surface, and the thickness of the intermediate portion is greater than the thickness of the second portion.

2. The optical semiconductor element according to claim 1, wherein the upper surface of the intermediate portion is located higher than the upper surface of the second portion.

3. The optical semiconductor element according to claim 1 or 2, wherein a nitrogen-polar face of the nitride semiconductor is exposed on the upper surface side of the first portion.

4. An optical semiconductor element according to any one of claims 1 to 3, wherein the surface roughness of the upper surface of the second portion is smaller than the surface roughness of the upper surface of the first portion.

5. The optical semiconductor element according to claim 3, wherein the nitrogen-polar face is located below the upper surface of the second portion.

6. The optical semiconductor element according to any one of claims 1 to 5, wherein the intermediate portion includes a ridge portion that protrudes upward beyond the second portion.

7. The optical semiconductor element according to claim 6, wherein the thickness of the ridge portion is smaller than the thickness of the second portion.

8. An optical semiconductor element according to any one of claims 1 to 7, wherein the group of protrusions includes a plurality of protrusions, and the height of each of the plurality of protrusions is equal to or less than the thickness of the second portion.

9. An optical semiconductor element according to any one of claims 1 to 8, wherein the threading dislocation density of the first portion is 1 / 10 or less of the threading dislocation density of the intermediate portion.

10. The optical semiconductor element according to any one of claims 1 to 9, wherein the group of protrusions is located over the entire top surface of the first portion.

11. The optical semiconductor element according to any one of claims 1 to 10, wherein the surface roughness of the upper surface of the intermediate portion is greater than the surface roughness of the upper surface of the second portion.

12. An optical semiconductor element according to any one of claims 1 to 11, wherein the first and second portions are positioned side by side in a first direction in a plan view, and each of the first and second portions has a width in the first direction greater than that of the intermediate portion.

13. The optical semiconductor element according to claim 12, wherein the first direction is the a-axis direction of the nitride semiconductor.

14. An optical semiconductor element according to any one of claims 1 to 13, wherein the upper surface of the second portion is located at the same position as or above the tips of the projections in the vertical direction.

15. A semiconductor substrate comprising: a template substrate including a first growth-inhibiting portion and a second growth-inhibiting portion, and a first seed portion located between the first and second growth-inhibiting portions in a planar view; and a first semiconductor layer including a nitride semiconductor, wherein the first semiconductor layer has a base portion located above the first seed portion, a first wing portion located above the first growth-inhibiting portion and with a gap between it and the first growth-inhibiting portion, and a second wing portion located above the second growth-inhibiting portion, wherein the first wing portion includes a group of protrusions located on its underside, and the surface roughness of the underside of the second wing portion is smaller than the surface roughness of the underside of the first wing portion.

16. A method for manufacturing an optical semiconductor element, comprising: a step of preparing a semiconductor substrate having a first semiconductor layer including a nitride semiconductor, the first semiconductor layer including a first growth inhibiting portion and a second growth inhibiting portion, a first seed portion located between the first and second growth inhibiting portions in a planar view, a first growth layer located above the first growth inhibiting portion and with a gap located between the first growth inhibiting portion and the first growth inhibiting portion, and a second growth layer located above the second growth inhibiting portion; and a step of forming a group of protrusions on the underside of the first growth layer without forming a group of protrusions on the underside of the second growth layer.

17. The method for manufacturing an optical semiconductor element according to claim 16, wherein the underside of the first growth layer is etched by introducing an etching solution into the gap without introducing an etching solution between the second growth suppression portion and the second growth layer.

18. The method for manufacturing an optical semiconductor element according to claim 16 or 17, wherein a group of protrusions is formed on the lower surface side of the first growth layer by etching the lower surface of the first growth layer.

19. A method for manufacturing an optical semiconductor element according to any one of claims 16 to 18, wherein the first semiconductor layer includes a base portion connected to the first and second growth layers, and a ridge portion extending from the first seed portion in the c-axis direction of the nitride semiconductor and connected to the base portion.

20. A method for manufacturing an optical semiconductor element described in any one of claims 16 to 19, wherein the first semiconductor layer includes a first wing portion as the first growth layer and a second wing portion as the second growth layer.

21. A method for manufacturing an optical semiconductor element as described in claim 20, wherein the second growth suppression portion includes a mesa portion that overlaps an end of the second wing portion in a planar view, and the mesa portion prevents an etching solution from penetrating between the second growth suppression portion and the second wing portion.

22. The method for manufacturing an optical semiconductor element according to claim 17, wherein the semiconductor substrate has a second semiconductor layer adjacent to the first semiconductor layer via a gap, and the etching solution is introduced through the gap.

23. A method for manufacturing an optical semiconductor element as described in claim 21, wherein the semiconductor substrate has a first mask portion that functions as the first growth suppression portion, a second mask portion that functions as the second growth suppression portion, and an opening that overlaps with the first seed portion, and the mesa portion includes a locally thick region in the second mask portion.

24. A method for manufacturing an optical semiconductor element according to any one of claims 16 to 23, wherein the semiconductor substrate has a second seed portion and a third semiconductor layer including a region extending from the second seed portion and located above the second growth inhibition portion, the second growth inhibition portion being located between the first and second seed portions in a planar view, and the first semiconductor layer and the third semiconductor layer meeting above the second growth inhibition portion.

25. A method for manufacturing an optical semiconductor element as described in claim 24, wherein a ridge portion rising from the first seed portion and a ridge portion rising from the second seed portion prevent an etching solution from penetrating between the second growth suppression portion and the second growth layer.

26. The method for manufacturing an optical semiconductor element according to claim 24, further comprising the step of dividing the first semiconductor layer and the third semiconductor layer to obtain a second wing portion as the second growth layer.

27. The method for manufacturing an optical semiconductor device according to claim 20, further comprising the step of forming a light emitting layer above the first wing portion.

28. A method for manufacturing an optical semiconductor element as described in claim 27, wherein the semiconductor substrate includes a mask pattern having a first mask portion that functions as the first growth inhibition portion, a second mask portion that functions as the second growth inhibition portion, and an opening that overlaps with the first seed portion, and the first and second mask portions are removed before or after the light-emitting layer is formed.

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