Circuit board

Abstract

This circuit board includes a build-up layer including an upper surface and a lower surface; and a bump disposed on the build-up layer and disposed to penetrate through the upper surface of the build-up layer, wherein the bump includes a penetrating portion disposed between the upper surface of the build-up layer and the lower surface of the build-up layer and a protruding portion disposed on the upper surface of the build-up layer, and the width of the protruding portion is identical to the width of the penetrating portion.

Description

circuit board

[0001] This embodiment relates to a circuit board.

[0002]

[0003] Electronic components employed in electronic devices include various active and passive circuit elements, and these circuit elements may be integrated into semiconductor chips or dies. Furthermore, the semiconductor chips or dies may be provided in the form of electronic packages mounted on a substrate including circuit wiring, such as a printed circuit board (PCB).

[0004] Meanwhile, flip-chip connection structures, which utilize connection structures to mount and electrically connect semiconductor chips on printed circuit boards, are widely used in electronic packages. For example, flip-chip connection structures utilizing bumps are advantageous for implementing stacked structures of various semiconductor chips. Furthermore, flip-chip connection structures facilitate the use of multiple connection structures to secure a large number of input / output (I / O) terminals.

[0005] Among the methods for forming such connection structures, there is the Solder-On-Pad (SOP) method. The SOP method manufactures connection structures by printing metallic paste or mounting ball-shaped solder on the connection pads on the upper surface of a printed circuit board exposed by a solder mask pattern, and then reflowing to form spherical solder balls through the surface tension effect. However, as the integration level of semiconductor chips increases and their size decreases, there is a problem that the SOP method has limitations in implementing connection members with fine pitches.

[0006] Recently, a method has been proposed for introducing copper posts as connecting elements. This method involves selectively forming copper posts on a printed circuit board using electroplating. Compared to the conventional SOP method, this method can facilitate the implementation of fine pitches.

[0007]

[0008] The present embodiment provides a circuit board capable of improving production efficiency by forming a pad and a post as one piece.

[0009]

[0010] A circuit board according to the present embodiment comprises: a build-up layer including an upper surface and a lower surface; and a bump disposed on the build-up layer and disposed to penetrate the upper surface of the build-up layer, wherein the bump includes a penetration portion disposed between the upper surface of the build-up layer and the lower surface of the build-up layer and a protrusion portion disposed on the upper surface of the build-up layer, and a width of the protrusion portion and a width of the penetration portion are the same.

[0011] The size of the crystal grains of the above-mentioned penetration portion may be the same as the size of the crystal grains of the above-mentioned protrusion portion.

[0012] The horizontal width of the protrusion may be the same as the horizontal width of the penetration.

[0013] The horizontal width of the protrusion may be greater than the horizontal width of the penetration.

[0014] The upper surface of the above bump may include a flat surface and a curved surface having a certain curvature.

[0015] The above curved surface can form the upper edge of the bump based on the above flat surface.

[0016] A protective layer is disposed on the above build-up layer, and the protective layer can cover a portion of a side surface of the protrusion of the bump.

[0017] The above bump includes a first metal layer and a second metal layer surrounding the first metal layer, and the second metal layer can be in contact with the upper surface of the build-up layer.

[0018] The materials of the first metal layer and the second metal layer may be different.

[0019] The material of the first metal layer may be copper (Cu), and the material of the second metal layer may be nickel (Ni).

[0020]

[0021] In this embodiment, the bump is implemented by a penetration portion and a protrusion portion formed integrally, compared to the conventional technology in which the pad and the post are formed through separate processes, so there is an advantage in that production efficiency can be improved.

[0022] In particular, there is an advantage in that durability can be improved by the bump structure formed as one piece, thereby complementing the vulnerability to cracks caused by the seed layer being placed between the conventional pad and post.

[0023]

[0024] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] Figure 2 is an enlarged view of a portion of Figure 1.

[0026] Figures 3 to 8 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0027] Figure 9 is a drawing showing a modified example of a circuit board according to an embodiment of the present invention.

[0028]

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0032] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0033] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0034] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0035] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0036] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0037] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of a portion of FIG. 1, and FIGS. 3 to 8 are views illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0038] Referring to FIGS. 1 to 8, a circuit board (10) according to an embodiment of the present invention may include a build-up layer (20), a bump (120), a circuit pattern (160), and a protective layer (180).

[0039] The above-mentioned build-up layer (20) is formed by stacking at least one insulating layer in a vertical direction and including a circuit layer arranged on each insulating layer, thereby enabling the circuit board to perform electrical connection and insulation functions between circuit layers, and a support function for arranging electronic components on the circuit board, and forming an overall frame. For example, the build-up layer (20) may include a first insulating layer (100), a second insulating layer (200), a third insulating layer (300), a fourth insulating layer (400), and a fifth insulating layer (500). Each of the first to fifth insulating layers (100, 200, 300, 400, 500) may include glass or plastic. The first to fifth insulating layers (100, 200, 300, 400, 500) may each include chemically strengthened / semi-strengthened glass such as sodalime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

[0040] The first to fifth insulating layers (100, 200, 300, 400, 500, 600) are each formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a prepreg (PPG) including glass fibers in a resin can be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers can be included.

[0041] The above build-up layer (20) may include a circuit pattern and a via.

[0042] The circuit pattern may include a first circuit pattern (160) disposed on the first insulating layer (100), a second circuit pattern (210) disposed on the second insulating layer (200), a third circuit pattern (310) disposed on the third insulating layer (300), a fourth circuit pattern (410) disposed on the fourth insulating layer (400), and a fifth circuit pattern (510) disposed on the fifth insulating layer (500).

[0043] The first circuit pattern (160) may be embedded in the upper surface of the first insulating layer (100). The first circuit pattern (160) may be arranged to overlap with the penetration portion (122) of the bump (120) described later in the horizontal direction. The first circuit pattern (160) may include a plurality of metal patterns spaced apart in the horizontal direction.

[0044] The above second circuit pattern (210) can be embedded in the second insulating layer (200).

[0045] The above third circuit pattern (310) can be embedded in the third insulating layer (300).

[0046] The above fourth circuit pattern (410) can be embedded in the fourth insulating layer (400).

[0047] The above fifth circuit pattern (510) can be embedded in the above fifth insulating layer (510).

[0048] The above vias include a first via (130) arranged in the first insulating layer (100) to electrically connect the bump (120) and the second circuit pattern (210), a second via (220) arranged in the second insulating layer (200) to electrically connect the second circuit pattern (210) and the third circuit pattern (310), a third via (320) arranged in the third insulating layer (300) to electrically connect the third circuit pattern (310) and the fourth circuit pattern (410), a fourth via (420) arranged in the fourth insulating layer (400) to electrically connect the fourth circuit pattern (410) and the fifth circuit pattern (510), and a fifth via (420) arranged in the fifth insulating layer (500) to electrically connect one end to the fifth circuit pattern (510) and the lower end to the It may include a fifth via (520) exposed to the lower surface of the fifth insulating layer (500).

[0049] The structure of the above-described build-up layer (20) is described as being implemented through five insulating layers, but is not limited thereto, and the build-up layer can be formed to have circuit patterns and vias of various layers and shapes according to the selection of a person skilled in the art.

[0050] As illustrated in FIG. 2, the first insulating layer (100) includes an upper surface and a lower surface, and a semiconductor package can be implemented by combining electronic components (not shown) on the first insulating layer (100). The electronic components can include active components or passive components, and thus can include transistors, IC semiconductor chips, capacitors, resistors, inductors, and the like, and specifically, can be semiconductor components such as CPUs, RAMs, FPGAs, and GPUs.

[0051] The circuit board (10) may include a bump (120). The electronic component may be coupled to the bump (120). The bump (120) may be disposed on the build-up layer (20). The bump (120) may be disposed on the first insulating layer (100). The bump (120) may be formed of a metal material, and for example, the material of the bump (120) may be copper (Cu).

[0052] The above bump (120) may be arranged so that at least a portion thereof is embedded within the first insulating layer (100), and another portion thereof protrudes upward through the upper surface of the first insulating layer (100).

[0053] In more detail, the bump (120) may include a penetration portion (122) disposed between the upper surface of the first insulating layer (100) and the lower surface of the first insulating layer (100), and a protrusion portion (124) disposed on the upper surface of the first insulating layer (100) and protruding upward from the penetration portion (122). The horizontal width of the penetration portion (122) may be the same as the horizontal width of the protrusion portion (124). The penetration portion (122) and the protrusion portion (124) may be formed as one body. The penetration portion (122) and the protrusion portion (124) may be formed integrally. In the past, a seed layer (not shown) was placed using electroless plating, and bumps were placed through a process of placing a penetration portion and a protrusion portion on the seed layer (not shown). However, in this case, since the grain size of the seed layer is small, cracks may occur in the seed layer due to heat generated when attaching an electronic device and / or when operating the electronic device, which may lower the reliability of the semiconductor package. However, the bump according to the present invention can significantly improve the reliability due to cracks by not placing a seed layer (not shown) between the bump and the build-up layer (100) and / or making the horizontal widths of the protrusion portion and the penetration portion of the bump the same, and can alleviate warping of the circuit board. This will be described later through the manufacturing process of the circuit board (10) illustrated in FIGS. 3 to 8.

[0054] Since the through-hole (122) and the protrusion (124) are formed integrally, the average grain size of the through-hole (122) and the average grain size of the protrusion (124) may be the same. Here, the average grain size is based on the average value of the sizes of the grains included in each region. The average grain size may be based on the average grain diameter of the grains included in the through-hole (122) and the protrusion (124).

[0055] Meanwhile, the sizes of the penetration portion (122) and the protrusion portion (124) are exemplary, and the horizontal width of the penetration portion (122) may be different from the horizontal width of the protrusion portion (124). For example, the horizontal width of the protrusion portion (124) may be larger than the horizontal width of the penetration portion (122).

[0056] The upper surface of the above bump (120) may include a flat surface (126) and a curved surface (125). The curved surface (125) may be formed in an edge region of the upper surface of the bump (120). The curved surface (125) may be formed at an edge of the upper surface of the bump (120) with the flat surface (126) as the center. The curved surface (125) may have a certain curvature. The curved surface (125) has the advantage of preventing light scattering in an AOI (Automatic Optical Inspection) inspection compared to a conventional square pillar-shaped bump.

[0057] The above bumps (120) may be provided in multiple numbers and arranged to be spaced apart from each other in the horizontal direction. For example, the above bumps (120) may be arranged two on each side with the first circuit pattern (160) as the center. The above first circuit pattern (160) may be arranged to overlap the penetration portion (122) of the bump (120) in the horizontal direction.

[0058] A protective layer (180) may be disposed on the upper surface of the build-up (20), that is, the upper surface of the first insulating layer (100). The protective layer (180) may be disposed to cover at least a portion of the side surface of the protrusion (124), which is the region of the bump (120) protruding upward from the upper surface of the first insulating layer (100). When a semiconductor element is disposed on the circuit board (10) using a material such as solder, the protective layer (180) may perform a function of preventing a short circuit between solders due to low wettability with the solder. The protective layer (180) may use a photocurable insulating material. For example, the protective layer (180) may use a solder resist.

[0059] FIG. 9 is a drawing illustrating a modified example of a circuit board according to an embodiment of the present invention. Referring to FIG. 9, the bump (120) may include a plurality of metal layers. In this case, the penetration portion (122) and the protrusion portion (124) of the above-described embodiment are defined as a first metal layer, and the plurality of metal layers may be understood to include a first metal layer and a second metal layer (190) disposed on an outer surface of the first metal layer. The second metal layer (190) may be disposed to surround the first metal layer. In FIG. 9, the second metal layer (190) is illustrated to surround the upper surface and side surfaces of the bump (120), but is not limited thereto and may be disposed only on an exposed surface exposed from the protective layer (180). That is, it can be arranged on one surface of the bump (120) on which the electronic component is to be arranged, and can have the function of improving connection reliability, and can be arranged to wrap around the other surface of the bump (120) embedded in the protective layer (180) for convenience of the process. The second metal layer (190) can be arranged to wrap around the outer surface of the protrusion (124). The lower surface of the second metal layer (190) can be in contact with the upper surface of the build-up layer (20). At least a portion of the second metal layer (190) can be embedded in the protective layer (180).

[0060] By the shape of the flat surface (126) and the curved surface (125) of the upper surface of the first metal layer, the upper surface of the second metal layer (190) can also have a curved surface with a certain curvature formed at the edge centered on the flat surface, thereby reducing the scattering of light during the AOI (Automatic Optical Inspection) inspection, thereby facilitating the AOI (Automatic Optical Inspection) inspection, and thereby making it easier to improve the yield of the circuit board.

[0061] The material of the first metal layer and the material of the second metal layer (190) may be different from each other. For example, the material of the first metal layer may be copper (Cu), and the material of the second metal layer (190) may be nickel (Ni).

[0062] According to the structure as described above, compared to the conventional technology in which the pad and the post are formed through separate processes, the penetration portion (122) and the protrusion portion (124) are formed integrally, so there is an advantage in that production efficiency can be improved.

[0063] In particular, there is an advantage in that durability can be improved by the bump structure formed as one piece, thereby complementing the vulnerability to cracks caused by the seed layer being placed between the conventional pad and post.

[0064] When explaining the manufacturing process of the above circuit board (10), first, as illustrated in FIG. 3, a sacrificial layer (40) is placed under the interposition of a metal layer (30) on one surface of a core layer (20), thereby forming a mold for manufacturing the circuit board (10). In this case, the material of the sacrificial layer (40) may be nickel (Ni), and the strength of the sacrificial layer (40) may be reinforced through the core layer (20).

[0065] Next, as illustrated in FIG. 4, the surface of the sacrificial layer (40) may be patterned. Here, the surface of the sacrificial layer (40) to be patterned may be the opposite surface to the surface facing the core layer (20). A pattern groove (42) may be implemented by surface patterning of the sacrificial layer (40). The pattern groove (42) may be formed by etching the sacrificial layer (40).

[0066] Thereafter, as illustrated in FIG. 5, the pattern groove (42) may be plated to form a metal layer on the bottom surface of the pattern groove (42). Meanwhile, in order to form the first circuit pattern (160), a metal pattern for forming the first circuit pattern (160) may be plated between the plurality of pattern grooves (42) on the surface of the sacrificial layer (40).

[0067] Meanwhile, when implementing multiple metal layers on the outer surface of the bump (120) as in the modified example of FIG. 9, multiple metal layers can be plated on the pattern groove (42) in the process of FIG. 4.

[0068] Next, as illustrated in FIG. 6, the build-up layer (20) may be formed on the surface of the sacrificial layer (40) on which the bump (120) and the first circuit pattern (160) are plated. In this case, as described above, the bump (120) and the first circuit pattern (160) may be embedded in the surface of the build-up layer (20).

[0069] Thereafter, as shown in FIG. 7, the core layer (20) is separated from the surface of the sacrificial layer (40) on which the build-up layer (20) is formed, and as shown in FIG. 8, the circuit board (10) can be manufactured through a process in which the sacrificial layer (40) is also removed.

[0070] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0071] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A build-up layer including the upper and lower surfaces; and A bump is disposed on the build-up layer and is disposed to penetrate the upper surface of the build-up layer, The above bump includes a penetration portion arranged between the upper surface of the build-up layer and the lower surface of the build-up layer and a protrusion arranged on the upper surface of the build-up layer, A circuit board in which the width of the protrusion and the width of the penetration are the same.

2. In paragraph 1, A circuit board in which the size of the crystal grains of the above-mentioned penetration portion is the same as the size of the crystal grains of the above-mentioned protrusion portion.

3. In paragraph 1, A circuit board in which the horizontal width of the protrusion is the same as the horizontal width of the penetration.

4. In paragraph 1, A circuit board in which the horizontal width of the protrusion is greater than the horizontal width of the penetration.

5. In paragraph 1, A circuit board having a top surface of the above bump including a flat surface and a curved surface having a certain curvature.

6. In paragraph 5, The above curved surface is a circuit board that forms the upper edge of the bump based on the above flat surface.

7. In paragraph 1, Including a protective layer disposed on the above build-up layer, The above protective layer is a circuit board that covers a portion of the side of the protrusion of the above bump.

8. In paragraph 1, The above bump includes a first metal layer and a second metal layer surrounding the first metal layer, A circuit board in which the second metal layer is in contact with the upper surface of the build-up layer.

9. In paragraph 8, A circuit board in which the materials of the first metal layer and the second metal layer are different.

10. In paragraph 7, The material of the first metal layer is copper (Cu), A circuit board in which the material of the second metal layer is nickel (Ni).

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