Gate drive device and electric power conversion device

Abstract

This gate drive device comprises: a constant electric current off circuit that discharges a gate of a semiconductor switching element at a constant electric current; and a mirror clamp circuit that, when the gate voltage of the semiconductor switching element becomes less than a prescribed threshold value, holds the gate voltage at a low level. The constant electric current off circuit is provided with a drive switch that is connected to the gate of the semiconductor switching element, a reference electric power supply that generates a prescribed reference voltage, and a differential amplifier that applies a drive signal to the drive switch on the basis of a comparison between the reference voltage and a voltage corresponding to the constant electric current. The threshold value for the mirror clamp circuit can be set and changed to a value that is equal to or higher than the reference voltage of the constant electric current off circuit.

Description

Gate drivers and power converters

[0001] The present invention relates to a gate driver and a power converter.

[0002] An inverter that drives a three-phase AC motor is equipped with six switching elements in three-phase upper and lower arms, and gate drive circuits for driving each switching element are also provided for each of the six arms. The upper and lower arm switching elements are turned on and off using gate drive signals from the gate drive circuit, thereby generating three-phase AC current for driving the motor. Gate drive circuits are classified into voltage-driven and constant-current-driven types. For example, the gate drive circuit described in Patent Document 1 is a constant-current-driven type, and a constant-current-off circuit is used to implement a Miller clamp function for preventing erroneous firing when the semiconductor elements are turned off.

[0003] Japanese Patent Application Publication No. 2017-188977

[0004] However, in a gate drive circuit using constant current slew rate control, the slew rate decreases just before the semiconductor element turns off, which causes problems such as increased switching loss and a longer body diode conduction time.

[0005] A gate driver according to one aspect of the present invention is a gate driver comprising: a constant current off circuit that discharges the gate of a semiconductor switching element with a constant current; and a Miller clamp circuit that holds the gate voltage of the semiconductor switching element at a low level when the gate voltage falls below a predetermined threshold, wherein the constant current off circuit has a drive switch connected to the gate of the semiconductor switching element, a reference power supply that generates a predetermined reference voltage, and a differential amplifier that provides a drive signal to the drive switch based on a comparison between a voltage corresponding to the constant current and the reference voltage, and the threshold of the Miller clamp circuit is settable to a value equal to or greater than the reference voltage of the constant current off circuit.

[0006] According to the present invention, in a gate drive circuit that performs constant current slew rate control, it is possible to reduce switching loss and shorten the body diode conduction time.

[0007] FIG. 1 is a diagram showing a schematic configuration of a power conversion device. FIG. 2 is a block diagram showing the configuration of one phase of the power conversion device. FIG. 3 is a diagram explaining a gate drive IC. FIG. 4 is a diagram showing a comparative example. FIG. 5 is a timing chart showing a turn-off operation in the comparative example. FIG. 6 is a timing chart showing a turn-off operation in the embodiment, where Vref2 = Vref1 is set. FIG. 7 is a timing chart showing a turn-off operation in the embodiment, where Vref2 > Vref1 is set. FIG. 8 is a diagram showing the basic configuration of an active dead time control unit. FIG. 9 is a diagram explaining energization of a free wheel diode during PWM control operation in the comparative example. FIG. 10 is a diagram explaining energization of a free wheel diode during PWM control operation in the embodiment. FIG. 11 is a diagram explaining a modified example.

[0008] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows one example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] 1 is a diagram showing an example of a power conversion device, and is a diagram showing a schematic configuration of a power conversion device 200 that supplies three-phase AC current to a three-phase AC motor 100. In this embodiment, the motor 100 is described as an example of a device connected to the power conversion device 200, but the device is not limited to the motor 100 and may be any device that operates by connecting to an inverter, such as a generator. The power conversion device 200 includes an inverter 201 having six power semiconductor elements T1a, T1b, T2a, T2b, T3a, and T3b that form three-phase upper and lower arms.

[0010] The power semiconductor elements T1a to T3b are, for example, MOSFETs or IGBTs. A freewheeling diode is connected in parallel to each of the power semiconductor elements T1a to T3b in the opposite direction to the current flow direction during ON operation. In the case of a MOSFET, a body diode (parasitic diode) is included in the element, and this body diode is used as the freewheeling diode.

[0011] The power conversion device 200 includes an inverter 201, a control device 202, and a gate drive device 203. The control device 202 is equipped with a microcomputer and generates a PWM (Pulse Width Modulation) signal for supplying three-phase AC current based on the magnetic pole position of the rotor of the motor 100 detected by a magnetic pole position sensor 301 and the motor current value detected by a current sensor 302. The PWM signal generated by the control device 202 is input to the gate drive device 203 provided with a gate drive IC.

[0012] The gate drive device 203 is provided with six gate drive ICs corresponding to the six power semiconductor elements T1a to T3b. The gate drive device 203 generates gate drive signals for driving each of the power semiconductor elements T1a to T3b of the inverter 201 based on the PWM signal from the control device 202, and outputs the signals to each of the power semiconductor elements T1a to T3b. As a result, the DC power from the high-voltage battery 300 is converted into AC power and supplied to the motor 100.

[0013] 2 is a block diagram showing the configuration of one phase of the power conversion device shown in FIG. 1 . The gate driver 203 includes gate driver ICs 205a and 205b corresponding to the power semiconductor elements T1a and T1b, and an active dead time control unit 204. The gate driver ICs 205a and 205b incorporate gate control functions for the power semiconductor elements T1a and T1b. The gate driver ICs 205a and 205b have the same configuration and include an ON function unit 210, a constant current OFF function unit 211, a Miller clamp circuit 212, and a gate monitor unit 213. The ON function unit 210, the constant current OFF function unit 211, the Miller clamp circuit 212, and the gate monitor unit 213 will be described in detail below.

[0014] In this embodiment, the gate driving ICs 205a and 205b basically operate based on commands from the control device 202, but the setting of the dead time related to the on / off of the power semiconductor elements T1a and T1b takes into consideration not only the commands from the control device 202 but also a signal from the active dead time control unit 204. In the example shown in Fig. 2, it is assumed that the constant current off function unit 211 and the Miller clamp circuit 212 are built into the gate driving ICs 205a and 205b, but they can also be realized by external circuits or discrete circuits.

[0015] 3 is a diagram illustrating the gate driver IC, showing the gate driver IC 205a and power semiconductor element T1a on the upper arm side. As mentioned above, the gate driver IC 205b has the same configuration as the gate driver IC 205a, and the following description will be given using the gate driver IC 205a as a representative example. In the gate driver IC 205a shown in FIG. 3, the switching element T5, such as a MOSFET, corresponds to the ON function unit 210 in FIG. 2, and the switching element T5 is connected to the gate terminal G of the power semiconductor element T1a via an ON gate resistor R1a.

[0016] The differential amplifier 221, switches SW1 and SW2, low-speed reference power supply 222, and high-speed reference power supply 223 correspond to the constant current off function unit 211 in Fig. 2, and these, together with a switching element T4a such as a MOSFET and an off-gate resistor R2a, constitute a constant current off circuit 220. The switching element T4a is connected to the gate terminal G of the power semiconductor element T1a. The low-speed reference power supply 222 and high-speed reference power supply 223, whose voltage values ​​are variable, are power supplies for setting the constant current drive reference voltage Vref1.

[0017] The switching element T6 such as a MOSFET, the differential amplifier 224, the variable reference power supply 225, the fixed reference power supply 226, and the switches SW3 and SW4 correspond to the Miller clamp circuit 212 in Fig. 2. The Miller clamp circuit 212 is connected to the gate terminal G of the power semiconductor element T1a. The variable reference power supply 225 and the multiple fixed reference power supplies 226 are power supplies for setting the Miller clamp reference voltage Vref2.

[0018] When the power semiconductor element T1a is turned on, a high-state PWM signal is input from the control device 202 to the gate drive IC 205a. As a result, the switching element T5 is turned on, a gate voltage is applied to the gate terminal G of the power semiconductor element T1a, and a gate current flows into the gate terminal G via the on-gate resistor R1a. Meanwhile, the switch SW1 of the constant current off circuit 220 is open when the PWM signal is high and is closed when the PWM signal is low. Therefore, when the power semiconductor element T1a is turned on, the switch SW1 is open, and the constant current off circuit 220 does not operate.

[0019] To turn off the power semiconductor element T1a, a low-state PWM signal is input from the control device 202 to the gate drive IC 205a. As a result, the switch SW1 of the constant current off circuit 220 is closed, and the constant current off circuit 220 is activated. Meanwhile, the switching element T5 is turned off.

[0020] A constant current drive reference voltage Vref1 is input to the non-inverting input terminal of the differential amplifier 221. The differential amplifier 221 compares the voltage of the off-gate resistor R2a with the constant current drive reference voltage Vref1 to adjust the gate voltage of the switching element T4a, thereby performing constant current control so that the current Ig1 flowing through the off-gate resistor R2a becomes Ig1=Vref1 / R2a.

[0021] 3, the voltage value of the low-speed reference power supply 222 is controlled by a Vref1(L) control signal input from the control device 202. Similarly, the voltage value of the high-speed reference power supply 223 is controlled by a Vref1(H) control signal input from the control device 202. The switch SW2 is a switch that switches the reference power supplies connected to the differential amplifier 221, and is switched based on a Vref1 switching signal input from the control device 202. In the example shown in FIG. 3, the low-speed reference power supply 222 is connected to the non-inverting input terminal of the differential amplifier 221.

[0022] 3, two types of reference power supplies 222, 223 are provided for the constant current drive reference voltage Vref1, one for a low-speed mode and one for a high-speed mode. However, three or more types of reference power supplies may be provided. The voltage values ​​of the multiple fixed reference power supplies 226 provided in the Miller clamp circuit 212 are different, and by selecting one of them, it is possible to set Vref2 > Vref1. Furthermore, as with the constant current drive reference voltage Vref1, two types of reference power supplies, one for a low-speed mode and one for a high-speed mode, may be provided for the Miller clamp reference voltage Vref2, and each may be linked to the low-speed mode and the high-speed mode of the constant current drive reference voltage Vref1.

[0023] In the Miller clamp circuit 212, a Miller clamp reference voltage Vref2 is input to the non-inverting input terminal of the differential amplifier 224. The differential amplifier 224 compares the gate voltage Vgs1 of the power semiconductor element T1a with the Miller clamp reference voltage Vref2, and turns on the switching element T6 when Vgs1<Vref2. This keeps the gate voltage Vgs1 at a low level, and the Miller clamp function operates at turn-off.

[0024] As described above, the Miller clamp circuit 212 includes one variable reference power supply 225 and multiple fixed reference power supplies 226 as power supplies for the Miller clamp reference voltage Vref2. The switch SW4 is a switch that switches the reference power supplies connected to the differential amplifier 224, and is switched based on a Vref2 switching signal input from the control device 202. In the example shown in FIG. 3, the variable reference power supply 225 is connected to the non-inverting input terminal of the differential amplifier 224.

[0025] The voltage value of the variable reference power supply 225 is controlled by either the Vref1(L) control signal or the Vref1(H) control signal, by switching the switch SW3. The switching control of the switch SW3 is performed by a Vref1 switching signal from the control device 202. That is, when the low-speed reference power supply 222 is selected as the power supply for the constant current drive reference voltage Vref1 by the Vref1 switching signal, the switch SW3 is switched so that the Vref1(L) control signal is input to the variable reference power supply 225. On the other hand, when the high-speed reference power supply 223 is selected as the power supply for the constant current drive reference voltage Vref1 by the Vref1 switching signal, the switch SW3 is switched so that the Vref1(H) control signal is input to the variable reference power supply 225. As a result, the Miller clamp reference voltage Vref2 is set to a voltage value equal to the constant current drive reference voltage Vref1 (Vref2 = Vref1).

[0026] The output signal of the differential amplifier 224 is input to the switch SW1 via a signal line (hereinafter referred to as the stop circuit) 227. Hereinafter, the signal input to the switch SW1 by the stop circuit 227 will be referred to as the Miller clamp operation signal Sm. The stop circuit 227 inverts the High / Low signal output from the differential amplifier 224 and inputs it to the switch SW1. Therefore, when the Miller clamp circuit 212 is operating, a Miller clamp operation signal Sm(L) in a Low state, indicating that the Miller clamp circuit 212 is operating, is input to the switch SW1. The switch SW1 receives both a PWM signal and a Miller clamp operation signal Sm; however, the Miller clamp operation signal Sm(L) takes priority during Miller clamp operation, and the PWM signal takes priority when the Miller clamp is not operating. This forces the switch SW1 to open during Miller clamp operation, stopping the operation of the constant current off circuit 220.

[0027] In the Miller clamp circuit 212, the variable reference power supply 225, the fixed reference power supply 226, and the switches SW3 and SW4 are provided, so that the value of the Miller clamp reference voltage Vref2 can be set to be equal to or higher than the constant current drive reference voltage Vref1. On the other hand, as described in the publicly known document 1, Vref2 is conventionally set to be smaller than Vref1.

[0028] (Turn-off operation in a comparative example) Figures 4 and 5 are diagrams illustrating a comparative example to this embodiment. Figure 4 is a diagram showing the configuration of a comparative example corresponding to the configuration of Figure 3 described above. In the gate driver IC 505a of Figure 4, the constant current drive reference voltage Vref1 of the constant current off circuit 520 and the Miller clamp reference voltage Vref2 of the Miller clamp circuit 512 are set so that Vref2 < Vref1. It is assumed here that Vref1 = 4 V and Vref2 = 2 V.

[0029] 5 is a timing chart showing the turn-off operation in the comparative example. Waveform (a) shows the PWM signal, and waveform (b) shows the Miller clamp operation signal Sm. Waveform (c) is the gate voltage Vgs1 of the power semiconductor element T1a. Of the gate current Ig of the power semiconductor element T1a, Ig1 shown in waveform (d) is the current flowing through the constant current off circuit 520, and Ig2 shown in waveform (e) is the current flowing through the Miller clamp circuit 512. In waveform (f), Vds1 is the drain-source voltage of the power semiconductor element T1a, and Id1 is the drain current of the power semiconductor element T1a.

[0030] 5, it is assumed that the power semiconductor element T1a is in the ON state at time t<t1. In this case, the input PWM signal is High, so the gate voltage Vgs1 is in the High state, the gate current Ig is zero, and the currents Ig1 and Ig2 are also zero. When the PWM signal changes from High to Low at time t1, an inverted signal of High is input to the switch SW1. As a result, the switch SW1 is closed, and the constant current off circuit 520 is activated, and constant current control is performed so that the current Ig1 flowing through the off-gate resistor R2a becomes Ig1=Vref1 / R2a.

[0031] If Vref1 is set to 4V, when the gate voltage Vgs1 of the power semiconductor device T1a falls below Vref1 (=4V) at time t2, the constant current off circuit 520 is no longer able to pass a constant current (=Vref1 / R2a). At this time, the off-gate resistor R2a limits the current Ig1 to Ig1 = Vgs1 / R2a, extending the turn-off time. If the gate voltage Vgs1 further decreases and falls below Vref2 (=2V) at time t3, the Miller clamp circuit 512 operates, causing the current Ig2 to flow through the Miller clamp circuit 512. When the Miller clamp circuit 512 operates at time t3, the Miller clamp operation signal Sm changes from high to low, opening the switch SW1 and stopping the operation of the constant current off circuit 520. This completes the turn-off operation of the power semiconductor device T1a.

[0032] (Turn-Off Operation in the Embodiment) As described above, in the embodiment, the Miller clamp reference voltage Vref2 can be set so that Vref2≧Vref1. FIG. 6 shows the turn-off operation when Vref2=Vref1 is set in the embodiment. This corresponds to the case where the variable reference power supply 225 is selected by the switch SW4 as shown in FIG. 3. FIG. 7 shows the turn-off operation when Vref2>Vref1 is set in the embodiment. This corresponds to the case where the fixed reference power supply 226 having a value greater than the constant current drive reference voltage Vref1 is selected by the switch SW4 in FIG. 3.

[0033] First, the turn-off operation in the case of FIG. 6 where Vref2 = Vref1 (= 4 V) will be described. Also in FIG. 6, assume that the power semiconductor device T1a is in the on state at time t<t1. In this case, the input PWM signal is high, so the gate voltage Vgs1 is high, the gate current Ig is zero, and the currents Ig1 and Ig2 are also zero. When the PWM signal changes from high to low at time t1, the switch SW1 closes, activating the constant current off circuit 220, and constant current control is performed so that the current Ig1 flowing through the off-gate resistor R2a becomes Ig1 = Vref1 / R2a.

[0034] When the gate voltage Vgs1 of the power semiconductor element T1a drops below 4 V at time t2, the Miller clamp circuit 212 operates because Vref2 = Vref1 = 4 V. As described above, when the gate voltage Vgs1 of the power semiconductor element T1a falls below Vref1 (= 4 V), the constant current off circuit 520 is no longer able to pass a constant current (= Vref1 / R2a). However, when the gate voltage Vgs1 falls below 4 V, the Miller clamp circuit 212 operates, and the current Ig2 flows through the Miller clamp circuit 212, allowing the gate voltage Vgs1 to be quickly lowered, thereby shortening the turn-off time compared to the case of FIG. 5.

[0035] Note that shortening the turn-off time increases the drain-source voltage Vds1 surge voltage, as shown in waveform (f). However, in the region where the drain current Id1 is low, the surge voltage that occurs is low to begin with, so the margin for the Vds1 surge is large. In the present invention, this margin is utilized to shorten the turn-off time.

[0036] When Miller clamp operation begins at time t2, a low-state Miller clamp operation signal Sm(L) is input to switch SW1 via the stop circuit 227 in FIG. 3 . As a result, switch SW1 opens, and the constant current off circuit 520 stops operating. This allows for a smooth start of the next turn-on operation. For example, if the stop circuit 227 does not have the function of opening switch SW1, and the operation delay of the constant current off circuit 520 is greater than the operation delay of the on-side circuit including switching element T5, the start of the next turn-on operation may be delayed. That is, when switching element T5 turns on, switching element T4a is also in the on state due to the operation delay of the constant current off circuit 520, resulting in a slow start of the turn-on operation.

[0037] Next, the turn-off operation in the case of FIG. 7 where Vref2 > Vref1 is described. Here, the constant current drive reference voltage Vref1 is set to 4 V, the same as in FIG. 6, and the Miller clamp reference voltage Vref2 is set to 6 V. In this case, the gate voltage Vgs1 falls below the Miller clamp reference voltage Vref2 (= 6 V) at time t21 (<t2), before time t2 when the gate voltage Vgs1 reaches the constant current drive reference voltage Vref1 (= 4 V). At time t21, the Miller clamp circuit 212 begins operating, causing the current Ig2 to flow. This allows the gate voltage Vgs1 to be quickly lowered, further shortening the turn-off time compared to the case of FIG. 6. However, the surge voltage of the drain-source voltage Vds1 is higher than in the case of FIG. 6.

[0038] When the drain current (main current) Id1 of the power semiconductor element T1a is small, the turn-off time may be particularly long due to the characteristics of the semiconductor element. In this case, setting the Miller clamp reference voltage Vref2 higher than the constant current drive reference voltage Vref1 can further reduce the turn-off time. Although the surge voltage of the drain-source voltage Vds1 increases compared to when Vref2 = Vref1, this is not a problem when the drain current Id1 is small, for example, because the surge voltage margin is large.

[0039] (Method of Setting Vref1 and Vref2) In this embodiment, as shown in FIG. 3, the Miller clamp reference voltage Vref2 can be set to Vref2≧Vref1. By setting Vref2≧Vref1 according to the magnitude of the drain current Id1, it is possible to reduce switching loss. Here, an example of a method of setting Vref1 and Vref2 will be described. Note that the following description is just an example, and an optimal design is required depending on the characteristics of the power semiconductor elements, the inductance value of the main circuit, etc.

[0040] First, three ranges for the magnitude of the drain current Id1 are determined in advance: small, medium, and large. For example, 0 to 50 A is set as small current, 50 to 500 A as medium current, and 500 to 1000 A as large current. When the drain current Id1 is small, the Vds1 surge generated is small. Therefore, by setting Vref2 > Vref1 and shortening the switching time, the dead time and loss reduction effects are maximized. The constant current drive reference voltage Vref1 can be set sufficiently high relative to the gate threshold voltage Vth of the power semiconductor element, so it is set to a fixed value. For example, Vref1 = 5 V (fixed) and Vref2 = 5.5 V (fixed).

[0041] When the drain current Id1 is medium, the constant current drive reference voltage Vref1 varies depending on the magnitude of the drain current Id1 through slew rate control. The load current command value is determined within the control device 202, and the constant current drive reference voltage Vref1 is also controlled as needed within the control device 202 based on that information. Therefore, by linking the Miller clamp reference voltage Vref2 with the constant current drive reference voltage Vref1, it is possible to shorten the dead time. For example, the settings are Vref1 = 4 to 5 V (variable) and Vref2 = Vref1 (linked).

[0042] When the drain current Id1 is large, the Vds1 surge is large. Therefore, if the Miller clamp reference voltage Vref2 is significantly higher than the gate threshold voltage Vth of the power semiconductor element, the Vds1 surge will also be excessive, potentially destroying the power semiconductor element. Therefore, the Miller clamp reference voltage Vref2 is fixed to a voltage sufficiently lower than the gate threshold voltage Vth of the power semiconductor element. For example, Vref1 is set to 4 to 5 V (variable) and Vref2 is set to 3.5 V (fixed). The constant current drive reference voltage Vref1 may be controlled by the control device 202 according to the load current, as in the case of a medium current, or it may be set to a fixed value with a margin. Because the Vds1 surge also depends on the junction temperature of the power semiconductor element, the control device 202 sets the constant current drive reference voltage Vref1 taking into account temperature monitor information.

[0043] (Explanation of Active Dead Time Control) FIG. 8 is a diagram showing the most basic configuration of the active dead time control unit 204 shown in FIG. 2. The INA terminal and INB terminal are input terminals for PWM signals, with the INA terminal being high active and the INB terminal being low active. The INA terminal and the INB terminal form an AND input, and when both are active, the gate output becomes high. The OSFB terminal, which outputs the gate state as feedback, corresponds to the gate monitor unit 213 shown in FIG. 2, and outputs the result of comparing the monitored gate voltage with the active dead time control threshold (hereinafter referred to as the active dead time threshold) as the OSFB signal. The OSFB terminal outputs high when the gate voltage is equal to or greater than the active dead time threshold, and low when it is below the active dead time threshold.

[0044] In the upper arm gate drive IC 205a, the PWM signal (upper arm) from the control device 202 is input to the INA terminal, and the OSFB signal from the lower arm gate drive IC 205b is input to the INB terminal. In the lower arm gate drive IC 205b, the PWM signal (lower arm) from the control device 202 is input to the INA terminal, and the OSFB signal from the upper arm gate drive IC 205a is input to the INB terminal. The OSFB signals of the upper and lower arms are also input to the control device 202. This circuit configuration, in which the OSFB signal of one arm is input to the INB terminal of the opposite arm, corresponds to the active dead time control unit 204.

[0045] Because the OSFB signal of the opposing arm is input to the INB terminal of the own arm, even if the PWM signal input to the INA terminal is High, the turn-on operation of the power semiconductor element on the own arm will not be initiated unless the OSFB signal on the opposing arm input to the INB terminal is Low. In other words, even if the PWM signal on the own arm from the control device 202 is High and the PWM signal on the opposing arm is Low, the turn-on operation of the power semiconductor element on the own arm will not be initiated unless the gate voltage of the power semiconductor element on the opposing arm falls below the active dead time threshold and the OSFB signal input to the INB terminal becomes Low. This makes it possible to prevent short circuits between the upper and lower ends of the power semiconductor elements T1a and T1b.

[0046] (Explanation of Body Diode Operation: Comparative Example) FIG. 9 is a diagram illustrating the conduction of a freewheeling diode (body diode) during PWM control operation. FIG. 9 shows the comparative example shown in FIGS. 4 and 5 with an active dead time control unit 204. In FIG. 9, waveform (a) shows the PWM signal of the upper arm, and waveform (b) shows the gate voltage Vgs1 of the power semiconductor element T1a. In waveform (c), Id1 is the drain current of the power semiconductor element T1a, and Vds1 is the drain-source voltage of the power semiconductor element T1a. Waveform (d) shows the PWM signal of the lower arm, and waveform (e) shows the gate voltage Vgs2 of the power semiconductor element T1b. In waveform (f), Vds2 is the drain-source voltage of the power semiconductor element T1b, and Id2 is the drain current of the power semiconductor element T1b.

[0047] When the power semiconductor elements T1a and T1b are operated by PWM control, in the freewheeling mode of the load inductor, a freewheeling current flows through the freewheeling diode (body diode) D1 of the power semiconductor element T1a (see FIG. 8) or the freewheeling diode (body diode) D2 of the power semiconductor element T1b (see FIG. 8). Waveforms (a), (b), and (c) in FIG. 9 are the same as waveforms (a), (b), and (f) in FIG. 5. As shown in waveform (d), the PWM signal of the lower arm rises from low to high at time t31. That is, the dead time Δtd set by the software of the control device 202 is Δtd = t31 - t1.

[0048] 9, the active dead time threshold is set to 2 V, and when the monitored gate voltage Vgs1 falls below the active dead time threshold (= 2 V), the OSFB signal output from the OSFB terminal on the upper arm changes from high to low. This OSFB signal is input to the INB terminal on the lower arm via the active dead time control unit 204. The time at which the low OSFB signal is input to the INB terminal is (t3 + Δt), and is input with a delay of a predetermined time Δt. This predetermined time (delay time) Δt is generated by active dead time control as a safety margin for the dead time, and although not shown in FIG. 8, the active dead time control unit 204 is provided with a delay circuit or the like.

[0049] When the PWM signal of the upper arm changes from high to low at time t1, the switch SW1 closes and the constant current off circuit 520 starts operating. When the constant current off circuit 520 starts operating and the drain current Id1 and drain-source voltage Vds1 of the power semiconductor element T1a change as shown in waveform (c), the drain current Id2 and drain-source voltage Vds12 of the power semiconductor element T1b change accordingly as shown in waveform (f). At time 31, the PWM signal of the lower arm changes from low to high, but because the OSFB signal input from the upper arm side to the INB terminal of the lower arm side is high, the gate output of the gate drive IC 505b remains low and the power semiconductor element T1b also remains off.

[0050] When the gate voltage Vgs1 of the power semiconductor element T1a falls below Vref2 (=2 V) at time t3, the Miller clamp circuit 512 operates, causing the gate voltage Vgs1 to drop rapidly. Furthermore, when a predetermined time Δt has elapsed since the gate voltage Vgs1 fell below the active dead time threshold (=2 V) at time t3, the OSFB signal input to the INB terminal on the lower arm side changes from High to Low. As a result, the gate output of the gate drive IC 505b changes to High, starting the turn-on operation of the lower arm power semiconductor element T1b, and the gate voltage Vgs2 of the power semiconductor element T1b rises, as shown in waveform (e).

[0051] At time (t3+Δt), the gate voltage Vgs2 begins to rise, and when the gate voltage Vgs2 reaches the gate threshold voltage Vth at time t32, the power semiconductor element T1b on the lower arm side turns on. Therefore, in the freewheeling mode of the load inductor, a freewheeling current flows through the body diode D1 of the power semiconductor element T1b during period A from time t1 to time t32, and after time t32, current flows through the MOSFET (IGBT) instead of the body diode D1. The body diode D1 generally has a relatively large conduction loss, and if the current is applied for a long time, the element may deteriorate.

[0052] Note that if the timing (time t31) when the PWM signal of the lower arm changes from low to high occurs between time t1 and time (t3+Δt), the time when the gate voltage Vgs2 on the lower arm side starts to rise is always time (t3+Δt). In other words, the active dead time (= t3 - t1 + Δt) becomes the actual dead time. On the other hand, if the timing (time t31) when the PWM signal of the lower arm changes from low to high occurs later than time (t3+Δt), the dead time Δtd (= t31 - t1) set by the software of the control device 202 becomes the actual dead time. In other words, in this case, there is no opportunity for active dead time control to operate.

[0053] (Explanation of Body Diode Operation: Embodiment) FIG. 10 is a diagram illustrating energization of a freewheeling diode (body diode) in an embodiment. Waveforms (a) to (f) shown in FIG. 10 correspond to waveforms (a) to (f) of the signals shown in FIG. 9. FIG. 10 shows an example where Vref1 = Vref2 = 4 V, and it is also assumed here that the timing at which the gate voltage Vgs2 on the lower arm rises under active dead time control is when a predetermined time Δt has elapsed since the gate voltage Vgs1 on the upper arm fell below the active dead time threshold (= 2 V).

[0054] 10, when the gate voltage Vgs1 falls below 4 V at time t2, the Miller clamp circuit 512 operates, and the turn-off time toff1 of the power semiconductor device T1a is shortened compared to the case of FIG. 9. Then, when the gate voltage Vgs1 rapidly decreases after time t2 and falls below the active dead time threshold (= 2 V) at time t33, the gate voltage Vgs2 on the lower arm rises after a predetermined time Δt has elapsed. In other words, the active dead time (= t33 - t1 + Δt) is the actual dead time.

[0055] As described above, in the present embodiment shown in FIG. 10, the turn-off time toff1 is shorter than in the case of FIG. 9, and the period from time t1 until the gate voltage Vgs1 falls below the active dead time threshold (=2 V) is shorter, so that the rise of the gate voltage Vgs2 on the lower arm side begins at an earlier timing. As a result, the conduction period A of the body diode D1 of the power semiconductor element T1b is also shorter than in the case of FIG. 9. Note that even in a configuration that does not use active dead time control, the same effect can be obtained by shortening the dead time command value on the control device 202 side by the amount that the turn-off time toff1 is shortened.

[0056] (Modification) In the configuration shown in Fig. 3, the constant current drive reference voltage Vref1 is switched by hardware, but the present invention can also be applied to a configuration in which the constant current drive reference voltage Vref1 is switched by software. Fig. 11 shows a modification in which the configuration shown in Fig. 3 is changed to a software system. Only a variable reference power supply 230 is provided as the power supply for the constant current drive reference voltage Vref1, and the value of the constant current drive reference voltage Vref1 is controlled by a Vref1 switching / control signal from the control device 202. The software in the control device 202 determines in advance the voltage ranges for high speed and low speed, and the switching between high speed and low speed is performed by software, as in the case of Fig. 3.

[0057] The Vref1 switching control signal from the control device 202 is also input to the variable reference power supply 225 of the Miller clamp circuit 212. The voltage value of the variable reference power supply 225 (Miller clamp reference voltage Vref2) is controlled in conjunction with the switching between high speed and low speed of the constant current drive reference voltage Vref1. Switching between the variable reference power supply 225 and the fixed reference power supply 226 is performed by opening and closing the switch SW4 using the Vref2 switching signal from the control device 202. In this method, the high speed and low speed switching of the constant current drive reference voltage Vref1 is performed by controlling the variable reference power supply 230 using software or the like, which may result in slower responsiveness than when switching between the low speed reference power supply 222 and the high speed reference power supply 223 using hardware.

[0058] 11, the Miller clamp reference voltage Vref2 is configured to include a variable reference power supply 225 and multiple fixed reference power supplies 226, but it may also be configured to include only the variable reference power supply 225. In that case, the variable reference power supply 225 is controlled by a Vref2 control signal from the control device 202 instead of the Vref1 switching / control signal, and the voltage is changed by control linked to the constant current drive reference voltage Vref1 and control other than that linked to it.

[0059] According to the embodiment and modified examples of the present invention described above, the following advantageous effects are achieved.

[0060] (1) As shown in FIGS. 1 to 3, the gate driver 203 includes a constant current off circuit 220 that discharges a constant current from the gate of a power semiconductor element T1a, which is a semiconductor switching element, and a Miller clamp circuit 212 that holds the gate voltage Vgs1 of the power semiconductor element T1a at a low level when the gate voltage Vgs1 falls below a predetermined threshold (Miller clamp reference voltage Vref2). The constant current off circuit 220 has a drive switch (switching element T4a) connected to the gate of the power semiconductor element T1a, reference power supplies (low speed reference power supply 222 and high speed reference power supply 223) that generate a predetermined reference voltage (constant current drive reference voltage Vref1), and a differential amplifier 221 that provides a drive signal to the constant current drive reference voltage Vref1 based on a comparison between the voltage of the off gate resistor R2a corresponding to the constant current during discharge and the constant current drive reference voltage Vref1, and the Miller clamp reference voltage Vref2 of the Miller clamp circuit 212 can be set to a value equal to or higher than the constant current drive reference voltage Vref1 of the constant current off circuit 220.

[0061] By configuring the Miller clamp reference voltage Vref2 to be settable such that Vref2≧Vref1, the Miller clamp reference voltage Vref2 can be increased when the drain current Id1 of the power semiconductor element T1a is low. Increasing the Miller clamp reference voltage Vref2 allows the Miller clamp operation to occur at an earlier stage during the turn-off operation, thereby shortening the turn-off time. As a result, turn-off loss (switching loss) can be reduced. Furthermore, shortening the turn-off time allows the dead time period to be shortened accordingly. By shortening the dead time period, the conduction period A of the body diode of the power semiconductor element T1a can also be shortened, thereby suppressing conduction loss and body diode degradation due to the body diode.

[0062] (2) In (1) above, as shown in Figure 6 etc., the Miller clamp reference voltage Vref2 of the Miller clamp circuit 212 is set to a value equal to the constant current drive reference voltage Vref1 of the constant current off circuit 220. By setting Vref1 = Vref2, the Miller clamp operation starts simultaneously with the end of constant current off, and the increase in Vds surge can be minimized while shortening the turn-off time.

[0063] Furthermore, since the Vds surge increases when the drain current Id is large, the control device 202 controls the Vds surge to fall within the rated value of the power semiconductor element by lowering the constant current drive reference voltage Vref1 when the drain current Id command value is large. Conversely, since the Vds surge is low when the drain current Id is small, the control device 202 controls the Vds surge to fall within the rated value of the power semiconductor element by raising the constant current drive reference voltage Vref1 to increase the switching speed and enhance the loss reduction effect. When the constant current drive reference voltage Vref1 is changed in accordance with the drain current Id in this way, the Miller clamp reference voltage Vref2 also changes in conjunction with the constant current drive reference voltage Vref1, i.e., Vref1 = Vref2. This eliminates the need to set the Miller clamp reference voltage Vref2 separately, thereby reducing the number of design steps.

[0064] (3) In the above (1), as shown in FIGS. 2, 8 to 10, etc., a constant current off circuit 220 and a Miller clamp circuit 212 are provided for each of the semiconductor switching element (power semiconductor element T1a) and the paired arm semiconductor switching element (power semiconductor element T1b) connected in series to the power semiconductor element T1a, and an active dead time control unit 204 is further provided which turns on the power semiconductor element T1b a predetermined period (predetermined time Δt) after the gate voltage of the power semiconductor element T1a falls below a threshold value (Miller clamp reference voltage Vref2).

[0065] As shown in Fig. 8, by providing an active dead time control unit 204 that inputs the OSFB signal of the opposing arm to the INB terminal of the own arm, it is possible to instantly turn on the own arm when the gate voltage of the opposing arm falls below the active dead time threshold. Furthermore, as shown in Fig. 10, in a situation where the software-based dead time setting is relatively short and the active dead time is active, setting Vref2 ≧ Vref1 can shorten the period A during which a return current flows through the body diode compared to the case where Vref2 < Vref1 shown in Fig. 9. As a result, the conduction time of the body diode can be shortened, and conduction loss due to the body diode and degradation of the body diode element can be suppressed.

[0066] (4) In the above (1), as shown in FIG. 3 and other figures, a stop circuit 227 is further provided that stops the operation of the constant current off circuit 220 when the Miller clamp circuit 212 is operating. In this way, by stopping the operation of the constant current off circuit 220 when the Miller clamp circuit is operating, the operation of the constant current off circuit 220 is stopped at the time of the next turn-on, allowing the turn-on operation to start smoothly and improving the turn-on responsiveness. For example, without the stop circuit 227, the constant current off circuit would stop operating simultaneously with the start of turn-on. Therefore, for example, if the operation delay of the constant current off circuit 220 is greater than the delay in the turn-on operation, the start of turn-on may be delayed.

[0067] (5) In (1) above, as shown in FIG. 3 and other figures, the reference power supply can generate multiple constant current drive reference voltages Vref1 with different voltage values. This allows for selecting the optimal constant current drive reference voltage Vref1 depending on the drain current Ids, junction temperature, etc., and changing the slew rate, thereby improving the trade-off between Vds surge and turn-off loss (switching loss). The constant current drive reference voltage Vref1 can be changed by providing multiple power supplies in hardware and switching them using a switch, or by controlling a variable voltage power supply in software.

[0068] (6) In the above (1), as shown in Fig. 3 etc., the threshold value of the Miller clamp circuit 212 (Miller clamp reference voltage Vref2) can be set to a plurality of different values ​​equal to or greater than the reference voltage (constant current drive reference voltage Vref1). In the example shown in Fig. 3, a variable reference power supply 225 and a plurality of fixed reference power supplies 226 are provided as power supplies for generating the Miller clamp reference voltage Vref2.

[0069] By allowing the Miller clamp reference voltage Vref2 to be set to multiple different values, even when the voltage value of the constant current drive reference voltage Vref1 is changed, the Miller clamp reference voltage Vref2 can be set so that Vref2 ≥ Vref1 according to the changed value of the constant current drive reference voltage Vref1. For example, when the drain current Ids is small, the turn-off time may be particularly long due to the characteristics of the power semiconductor device. In this case, setting the Miller clamp reference voltage Vref2 higher than the constant current drive reference voltage Vref1 can further reduce the turn-off time. Note that, although setting the Miller clamp reference voltage Vref2 to Vref2 > Vref1 increases the Vds surge, the impact is minimal when the drain current Ids is small because the Vds surge margin is large.

[0070] (7) As shown in Figures 1 to 3, etc., the power conversion device 200 includes the gate drive device 203 described in (1) to (6) above, semiconductor switching elements (power semiconductor elements T1a to T3a, T1b to T3b) that are turned on and off by the gate drive device 203, and a control device 202 that inputs control commands to the gate drive device 203 to turn on and off the power semiconductor elements T1a to T3a, T1b to T3b.

[0071] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0072] 100...motor, 200...power conversion device, 201...inverter, 202...control device, 203...gate drive device, 204...active dead time control unit, 205a, 205b...gate drive IC, 210...on function unit, 211...constant current off function unit, 212...miller clamp circuit, 213...gate monitor unit, 220...constant current off circuit, 221, 224...differential amplifier, 222...low speed reference power supply, 223...high speed reference power supply, 225, 230...variable reference power supply, 226...fixed reference power supply, 227...stop circuit, D1, D2...freewheeling diode (body diode), T1b, T2a, T2b, T3a, T3b...power semiconductor element, Vref1...constant current drive reference voltage, Vref2...miller clamp reference voltage

Claims

1. A gate driver comprising: a constant current off circuit that discharges the gate of a semiconductor switching element with a constant current; and a Miller clamp circuit that holds the gate voltage of the semiconductor switching element at a low level when the gate voltage falls below a predetermined threshold, wherein the constant current off circuit has: a drive switch connected to the gate of the semiconductor switching element; a reference power supply that generates a predetermined reference voltage; and a differential amplifier that provides a drive signal to the drive switch based on a comparison between a voltage corresponding to the constant current and the reference voltage, and wherein the threshold of the Miller clamp circuit is settable to a value equal to or greater than the reference voltage of the constant current off circuit.

2. A gate driver circuit according to claim 1, wherein the threshold of the Miller clamp circuit is set to a value equal to the reference voltage of the constant current off circuit.

3. A gate driver according to claim 1, comprising the constant current off circuit and the Miller clamp circuit for each of the semiconductor switching elements and the paired arm semiconductor switching elements connected in series to the semiconductor switching elements, and further comprising an active dead time control section that turns on the paired arm semiconductor switching element a predetermined period after the gate voltage of the semiconductor switching element falls below the threshold.

4. The gate driver according to claim 1, further comprising a stop circuit that stops operation of the constant current off circuit when the Miller clamp circuit is in operation.

5. A gate driver according to claim 1, wherein the reference power supply is capable of generating a plurality of reference voltages having different voltage values.

6. A gate driver according to claim 5, wherein the threshold of the Miller clamp circuit is configurable to a plurality of different values ​​equal to or greater than the reference voltage.

7. A power conversion device comprising: a gate drive device according to any one of claims 1 to 6; a semiconductor switching element that is turned on and off by said gate drive device; and a control device that inputs a control command to said gate drive device to turn on and off said semiconductor switching element.

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