Easily integrable high-voltage-withstanding enhancement-mode gallium nitride device

Abstract

An easily integrable high-voltage-withstanding enhancement-mode gallium nitride device, wherein a nucleation layer, a buffer layer and a GaN layer are arranged on a second silicon substrate; a p-GaN region and an AlGaN barrier layer are arranged on the GaN layer; a first n-GaN region is arranged in the p-GaN region; a first metal electrode is connected to the first n-GaN region; a first SiO2 oxide layer is arranged on the p-GaN region; a second metal electrode is arranged on the first SiO2 oxide layer; the AlGaN barrier layer is provided with a fourth metal electrode, and the AlGaN barrier layer is provided with a second n-GaN region and a second SiO2 oxide layer; the second SiO2 oxide layer is provided with a third metal electrode; the second n-GaN region divides the AlGaN barrier layer into first and second AlGaN barrier layers; the second SiO2 oxide layer and the third metal electrode are located between the second n-GaN region and a fourth metal electrode; and the third metal electrode is connected to the first metal electrode. The second n-GaN region and the third metal electrode alleviate the edge effect.

Description

A high-voltage enhancement-mode gallium nitride device that is easy to integrate Technical Field

[0001] The present invention belongs to the field of power semiconductor devices, and in particular relates to a high-voltage enhanced gallium nitride device that is easy to integrate. Background Art

[0002] Gallium nitride (GaN) belongs to the category of third-generation semiconductors. It has gradually come into the public eye due to its wide bandgap, high breakdown voltage, and high electron saturation velocity. Among GaN-based transistors, HEMTs (High Electron Mobility Transistors) are increasingly being used in various circuits due to the high mobility brought about by the two-dimensional electron gas (2DEG) generated by the polarization effect.

[0003] In power electronics, enhancement-mode (also known as normally-on) devices can significantly improve device reliability because they can remain in the off state at zero bias. Depletion-mode devices, on the other hand, remain in the on state even when the gate is at zero bias, significantly impacting the reliability of power circuits. Furthermore, in the field of power devices, withstand voltage is a key factor in evaluating a device's performance, so designing a device with a high withstand voltage is essential.

[0004] The breakdown voltage of a GaN HEMT is related to the gate-drain distance. When the gate-drain distance is small, increasing it can improve the device's breakdown voltage. However, as the gate-drain distance increases, the rate of increase in the device's breakdown voltage gradually decreases, meaning the device's breakdown voltage exhibits diminishing returns. Existing GaN HEMTs improve their breakdown voltage by changing the peak electric field position between the device's gate and drain. A more uniform electric field distribution between the gate and drain prevents the high peak electric field that can easily cause device breakdown, improving the device's breakdown voltage. For example, CN111403480A introduces a T-shaped gate field plate and p-GaN structure. The p-GaN region influences the gate electric field distribution. Combined with the T-shaped gate field plate, the electric field peak is shifted below the gate field plate, improving the device's breakdown voltage. For example, CN113035935B introduces an AlGaN barrier layer with a gradient thickness from the gate to the drain, thereby altering the two-dimensional electron gas concentration and mitigating the electric field peak, resulting in a device with high breakdown voltage. However, these devices operate within a fixed gate-to-drain distance. As the gate-to-drain distance increases, they prematurely experience diminishing returns, limiting their potential improvement in device withstand voltage. Therefore, designing an enhancement-mode device that is easy to integrate, delays the onset of diminishing returns, and offers a high withstand voltage threshold is crucial.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to design a high-voltage-withstand-voltage enhancement-mode gallium nitride device that is easy to integrate and can alleviate the marginal decreasing effect of the device's voltage-withstand-voltage.

[0007] The technical solution adopted in the present invention is as follows:

[0008] A high-voltage enhancement-mode gallium nitride device that is easy to integrate includes: a second silicon substrate, a nucleation layer, a buffer layer, and a GaN layer arranged from bottom to top on the second silicon substrate, a p-GaN region and an AlGaN barrier layer arranged on the GaN layer, a first n-GaN region arranged within the p-GaN region, a first metal electrode connected to the n-GaN region, a first SiO2 oxide layer arranged on the p-GaN region, and both ends of the first SiO2 oxide layer extending to the n-GaN region and the AlGaN barrier layer respectively, and a second metal electrode arranged on the first SiO2 oxide layer and serving as the gate of the device. A fourth metal electrode is provided on the AlGaN barrier layer and serves as the drain of the device, a second n-GaN region and a second SiO2 oxide layer are provided on the AlGaN barrier layer, a third metal electrode is provided on the second SiO2 oxide layer, the second n-GaN region extends deep into the GaN layer and divides the AlGaN barrier layer into a first AlGaN barrier layer and a second AlGaN barrier layer, the second SiO2 oxide layer and the third metal electrode are located between the second n-GaN region and the fourth metal electrode, and the third metal electrode is connected to the first metal electrode and serves as the source of the device.

[0009] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0010] (1) The second n-GaN region and the third metal electrode of the present invention alleviate the marginal decreasing effect of the device's withstand voltage and improve the withstand voltage threshold. Specifically, the present invention introduces the second n-GaN region and the third metal electrode, so that when the device is under withstand voltage, the depletion region starts to widen from the second metal electrode. When widening to the second n-GaN region, the second n-GaN region slows down the depletion rate, the induced potential of the second n-GaN region gradually increases, and the induced potential difference between the second n-GaN region and the third metal electrode assists the second AlGaN barrier layer in improving the energy band. When the energy band of the second AlGaN barrier layer is higher than the Fermi level of the GaN layer, the 2DEG channel region generated by depletion polarization, the depletion layer restarts to widen from the second n-GaN region. For example, referring to Figure 1, the depletion layer restarts to widen from the second n-GaN region to the right side of the figure, which alleviates the marginal decreasing effect of the device's withstand voltage, increases the withstand voltage threshold of the device, and further improves the withstand voltage level of the device.

[0011] (2) Enhancement-mode devices. By etching the first n-GaN region, p-GaN region, and first AlGaN barrier layer on the gallium nitride device, the polarization effect formed by AlGaN and GaN is weakened in the area below the second metal electrode and the first SiO2 oxide layer where the grooves are cut, and the energy band of GaN is increased. When the energy band is increased to the Fermi level of the GaN layer, the 2DEG in the channel region is depleted, achieving the enhancement mode of the grooved portion. Moreover, when the gate voltage of the device drops from the threshold, the depletion region below the grooved portion will diffuse laterally due to the smaller width of the ungrooved portion, thereby achieving the enhancement mode of the entire device. Enhancement-mode devices do not have the problem of device failure due to overshoot in depletion-mode devices, thereby improving the reliability of the designed device.

[0012] (3) Ease of integration. With the continuous development of technology, power devices are gradually moving towards integration. The device of the present invention is integrated on an SOI substrate, which enables the high-voltage enhanced gallium nitride device to be integrated with other devices, thereby improving the device's integration level.

[0013] (4) Increase the device operating temperature. The introduced insulating SiO2 layer can hinder the movement of high-temperature electrons from the first silicon substrate to the buffer layer, thereby increasing the device's operating temperature and enabling the device to operate under ultra-high temperature conditions.

[0014] (5) Eliminate crosstalk between devices. When multiple devices work together, they may interfere with each other due to the contact between substrates. The insulating SiO2 layer in the structure of the present invention can separate the designed device from other devices, eliminating substrate crosstalk between multiple devices in integrated circuit applications.

[0015] (6) Alleviating dynamic resistance degradation. During the operation of a GaN device, because the substrate is not connected to the source, the substrate voltage activates traps in the buffer layer, causing dynamic resistance degradation in the GaN device. The present invention can alleviate the dynamic resistance degradation caused by substrate floating by drilling a hole from the first metal electrode to the second silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] FIG1 is a structural diagram of a high-voltage enhancement-mode gallium nitride device that is easy to integrate provided by the present invention;

[0018] FIG2 is a schematic cross-sectional view of L1 and L2 along the X-axis in the structural diagram of the present invention, wherein FIGa is a schematic cross-sectional view of L1 along the X-axis, and FIGb is a schematic cross-sectional view of L2 along the X-axis;

[0019] FIG3 is a schematic cross-sectional view of L3, L4, L5, and L6 along the Y axis in the structure diagram of the present invention, wherein FIGa is a schematic cross-sectional view of L3 along the Y axis, FIGb is a schematic cross-sectional view of L4 along the Y axis, FIGc is a schematic cross-sectional view of L5 along the Y axis, and FIGd is a schematic cross-sectional view of L6 along the Y axis;

[0020] FIG4 is a flow chart of the present invention for achieving depletion layer broadening of the overall enhanced device. DETAILED DESCRIPTION

[0021] In order to make the purpose, content, and advantages of the present invention clearer, the specific embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0022] A high-voltage enhancement-mode gallium nitride device that is easy to integrate includes: a second silicon substrate 3, a nucleation layer 4, a buffer layer 5, and a GaN layer 6 are arranged from bottom to top on the second silicon substrate 3, a p-GaN region 7 and an AlGaN barrier layer are provided on the GaN layer 6, a first n-GaN region 8 is provided within the p-GaN region 7, a first metal electrode 14 is connected to the first n-GaN region 8, a first SiO2 oxide layer 12 is provided on the p-GaN region 7, and both ends of the first SiO2 oxide layer 12 extend to the first n-GaN region 8 and the AlGaN barrier layer 10 respectively, and a second metal electrode 15 is provided on the first SiO2 oxide layer 12 and serves as the gate of the device. A fourth metal electrode 17 is provided on the AlGaN barrier layer and serves as the drain of the device. A second n-GaN region 9 and a second SiO2 oxide layer 13 are provided on the AlGaN barrier layer. A third metal electrode 16 is provided on the second SiO2 oxide layer 13. The second n-GaN region 9 extends deep into the GaN layer 6 and divides the AlGaN barrier layer into a first AlGaN barrier layer 10 and a second AlGaN barrier layer 11. The second SiO2 oxide layer 13 and the third metal electrode 16 are located between the second n-GaN region 9 and the fourth metal electrode 17. The third metal electrode 16 is connected to the first metal electrode 14 and serves as the source of the device.

[0023] In this embodiment:

[0024] An insulating SiO2 layer 2 is provided below the second silicon substrate 3, and a first silicon substrate 1 is provided below the insulating SiO2 layer 2; a groove is provided on the p-GaN region 7, the first n-GaN region 8, and the first AlGaN barrier layer 10 below the first SiO2 oxide layer 12, and the first SiO2 oxide layer 12 is partially sunken into the groove;

[0025] The first metal electrode, the second metal electrode, the third metal electrode and the fourth metal electrode are respectively composed of a single layer of elemental metal layers. As another embodiment, the first metal electrode, the second metal electrode, the third metal electrode and the fourth metal electrode are respectively composed of multiple layers of elemental metal layers, and the elemental metal is one of Au, Ti, Ni, W, Pt, and Al.

[0026] The following is a more detailed description of the specific implementation method with reference to the accompanying drawings:

[0027] As shown in Figure 1, a high-voltage enhancement-mode gallium nitride device designed by the present invention and easy to integrate includes, from bottom to top, a first silicon substrate 1, an insulating SiO2 layer 2, a second silicon substrate 3, a nucleation layer 4, a buffer layer 5, a GaN layer 6, a p-GaN region 7, a first n-GaN region 8, a second n-GaN region 9, a first AlGaN barrier layer 10, a second AlGaN barrier region 11, a first SiO2 oxide layer 12, a second SiO2 oxide layer 13, a first metal electrode 14, a second metal electrode 15, a third metal electrode 16, and a fourth metal electrode 17; the role of the nucleation layer is to help alleviate the lattice mismatch between the second silicon substrate 3 and the buffer layer 5.

[0028] The first metal electrode 14 of the structure is connected to the third metal electrode 16, serving as the source of the high-voltage enhancement-mode gallium nitride device. The connection can be an internal metal connection or an external wire connection (Figure 2(a) uses an external wire to connect the two metal electrodes). The second metal electrode 15 serves as the gate of the high-voltage enhancement-mode gallium nitride device, and the fourth metal electrode 17 serves as the drain of the high-voltage enhancement-mode gallium nitride device.

[0029] The high-voltage enhancement-mode gallium nitride device that is easy to integrate is characterized in that the materials of the first metal electrode 14, the second metal electrode 15, the third metal electrode 16, and the fourth metal electrode 17 are all composed of a single layer or multiple layers of a single metal, and the single metal includes but is not limited to Au, Ti, Ni, W, Pt, and Al.

[0030] When zero voltage or a negative voltage is applied to the gate of this high-voltage enhancement-mode gallium nitride device, the p-GaN region 7 and the 2DEG channel region below the second metal electrode 15 are closed. When a high voltage is applied to the device drain, the depletion region begins to widen from the boundary between the p-GaN region 7 and the GaN layer 6. When it widens to the second n-GaN region 9, the depletion rate slows down, and the induced potential in this region gradually increases. When the induced potential between this region and the third metal electrode 16 assists in improving the energy band of the second AlGaN barrier layer 11 and the GaN layer 6 below, and the GaN layer 6 is above its Fermi level, the 2DEG channel region generated by depletion polarization is depleted. At this time, there is no directional movement of carriers in the GaN layer 6 to the right of the second n-GaN region 9, and the depletion layer can restart from the right side of the second n-GaN region 9. Therefore, the introduction of the second n-GaN region 9 and the third metal electrode alleviates the marginal reduction effect of the device's withstand voltage and further improves the device's withstand voltage rating.

[0031] By etching grooves on the p-GaN region 7, the first n-GaN region 8, and the first AlGaN barrier layer 10 below the first SiO2 oxide layer 12, so that the first SiO2 oxide layer 12 is partially sunken into the grooves, and then the first SiO2 oxide layer and the second metal electrode 15 are deposited, the polarization effect formed by the grooved portion of the first AlGaN barrier layer 10 and the GaN layer 6 is weakened, and the energy band of the GaN layer 6 is relatively improved. When the groove depth is large enough to raise the energy band above the Fermi level of the GaN layer, the 2DEG in the channel region formed by the GaN layer 6 and the first AlGaN barrier layer 10 is depleted, so that when the gate is not biased, no carriers pass through the device, that is, the enhancement mode of the grooved portion of the device is achieved. Moreover, when the gate voltage of the device drops from the threshold, due to the small width of the ungrooved portion, the depletion region below the grooved portion will diffuse laterally, thereby achieving the enhancement mode of the entire device.

[0032] Furthermore, for the high-voltage enhancement-mode gallium nitride device, when the positive voltage applied to the device gate reaches the device threshold voltage, the region near the gate within the p-GaN region 7 inverts from p-type to n-type, allowing electrons to travel from the first n-GaN region 8 through the p-GaN region 7 to the second n-GaN region 9. At this point, the 2DEG channel formed by the GaN layer 6 and the first AlGaN barrier layer 10 further enhances the device's current capability. The potential difference between the second n-GaN region 9 and the third metal electrode 16 is zero, fully opening the 2DEG channel formed by the GaN layer and the second AlGaN barrier layer. Electrons flow toward the fourth metal electrode 17, forming a complete current path. In summary, the current path is: second metal electrode 15 → first n-GaN region 8 → p-GaN region 7 → 2DEG channel region formed by the first AlGaN barrier layer and GaN layer → second n-GaN region 9 → 2DEG channel region formed by the second AlGaN barrier layer 11 and GaN layer 6 → fourth metal electrode 17.

[0033] The selected insulating SiO2 layer structure 2 can hinder the movement of electrons from the first silicon substrate 1 to the second silicon substrate 3 at high temperatures, allowing the device to operate under ultra-high temperature conditions; it can eliminate substrate crosstalk among multiple devices in integrated circuit applications; it effectively achieves isolation of the device from other devices, reduces parasitic capacitance, reduces switching losses, and increases switching frequency.

[0034] For the high-voltage enhancement-mode gallium nitride device, drilling a hole from the first metal electrode 14 to the second silicon substrate 3 can alleviate the dynamic resistance degradation caused by substrate floating.

[0035] As shown in Figures 2(a), 2(b), and 3(b), cross-sectional views of the device of the present invention along L1, L2, and L4 are provided. L1 and L4 depict cross-sectional views of the device in different directions after etching the first AlGaN barrier layer, while L2 is a cross-sectional view of the device without etching the first AlGaN barrier layer. It can be seen that etching the first AlGaN barrier layer is to achieve the enhancement mode of the device, while leaving a portion of the unetched area is to increase the current capability of the device and reduce the on-resistance of the device.

[0036] Figure 3(a) shows a cross-sectional view of the device along L3. It can be seen that by performing spaced holes in the first metal electrode, the source of the device is directly connected to the second silicon substrate of the device. This prevents excess carriers from being trapped by electrons or holes due to the substrate floating when the drain is subjected to high voltage, thus preventing the current collapse effect (i.e., dynamic resistance degradation) from occurring when the device is turned on.

[0037] As shown in Figure 4(a), when the device is in the withstand voltage stage, the depletion layer expands from the AlGaN layer to the GaN layer. At the same time, the depletion layer expands not only in one direction, but in all directions, including the Y direction. As shown in Figure 4(b), since the distance of the ungrooved region in the Y direction is much smaller than the distance of the grooved region, the depletion layer of the device will reach the situation shown in Figure 4(b). At this time, the device will reach a critical situation. If the drain voltage of the device is increased, the depletion layer of the device will continue to expand and will reach the situation shown in Figure 4(c). In this case, the depletion layer of the device will be connected into one area, that is, the grooved area will deplete the ungrooved area, realizing the enhancement mode of the entire device.

[0038] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any improvements and modifications made by ordinary technicians in the field of the present invention based on the above disclosure without departing from the technical principles of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A high-voltage enhancement-mode gallium nitride device that is easy to integrate, comprising: A second silicon substrate (3) is provided on the second silicon substrate (3), a nucleation layer (4), a buffer layer (5) and a GaN layer (6) are provided from bottom to top, a p-GaN region (7) and an AlGaN barrier layer are provided on the GaN layer (6), a first n-GaN region (8) is provided in the p-GaN region (7), a first metal electrode (14) is connected to the first n-GaN region (8), a first SiO2 oxide layer (12) is provided on the p-GaN region (7), and both ends of the first SiO2 oxide layer (12) extend to the n-GaN region (8) and the AlGaN barrier layer (10), respectively, a second metal electrode (15) is provided on the first SiO2 oxide layer (12) and serves as a gate of the device, and a first electrode (15) is provided on the AlGaN barrier layer A fourth metal electrode (17) is provided and serves as a drain of the device, and is characterized in that a second n-GaN region (9) and a second SiO2 oxide layer (13) are provided on the AlGaN barrier layer, a third metal electrode (16) is provided on the second SiO2 oxide layer (13), the second n-GaN region (9) extends deep into the GaN layer (6) and divides the AlGaN barrier layer into a first AlGaN barrier layer (10) and a second AlGaN barrier layer (11), the second SiO2 oxide layer (13) and the third metal electrode (16) are located between the second n-GaN region (9) and the fourth metal electrode (17), and the third metal electrode (16) is connected to the first metal electrode (14) and serves as the source of the device.

2. The high-voltage enhancement-mode gallium nitride device that is easy to integrate according to claim 1, characterized in that: An insulating SiO2 layer (2) is provided below the second silicon substrate (3), and a first silicon substrate (1) is provided below the insulating SiO2 layer (2).

3. The high-voltage enhancement-mode gallium nitride device that is easy to integrate according to claim 1 or 2, characterized in that: A groove is provided on the p-GaN region (7), the first n-GaN region (8) and the first AlGaN barrier layer (10) below the first SiO2 oxide layer (12), and the first SiO2 oxide layer (12) is partially sunken into the groove.

4. The high-voltage enhancement-mode gallium nitride device that is easy to integrate according to claim 3, characterized in that: The first metal electrode, the second metal electrode, the third metal electrode and the fourth metal electrode are respectively composed of a single metal layer.

5. The high-voltage enhancement-mode gallium nitride device that is easy to integrate according to claim 3, characterized in that: The first metal electrode, the second metal electrode, the third metal electrode and the fourth metal electrode are respectively composed of multiple single metal layers.

6. The high-voltage enhancement-mode gallium nitride device that is easy to integrate according to claim 4 or 5, characterized in that: The elemental metal is one of Au, Ti, Ni, W, Pt, and Al.

Images